MICRON MT49H8M32FM

ADVANCE‡
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
REDUCED LATENCY
DRAM (RLDRAM)
MT49H8M32 – 1 Meg x 32 x 8 banks
MT49H16M16 – 2 Meg x 16 x 8 banks
For the latest data sheet, please refer to the Micron
Web site: www.micron.com/dramds
FEATURES
144-Ball T-FBGA
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Cyclic bank addressing for maximum data out
bandwidth
• Non-multiplexed addresses
• Non-interruptible sequential burst of two (2-bit
prefetch) and four (4-bit prefetch) DDR
• Target 600 Mb/s/p data rate
• Programmable Read Latency (RL) of 5-8
• Data valid signal (DVLD) activated as read data is
available
• Data Mask signals (DM0/DM1) to mask first and
second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• Pseudo-HSTL 1.8V I/O Supply
• Internal Auto Precharge
• Refresh requirements: 32ms at 100°C junction
temperature (8K refresh for each bank, 64K refresh
command must be issued in total each 32ms)
OPTIONS
MARKING
• Clock Cycle Timing
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200 MHz)
-3.3
-4
-5
• Configuration
8 Meg x 32
(1 Meg x 32 x 8 banks)
16 Meg x 16
(2 Meg x 16 x 8 banks)
row/column address multiplexing and is optimized for
fast random access and high-speed bandwidth.
RLDRAM is designed for communication data
storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache
applications requiring large amounts of memory.
MT49H8M32FM
MT49H16M16FM
• Package
144-ball, 11mm x 18.5mm T-FBGA
FM
POWER-UP INITIALIZATION
Since the RLDRAM does not have a designated reset
function, the following procedure must be executed in
order to initalize the internal state machine, regulators,
and force the DRAM to be in ready state.
• Apply power, then start clock
• After power on, an initial pause of 200µs is required
• MRS command for 2 clocks and set standard mode
register for 1 clock (2 dummies plus 1 valid MRS set)
• 8 refresh cycles (minimum), one on each bank and
separated by 2,048 cycles (tMRSC must be satisfied
between MRS and first REF command)
• Ready for normal operation (tRC cycles after the last
refresh command)
VALID PART NUMBERS
PART NUMBER
MT49H8M32FM-xx
MT49H16M16FM-xx
DESCRIPTION
8 Meg x 32
16 Meg x 16
GENERAL DESCRIPTION
The Micron ® 256Mb Reduced Latency DRAM
(RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR)
format where the data is provided and synchronized with
a differential echo clock signal. RLDRAM does not require
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
‡PRODUCTS
1
©2002, Micron Technology, Inc.
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
POWER-DOWN
Because the RLDRAM uses multiple power supply
voltage, the following sequence is required for powerdown.
• Take all input signals to be VSS or High-Z
It is recommended to place Schottky diodes on the
board between the 2.5V and 1.8V power supplies.
FUNCTIONAL BLOCK DIAGRAM
8 Meg x 32
Sense Amp and Data Bus
Column Decoder
Bank 6
Output Buffers
DQ0–DQ31
Memory Array
Bank 7
Control Logic and Timing Generator
VREF
Input Buffers
Column Decoder
Bank 5
Memory Array
Sense Amp and Data Bus
Column Decoder
Memory Array
DM1
DQS[3:0], DQS#[3:0]
Bank 3
DM0
DVLD
Memory Array
Row Decoder
CS#
Data Read Strobe
Bank 2
REF#
Data Valid
Memory Array
Row Decoder
Sense Amp and Data Bus
Column Decoder
Memory Array
Bank 4
Bank 1
Row Decoder
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
Row Decoder
Memory Array
Row Decoder
AS#
Bank 0
Column Decoder
Column Decoder
Memory Array
Row Decoder
WE#
Row Decoder
Refresh
Counter
CK
Row Decoder
Row Address
Buffer
C K#
Column Address
Buffer
Sense Amp and Data Bus
Column Address
Counter
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
A0–A18, B0, B1, B2
NOTE: 1. When the BL4 setting is used, A18 is a “Don’t Care.”
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
FUNCTIONAL BLOCK DIAGRAM
16 Meg x 16
Output Buffers
DQ0–DQ15
Sense Amp and Data Bus
Column Decoder
Column Decoder
Sense Amp and Data Bus
Bank 7
Control Logic and Timing Generator
VREF
Input Buffers
Bank 6
Memory Array
DM1
DQS[1:0], DQS#[1:0]
Bank 5
Memory Array
DM0
DVLD
Bank 3
Row Decoder
CS#
Data Read Strobe
Bank 2
Memory Array
REF#
Data Valid
Memory Array
Column Decoder
Bank 4
Column Decoder
Memory Array
Memory Array
Row Decoder
Sense Amp and Data Bus
Row Decoder
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
Row Decoder
Bank 1
Row Decoder
AS#
Bank 0
Memory Array
Column Decoder
Column Decoder
Memory Array
Row Decoder
WE#
Row Decoder
Refresh
Counter
CK
Row Decoder
Row Address
Buffer
CK#
Column Address
Buffer
Sense Amp and Data Bus
Column Address
Counter
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
A0–A19, B0, B1, B2
NOTE: 1. When the BL4 setting is used, A19 is a “Don’t Care.”
2. In the 16 Meg x 16 configuration, only DQS[1:0] and DQS#[1:0] are used.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
TABLE OF CONTENTS
General Description .......................................................
Power-Up Initialization ...................................................
Functional Block Diagram, 8 Meg x 32 ................
Power-Down ...................................................................
Functional Block Diagram, 16 Meg x 16 .............
8 Meg x 32 Ball Assignment (Top View)
144-Ball T-FBGA ...............................................
16 Meg x 16 PIN Assignment (Top View)
144-Ball T-FBGA ...............................................
Ball Descriptions ....................................................
Ball Descriptions (continued) ................................
Truth Table 1 ..........................................................
Programming Description ..............................................
RLDRAM Programming Table ..............................
Mode Register Description ............................................
Mode Register Command Table ...........................
IEEE 1149.1 Serial Boundary Scan (JTAG) ................
Disabling the JTAG Feature ..........................................
Figure 1, TAP Controller State Diagram ..............
Test Access Port (TAP) ..................................................
Test Clock (TCK) ........................................................
Test MODE SELECT (TMS) ......................................
Test Data-In (TDI) ......................................................
Test Data-Out (TDO) .................................................
Performing a TAP Reset ...........................................
TAP Registers ............................................................
Instruction Register ....................................................
Figure 2, TAP Controller Block Diagram .............
Bypass Register .........................................................
Boundary Scan Register ...........................................
Identification (ID) Register ........................................
TAP Instruction Set ........................................................
Overview .....................................................................
Extest ..........................................................................
Idcode .........................................................................
Sample Z ....................................................................
Sample/Preload .........................................................
Bypass ........................................................................
TAP Timing .............................................................
TAP AC Electrical Characteristics ........................
Reserved ....................................................................
TAP DC Electrical Characteristics and
Operating Conditions ........................................
Identification Register Definitions ........................
Scan Register Sizes ..............................................
Instruction codes ...................................................
Boundary Scan (Exit) Order .................................
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Absolute Maximum Ratings ..........................................
Recommended DC Operation Ranges ........................
DC Electrical Characteristics and
Operating Conditions ........................................
DC Electrical Characteristics and
Operating Conditions ........................................
IDD Electrical Characteristics and
Operating Conditions ........................................
Capacitance ...........................................................
AC Electrical Characteristics and
Operating Conditions ........................................
AC Electrical Characteristics ................................
1
1
2
2
3
5
5
6
7
8
9
9
10
10
11
11
11
11
11
11
11
12
12
12
12
12
12
12
13
13
13
13
13
13
13
14
14
14
14
Timing Waveforms
General Overview and Timing Definition
(BL2/WL2) ..........................................................
READ Timing (BL = 2) ...........................................
READ Timing (BL = 4) ...........................................
WRITE Timing (BL = 2, RL = 6) ...........................
WRITE Timing (BL = 4, RL = 6) ...........................
READ to WRITE Timing (BL = 2, WL = 2) ..........
WRITE to READ Timing (BL = 2, WL = 2) ..........
Refresh Timing .......................................................
Example of Refresh Implementation
(Cyclic Bank Burst Refresh) .............................
WRITE Data Mask Timing (BL = 2, WL = 2) .......
WRITE Data Mask Timing (BL = 4, WL = 1) .......
WRITE/READ and READ/WRITE Timing, Cyclic
Bank Access (RL = 6, BL = 2, WL = 3) ...........
WRITE/READ and READ/WRITE Timing, Cyclic
Bank Access (RL = 5, BL = 2, WL = 2) ...........
WRITE/READ and READ/WRITE Timing, Cyclic
Bank Access (RL = 6, BL = 4, WL = 2) ...........
WRITE/READ and READ/WRITE Timing, Cyclic
Bank Access (RL = 5, BL = 4, WL = 1) ...........
Random Access, Single Bank
(RL = 6, BL = 2, WL = 3) ...................................
Random Access, Single Bank
(RL = 5, BL = 2, WL = 2, tRC = 6) ....................
Random Access, Single Bank
(RL = 6, BL = 4, WL = 2) ...................................
Random Access, Single Bank
(RL = 5, BL = 4, WL = 1, tRC = 6) ....................
15
16
16
16
17
18
18
18
19
20
21
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Package Drawing
144-Ball T-FBGA .................................................... 42
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
8 MEG x 32 BALL ASSIGNMENT (Top View)
144-Ball T-FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VSS
VSS
VSS
VSS
VSS
DM0
A5
A8
AS#
WE#
A18
A15
DM1
VSS
VSS
VSS
VSS
VSS
2
3
4
5
6
7
8
VEXT
VREF
VSS
DQ8
DQ9
VSSQ
DQ10 DQ11 VDDQ
DQS1 DQS1# VSSQ
DQ12 DQ13 VDDQ
DQ14 DQ15 VSSQ
A6
A7
VDD
A9
VSS
VSS
B2
VDD
VDD
REF#
VDD
VDD
CS#
VSS
VSS
A16
A17
VDD
DQ22 DQ23 VSSQ
DQ20 DQ21 VDDQ
DQS2 DQS2# VSSQ
DQ18 DQ19 VDDQ
DQ16 DQ17 VSSQ
VEXT
VREF
VSS
9
10
11
VSS
VEXT
TMS
VSSQ
DQ1
DQ0
VDDQ DQ3
DQ2
VSSQ DQS0# DQS0
VDDQ DQ5
DQ4
VSSQ
DQ7
DQ6
VDD
A2
A1
VSS
VSS
A4
VDD
VDD
B0
VDD
VDD
B1
VSS
VSS
A14
VDD
A12
A11
VSSQ DQ31 DQ30
VDDQ DQ29 DQ28
VSSQ DQS3# DQS3
VDDQ DQ27 DQ26
VSSQ DQ25 DQ24
VSS
VEXT
TDO
12
TCK
VSS
VSS
VSS
VSS
DVLD
A0
A3
CK
CK#
A13
A10
NC
VSS
VSS
VSS
VSS
TDI
16 MEG x 16 BALL ASSIGNMENT (Top View)
144-Ball T-FBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
1
2
3
4
VSS
VSS
VSS
VSS
VSS
DM0
A5
A8
AS#
WE#
A19
A15
DM1
VSS
VSS
VSS
VSS
VSS
VEXT
NC
NC
NC
NC
NC
A6
A9
B2
REF#
CS#
A16
NC
NC
NC
NC
NC
VEXT
VREF
NC
NC
NC
NC
NC
A7
VSS
VDD
VDD
VSS
A17
NC
NC
NC
NC
NC
VREF
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
5
6
7
8
9
10
11
VSS
VEXT
TMS
VSSQ
DQ1
DQ0
VDDQ DQ3
DQ2
VSSQ DQS0# DQS0
VDDQ DQ5
DQ4
VSSQ
DQ7
DQ6
VDD
A2
A1
VSS
VSS
A4
VDD
VDD
B0
VDD
VDD
B1
VSS
VSS
A14
VDD
A12
A11
VSSQ DQ15 DQ14
VDDQ DQ13 DQ12
VSSQ DQS1# DQS1
VDDQ DQ11 DQ10
VSSQ
DQ9
DQ8
VSS
VEXT
TDO
5
12
TCK
VSS
VSS
VSS
VSS
DVLD
A0
A3
CK
CK#
A13
A10
A18
VSS
VSS
VSS
VSS
TDI
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
BALL DESCRIPTIONS
T-FBGA (x32) T-FBGA (x16)
SYMBOL
TYPE
12J, 12K
12J, 12K
CK, CK#
Input
Differential input clock pair
DESCRIPTION
2L
2L
CS#
Input
Chip select
1J
1J
AS#
Input
Address strobe
1K
1K
WE#
Input
Write enable
2K
2K
REF#
Input
Auto refresh
11J, 11K, 2J
11J, 11K, 2J
B[0:2]
Input
Bank select
12G, 11G, 10G,
12H, 11H, 1G,
2G, 3G, 1H,
2H, 12M, 11M,
10M, 12L, 11L,
1M, 2M, 3M, 1L
12G, 11G, 10G,
12H, 11H, 1G,
2G, 3G, 1H,
2H, 12M, 11M,
10M, 12L, 11L,
1M, 2M, 3M,
12N, 1L
A[0:18]
A[0:19]
Input
Address input
1F, 1N
1F, 1N
DM0, DM1
Input
Data Mask
11A
12V
11A
12V
TMS
TDI
Input
IEEE 1149.1 Test Inputs: JEDEC-standard 1.8V I/O levels.
These pins may be left Not Connected if the JTAG
function is not used in the circuit.
12A
12A
TCK
Input
IEEE 1149.1 Clock Input: JEDEC-standard 1.8V I/O levels.
This pin must be tied to VSS if the JTAG function is not
used in the circuit.
3A, 3V
3A, 3V
VREF
Input
Input Reference Voltage: Nominally VDDQ/2. Provides a
reference voltage for the input buffers.
11B, 10B, 11C,
10C, 11E, 10E,
11F, 10F, 2B,
3B, 2C, 3C, 2E,
3E, 2F, 3F, 2U,
3U, 2T, 3T, 2P,
3P, 2N, 3N,
11U, 10U, 11T,
10T, 11P, 10P,
11N, 10N
11B, 10B, 11C,
10C, 11E, 10E,
11F, 10F, 11U,
10U, 11T, 10T,
11P, 10P, 11N,
10N
DQ0–DQ31
Input/
Output
Synchronous Data I/Os: Input data must meet setup and
hold times around the rising edges of CK and CK#.
Output data is synchronized to DQS and DQS#.
11D, 2D, 2R,
11R, 10D, 3D,
3R, 10R
11D, 11R,
10D, 10R
12F
12F
DVLD
Output
Data Valid
DQS0–3 (x32) Output
DQS#0–3 (x32)
DQS0–1 (x16)
DQS#0–1 (x16)
Differential data read strobe
11V
11V
TDO
Output
IEEE 1149.1 Test Output: JEDEC-standard 1.8V I/O level.
2A, 2V,
10A, 10V
2A, 2V,
10A, 10V
VEXT
Supply
Power Supply: 2.5V nominal. See DC Electrical
Characteristics and Operating Condidtions for range.
3J, 3K, 4G,
4J, 4K, 4M,
9G, 9J, 9K,
9M, 10J, 10K
3J, 3K, 4G,
4J, 4K, 4M,
9G, 9J, 9K,
9M, 10J, 10K
VDD
Supply
Power Supply: 1.8V nominal. See DC Electrical
Characteristics and Operating Conditions for range.
(continued on next page)
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
BALL DESCRIPTIONS (continued)
T-FBGA (x32) T-FBGA (x16)
SYMBOL
TYPE
4C, 4E, 4P,
4T, 9C, 9E,
9P, 9T
4C, 4E, 4P,
4T, 9C, 9E,
9P, 9T
VDDQ
Supply
Power Supply: Isolated Output Buffer Supply. Nominally
1.8V. See DC Electrical Characteristics and Operating
Conditions for range.
1A–E, 1P–V,
3H, 3L, 4A,
4H, 4L, 4V,
9A, 9H, 9L,
9V, 10H, 10L,
12B–E, 12P–U
1A–E, 1P–V,
3H, 3L, 4A,
4H, 4L, 4V,
9A, 9H, 9L,
9V, 10H, 10L,
12B–E, 12P–U
VSS
Supply
Power Supply: GND.
4B, 4D, 4F,
4N, 4R, 4U,
9B, 9D, 9F,
9N, 9R, 9U
4B, 4D, 4F,
4N, 4R, 4U,
9B, 9D, 9F,
9N, 9R, 9U
VSSQ
Supply
Power Supply: Isolated Output Buffer Supply. GND.
12N
2B–2F, 2N–2U,
3B–3F, 3N–3U
NC
–
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
DESCRIPTION
No Connect: These signals are not internally connected
and may be connected to ground to improve package
heat dissipation.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
TRUTH TABLE1
OPERATION
CS#
AS#
WE#
REF#
A[19:0]2
B[2:0]
DM[1:0]
READ Cycle
L
L
H
H
VALID
VALID
X
WRITE Cycle
L
L
L
H
VALID
VALID
VALID
NOP: No operation
L
H
H
H
X
X
X
Deselect
H
X
X
X
X
X
X
L
H
H
L
X
VALID
X
L
L
L
L
VALID
X
X
Auto Refresh
MRS: Mode Register
Set3
NOTE: 1. X = “Don’t Care.”
H = logic HIGH.
L = logic LOW.
2. In the x32 configuration A19 is not used.
3. Only A17–A0 are used for the Mode Register Set Command.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
PROGRAMMING DESCRIPTION
RLDRAM for the two Burst Lengths (BL) are also indicated. Finally, the minimum allowed tRC in clock cycles
and in ns are shown as well. The shaded areas correspond
to configurations that are not allowed.
The following table shows, for three operating frequencies, the different RLDRAM configurations that can be
programmed into the Mode Register. The Read Latency
(RL) values and the Write Latencies (WL) used by the
RLDRAM Programming Table
FREQUENCY
Unit
Config. Nb.
RL
TCK
WL (BL2)
TCK
1
5
2
2
5
2
WL (BL4)
tRC (MIN)
TCK
TCK
1
5
1
6
ns
16.7
20.0
1
2
tRC
(MIN)
Config. Nb.
-3.3 (300 MHz)
3
4
5
5
6
7
2
3
4
1
7
2
8
3
9
23.3 26.7 30.0
-4 (250 MHz)
3
4
5
6
8
5
4
10
33.3
6
RL
WL (BL2)
TCK
TCK
5
2
5
2
5
2
6
3
7
4
8
5
WL (BL4)
tRC (MIN)
tRC (MIN)
TCK
TCK
ns
1
5
20
1
6
24
1
7
28
2
8
32
3
9
36
4
10
40
-5 (200 MHz)
3
4
5
6
Config. Nb.
RL
WL (BL2)
WL (BL4)
tRC (MIN)
tRC
(MIN)
1
2
TCK
TCK
TCK
TCK
5
2
1
5
5
2
1
6
5
2
1
7
6
3
2
8
7
4
3
9
8
5
4
10
ns
25
30
35
40
45
50
NOTE: 1. The speed sort -3.3 provides part functional up to 300 MHz in the configurations 4, 5,
and 6 only.
The functionality of the configurations 1, 2, and 3 is not guaranteed for speed sort 3.3.
2. The speed sort -4 provides part functional up to 250 MHz in the configurations 3, 4, 5,
and 6 only.
The functionality of the configurations 1 and 2 is not guaranteed for speed sort -4.
3. The speed sort -5 provides part functional up to 200 MHz in all configurations.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
MODE REGISTER DESCRIPTION
The address signals A[17:0] are used to set the mode
register.
Mode Register Command Table
Address
Mode Register
Commands
NOTE: 1.
2.
3.
4.
5.
6.
A17–A7
Reserved2
A6
A5
Test Mode
A4
A3
I/O Driver Matched Burst
Strength
Mode
Length
A2
A1
A0
RLDRAM
Configuration
A3
Burst Length
A2
A1
A0
RLDRAM
Configuration
0
23
0
0
0
33
1
4
0
0
1
1
0
1
0
2
A4
Matched Mode
0
1
1
3
0
Inactive3
1
0
0
4
1
Active4
1
0
1
5
A5
Driver Strength1
1
1
0
6
0
8mA3
1
1
1
3
1
4mA
A6
Test Mode
0
Default Mode3
1
Test Mode Entry
HSTL-complient current specification
Bits A17–A6 MUST be set LOW (Logic 0)
Default configuration
When Matched Mode is asserted, the automatic I/O impedance calibration is activated
Test Mode entry for vendor test mode only
The Mode Register Set default configuration corresponds to all address bits equal to zero
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
IEEE 1149.1 SERIAL BOUNDARY SCAN
(JTAG)
TEST ACCESS PORT (TAP)
TEST CLOCK (TCK)
The test clock is used only with the TAP controller. All
inputs are captured on the rising edge of TCK. All outputs
are driven from the falling edge of TCK.
The RLDRAM incorporates a serial boundary scan
Test Access Port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because their inclusion places an added delay in the critical
speed path of the RLDRAM. Note that the TAP controller
functions in a manner that does not conflict with the
operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 1.8V I/O
logic levels.
The RLDRAM contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID
register.
TEST MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It is
allowable to leave this pin unconnected if the TAP is not
used. The pin is pulled up internally, resulting in a logic
HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by
the instruction that is loaded into the TAP instruction
register. For information on loading the instruction register, see Figure 1. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI
is connected to the most significant bit (MSB) of any
register. (See Figure 2.)
DISABLING THE JTAG FEATURE
It is possible to operate the RLDRAM without using the
JTAG feature. To disable the TAP controller, TCK must be
tied LOW (VSS) to prevent clocking of the device. TDI and
TMS are internally pulled up and may be unconnected.
They may alternately be connected to VDD through a pullup resistor. TDO should be left unconnected. Upon powerup, the device will come up in a reset state which will not
interfere with the operation of the device.
Figure 1
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
TEST DATA-OUT (TDO)
The TDO output pin is used to serially clock data-out
from the registers. The output is active depending upon
the current state of the TAP state machine. (See Figure 1.)
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
(See Figure 2.)
When the TAP controller is in the Capture-IR state,
the two least significant bits are loaded with a binary “01”
pattern to allow for fault isolation of the board-level serial
test data path.
BYPASS REGISTER
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips.
The bypass register is a single-bit register that can be
placed between the TDI and TDO pins. This allows data to
be shifted through the RLDRAM with minimal delay. The
bypass register is set LOW (V SS) when the BYPASS
instruction is executed.
PERFORMING A TAP RESET
A RESET is performed by forcing TMS HIGH (VDD) for
five rising edges of TCK. This RESET does not affect the
operation of the RLDRAM and may be performed while the
RLDRAM is operating.
At power-up, the TAP is reset internally to ensure that
TDO comes up in a High-Z state.
BOUNDARY SCAN REGISTER
The boundary scan register is connected to all the
input and bidirectional pins on the RLDRAM. Several no
connect (NC) pins are also included in the scan register to
reserve pins. The RLDRAM has a 104-bit register.
The boundary scan register is loaded with the contents
of the RAM I/O ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the
Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and
SAMPLE Z instructions can be used to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in
which the bits are connected. Each bit corresponds to one
of the pins on the RLDRAM package. The MSB of the
register is connected to TDI, and the LSB is connected to
TDO.
TAP REGISTERS
Registers are connected between the TDI and TDO
pins and allow data to be scanned into and out of the
RLDRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is serially
loaded into the TDI pin on the rising edge of TCK. Data is
output on the TDO pin on the falling edge of TCK.
INSTRUCTION REGISTER
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in Figure
2. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Figure 2
TAP Controller Block Diagram
0
Bypass Register
7 6 5 4 3 2 1 0
TDI
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29 .
.
TDO
. 2 1 0
Identification Register
x .
.
.
.
. 2 1 0
Boundary Scan Register
TCK
TMS
TAP Controller
x = 103 for all configurations.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
IDENTIFICATION (ID) REGISTER
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE
command is loaded in the instruction register. The IDCODE
is hardwired into the RLDRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has a vendor code and other information described in the
Identification Register Definitions table.
ter upon power-up or whenever the TAP controller is
given a test logic reset state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and bidirectional pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock
can only operate at a frequency up to 10 MHz, while the
RLDRAM clock operates more than an order of magnitude
faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR
state, an input or output will undergo a transition. The TAP
may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no
guarantee as to the value that will be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will
capture the correct value of a signal, the RLDRAM signal
must be stabilized long enough to meet the TAP controller’s
capture setup plus hold time (tCS plus tCH). The RLDRAM
clock input might not be captured correctly if there is no
way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan
register.
Once the data is captured, it is possible to shift out the
data by putting the TAP into the Shift-DR state. This places
the boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is
not implemented, putting the TAP to the Update-DR state
while performing a SAMPLE/PRELOAD instruction will
have the same effect as the Pause-DR command.
TAP INSTRUCTION SET
OVERVIEW
Eight different instructions are possible with the threebit instruction register. All combinations are listed in the
Instruction Codes table (see page 16). Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.
The TAP controller used in this RLDRAM is not fully
compliant to the 1149.1 convention because some of the
mandatory 1149.1 instructions are not fully implemented.
The TAP controller cannot be used to load address, data
or control signals into the RLDRAM and cannot preload
the I/O buffers. The RLDRAM does not implement the
1149.1 commands EXTEST or INTEST or the PRELOAD
portion of SAMPLE/PRELOAD; rather it performs a capture of the I/O ring when these instructions are executed.
Instructions are loaded into the TAP controller during
the Shift-IR state when the instruction register is placed
between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI
and TDO pins. To execute the instruction once it is shifted
in, the TAP controller needs to be moved into the UpdateIR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to
be executed whenever the instruction register is loaded
with all 0s. EXTEST is not implemented in the TAP
controller, hence this device is not IEEE 1149.1 compliant.
The TAP controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the RLDRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. EXTEST does not place the
RLDRAM outputs in a High-Z state, CQ, CQ#.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the
bypass register is placed between TDI and TDO. The
advantage of the BYPASS instruction is that it shortens
the boundary scan path when multiple devices are connected together on a board.
IDCODE
The IDCODE instruction causes a vendor-specific, 32bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction regis-
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
RESERVED
These instructions are not implemented but are reserved for future use. Do not use these instructions.
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
TAP TIMING
1
2
3
4
5
6
Test Clock
(TCK)
tTHTL
tMVTH
tTHMX
tDVTH
tTHDX
t
TLTH
tTHTH
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTLOV
tTLOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2) (+20°C £ TJ £ +100°C, +1.7V £ VDD £ +1.9V)
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
TCK LOW to TDO unknown
TCK LOW to TDO valid
TDI valid to TCK HIGH
TCK HIGH to TDI invalid
Setup Times
TMS setup
Capture setup
Hold Times
TMS hold
Capture hold
SYMBOL
MIN
tTHTH
20
fTF
tTHTL
50
tTLTH
10
10
tTLOX
0
tTHDX
tMVTH
tCS
tTHMX
tCH
10
10
UNITS
ns
MHz
ns
ns
5
5
ns
ns
ns
ns
5
5
ns
ns
5
5
ns
ns
tTLOV
tDVTH
MAX
NOTE: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in Figure 4.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(+20°C £ TJ £ 110°C, +2.4V £ VDD £ +2.6V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
CONDITIONS
SYMBOL
MIN
MAX
VIH
VREF + 0.15 VDD + 0.3
VIL
VSSQ - 0.3 VREF - 0.15
0V £ VIN £ VDD
Output(s) disabled,
0V £ VIN £ VDDQ
IOLC = 100µA
IOLT = 2mA
|IOHC| = 100µA
|IOHT| = 2mA
ILI
ILO
-5.0
-5.0
UNITS
V
V
NOTES
1, 2
1, 2
5.0
5.0
µA
µA
VREF - TBD
VREF - TBD
1
1
1
1
VOL1
VOL2
VOH1
VREF + TBD
V
V
V
VOH2
VREF + TBD
V
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot:
VIH(AC) £ VDD + 1.5V for t £ tKHKH/2
Undershoot: VIL(AC) ³ -0.5V for t £ tKHKH/2
Power-up:
VIH £ +1.9 and VDD £ 1.7V and VDDQ £ 1.4V for t £ 200ms
During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD#, R/W#, etc.) may not have
pulse widths less than tKHKL (MIN) or operate at frequencies exceeding fKF (MAX).
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD
ALL DEVICES
REVISION NUMBER
(31:28)
00ab
DEVICE ID
(27:12)
0000000010100111
MICRON JEDEC ID
CODE (11:1)
00000101100
ID Register Presence
Indicator (0)
1
DESCRIPTION
ab = 10 for x32, 01 for x16.
This represents the part number
Allows unique identification of RLDRAM vendor.
Indicates the presence of an ID register.
SCAN REGISTER SIZES
REGISTER NAME
BIT SIZE
Instruction
8
Bypass
1
ID
32
Boundary Scan
104
INSTRUCTION CODES
INSTRUCTION
CODE
DESCRIPTION
EXTEST
0000 0000 Captures I/O ring contents. Places the boundary scan register between TDI and
TDO. This instruction is not 1149.1-compliant. This operation does not affect
RLDRAM operations.
IDCODE
0010 0001 Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect RLDRAM operations.
SAMPLE/PRELOAD 0000 0101 Captures I/O ring contents. Places the boundary scan register between TDI and
TDO. This instruction does not implement 1149.1 preload function and is
therefore not 1149.1-compliant.
BYPASS
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
1111 1111 Places the bypass register between TDI and TDO. This operation does not affect
RLDRAM operations.
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Boundary Scan (Exit) Order
BIT#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
FBGA BALL
J1
J2
H2
H1
G1
G3
G2
F1
F3
F3
F2
F2
E3
E3
E2
E2
D2
D3
C2
C2
C3
C3
B2
B2
B3
B3
B10
B10
B11
B11
C10
C10
C11
C11
D10
BIT#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
FBGA BALL
D11
E11
E11
E10
E10
F11
F11
F10
F10
F12
G11
G10
G12
H12
H11
J11
J12
K12
K11
L11
L12
M12
M10
M11
M12
N10
N10
N11
N11
P10
P10
P11
P11
R11
R10
BIT#
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
FBGA BALL
T11
T11
T10
T10
U11
U11
U10
U10
U3
U3
U2
U2
T3
T3
T2
T2
R3
R2
P2
P2
P3
P3
N2
N2
N3
N3
N1
M2
M3
M1
L1
L2
K2
K1
NOTE: 1. Any unused pins that are in the order will read as a logic “0.”
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
**Junction temperature depends upon package type,
cycle time, loading, ambient temperature, and airflow.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature .............................. -55°C to +150°C
I/O Voltage ................................... -0.3V to + VDDQ + 0.3V
Voltage on VEXT Supply Relative to VSS ... -0.3V to +2.8V
Voltage on VDD Supply Relative to VSS ..... -0.3V to +2.1V
Voltage on VDDQ Supply Relative to VSS .. -0.3V to +2.1V
Junction Temperature** ............................................ 100°C
RECOMMENDED DC OPERATION
RANGES
All values are recommended operating conditions unless otherwise noted. External on board (PCB) capacitance values are required as follows:
• VDDQ :2 x 0.1µF/device
• VDD
:2 x 0.1µF/device
• V R E F :0.1µF/device
• VEXT :0.1µF/device
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(+20°C £ TJ £ +110°C; +1.75V £ VDD £ +1.85V unless otherwise noted)
DESCRIPTION
SYMBOL
MIN
MAX
Supply Voltage
Supply Voltage
VEXT
VDD
2.38
1.75
2.63
1.85
Isolated Output Buffer Supply
Reference Voltage
VDDQ
VREF
1.7
1.9
0.95 x VDDQ/2 1.05 x VDDQ/2
UNITS NOTES
V
V
1
1,
V
V
1, 4
1, 2, 3
NOTE: 1. All voltages referenced to VSS (GND).
2. Typically the value of VREF is expect to be 0.5x VDDQ of the transmitting device. VREF is expected to track variations in
VDDQ.
3. Peak to peak AC noise on VREF must not exceed 2% VREF(DC).
4. During normal operation, VDDQ must not exceed VDD.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(+20°C £ TJ £ +110°C; +1.75V £ VDD £ +1.85V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
CONDITIONS
Matched Impedance Mode
Matched Impedance Mode
SYM
VIH
VIL
MIN
VREF + 0.15
VSSQ - 0.3
Output High Voltage
Output Low Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Output High Voltage
Matched Impedance Mode
Matched Impedance Mode
HSTL Strong
HSTL Strong
HSTL Strong
VOH
VOL
VIH
VIL
VOH
VDDQ
Output Low Voltage
Input High (Logic 1) Voltage
HSTL Strong
HSTL Weak
VOL
VIH
Input Low (Logic 0) Voltage
Output High Voltage
HSTL Weak
HSTL Weak
Output Low Voltage
Clock Input Leakage Current
Input Leakage Current
Output Leakage Current
Reference Voltage Current
MAX
VDDQ + 0.3
VREF - 0.15
UNITS NOTES
V
1, 2
V
1, 2
V
V
V
V
V
1, 3, 4
1, 3, 4
1, 2
1, 2
1, 3, 4
V
V
1, 3, 4
1, 2
VIL
VOH
V
V
1, 2
1, 3, 4
HSTL Weak
VOL
ILC
1, 3, 4
-5
5
V
µA
0V £ VIN £ VDDQ
ILI
ILO
IREF
-5
-5
-5
5
5
5
µA
µA
µA
VREF + 0.1
VSSQ - 0.3
VDDQ - 0.4
0
VDDQ + 0.3
VREF - 0.1
0.4
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot:
VIH (AC) £ VDD + 0.7V for t £ tKHKH/2
Undershoot: VIL (AC) ³ -0.5V for t £ tKHKH/2
Power-up:
VIH £ VDDQ + 0.3V and VDD £ 1.7V and VDDQ £ 1.4V for t £ 200ms
During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL
(MIN) or operate at cycle rates less than tKHKH (MIN).
3. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(+20°C £ TJ £ +110°C; VDD = MAX unless otherwise noted)
DESCRIPTION
Operating Supply
Current
Operating Supply
Current
Operating Supply
Current
Standby
Current
TYPICAL
CONDITIONS
SYMBOL
-3.3
-4
-5
UNITS
NOTES
BL = 2, tCK = MIN, tRC = MIN,
1 bank active, Address
change up to 8 times
during minimum tRC
IDD1(VDD)
248
208
168
mA
1
IDD1(VEXT)
17
16
15
mA
1
IDD4R(VDD)
403
337
271
mA
1
IDD4R(VEXT)
27
25
22
mA
1
IDD8(VDD)
610
509
409
mA
1
IDD8(VEXT)
41
36
32
mA
1
IDDS(VDD)
TBD
TBD
TBD
mA
IDDS(VEXT)
TBD
TBD
TBD
mA
BL = 4, tCK = MIN, tRC = MIN,
4 banks interleave, Address
change up to 8 times
during minimum tRC
Continous data
BL = 2, tCK = MIN, tRC = MIN,
8 banks interleave, Address
change up to 8 times
during minimum tRC
Continous data
tCK
= MIN, CS# = 1
all banks idle,
Command toggling
NOTE: 1. Values determined with outputs in high impedance state.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
CI
2
4
pF
CO
2
4
pF
CCK
2
4
pF
Address/Control Input Capacitance
Input/Output Capacitance (DQ)
TA = 25°C; f = 1 MHz
Clock Capacitance
AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(+20°C £ TJ £ +110°C; +1.75V £ VDD £ +1.85V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
CONDITIONS
Matched Impedance Mode
Matched Impedance Mode
SYMBOL
VIH
VIL
MIN
VREF + 0.3
VSSQ - 0.3
MAX
VDDQ + 0.3
VREF - 0.3
UNITS
V
V
CK Differential Input Voltage
CK Input Crossing Point
Matched Impedance Mode
Matched Impedance Mode
V ID
VIX
0.6
VREF - 0.15
VDDQ + 0.6
VREF + 0.15
V
V
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
CK Differential Input Voltage
HSTL Strong
HSTL Strong
HSTL Strong
VIH
VIL
VID
VREF + 0.2
VSSQ - 0.3
0.6
VDDQ + 0.3
VREF - 0.2
VDDQ + 0.6
V
V
V
CK Input Crossing Point
Input High (Logic 1) Voltage
HSTL Strong
HSTL Weak
VIX
VIH
VREF - 0.15
VREF + 0.15
V
V
Input Low (Logic 0) Voltage
CK Differential Input Voltage
CK Input Crossing Point
HSTL Weak
HSTL Weak
HSTL Weak
VIL
VID
VIX
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
21
V
V
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
AC ELECTRICAL CHARACTERISTICS
(Notes 4, 5) (+20°C £ TJ £ +110°C; +1.75V £ VDD £ +1.85V)
DESCRIPTION
Clock
Clock cycle time
Clock HIGH time
Clock LOW time
Clock to DQS,DQS#
DQS,DQS# HIGH time
DQS,DQS# LOW time
Output Times
DQS to output valid
DQS to output High-Z
DQS# to DVLD
MRS to any command
Setup Times
Address/Command
Data-in
Hold Times
Address/Command
Data-in
NOTE: 1.
2.
3.
4.
SYMBOL
tCK
tCKH
tCKL
tCKDQS
tDQSH
tDQSL
tQSQ
tQSQHZ
tQSVLD
tMRSC
tAS/tCS
tDS
tAH/tCH
tDH
-3.3
MIN MAX
MIN
MAX
MIN
MAX
UNITS
3.3
0.45
0.45
2.3
0.4
0.4
4.0
0.45
0.45
2.3
0.4
0.4
0.55
0.55
3.7
0.6
0.6
5.0
0.45
0.45
2.3
0.4
0.4
0.55
0.55
3.7
0.6
0.6
tCK
0.3
ns
ns
ns
tCK
-0.3
0.4
-0.4
4
0.55
0.55
3.7
0.6
0.6
0.3
0.4
-4
-0.3
0.4
-0.4
4
-5
0.3
0.4
-0.3
0.4
-0.4
4
NOTES
ns
0.4
tCK
ns
1
tCK
tCK
1.0
0.5
1.0
0.5
1.0
0.5
ns
ns
1.0
0.5
1.0
0.5
1.0
0.5
ns
ns
2
3
4
All timing parameters are referenced to VREF or to the signal crossing points for different signals.
Parameter only valid within one DQS/DQ group, e.g., DQS0, DQS0# and DQ0–DQ7; DQS1, DQS1# and DQ8–DQ15.
The rising and falling edges of DVLD are referenced to falling edges of DQS.
In Matched Impedance Mode, TBD cycles are required.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
GENERAL OVERVIEW AND TIMING DEFINITION
(BL2/WL2)
1
2
3
4
5
6
7
8
9
CK/CK#
tCKH
tCKL
tCK
tCS
tCH
tAS
tAH
CS#, AS#,
REF#
WE#
A[19:0]
BA[2:0]
DM[1:0]
tCKDQS
DQS[3:0]#
DQS[3:0]
tQSVLD
tQSVLD
DVLD
tQSQ
DQ
Q0a
tQSQH Z
Q0b
Q1a
Q1b
tDS
D0a
tDH
D0b
D1a
D1b
NOTE: 1. Address A[19:0] and commands CS#, AS#, WE#, REF# are referenced to the rising edge of the clock CK.
2. Input Data DQ is referenced to the rising or falling edge of the clock.
3. DVLD is referenced to the falling edge of DQS.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
READ TIMING
(BL = 2)
1
2
3
4
5
7
6
8
9
CK/CK#
CS#, AS#, REF#
A[19:0], BA[2:0]
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RB0
RL = 5 tCK
tRC = 8 tCK
DQS,
DQS#
DVLD
initial
Q0a
DQ
NOTE: 1.
2.
3.
4.
Q0a
Q0b
Q1a
Q1b
Q2a
Q2b
Q3a
Q3b
Starting with all banks closed, 8 banks cyclic access.
2-bit prefetch, BL = 2.
Read latency (RL) programmable.
CS# = 1 deactivates command inputs. DQS and DQS# not affected.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
READ TIMING
(BL = 4)
1
2
3
4
5
7
6
8
9
CK/CK#
CS#, AS#, REF#,
A[18:0], BA[2:0]
RB0
RB1
RB3
RB4
RB0
RL = 5 tCK
tRC = 8 tCK
DQS,
DQS#
DVLD
initial
DQ
NOTE: 1.
2.
3.
4.
Q0a
Q0a
Q0b
Q0c
Q0d
Q1a
Q1b
Q1c
Q1d
Starting with all banks closed, 4 bank cyclic access.
4 bit prefetch, BL = 4.
Read latency (RL) programmable.
CS# = 1 deactivates command inputs. DQS not affected.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE TIMING
(BL = 2, RL = 6)
1
2
3
4
5
7
6
8
9
CK/CK#
CS#, AS#,
REF#, A[19:0],
BA[2:0], DM[1:0]
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
WB0
tRC = 8 tCK
DQ
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
D5a
D5b
D6a
D6b
NOTE: 1. DQS and DQS# are not relevant during WRITE cycles.
2. Starting with all banks closed, 8 banks cyclic access.
3. Write latency WL = RL - BL/2 - 2 = 3.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE TIMING
(BL = 4, RL = 6)
1
2
3
4
5
7
6
8
9
CK/CK#
CS#, AS#, REF#,
A[18:0], BA[2:0],
DM[1:0]
WB0
WB1
WB2
WB3
WB0
tRC = 8 tCK
DQ
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
D3a
D3b
D3c
D3d
NOTE: 1. DQS and DQS# are not relevant during WRITE cycles.
2. Starting with all banks closed, 4 banks cyclic access.
3. Write latency WL = RL - BL/2 - 2 = 2.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
READ TO WRITE TIMING
(BL = 2, WL = 2)
Last READ
command 1
2
3
4
5
Earliest WRITE
command
7
6
8
9
CK/CK#
CS#, AS#, REF#,
A[19:0], BA[2:0],
DM[1:0]
RB3
NOP
NOP
NOP
NOP
WB4
NOP
RL = 5 tCK
DQS,
DQS#
DQ
Q0a
Q0b
Q1a
Q1b
Q2a
Q2b
Q3a
Q3b
D4a
D4b
Prevent bus
contention
NOTE: 1. In order to avoid bus contention from a READ to a WRITE the proper number of clock cycles has to be inserted.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE TO READ TIMING
(BL = 2, WL = 2)
Last WRITE
command
1
2
3
4
5
6
7
8
9
CK/CK#
CS#, AS#, REF#,
A[19:0], BA[2:0],
DM[1:0]
WB3
RB4
RB5
RL = 5 tCK
tRC = 8 tCK
DQS,
DQS#
DQ
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
D3a
D3b
Q4a
29
Q4b
Q5a
Q5b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
REFRESH TIMING
CK/CK#
CS#, AS#, RB5
REF#
RB6
RB7
RF0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RF0
RB1
RB2
RB3
RB4
RB5
DQS,
DQS#
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
RL = 5 tCK
tRC = 8 tCK
tRFC = tRC
NOTE: 1. Bank scheduled refresh.
2. Refresh cycle to be issued on closed bank.
3. Bank address from controller, row address generated internally.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
EXAMPLE OF REFRESH IMPLEMENTATION
(Cyclic Bank Burst Refresh)
CLK/CLK#
CMD/ADR
RF0
RF1
RF2
RF3
RF4
RF5
RF6
RF7
RF0
RF1
RF2
RF3
RF4
RF5
RF6
RF7
3.9µs
NOTE: 1. Cyclic Burst refresh on all Banks.
2. Each Refresh command on the next Bank is asserted on the next clock rising edge.
3. Cycle for a burst refresh: 32ms/8192 = 3.9µs.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE DATA MASK TIMING
(BL = 2, WL = 2)
CK/CK#
CMD
WR0
DQ
WR1
WR2
D0a
WR3
D0b
D1a
WR4
D1b
D2a
D2b
D3a
D3b
D4a
D4b
D4a
D4b
DM0
DM1
tAS
tAH
WR DATA
D0a
D0b
D1b
D2a
NOTE: 1. Shaded WR Data is not written into the memory.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE DATA MASK TIMING
(BL = 4, WL = 1)
CK/CK#
CMD
WR0
DQ
WR1
D0a
D0b
D0c
WR2
D0d
D1a
D1b
D1c
WR3
D1d
D2a
D2b
D2a
D2b
D2c
D2d
D3a
D3b
D3c
D3d
DM0
DM1
tAS
tAH
WR DATA
D0a
D0b
D0c
D0d
D1c
D1d
NOTE: 1. Shaded WR Data is not written into the memory.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE/READ AND READ/WRITE TIMING, CYCLIC BANK ACCESS
(RL = 6, BL = 2, WL = 3)
CK/CK#
CMD
WB7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RB0
RB1
DQS
tCKDQS
DQ
D4a
D4b
D5a
D5b
D6a
D6b
D7a
D7b
Q0a
Q0b
Q1a
Q1b
Q2a
tCKDQS
CMD
RB0
NOP
NOP
NOP
NOP
NOP
WB1
WB2
WB3
WB4
WB5
DQS
DQ
Q1a
Q1b
Q2a
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Q2b
Q3a
Q3b
Q4a
Q4b
Q5a
Q5b
34
Q6a
Q6b
Q7a
Q7b
Q7a
Q7b
D1a
D1b
D2a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE/READ AND READ/WRITE TIMING, CYCLIC BANK ACCESS
(RL = 5, BL = 2, WL = 2)
CK/CK#
CMD
WB7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RB0
RB1
DQS
tCKDQS
DQ
D5a
D5b
D6a
D6b
D7a
D7b
Q0a
Q0b
Q1a
Q1b
Q2a
Q3b
Q3a
tCKDQS
CMD
RB0
NOP
NOP
NOP
NOP
NOP
WB1
WB2
WB3
WB4
WB5
DQS
DQ
Q2a
Q2b
Q3a
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Q3b
Q4a
Q4b
Q5a
Q5b
Q6a
Q6b
35
Q7a
Q7b
Q0a
Q0b
D1a
D1b
D2a
D2b
D3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE/READ AND READ/WRITE TIMING, CYCLIC BANK ACCESS
(RL = 6, BL = 4, WL = 2)
CK/CK#
CMD
WB7
RB0
NOP
RB1
NOP
RB2
NOP
RB3
NOP
RB4
NOP
DQS
tCKDQS
DQ
D6a
D6b
D6c
D6d
D7a
D7b
D7c
D7d
Q0a
Q0b
Q0c
Q0d
Q1a
tCKDQS
CMD
RB0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WB1
NOP
WB2
DQS
DQ
Q4c
Q4d
Q5a
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Q5b
Q5c
Q5d
Q6a
Q6b
Q6c
Q6d
36
Q7a
Q7b
Q7c
Q7d
Q0a
Q0b
Q0c
Q0d
D1a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE/READ AND READ/WRITE TIMING, CYCLIC BANK ACCESS
(RL = 5, BL = 4, WL = 1)
CK/CK#
CMD
WB7
RB0
NOP
RB1
NOP
RB2
NOP
RB3
NOP
RB4
NOP
DQS
tCKDQS
DQ
D6c
D6d
D7a
D7b
D7c
D7d
Q0a
Q0b
Q0c
Q0d
Q1a
Q1b
Q1c
tCKDQS
CMD
RB0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WB1
NOP
WB2
DQS
DQ
Q5a
Q5b
Q5c
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Q5d
Q6a
Q6b
Q6c
Q6d
Q7a
Q7b
37
Q7c
Q7d
Q0a
Q0b
Q0c
Q0d
D1a
D1b
D1c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
RANDOM ACCESS, SINGLE BANK
(RL = 6, BL = 2, WL = 3)
CK
CMD
WB0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WB0
NOP
NOP
NOP
NOP
NOP
NOP
RB0
NOP
NOP
WB0
NOP
NOP
RB0
NOP
NOP
DQS
DQ
CMD
D0a
RB0
NOP
NOP
D0b
NOP
DQS
tCKDQS
DQ
CMD
Q0a
RB0
NOP
NOP
NOP
NOP
NOP
NOP
Q0b
NOP
DQS
DQ
CMD
Q0a
WB0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Q0b
DQS
DQ
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
D0a
D0b
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
RANDOM ACCESS, SINGLE BANK
(RL = 5, BL = 2, WL = 2, tRC = 6)
CK
CMD
WB0
NOP
NOP
NOP
NOP
NOP
WB0
NOP
NOP
NOP
NOP
DQS
DQ
CMD
D0a
RB0
NOP
D0b
NOP
D0a
NOP
NOP
NOP
RB0
D0b
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
tCKDQS
DQ
CMD
Q0a
RB0
NOP
NOP
NOP
NOP
NOP
Q0b
WB0
DQS
DQ
CMD
Q0a
WB0
NOP
NOP
NOP
NOP
NOP
RB0
Q0b
D0a
NOP
NOP
D0b
DQS
DQ
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
D0a
D0b
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
RANDOM ACCESS, SINGLE BANK
(RL = 6, BL = 4, WL = 2)
CK
CMD
WB0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WB0
NOP
NOP
DQS
DQ
CMD
D0a
RB0
NOP
D0b
NOP
D0c
D0d
NOP
D0a
NOP
NOP
NOP
NOP
RB0
NOP
NOP
NOP
NOP
DQS
tCKDQS
DQ
CMD
Q0a
RB0
NOP
NOP
NOP
NOP
NOP
NOP
Q0b
NOP
Q0c
Q0d
WB0
DQS
DQ
CMD
Q0a
WB0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Q0b
Q0c
RB0
Q0d
D0a
NOP
NOP
DQS
DQ
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
D0a
D0b
D0c
D0d
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
RANDOM ACCESS, SINGLE BANK
(RL = 5, BL = 4, WL = 1, tRC = 6)
CK
CMD
WB0
NOP
NOP
NOP
NOP
NOP
WB0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WB0
NOP
NOP
DQS
DQ
CMD
D0a
RB0
D0b
NOP
D0c
D0d
NOP
D0a
NOP
NOP
NOP
RB0
D0b
NOP
D0c
D0d
DQS
tCKDQS
DQ
CMD
Q0a
RB0
NOP
NOP
NOP
NOP
NOP
Q0b
NOP
Q0c
Q0d
NOP
DQS
DQ
CMD
Q0a
WB0
NOP
NOP
NOP
NOP
NOP
RB0
Q0b
Q0c
NOP
Q0d
D0a
NOP
NOP
D0b
D0c
NOP
DQS
DQ
D0a
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
D0b
D0c
D0d
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
144-BALL T-FBGA
0.850 ±0.075
0.155 ±0.013
SEATING PLANE
C
0.10 C
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 37% Pb, 2%Ag
SOLDER BALL PAD: Ø .33mm
SUBSTRATE: PLASTIC LAMINATE
8.80
144X Ø .45 TYP
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE
PRE-REFLOW DIAMETER
IS Ø 0.40
0.80
(TYP)
2.20 ±0.05
CTR
BALL A1
MOLD COMPOUND: EPOXY NOVOLAC
PIN A1 ID
PIN A1 ID
BALL A12
9.25 ±0.05
18.50 ±0.10
CL
17.00
1.00
(TYP)
8.50 ±0.05
4.40 ±0.05
CL
5.50 ±0.05
1.20 MAX
11.00 ±0.10
NOTE: 1. All dimensions in millimeters.
DATA SHEET DESIGNATION
Advance: This data sheet contains initial descriptions of products still under development.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
REVISION HISTORY
Rev. 3, Advance ................................................................................................................................................................... 6/02
• Removed confidential mark
Rev. 2, Advance ................................................................................................................................................................... 2/02
•?
•?
Original document, Advance .......................................................................................................................................... 12/01
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.