4 MEG x 16 EDO DRAM DRAM MT4LC4M16R6, MT4LC4M16N3 For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/dramds.html FEATURES PIN ASSIGNMENT (Top View) • Single +3.3V ±0.3V power supply • Industry-standard x16 pinout, timing, functions, and package • 12 row, 10 column addresses (R6) 13 row, 9 column addresses (N3) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention OPTIONS 50-Pin TSOP VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC VCC WE# RAS# NC NC NC NC A0 A1 A2 A3 A4 A5 VCC MARKING • Plastic Package 50-pin TSOP (400 mil) TG • Timing 50ns access 60ns access -5 -6 • Refresh Rates 4K 8K Standard Refresh Self Refresh R6 N3 None S* • Operating Temperature Range Commercial (0°C to +70°C) †A12 NOTE: 1. The “#” symbol indicates signal is active LOW. VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC VSS CASL# CASH# OE# NC NC NC/A12† A11 A10 A9 A8 A7 A6 VSS for N3 version, NC for R6 version. Configuration Refresh Row Address Column Addressing None 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 MT4LC4M16R6 MT4LC4M16N3 4 Meg x 16 4K 4K (A0-A11) 1K (A0-A9) 4 Meg x 16 8K 8K (A0-A12) 512 (A0-A8) *Contact factory for availability. Part Number Example: 4 MEG x 16 EDO DRAM PART NUMBERS MT4LC4M16R6TG-5 PART NUMBER MT4LC4M16R6TG-x MT4LC4M16R6TG-x S MT4LC4M16N3TG-x MT4LC4M16N3TG-x S KEY TIMING PARAMETERS SPEED -5 -6 tRC 84ns 104ns 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 tRAC 50ns 60ns tPC 20ns 25ns tAA 25ns 30ns tCAC tCAS 13ns 15ns 8ns 10ns REFRESH ADDRESSING PACKAGE REFRESH 4K 4K 8K 8K 400-TSOP Standard 400-TSOP Self 400-TSOP Standard 400-TSOP Self x = speed 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM FUNCTIONAL BLOCK DIAGRAM MT4LC4M16R6 (12 row addresses) WE# CASL# CAS# 16 DATA-IN BUFFER CASH# DQ0DQ15 16 DATA-OUT BUFFER NO. 2 CLOCK GENERATOR OE# 16 10 COLUMNADDRESS BUFFER(10) 16 COLUMN DECODER 10 1,024 REFRESH CONTROLLER A0A11 SENSE AMPLIFIERS I/O GATING 1,024 x 16 12 4,096 4,096 x 16 ROW SELECT 12 ROW DECODER 12 ROWADDRESS BUFFERS (12) COMPLEMENT SELECT REFRESH COUNTER 4,096 x 1,024 x 16 MEMORY ARRAY NO. 1 CLOCK GENERATOR RAS# VDD VSS FUNCTIONAL BLOCK DIAGRAM MT4LC4M16N3 (13 row addresses) WE# CASL# CAS# 16 DATA-IN BUFFER CASH# DQ0DQ15 16 DATA-OUT BUFFER NO. 2 CLOCK GENERATOR OE# 16 9 COLUMNADDRESS BUFFER(9) 16 COLUMN DECODER 9 512 REFRESH CONTROLLER A0A12 SENSE AMPLIFIERS I/O GATING 512 x 16 RAS# 13 8192 NO. 1 CLOCK GENERATOR 8192 x 16 ROW SELECT 13 ROW DECODER 13 ROWADDRESS BUFFERS (13) COMPLEMENT SELECT REFRESH COUNTER 8192 x 512 x 16 MEMORY ARRAY Vcc Vss 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM GENERAL DESCRIPTION the last to transition back HIGH. The CAS# functionality and timing related to driving or latching data is such that each CAS# signal independently controls the associated eight DQ pins. The row address is latched by the RAS# signal, then the column address is latched by CAS#. This device provides EDO-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE or READMODIFY-WRITE) within a given row. The 4 Meg x 16 DRAM must be refreshed periodically in order to retain stored data. The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns on the MT4LC4M16R6 or 8,192 rows by 512 columns on the MT4LC4M16N3. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 row-address bits (A0-A11) and 10 column-address bits (A0-A9) on the MT4LC4M16R6 or 13 row-address bits (A0-A12) and 9 column-address bits (A0-A8) on the MT4LC4M16N3 version. In addition, both byte and word accesses are supported via the two CAS# pins (CASL# and CASH#). The CAS# functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) is such that the internal CAS# signal is determined by the first external CAS# signal (CASL# or CASH#) to transition LOW and DRAM ACCESS Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS# signals results in a word access via the 16 I/O pins (DQ0-DQ15). Using only one of the two signals results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for WORD WRITE LOWER BYTE WRITE RAS# CASL# CASH# WE# LOWER BYTE (DQ0-DQ7) OF WORD UPPER BYTE (DQ8-DQ15) OF WORD STORED DATA 1 INPUT DATA 0 1 0 1 STORED DATA 0 STORED DATA 0 INPUT DATA 1 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 0 1 X X 1 0 1 0 1 0 X X 1 0 0 1 X X X 1 0 1 1 0 1 1 0 1 X X X 1 0 1 X X 1 1 X 1 1 1 1 1 1 1 X X X 1 1 1 0 0 0 0 INPUT DATA ADDRESS 0 INPUT DATA STORED DATA 1 ADDRESS 1 X = NOT EFFECTIVE (DON'T CARE) Figure 1 WORD and BYTE WRITE Example 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM DRAM ACCESS (continued) the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READMODIFY-WRITE occurs when WE falls after CAS# (CASL# or CASH#) is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READ-MODIFYWRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no write will occur, and the data outputs will drive read data from the accessed location. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. EDO PAGE MODE DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. If CAS# went HIGH and OE# was LOW (active), the output buffers would be disabled. The 64Mb EDO DRAM offers an accelerated page mode cycle by eliminating output disable from CAS# HIGH. This option is called EDO, and it allows CAS# precharge time (tCP) to occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms). EDO operates like any DRAM READ or FAST-PAGEMODE READ, except data is held valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW and WE# is held HIGH. OE# can be brought LOW or HIGH while CAS# and RAS# are LOW, and the DQs will transition between valid data and High-Z. Using OE#, there are WORD READ LOWER BYTE READ RAS# CASL# CASH# WE# LOWER BYTE (DQ0-DQ7) OF WORD UPPER BYTE (DQ8-DQ15) OF WORD STORED DATA 1 OUTPUT DATA 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 OUTPUT DATA 1 1 0 1 1 1 1 STORED DATA 1 1 0 1 1 STORED DATA OUTPUT DATA 1 OUTPUT DATA 1 STORED DATA 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 Z Z 0 1 0 1 0 1 Z Z Z Z 0 1 Z Z Z 0 1 0 0 1 0 0 1 0 Z Z Z Z Z Z 0 1 0 Z Z Z 0 0 0 0 0 0 0 0 0 Z Z Z Z Z Z 0 0 0 ADDRESS 0 ADDRESS 1 Z = High-Z Figure 2 WORD and BYTE READ Example 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM RAS# V IH V IL CAS# V IH V IL ADDR V IH V IL ROW DQ V IOH V IOL COLUMN (A) OPEN COLUMN (B) VALID DATA (A) VALID DATA (A) VALID DATA (C) VALID DATA (D) tOD tOD tOES OE# COLUMN (D) VALID DATA (B) tOD V IH V IL COLUMN (C) tOEHC tOE tOEP The DQs go back to Low-Z if tOES is met. The DQs remain High-Z until the next CAS# cycle if tOEHC is met. The DQs remain High-Z until the next CAS# cycle if tOEP is met. Figure 3 OE# Control of DQs RAS# V IH V IL CAS# V IH V IL ADDR V IH V IL DQ V IOH V IOL ROW COLUMN (A) OPEN COLUMN (B) COLUMN (C) VALID DATA (A) VALID DATA (B) V IH V IL OE# V IH V IL INPUT DATA (C) tWHZ tWHZ WE# COLUMN (D) tWPZ The DQs go to High-Z if WE# falls and, if tWPZ is met, will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated). WE# may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated). DON’T CARE UNDEFINED Figure 4 WE# Control of DQs 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM EDO PAGE MODE (continued) rows for N3 or 4,096 rows for R6). The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC4M16N3 internally refreshes two rows for each CBR cycle, whereas the MT4LC4M16R6 refreshes one row for every CBR cycle. For either device, executing 4,096 CBR cycles will refresh the entire device. The CBR REFRESH will invoke the internal refresh counter for automatic RAS# addressing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method, only one row is refreshed on each cycle. Thus, 8,192 RAS-only REFRESH cycles are needed every 64ms on the MT4LC4M16N3 in order to refresh the entire device. JEDEC strongly recommends the use of CBR REFRESH for this device. An optional self refresh mode is also available on the “S” version. The self refresh feature is initiated by performing a CBR Refresh cycle and holding RAS# low for the specified tRASS. The “S” option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 31.25µs per cycle, when using a distributed CBR refresh. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh, however, if the controller is using RAS# only or burst CBR refresh then a burst refresh using tRC (MIN) is required. two methods to disable the outputs and keep them disabled during the CAS# HIGH time. The first method is to have OE# HIGH when CAS# transitions HIGH and keep OE# HIGH for tOEHC thereafter. This will disable the DQs, and they will remain disabled (regardless of the state of OE# after that point) until CAS# falls again. The second method is to have OE# LOW when CAS# transitions HIGH and then bring OE# HIGH for a minimum of tOEP anytime during the CAS# HIGH period. This will disable the DQs, and they will remain disabled (regardless of the state of OE# after that point) until CAS# falls again (see Figure 3). During other cycles, the outputs are disabled at tOFF time after RAS# and CAS# are HIGH or at tWHZ after WE# transitions LOW. The tOFF time is referenced from the rising edge of RAS# or CAS#, whichever occurs last. WE# can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 4. EDO-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the EDO-PAGE-MODE operation. DRAM REFRESH The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all rows in the 4 Meg x 16 DRAM array at least once every 64ms (8,192 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VCC Relative to VSS ................ -1V to +4.6V Voltage on NC, Inputs or I/O Pins Relative to VSS ....................................... -1V to +4.6V Operating Temperature, TA (ambient) Commercial ......................................... 0°C to +70°C Storage Temperature (plastic) ........... -55°C to +150°C Power Dissipation ................................................... 1W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Note: 1) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SUPPLY VOLTAGE VCC 3 3.6 V INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC VIH 2 VCC + 0.3 V 35 INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC VIL -0.3 0.8 V 35 II -2 2 µA 36 OUTPUT HIGH VOLTAGE: IOUT = -2mA VOH 2.4 – V OUTPUT LOW VOLTAGE: IOUT = 2mA VOL – 0.4 V IOZ -5 5 µA INPUT LEAKAGE CURRENT: Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); All other pins not under test = 0V OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V); DQ is disabled and in High-Z state 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 7 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM Icc OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 6; notes appear on page 11) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION MAX SYMBOL SPEED 4K 8K ICC1 ALL 1 1 mA ICC2 ALL 500 500 µA OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC3 -5 -6 150 165 115 130 mA 26 OPERATING CURRENT: EDO PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) ICC4 -5 -6 120 125 120 125 mA 26 REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) ICC5 -5 -6 150 165 115 130 mA 22 REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC6 -5 -6 150 165 150 165 mA 4, 7, 23 REFRESH CURRENT: Extended (“S” version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A10, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open); tRC = 125µs ICC7 ALL 400 400 µA 4, 7, 23, 37 REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with RAS# ≥ tRASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V; A0-A10, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) ICC8 ALL 350 350 µA 4, 7, 37 STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (RAS# = CAS# ≥ VCC - 0.2V; DQs may be left open; Other inputs: VIN ≥ VCC - 0.2V or VIN ≤ 0.2V) 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 8 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM CAPACITANCE (Note: 2; notes appear on page 11) PARAMETER SYMBOL MAX UNITS Input Capacitance: Address pins CI1 5 pF Input Capacitance: RAS#, CAS#, WE#, OE# CI2 7 pF Input/Output Capacitance: DQ CIO 7 pF NOTES AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes appear on page 11) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Access time from column address Column-address setup to CAS# precharge Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) Last CAS# going LOW to first CAS# to return HIGH CAS# to output in Low-Z Data output hold after CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 -5 -6 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLCH tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH MIN 8 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tOEHC 5 5 4 0 0 10 5 5 0 0 ns ns ns ns ns tOEP tOES tOFF tORD 9 MAX 25 12 38 0 0 42 MIN 15 45 0 0 49 13 8 8 15 8 5 0 3 8 10,000 15 10 10 15 10 5 0 3 10 28 5 38 5 28 8 8 0 0 MAX 30 12 12 12 10,000 35 5 45 5 35 10 10 0 0 15 15 15 28 28 18 29 28 30, 32 4, 31 31 29 13, 33 29 31 31 4, 28 18, 28 31 19, 29 19, 29 24, 25 20 25 17, 24, 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes appear on page 11) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period Refresh period (“S” version) RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WE# to outputs in High-Z WRITE command pulse width WE# pulse widths to disable outputs WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 -5 SYMBOL tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP 10 MIN 20 47 -6 MAX MIN 25 56 50 9 7 50 50 100 84 11 0 0 10,000 125,000 60 12 10 60 60 100 104 14 0 0 64 128 30 5 90 0 13 116 67 13 2 8 38 0 50 10,000 125,000 64 128 40 5 105 0 15 140 79 15 2 10 45 0 12 5 10 8 8 MAX 50 15 5 10 10 10 UNITS ns ns ns ns ns ns ns µs ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 34 34 15 14, 28 16, 30 28 22, 23 23 16 35 18 35 18, 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM NOTES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 18. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, tAWD, and tCWD define READMODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. OE# held HIGH and WE# taken LOW after CAS# goes LOW results in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD, and tAWD are not applicable in a LATE WRITE cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not possible. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 22. RAS#-ONLY REFRESH requires that all 8,192 rows of the MT4LC4M16N3 or all 4,096 rows of the MT4LC4M16R6 be refreshed at least once every 64ms. 23. CBR REFRESH for either device requires that at least 4,096 cycles be completed every 64ms. 24. The DQs go High-Z during READ cycles once tOD or tOFF occur. If CAS# stays LOW while OE# is brought HIGH, the DQs will go High-Z. If OE# is brought back LOW (CAS# still LOW), the DQs will provide the previously read data. 25. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE# is taken back LOW while CAS# remains LOW, the DQs will remain open. 26. Column address changed once each cycle. 27. The first CASx# edge to transition LOW. All voltages referenced to VSS. This parameter is sampled. VCC = +3.3V; f = 1 MHz; TA = 25°C. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. An initial pause of 100µs is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 2.5ns. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. If CAS# and RAS# = VIH, data output is High-Z. If CAS# = VIL, data output may contain data from the last valid READ cycle. Measured with a load equivalent to two TTL gates and 100pF; and VOL = 0.8V and VOH = 2V. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM NOTES (continued) 28. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 29. Each CASx# must meet minimum pulse width. 30. The last CASx# edge to transition HIGH. 31. Last falling CASx# edge to first rising CASx# edge. 32. Last rising CASx# edge to first falling CASx# edge. 33. Last rising CASx# edge to next cycle’s last rising CASx# edge. 34. Last CASx# to go LOW. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 35. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width £ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width £ 3ns, and the pulse width cannot be greater than one third of the cycle rate. 36. NC pins are assumed to be left floating and are not tested for leakage. 37. Self refresh and extended refresh for either device requires that at least 4,096 cycles be completed every 128ms. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM READ CYCLE tRC tRP tRAS RAS# V IH V IL tCSH tRSH tRCD tCRP CAS# tRRH tCAS V IH V IL tAR tRAD tRAH tASR tASC tCAH tACH ADDR V IH V IL ROW ROW COLUMN tRCH tRCS WE# V IH V IL tAA tRAC NOTE 1 tOFF tCAC tCLZ DQ V OH V OL OE# V IH V IL OPEN OPEN VALID DATA tOE tOD DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH -6 12 15 45 0 ns ns tRAC tASC 38 0 tRAD 9 tASR 0 ns ns ns tRAH 7 50 84 ns ns tRCD ns ns tRCS ns ns tRRH tCAC 8 tCAS 8 5 tCLZ tCRP tCSH tOD MIN 15 10 10,000 0 5 38 0 MAX 30 0 13 tCAH tCLCH MAX 25 -5 UNITS ns ns tAR MIN 10 5 10,000 0 5 12 45 0 15 SYMBOL tOE tOFF tRAS tRC tRCH tRP tRSH MIN 0 -6 MAX 12 12 MIN 0 50 MAX 15 15 UNITS ns ns 60 ns ns 12 10,000 10 60 104 10,000 ns ns ns 11 0 14 0 ns ns 0 30 0 40 ns ns 0 13 0 15 ns ns NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM EARLY WRITE CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tCRP CAS# tRCD tCAS V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH tACH ROW COLUMN tCWL tRWL tWCR tWCH tWCS tWP WE# V IH V IL tDS V DQ V IOH IOL OE# tDH VALID DATA V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH tAR tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL tDH tDS 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 MIN -6 MAX MIN -5 MAX UNITS SYMBOL tRAD tRAH 12 38 15 45 ns ns 0 0 8 0 0 10 ns ns ns tRAS ns ns tRP 8 5 10,000 10 5 10,000 tRC tRCD tRSH 5 38 8 5 45 10 ns ns ns tRWL 8 0 10 0 ns ns tWCS tWCH tWCR tWP 14 -6 MIN 9 7 MAX MIN 12 10 MAX UNITS ns ns 50 84 10,000 60 104 10,000 ns ns 11 30 13 14 40 15 ns ns ns 13 8 15 10 ns ns 38 0 5 45 0 5 ns ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRWC tRAS RAS# V IH V IL tCRP CAS# tCSH tRSH tCAS tRCD V IH V IL tAR tRAD tRAH tASR ADDR tRP V IH V IL tASC tCAH ROW COLUMN tRCS WE# tACH ROW tRWD tCWD tCWL tRWL tAWD tWP V IH V IL tAA tRAC tCAC tDS tCLZ V DQ V IOH IOL VALID D OUT OPEN tOE OE# tDH VALID D IN tOD OPEN tOEH V IH V IL DON’ T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tACH tAR tASC tASR tAWD tCWL tDH 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 30 tDS 0 0 0 0 ns ns tOEH ns ns ns tRAD ns ns tRCD 42 49 13 8 tCWD SYMBOL 15 45 8 5 tCSH UNITS 12 38 tCAS tCRP -5 MAX ns ns ns tCAH tCLZ MIN 25 tCAC tCLCH -6 MAX 15 10 10,000 10 5 10,000 tOD MIN 0 0 tOE tRAS tRCS 0 5 38 0 5 45 ns ns ns tRP 28 8 35 10 ns ns tRWD 8 10 ns tWP tRSH tRWC tRWL 15 12 12 8 tRAC tRAH -6 MAX MIN 0 0 UNITS 15 15 ns ns ns 60 ns ns 10,000 ns ns ns 10 50 9 7 50 MAX 10,000 12 10 60 11 0 14 0 ns ns 30 13 116 40 15 140 ns ns ns 67 13 79 15 ns ns 5 5 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM EDO-PAGE-MODE READ CYCLE tRASP tRP V IH V IL RAS# tCSH tCRP tRCD tPC tCP tCAS tCAS tRSH tCAS tCP tCP V IH V IL CAS# tAR tRAD tRAH tASR V IH V IL ADDR ROW tACH tACH tACH tASC tCAH tASC COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRCS tRCH V IH V IL WE# tAA tRAC tAA tCPA tCAC tCAC DQ V OH V OL VALID DATA OPEN tOFF tOEHC VALID DATA tOE OE# tCAC tCLZ tCOH tCLZ VALID DATA OPEN tOE tOD tOES V IH V IL tRRH tAA tCPA tOD tOES tOEP DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH -5 -6 12 15 45 0 ns ns tOEP tASC 38 0 tASR 0 0 ns ns ns tOFF ns ns tRAD ns ns ns tRASP tRCS tRRH tCAC 8 tCAS 8 5 tCLZ tCOH tCP MIN 13 tCAH tCLCH MAX 25 15 10 10,000 0 3 8 tCPA MAX 30 SYMBOL tOE UNITS ns ns tAR MIN 10 5 10,000 0 3 10 tCRP 5 5 ns ns tCSH 38 0 45 0 ns ns tOD 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 28 12 35 15 tOEHC tOES tPC MIN 5 5 4 0 20 tRAC tRAH tRCD tRCH tRP tRSH 16 -6 MAX 12 MIN 10 5 5 12 0 25 50 9 7 50 11 MAX 15 ns ns ns 15 ns ns 60 ns ns ns 125,000 ns ns 12 10 125,000 60 14 UNITS ns 0 0 30 0 0 40 ns ns ns 0 13 0 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM EDO-PAGE-MODE EARLY WRITE CYCLE t RP t RASP RAS# V IH V IL t CSH t PC t CRP CAS# t RCD t CAS t RSH t CP t CAS t CP t CAS t CP V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAH tACH t ASC ROW t ACH t CAH t ASC COLUMN t WCH t WCS t CAH COLUMN t CWL ROW t CWL t WCH t WP WE# t ASC COLUMN t CWL t WCS t ACH t CAH t WCS t WP t WCH t WP V IH V IL t WCR t DS V DQ V IOH IOL t DH t DS VALID DATA t DH t DS VALID DATA t RWL t DH VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH tAR tASC tASR tCAH tCAS tCLCH tCP tCRP tCSH tCWL tDH tDS 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 MIN -6 MAX 12 38 0 0 8 8 MIN -5 MAX 15 45 0 0 10,000 10 10 10,000 UNITS SYMBOL ns ns ns ns tPC ns ns tRCD tRAD 7 tRASP 50 11 30 tRP 5 10 5 ns ns ns tRSH 38 8 45 10 ns ns tWCR 8 0 10 0 ns ns tWP tRWL tWCH tWCS -6 MAX 20 9 tRAH 5 8 5 17 MIN MIN MAX 25 12 ns ns 10 125,000 60 14 40 UNITS ns 125,000 ns ns ns 13 13 15 15 ns ns 8 38 0 10 45 0 ns ns ns 5 5 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP RAS# V IH V IL tCSH tCRP CASL#/CASH# tPRWC NOTE 1 tPC tRCD tCP tCAS tRSH tCP tCAS tCP tCAS V IH V IL tAR tRAD tRAH tASR ADDR tRP V IH V IL tASC tCAH ROW tASC COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRWD tRCS WE# tCWL tWP tAWD tCWD tAA tAA tDH tCPA tDS tCAC tCLZ V IOH V IOL tAA tDH tCAC tCLZ tOE tDS tCAC tCLZ VALID VALID D OUT D IN VALID VALID D OUT D IN VALID VALID D OUT D IN OPEN tDH tCPA tDS tOD OE# tWP tAWD tCWD V IH V IL tRAC DQ tRWL tCWL tCWL tWP tAWD tCWD tOD tOD tOE tOE OPEN tOEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR -6 MAX MIN 25 tASR 38 0 0 45 0 0 tAWD 42 49 tASC tCAC tCAH tCAS tCLCH tCLZ tCP 13 8 8 5 10,000 0 8 tCPA -5 MAX UNITS 30 ns ns ns ns 15 10 10 5 10,000 0 10 tOEH ns ns tPC ns ns ns tRAC ns ns tRASP tRCS tPRWC 7 50 11 5 tCSH 38 28 8 45 35 10 ns ns ns tRSH 8 10 ns tWP tDH tRP tRWD tRWL MIN 0 0 MAX 15 UNITS ns ns 15 ns 10 25 56 50 tRAH 5 12 8 20 47 9 tRCD -6 MAX 12 tRAD tCRP tCWL 35 MIN 0 0 tOE ns ns tCWD 28 SYMBOL tDS tOD ns ns ns 60 12 125,000 10 60 14 125,000 ns ns ns ns ns 0 30 0 40 ns ns 13 67 13 15 79 15 ns ns ns 5 5 ns NOTE: 1. tPC is for LATE WRITE cycles only. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RP t RASP RAS# V IH V IL t CSH tPC tCRP CAS# t RCD tRSH tPC t CP t CAS t CP t CAS t CP t CAS V IH V IL tAR tRAD tASR ADDR V IH V IL t ACH tRAH tASC tCAH t ASC COLUMN (A) ROW t CAH COLUMN (B) V IH V IL ROW tWCS tWCH tAA tAA tCPA tRAC tCAC tCAC tCOH DQ V IOH V IOL t CAH COLUMN (N) tRCH tRCS WE# tASC OPEN VALID DATA (A) t DS t DH t WHZ VALID DATA (B) VALID DATA IN tOE OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA -6 MAX MIN UNITS SYMBOL 30 tOE tACH 12 15 ns ns tAR 38 0 0 45 0 0 ns ns ns tRAC 15 ns ns tRASP 10,000 ns ns ns tRCH tRSH tASC tASR 25 -5 MAX tCAC 13 tCAH 8 tCAS 8 3 8 tCOH tCP tCPA 10 10,000 10 3 10 tCRP 5 5 ns ns tCSH tDH 38 8 45 10 ns ns tDS 0 0 ns 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 28 35 tPC -6 MAX MIN 12 20 9 tRAH 7 50 11 MAX UNITS 15 ns ns 60 ns ns 25 50 tRAD tRCD 12 125,000 10 60 14 125,000 ns ns ns 0 0 0 0 ns ns tWCH 30 13 8 40 15 10 ns ns ns tWCS 0 tRCS tRP tWHZ 19 MIN 0 12 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM READ CYCLE (with WE#-controlled disable) RAS# V IH V IL tCSH tRCD tCRP CASL#/CASH# tCAS tCP V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH tASC COLUMN COLUMN tRCS WE# tRCH tWPZ tRCS V IH V IL tAA tRAC tCAC tCLZ V DQ V OH OL tWHZ OPEN OPEN VALID DATA tOE OE# tCLZ tOD V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN 38 0 0 tCAC 8 tCAS 8 0 8 tCP tCRP tCSH 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 MIN 5 38 -5 MAX 30 45 0 0 13 tCAH tCLZ -6 MAX 25 15 10 10,000 10 0 10 5 45 10,000 UNITS ns SYMBOL tOD ns ns ns tOE ns ns tRAH ns ns ns tRCH ns ns tWPZ MAX MIN MAX 0 12 0 15 ns 15 60 ns ns 12 50 tRAC tRAD tRCD tRCS UNITS 9 7 11 12 10 14 ns ns ns 0 0 0 0 ns ns tWHZ 20 -6 MIN 12 10 15 10 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) tRC tRAS RAS# tRP V IH V IL tRPC tCRP CASL#/CASH# V IH V IL tASR ADDR V IH V IL tRAH ROW ROW V Q V OH OL OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP RAS# tRAS tRP NOTE 1 tRAS V IH V IL tRPC tCP CASL#/CASH# V IH V IL DQ V OH V OL tCSR tCSR tCHR OPEN tWRP WE# tRPC tCHR tWRH tWRP tWRH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR MIN -6 MAX MIN -5 MAX UNITS SYMBOL tRAS tRC 0 8 0 10 ns ns 10 5 5 ns ns ns tRP tCSR 8 5 5 tRAH 7 10 ns tWRP tCHR tCP tCRP tRPC tWRH MIN 50 84 -6 MAX 10,000 MIN 60 104 MAX 10,000 UNITS ns ns 30 5 40 5 ns ns 8 8 10 10 ns ns NOTE: 1. End of first CBR REFRESH cycle. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW) tRC tRAS tRP tRAS V IH V IL RAS# tCRP tRSH tRCD tCHR V IH V IL CASL#/CASH# tAR tRAD tASR V IH V IL ADDR tRAH tASC ROW tCAH COLUMN tAA tRAC tCAC tCLZ V IOH V IOL DQx tOFF OPEN VALID DATA OPEN tOD tOE V IH V IL OE# tORD DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC MIN -6 MAX 25 MIN 38 45 0 0 0 0 -5 MAX 30 UNITS ns ns SYMBOL tOE tOFF tORD tCAH 8 10 ns ns ns ns tCHR 8 0 10 0 ns ns tRAS ns ns tRP tASR tCAC tCLZ tCRP tOD 13 5 0 12 15 5 0 15 MIN 0 0 tRAC tRAD tRAH tRCD tRSH -6 MAX 12 12 MIN 0 0 50 9 7 50 11 30 13 MAX 15 15 60 12 10 10,000 60 14 10,000 40 15 UNITS ns ns ns ns ns ns ns ns ns ns NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) RAS# V IH V IL V IH V IL DQ V OH V OL WE# tRPS (( )) tRPC tCSR NOTE 2 tRPC (( )) tCP CASL#/ CASH# NOTE 1 tRASS tRP (( )) tCP tCHD (( )) (( )) (( )) tWRP OPEN tWRP tWRH tWRH (( )) (( )) V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tCHD tCLCH tCP tCSR tRASS MIN 15 5 8 5 100 -5 -6 MAX MIN 15 5 10 5 100 MAX SYMBOL tRP tRPC tRPS tWRH tWRP UNITS ns ns ns ns ns MIN 30 5 90 8 8 -6 MAX MIN 40 5 105 10 10 MAX UNITS ns ns ns ns ns NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 4 MEG x 16 EDO DRAM 50-PIN PLASTIC TSOP (400 mil) 21.04 20.88 .88 TYP 50 11.86 11.66 10.21 10.11 1 SEE DETAIL A 25 .80 TYP PIN #1 ID .18 .13 .45 .30 .25 .20 .05 GAGE PLANE .10 1.2 MAX .60 .40 DETAIL A .80 TYP NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. 4 Meg x 16 EDO DRAM D29_C.p65 – Rev. 2/01 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc.