MICRON MT8LDT864

4, 8 MEG x 64
DRAM SODIMMs
SMALL-OUTLINE
DRAM MODULE
MT4LDT464H (X)(S), MT8LDT864H (X)(S)
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/datasheets/datasheet.html
FEATURES
PIN ASSIGNMENT (Front View)
• JEDEC pinout in a 144-pin, small-outline, dual inline memory module (SODIMM)
• 32MB (4 Meg x 64) and 64MB (8 Meg x 64)
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Optional Self Refresh Mode (S)
• Serial presence-detect (SPD)
OPTIONS
144-Pin Small-Outline DIMM
(I-1; 32MB)
(I-2; 64MB)
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
MARKING
• Package
144-pin SODIMM (gold)
G
• Timing
50ns access
60ns access
-5
-6
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
None
X
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
None
S*
*Contact factory for availability
KEY TIMING PARAMETERS
FPM Operating Mode
SPEED
-5
-6
tRC
90ns
110ns
tRAC
50ns
60ns
tPC
30ns
35ns
tAA
25ns
30ns
tCAC
13ns
15ns
tRP
30ns
40ns
EDO Operating Mode
SPEED
-5
-6
tRC
tRAC
tPC
tAA
tCAC
tCAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
NOTE:
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
1
FRONT
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
CAS0#
CAS1#
VDD
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
DQ14
DQ15
VSS
RSVD
RSVD
RFU
VDD
RFU
WE#
RAS0#
NC
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
BACK
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
VSS
CAS4#
CAS5#
VDD
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
DQ45
DQ46
DQ47
VSS
RSVD
RSVD
RFU
VDD
RFU
RFU
NC
NC
PIN
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
FRONT
OE#
VSS
RSVD
RSVD
VDD
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VDD
A6
A8
VSS
A9
A10
VDD
CAS2#
CAS3#
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VDD
PIN
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
BACK
RFU
VSS
RSVD
RSVD
VDD
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VDD
A7
A11
VSS
NC (A12)
NC (A13)
VDD
CAS6#
CAS7#
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VDD
Symbols in parentheses are not used on these modules but
may be used for other modules in this product family. They
are for reference only.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
PART NUMBERS
CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles.
Returning RAS# HIGH terminates the FAST-PAGEMODE operation.
FPM Operating Mode
PART NUMBER
MT4LDT464HG-x
MT4LDT464HG-x S
MT8LDT864HG-x
MT8LDT864HG-x S
x = speed
CONFIGURATION
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
REFRESH
Standard
Self
Standard
Self
CONFIGURATION
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
REFRESH
Standard
Self
Standard
Self
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” option,
is an accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out
even after CAS# goes back HIGH. EDO provides for
CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS#
output control provides for pipelined READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO operates as any DRAM READ or
FAST-PAGE-MODE READ, except data will be held
valid after CAS# goes HIGH, as long as RAS# and OE#
are held LOW and WE# is held HIGH. (Refer to the 8
Meg x 8 EDO DRAM data sheet for additional information on EDO functionality.)
EDO Operating Mode
PART NUMBER
MT4LDT464HG-x X
MT4LDT464HG-x XS
MT8LDT864HG-x X
MT8LDT864HG-x XS
x = speed
GENERAL DESCRIPTION
The MT4LDT464H (X)(S) and MT8LDT864H (X)(S)
are randomly accessed 32MB and 64MB memories
organized in a small-outline, x64 configuration. They
are specially processed to operate from 3V to 3.6V for
low-voltage memory systems.
During READ or WRITE cycles, each location is
uniquely addressed via the address bits. The row address is latched by the RAS# signal, then the column
address is latched by the CAS# signal.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFYWRITE is attempted while keeping OE# LOW, no
WRITE will occur, and the data outputs will drive read
data from the access location.
REFRESH
Memory cell data is retained in its correct state by
maintaining power and executing any RAS# cycle
(READ, WRITE) or RAS# refresh cycle (RAS#-ONLY,
CBR or HIDDEN) so that all combinations of RAS#
addresses are executed at least every tREF, regardless of
sequence. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# addressing.
An optional self refresh mode is also available on
the “S” version. The “S” option allows the user the
choice of a fully static, low-power data retention mode
or a dynamic refresh mode at the extended refresh
period of 128ms, or 125µs per row when using distributed CBR REFESH. The optional self refresh feature is
initiated by performing a CBR REFRESH cycle and
holding RAS# LOW for the specified tRASS.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of tRPS. This delay allows
for the completion of any internal refresh cycles that
may be in process at the time of the RAS# LOW-toHIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst refresh sequence,
all 1,240 rows must be refreshed within the average
internal refresh rate, prior to the resumption of normal
operation.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data
operations (READ or WRITE) within a row-addressdefined page boundary. The FAST-PAGE-MODE cycle
is always initiated with a row address strobed in by
RAS#, followed by a column address strobed in by
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LDT464H (X) (32MB)
DQ0-DQ15
WE#
DQ16-DQ31
16
16
DQ0-DQ15
DQ0-DQ15
WE#
WE#
U1
OE#
U2
OE#
OE#
RAS0#
RAS#
RAS#
CAS0#
CASL#
CASL#
CAS1#
CASH# A0ÐA11
CASH# A0ÐA11
12
CAS2#
12
CAS3#
A0-A11
DQ32-DQ47
DQ48-DQ63
16
16
DQ0-DQ15
DQ0-DQ15
WE#
WE#
U3
U4
OE#
OE#
RAS#
RAS#
CAS4#
CASL#
CASL#
CAS5#
CASH# A0ÐA11
CASH# A0ÐA11
12
CAS6#
12
CAS7#
SPD
SCL
SA0
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
U1-U4 = MT4LC4M16R6 EDO PAGE MODE
U1-U4 = MT4LC4M16F5 FAST PAGE MODE
SDA
SA1
SA2
3
VDD
U1-U4
VSS
U1-U4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM
MT8LDT864H (X) (64MB)
WE#
DQ0-DQ7
DQ8-DQ15
8
8
8
8
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
WE#
WE#
U1
OE#
DQ16-DQ23
WE#
DQ24-DQ31
WE#
U2
U3
U4
OE#
OE#
OE#
OE#
RAS0#
RAS#
RAS#
RAS#
RAS#
CAS0#
CAS#
CAS1#
CAS#
CAS#
CAS#
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
12
12
12
12
CAS2#
CAS3#
A0-A11
DQ32-DQ39
DQ40-DQ47
DQ56-DQ63
8
8
8
8
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
DQ0-DQ7
WE#
WE#
U5
CAS4#
DQ48-DQ55
WE#
U6
WE#
U7
U8
OE#
OE#
OE#
OE#
RAS#
RAS#
RAS#
RAS#
CAS#
CAS#
CAS#
CAS5#
CAS#
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
12
12
12
12
CAS6#
CAS7#
SPD
SDA
SCL
SA0
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
SA1
SA2
VDD
U1-U8
U1-U8 = MT4LC8M8B6 FAST PAGE MODE
VSS
U1-U8
U1-U8 = MT4LC8M8C2 EDO PAGE MODE
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has
been met.
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presencedetect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various DRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals.
SPD STOP CONDITION
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the SPD device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to
indicate successful data transfers. The transmitting
device, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
The SPD device will always respond with an acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Figures 1 and 2).
SCL
SCL
SDA
SDA
DATA STABLE
DATA
CHANGE
DATA STABLE
START
BIT
STOP
BIT
Figure 2
Definition of Start and Stop
Figure 1
Data Validity
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Figure 3
Acknowledge Response From Receiver
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
operation have been selected, the SPD device will respond with an acknowledge after the receipt of each
subsequent eight-bit word. In the read mode the SPD
device will transmit eight bits of data, release the SDA
line and monitor the line for an acknowledge. If an
acknowledge is detected and no stop condition is
generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the
slave will terminate further data transmissions and
await the stop condition to return to standby power
mode.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
SERIAL PRESENCE-DETECT MATRIX
BYTE
0
1
2
DESCRIPTION
ENTRY (VERSION) BIT7
NUMBER OF BYTES USED BY MICRON
128
1
TOTAL NUMBER OF SPD MEMORY BYTES
256
0
MEMORY TYPE
FAST PAGE MODE
0
EDO PAGE MODE
0
3
4
NUMBER OF ROW ADDRESSES
NUMBER OF COLUMN ADDRESSES
5
6
7
8
9
BIT6
0
0
0
0
BIT5
0
0
0
0
BIT4
0
0
0
0
BIT3
0
1
0
0
BIT2
0
0
0
0
BIT1
0
0
0
1
BIT0
0
0
1
0
HEX
80
08
01
02
12
10 (32MB)
11 (64MB)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0C
0A
0B
NUMBER OF BANKS
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS
RAS# ACCESS TIME (tRAC)
1
64
0
LVTTL
50ns (-5)
60ns (-6)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
01
40
00
01
32
3C
10
CAS# ACCESS TIME (tCAC)
13ns (-5)
15ns (-6)
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0D
0F
11
12
MODULE CONFIGURATION TYPE
REFRESH RATE/TYPE15.6µs/NORMAL
NONPARITY
0
2x - 31.25µs/SELF
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
00
1
00
13
DRAM WIDTH (PRIMARY DRAM)
x16 (32MB)
x8 (64MB)
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
10
08
NONE
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
1
1
1
1
0
1
0
1
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
1
0
1
1
0
1
0
1
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
1
0
1
0
1
0
1
1
1
0
0
0
1
x
0
0
0
1
0
x
x
x
–
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
1
0
x
0
1
1
0
0
x
x
x
–
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
1
0
x
1
0
1
0
0
x
x
x
–
00
00
00
31
3D
30
3C
2A
36
29
35
2C
FF
01
02
03
04
xx
01
02
03
04
00
xx
xx
xx
–
14
15-61
62
63
ERROR CHECKING DRAM DATA WIDTH
RESERVED
SPD REVISION
CHECKSUM FOR BYTES 0-62
64
65-71
72
MANUFACTURER’S JEDEC ID CODE
MANUFACTURER’S JEDEC CODE (CONT.)
MANUFACTURINGLOCATION
73-90
91
MODULE PART NUMBER (ASCII)
PCB IDENTIFICATION CODE
92
93
94
95-98
99-125
IDENTIFICATION CODE (CONT.)
YEAR OF MANUFACTURE IN BCD
WEEK OF MANUFACTURE IN BCD
MODULE SERIAL NUMBER
MANUFACTURE SPECIFIC DATA (RSVD)
REV. 0
32MB -5 (EDO)
32MB -6 (EDO)
32MB -5 (FPM)
32MB -6 (FPM)
64MB -5 (EDO)
64MB -6 (EDO)
64MB -5 (FPM)
64MB -6 (FPM)
MICRON
1
2
3
4
0
03
NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”
2. x = Variable Data.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Voltage on VDD Supply
Relative to VSS ..................................... -1V to +4.6V
Voltage on Inputs or I/O Pins
Relative to VSS ................................. -1V to +4.6V
Operating Temperature, TA (ambient) .. 0°C to +70°C
Storage Temperature (plastic) ........... -55°C to +125°C
Power Dissipation (32MB) ..................................... 4W
Power Dissipation (64MB) ..................................... 8W
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
VDD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
VIH
2
VDD + 0.3
V
30
INPUT LOW VOLTAGE: Logic 0; All inputs
VIL
-0.5
0.8
V
30
23
23
INPUT LEAKAGE CURRENT:
Any input 0V ≤ VIN ≤ VDD + 0.3V
(All other pins not under test = 0V)
RAS0#
A0-A11, WE#, OE#
CAS0#-CAS7#
II1
II2
II3
-16
-16
-2
16
16
2
µA
µA
µA
OUTPUT LEAKAGE CURRENT:
DQ is disabled; 0V ≤ VOUT ≤ VDD + 0.3V
DQ0-DQ63
IOZ
-10
10
µA
VOH
2.4
–
V
VOL
–
0.4
V
OUTPUT LEVELS:
Output High Voltage (IOUT = -2mA)
Output Low Voltage (IOUT = 2mA)
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6) (VDD = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
SYMBOL SIZE
-5
-6
UNITS NOTES
STANDBY CURRENT: TTL
(RAS# = CAS# = VIH)
ICC1
32MB
64MB
4
8
4
8
mA
STANDBY CURRENT: CMOS
(RAS# = CAS# = VDD - 0.2V)
ICC2
32MB
64MB
2
4
2
4
mA
26
32MB
64MB
700
1400
660
1320
mA
3, 22
32MB
64MB
420
840
380
760
mA
3, 22
32MB
ICC5
64MB
(X only)
620
1200
500
1000
mA
3, 22
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
ICC3
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN];
tCP, tASC = 10ns)
ICC4
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
ICC6
32MB
64MB
700
1400
660
1320
mA
3, 22
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
ICC7
32MB
64MB
700
880
660
800
mA
3, 4
ICC8
32MB
64MB
1.6
3.2
1.6
3.2
mA
3, 4, 5
ICC9
32MB
64MB
1.6
2.4
1.6
2.4
mA
3, 4, 5
REFRESH CURRENT: Extended (“S” version only)
Average power supply current: CAS# = 0.2V or CBR cycling;
RAS# = tRAS (MIN); WE# = VDD - 0.2V; A0-A11,
OE# and DIN = VDD - 0.2V or 0.2V (DIN may be left open)
REFRESH CURRENT: Self (“S” version only)
Average power supply current: CBR with RAS# ≥
tRASS (MIN) and CAS# held LOW; WE# = VDD - 0.2V; A0-A11,
OE# and DIN = VDD - 0.2V or 0.2V (DIN may be left open)
CAPACITANCE
MAX
PARAMETER
SYMBOL 32MB 64MB UNITS NOTES
Input Capacitance: A0-A11
CI1
24
46
pF
2
Input Capacitance: WE#, OE#, RAS0#
CI2
32
62
pF
2
Input Capacitance: CAS0#-CAS7#, SCL
CI3
10
10
pF
2
Input/Output Capacitance: DQ0-DQ63
CIO1
10
18
pF
2
Input/Output Capacitance: SDA
CIO2
10
10
pF
2
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
Access time from column address
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# LOW to “Don’t Care” during Self Refresh
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE# setup prior to RAS# during
HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (FAST PAGE MODE)
RAS# pulse width during Self Refresh
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
-5
SYMBOL
tAA
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
tCHR
tCLZ
tCP
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDS
tOD
tOE
tOEH
MIIN
tOFF
3
0
tORD
tPC
-6
MAX
25
40
0
0
48
13
8
13
15
15
3
8
10,000
15
10
15
15
15
3
10
30
5
50
5
36
13
8
0
3
13
13
13
tRAC
13
8
50
50
100
tRAH
tRAS
tRASP
tRASS
10
10,000
35
5
60
5
40
15
10
0
3
15
15
15
13
3
0
15
35
85
50
tRAD
MAX
30
45
0
0
55
30
76
tPRWC
MIN
10,000
125,000
60
15
10
60
60
100
10,000
125,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
ns
ns
17, 24
ns
ns
ns
ns
ns
ns
ns
µs
27
27
4
21
13
27
18
18
28
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period (4,096 cycles)
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time exiting Self Refresh
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time
RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
WRITE command pulse width
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
-5
SYMBOL
tRC
tRCD
tRCH
tRCS
tREF
tRP
tRPC
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
11
MIN
90
18
0
0
-6
MAX
MIN
110
20
0
0
64
30
0
90
0
13
131
73
13
2
8
40
0
8
10
10
50
MAX
64
40
0
105
0
15
155
85
15
2
10
45
0
10
10
10
50
UNITS
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
14
16
16
27
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
PARAMETER
Access time from column address
Column-address setup to CAS# precharge
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# LOW to “Don’t Care” during Self Refresh
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
Data output hold after next CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OE# HIGH hold from CAS# HIGH
OE# HIGH pulse width
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
-5
SYMBOL
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
tCHR
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDS
tOD
tOE
tOEH
MIN
8
tOEHC
5
5
4
0
tOEP
tOES
tOFF
12
-6
MAX
25
12
38
0
0
42
MIN
NOTES
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
5
0
ns
ns
ns
ns
28
15
45
0
0
49
13
8
8
15
8
0
3
8
10,000
15
10
10
15
10
0
3
10
28
5
38
5
28
8
8
0
0
MAX
30
12
12
12
10,000
35
5
45
5
35
10
10
0
0
15
15
15
27
4
13
27
18
18
28
17, 24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
PARAMETER
OE# setup prior to RAS#
during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (EDO PAGE MODE)
RAS# pulse width during Self Refresh
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period (4,096 cycles)
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time exiting Self Refresh
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time
RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
Output disable delay from WE#
WRITE command pulse width
WE# pulse to disable at CAS# HIGH
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
-5
SYMBOL
tORD
MIN
0
tPC
20
47
tPRWC
tRAC
-6
MAX
MIN
0
25
56
50
tRAD
9
9
50
50
100
84
11
0
0
tRAH
tRAS
tRASP
tRASS
tRC
tRCD
tRCH
tRCS
tREF
10,000
125,000
60
12
10
60
60
100
104
14
0
0
64
tRP
30
5
90
0
13
116
67
13
2
8
38
0
0
5
10
8
8
tRPC
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
tWCS
tWHZ
tWP
tWPZ
tWRH
tWRP
13
MAX
50
12
10,000
125,000
64
40
5
105
0
15
140
79
15
2
10
45
0
0
5
10
10
10
50
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
15
14
16
16
28
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: IOUT = 3mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
STANDBY CURRENT:
SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10%
POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz
SYMBOL
MIN
MAX
VDD
3
3.6
VIH
VDD x 0.7 VDD + 0.5
V IL
-1
VDD x 0.3
VOL
–
0.4
I LI
–
10
I LO
–
10
–
30
I SB
UNITS
V
V
V
V
µA
µA
µA
–
mA
ICC
2
NOTES
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
SYMBOL
tAA
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
tSCL
tSU:DAT
tSU:STA
tSU:STO
tWR
14
MIN
0.3
4.7
300
MAX
3.5
300
0
4
4
100
4.7
1
100
250
4.7
4.7
10
UNITS
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
NOTES
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
NOTES
16.Either tRCH or tRRH must be satisfied for a READ
cycle.
17. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
18.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
19.If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
Additionally, with EDO, WE# must be pulsed
during CAS# HIGH time in order to place I/O
buffers in High-Z.
20.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21.The 3ns minimum is a parameter guaranteed by
design.
22.Column address changed once each cycle.
23.8MB module values will be half of those shown.
24.With the FPM option, tOFF is determined by the
first RAS# or CAS# signal to transition HIGH. In
comparison, tOFF on an EDO option is determined by the latter of the RAS# and CAS# signals
to transition HIGH.
25.Applies to both FPM and EDO operating modes.
26.All other inputs at 0.2V or VDD - 0.2V.
27. tWCS, tRWD, tAWD and tCWD are not restrictive
operating parameters. tWCS applies to EARLY
WRITE cycles. tRWD, tAWD and tCWD apply to
READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and
tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and
tCWD ≥ tCWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW result in a LATE
WRITE (OE#-controlled) cycle. tWCS, tRWD,
tCWD and tAWD are not applicable in a LATE
WRITE cycle.
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD = +3.3V; f = 1 MHz.
3. ICC is dependent on output loading and cycle
rates. Specified values are obtained with minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured.
6. An initial pause of 100µs is required after powerup, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 5ns for FPM and
tT = 2.5ns for EDO.
8. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
9. In addition to meeting the transition rate
specification, all input signals must transit between
VIH and VIL (or between VIL and VIH) in a monotonic manner.
10.If CAS# = VIH, data output is High-Z.
11.If CAS# = VIL, data output may contain data from
the last valid READ cycle.
12.Measured with a load equivalent to two TTL gates
and 100pF and VOL = 0.8V and VOH = 2V.
13.If CAS# is LOW at the falling edge of RAS#, Q will
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for tCP.
14.The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
tRCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively
by tCAC (tRAC [MIN] no longer applied). With or
without the tRCD (MAX) limit, tAA and tCAC
must always be met.
15.The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
tRAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively
by tAA (tRAC and tCAC no longer applied). With
or without the tRAD (MAX) limit, tAA, tRAC and
tCAC must always be met.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
NOTES (continued)
sequence to the end of the EEPROM internal erase/
program cycle. During the WRITE cycle, the
EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the
EEPROM does not respond to its slave address.
30.VIH overshoot: VIH (MAX) = VDD + 2V for a pulse
width ≤ 10ns, and the pulse width cannot be
greater than one third of the cycle rate. VIL
undershoot: VIL (MIN) = -2V for a pulse width ≤
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
28.LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after tOEH is met. If CAS# goes HIGH prior
to OE# going back LOW, the DQs will remain
open.
29.The SPD EEPROM WRITE cycle time (tWR) is the
time from a valid stop condition of a write
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
READ CYCLE 25
tRC
tRP
tRAS
V IH
V IL
RAS#
tCSH
tRSH
tRCD
tCRP
tRRH
tCAS
V IH
V IL
CASL#/CASH#
tASR
V IH
V IL
ADDR
tAR
tASC
tRAD
tRAH
ROW
tCAH
tACH
ROW
COLUMN
tRCH
tRCS
V IH
V IL
WE#
tAA
tRAC
NOTE 1
tOFF
tCAC
tCLZ
DQ
V OH
V OL
OPEN
OPEN
VALID DATA
tOE
tOD
V IH
V IL
OE#
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH (EDO)
tAR (EDO)
tASC
MIN
-5
-6
MAX
25
MIN
12
38
15
45
0
0
0
0
MAX
30
SYMBOL
tOE (FPM)
tOFF (EDO)
tOFF (FPM)
tRAC
UNITS
ns
ns
ns
40
45
ns
ns
ns
ns
10
10
ns
ns
tRAH
(EDO)
8
8
(FPM)
tCLZ (EDO)
tCLZ (FPM)
13
0
3
ns
ns
ns
tRC (EDO)
tCRP
5
38
ns
ns
tRCD
ns
ns
tRCS
15
15
15
ns
ns
tRRH
tASR
tCAC
tAR
13
(FPM)
tCAH
tCAS
tCAS
tCSH
(EDO)
tCSH
(FPM)
tOD (EDO)
tOD
(FPM)
tOE (EDO)
50
0
3
10,000
10,000
15
15
0
3
10,000
10,000
5
45
12
13
12
60
0
3
tRAD
tRAD
tRAH
tRCH
tRP
tRSH
MIN
0
3
MAX
15
15
15
60
UNITS
ns
ns
ns
ns
9
13
12
15
ns
ns
(EDO)
(FPM)
9
8
50
10
10
60
ns
ns
ns
(FPM)
tRCD
0
3
-6
MAX
13
12
13
50
(EDO)
(FPM)
tRAS
tRC
MIN
(EDO)
(FPM)
10,000
10,000
84
90
104
110
ns
ns
11
18
0
14
20
0
ns
ns
ns
0
30
0
40
ns
ns
0
13
0
15
ns
ns
NOTE: 1. For EDO, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM, tOFF is referenced from
rising edge of RAS# or CAS#, whichever occurs first.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
EARLY WRITE CYCLE 25
tRC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
tCRP
CASL#/CASH#
tRCD
tCAS
tAR
tASC
tCAH
V IH
V IL
tRAD
tASR
ADDR
V IH
V IL
tACH
tRAH
ROW
ROW
COLUMN
tCWL
tRWL
tWCR
tWCH
tWCS
tWP
WE#
V IH
V IL
tDS
V
DQ V IOH
IOL
OE#
tDH
VALID DATA
V IH
V IL
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tACH (EDO)
tAR (EDO)
tAR
(FPM)
tASC
tASR
tCAH
tCAS
(FPM)
tCAS
(EDO)
tCRP
tCSH
MIN
12
38
-6
MAX
MIN
15
45
-5
MAX
UNITS
ns
ns
SYMBOL
tRAH (EDO)
tRAH (FPM)
40
0
45
0
ns
ns
tRAS
0
8
13
0
10
15
ns
ns
ns
tRC (EDO)
ns
ns
tRP
8
5
10,000
10,000
10
5
10,000
10,000
tRC
(FPM)
tRCD
(FPM)
tRCD (EDO)
tRSH
(FPM)
(EDO)
tCWL (FPM)
50
38
13
60
45
15
ns
ns
ns
tRWL
tWCR
(EDO)
tCWL (EDO)
8
8
10
10
ns
ns
tWCR
(FPM)
0
—
9
0
15
12
ns
ns
ns
tWP (FPM)
tCSH
tDH
tDS
tRAD
(FPM)
tRAD (EDO)
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
tWCH
tWCS
tWP (EDO)
18
-6
MIN
9
8
MAX
MIN
10
10
MAX
UNITS
ns
ns
50
90
10,000
60
110
10,000
ns
ns
84
18
11
104
20
14
ns
ns
ns
30
13
40
15
ns
ns
13
8
38
15
10
45
ns
ns
ns
40
0
45
0
ns
ns
8
5
10
5
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
FAST-PAGE-MODE READ CYCLE
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CASL#/CASH#
tRP
tRCD
tPC
tCP
tCAS
tCAS
tRSH
tCAS
tCP
tCP
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
V IH
V IL
tASC
ROW
tCAH
COLUMN
tRCS
WE#
tASC
tCAH
COLUMN
COLUMN
ROW
tRCS
tRRH
tRCH
V IH
V IL
tCAC
tAA
tCPA
tOFF
tCLZ
V IOH
V IOL
tCAC
tAA
tCPA
tOFF
tCLZ
OPEN
tOE
OE#
tCAH
tRCS
tRCH
tRCH
tAA
tRAC
DQ
tASC
tCAC
tOFF
tCLZ
VALID
DATA
tOD
tOE
VALID
DATA
tOD
tOE
VALID
DATA
tOD
OPEN
V IH
V IL
DON’T CARE
UNDEFINED
FAST PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
tASC
tASR
MIN
tCAS
tCLZ
tCP
UNITS
ns
SYMBOL
tOE
MAX
13
3
13
tOFF
0
0
0
0
tPC
15
ns
ns
ns
tRAD
13
tRAH
10,000
ns
ns
8
50
tRCD
35
ns
ns
ns
ns
ns
tRP
ns
13
8
13
10,000
3
8
10
15
3
10
30
tCSH
tOD
3
5
60
13
3
15
30
tRAC
tRASP
MIN
MAX
15
UNITS
ns
3
15
ns
60
ns
ns
ns
35
50
15
125,000
10
60
125,000
ns
ns
18
0
0
20
0
0
ns
ns
ns
tRRH
30
0
40
0
ns
ns
tRSH
13
15
ns
tRCH
tRCS
19
-6
MIN
ns
5
50
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
-5
MAX
30
5
tCPA
tCRP
MIN
40
tCAC
tCAH
-6
MAX
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
EDO-PAGE-MODE READ CYCLE
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CASL#/CASH#
tRP
tPC
tCP
tCAS
tRCD
tCAS
tRSH
tCAS
tCP
tCP
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tACH
tACH
tASC
tRAH
ROW
tASC
tCAH
COLUMN
tACH
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRCS
WE#
tRCH
V IH
V IL
tAA
tRAC
tAA
tCPA
tCAC
tCAC
DQ
V OH
V OL
VALID
DATA
OPEN
tOE
OE#
tCAC
tCLZ
tOFF
tOEHC
tCOH
tCLZ
VALID
DATA
VALID
DATA
OPEN
tOE
tOD
tOES
V IH
V IL
tRRH
tAA
tCPA
tOD
tOES
tOEP
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
-6
12
15
45
0
ns
ns
tOES
tASC
38
0
tASR
0
ns
ns
ns
tPC
tRAD
9
ns
ns
tRAH
9
50
ns
ns
ns
tRCD
ns
ns
tRP
ns
ns
tCAC
8
tCAS
8
0
tCOH
tCP
tCSH
tOD
0
tOE
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
15
10
10,000
10
0
10,000
3
10
28
5
38
MAX
30
0
3
8
tCPA
tCRP
MIN
13
tCAH
tCLZ
MAX
25
-5
UNITS
ns
ns
tAR
MIN
35
5
45
12
12
0
15
15
SYMBOL
tOEHC
tOEP
tOFF
MIN
5
5
4
0
MIN
10
5
5
0
MAX
15
25
50
60
12
125,000
10
60
125,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
0
0
14
0
0
ns
ns
ns
tRRH
30
0
40
0
ns
ns
tRSH
13
15
ns
tRCH
tRCS
20
12
20
tRAC
tRASP
-6
MAX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
FAST/EDO-PAGE-MODE EARLY WRITE CYCLE 25
tRP
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CASL#/CASH#
tRCD
tCAS
tPC
tCP
tCAS
tRSH
tCAS
tCP
tCP
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tACH
tACH
tRAH
tASC
ROW
tCAH
tASC
COLUMN
tWCS
tWP
WE#
tASC
COLUMN
tCWL
tWCH
tWCS
tACH
tCAH
tCAH
COLUMN
tCWL
tWCH
ROW
tCWL
tWCH
tWCS
tWP
tWP
V IH
V IL
tRWL
tWCR
tDS
V
DQ V IOH
IOL
OE#
tDH
tDS
VALID DATA
tDH
tDS
VALID DATA
tDH
VALID DATA
V IH
V IL
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tACH (EDO)
tAR (EDO)
tAR (FPM)
tASC
MIN
12
38
40
-6
MAX
0
0
tASR
tCAH
tCAS
(EDO)
tCAS (FPM)
tCP
8
8
13
MIN
15
45
45
-5
MAX
0
0
10,000
10,000
10
10
15
10,000
10,000
UNITS
ns
ns
ns
SYMBOL
tPC (FPM)
tRAD (EDO)
tRAD (FPM)
ns
ns
tRAH
ns
ns
ns
tRASP
(EDO)
(FPM)
9
9
(EDO)
tRCD (FPM)
50
11
18
tRAH
tRCD
8
5
10
5
ns
ns
tRP
(EDO)
(FPM)
tCWL (EDO)
38
50
8
45
60
10
ns
ns
ns
tRWL
tWCR
(EDO)
tCWL
13
8
15
10
ns
ns
tWCR
(FPM)
0
20
0
25
ns
ns
tWP (EDO)
tCRP
tCSH
tCSH
(FPM)
tDH
tDS
tPC (EDO)
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
tRSH
tWCH
tWCS
tWP (FPM)
21
MIN
30
9
13
-6
MAX
MIN
35
12
15
MAX
10
10
125,000
60
14
20
UNITS
ns
ns
ns
ns
ns
125,000
ns
ns
ns
30
13
40
15
ns
ns
13
8
38
15
10
45
ns
ns
ns
38
0
45
0
ns
ns
5
8
5
10
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
READ-WRITE CYCLE 25
(LATE WRITE and READ-MODIFY-WRITE cycles)
t RWC
t RAS
RAS#
t RP
V IH
V IL
t CSH
t RSH
t CRP
CAS#
t RCD
t AR
t RAD
t ASR
ADDR
t CAS
V IH
V IL
V IH
V IL
t ASC
t CAH
t ACH
t RAH
ROW
COLUMN
t RCS
WE#
ROW
t RWD
t CWL
t CWD
t RWL
t AWD
t WP
V IH
V IL
t AA
t RAC
t CAC
t DS
t CLZ
V
DQ V IOH
IOL
VALID D OUT
OPEN
t OE
OE#
t DH
VALID D IN
t OD
OPEN
t OEH
V IH
V IL
DON’T CARE
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH (EDO)
tAR (EDO)
tAR (FPM)
tASC
tASR
tAWD (EDO)
tAWD
(FPM)
MIN
MIN
MAX
30
15
45
45
0
0
49
48
55
13
tCAH
-5
-6
MAX
25
12
38
40
0
0
42
tCAC
UNDEFINED
9
8
10
10
ns
ns
(EDO)
tRCD (FPM)
50
11
18
tRAH
ns
ns
tRCD
tRAH
tCLZ (FPM)
3
5
38
3
5
45
ns
ns
ns
tRCS
(FPM)
tCWD (EDO)
50
28
60
35
ns
ns
tRWC (EDO)
tRWC
tCWD
36
8
13
40
10
15
ns
ns
ns
tRWD
8
0
10
0
ns
ns
tWP (EDO)
tCRP
tCSH
(EDO)
tCSH
(FPM)
tCWL (EDO)
tCWL (FPM)
tDH
tDS
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
10,000
tRAS
60
14
20
10,000
ns
ns
ns
0
40
ns
ns
(FPM)
13
116
131
15
140
155
ns
ns
ns
(EDO)
(FPM)
67
73
79
85
ns
ns
13
5
8
15
5
10
ns
ns
ns
tRSH
tRWD
10,000
0
30
tRP
tRWL
tWP (FPM)
22
60
10
15
(EDO)
(FPM)
ns
ns
ns
13
0
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
(FPM)
tCLZ (EDO)
15
0
MAX
15
15
15
12
15
(EDO)
10,000
8
13
MIN
0
3
50
(EDO)
tRAD (FPM)
tCAS
10,000
-6
MAX
12
13
12
9
13
tRAD
8
8
tCAS
MIN
0
3
tRAC
ns
15
10
10
SYMBOL
tOD (EDO)
tOD (FPM)
tOE (EDO)
tOEH (EDO)
tOEH (FPM)
UNITS
ns
ns
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
FAST/EDO-PAGE-MODE READ-WRITE CYCLE 25
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP
RAS#
V IH
V IL
tCSH
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
V IH
V IL
tCP
tCAS
tASC
ROW
tPRWC NOTE 1
tPC
tRCD
tCRP
CASL#/CASH#
tRP
tCAH
tASC
COLUMN
tRSH
tCP
tCAS
tCAH
tCP
tCAS
tASC
COLUMN
tCAH
COLUMN
ROW
tRWD
tRCS
WE#
tRWL
tCWL
tCWL
tWP
tAWD
tCWD
tWP
tAWD
tCWD
V IH
V IL
tAA
tAA
tRAC
tDH
t CAC
VALID
D OUT
OPEN
VALID
D OUT
VALID
D IN
tOD
OE#
tDS
tCAC
tCLZ
VALID
D IN
tOE
tDH
tCPA
tDS
tCAC
tCLZ
t CLZ
V IOH
V IOL
tAA
tDH
tCPA
tDS
DQ
tCWL
tWP
tAWD
tCWD
VALID
D OUT
VALID
D IN
tOD
tOE
tOD
tOE
-5
tCAS
MIN
DON’T CARE
UNDEFINED
-6
MAX
25
38
40
0
0
42
48
MIN
-5
MAX
30
45
45
0
0
49
55
13
8
15
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
tOD (EDO)
tOD (FPM)
tOE (EDO)
tOE (FPM)
tOEH (EDO)
tOEH (FPM)
tPC (EDO)
tPC (FPM)
tPRWC (EDO)
(EDO)
8
10,000
10
10,000
ns
tPRWC
(FPM)
tCLZ (EDO)
tCLZ (FPM)
13
0
3
10,000
15
0
3
10,000
ns
ns
ns
tRAC
ns
ns
tRAH
tCAS
tCP
8
tCPA (EDO)
tCPA
10
28
(FPM)
tCRP
35
(EDO)
tRCD (FPM)
50
11
18
tRASP
tRCD
ns
ns
tRCS
36
8
13
40
10
15
ns
ns
ns
tRSH
8
0
10
0
ns
ns
tRWL
tDS
ns
ns
ns
60
35
(FPM)
85
10
10
50
28
tDH
76
9
8
(FPM)
(EDO)
tCWL
10
15
25
35
56
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
(EDO)
(FPM)
tRAH
(EDO)
(FPM)
MAX
15
15
15
15
ns
ns
ns
tCSH
tCWL (EDO)
8
13
20
30
47
MIN
0
3
12
15
tCSH
tCWD
-6
MAX
12
13
12
13
9
13
ns
ns
ns
35
MIN
0
3
50
(EDO)
tRAD (FPM)
5
45
30
(FPM)
tRAD
5
38
tCWD
tOEH
V IH
V IL
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
SYMBOL
tAA
tAR (EDO)
tAR (FPM)
tASC
tASR
tAWD (EDO)
tAWD (FPM)
tCAC
tCAH
OPEN
125,000
60
60
14
20
125,000
ns
ns
ns
0
30
0
40
ns
ns
13
67
73
15
79
85
ns
ns
ns
tWP (EDO)
13
5
15
5
ns
ns
tWP (FPM)
8
10
ns
tRP
tRWD
(EDO)
tRWD (FPM)
NOTE: 1. tPC is for LATE WRITE cycles only.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t RP
t RASP
RAS#
V IH
V IL
t CSH
tPC
tCRP
CASL#/CASH#
t RCD
tRSH
tPC
t CP
t CAS
t CP
t CAS
t CP
t CAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
t ACH
tRAH
tASC
tCAH
t ASC
COLUMN (A)
ROW
t CAH
COLUMN (B)
WE#
ROW
tWCS
tWCH
tAA
tAA
tCPA
tRAC
tCAC
tCAC
tCOH
DQ V IOH
V IOL
t CAH
COLUMN (N)
tRCH
tRCS
V IH
V IL
tASC
OPEN
VALID DOUT
t DS
t DH
t WHZ
VALID
DOUT
VALID DIN
tOE
OE#
V IH
V IL
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
-6
12
15
38
0
45
0
ns
ns
tRAC
tASC
tASR
0
ns
ns
ns
tRAH
ns
ns
tRCH
tRP
tWCS
tCAC
MAX
25
MIN
-5
UNITS
ns
ns
tAR
MIN
0
13
tCAH
8
tCAS
tCOH
8
3
tCP
8
MAX
30
15
10
10,000
10
3
10,000
tCRP
5
5
ns
ns
ns
tCSH
tDH
38
8
45
10
ns
ns
tDS
0
0
ns
tCPA
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
10
28
35
SYMBOL
MIN
tOE
tPC
tRAD
tRASP
tRCD
tRCS
tRSH
tWCH
tWHZ
24
-6
MAX
MIN
12
20
15
25
50
9
9
50
11
MAX
60
14
ns
ns
60
ns
ns
ns
125,000
ns
ns
12
10
125,000
UNITS
0
0
30
0
0
40
ns
ns
ns
13
8
15
10
ns
ns
0
0
12
0
0
15
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
FAST-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
tRASP
RAS#
tRP
V IH
V IL
tRSH
tCSH
tRCD
tCRP
CASL#/CASH#
tPC
tCAS
tCP
tCAS
tCP
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tASC
tRAH
ROW
tASC
tCAH
COLUMN
tCAH
COLUMN
tRCS
tWP
tWCH
tWCS
WE#
V IH
V IL
tCAC
NOTE 1
t OFF
tDS
t CLZ
Q
V OH
V OL
ROW
tCWL
tRWL
VALID
DATA
OPEN
tDH
VALID DATA
tAA
tRAC
OE#
V IH
V IL
DON’T CARE
UNDEFINED
FAST PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
tASC
tASR
MIN
40
0
0
tCAC
8
tCAS
13
3
8
tCP
tCRP
tCSH
tCWL
tDH
tDS
MIN
-5
MAX
30
45
0
0
15
10
10,000
15
3
10
UNITS
ns
SYMBOL
tOFF
tPC
ns
ns
ns
13
tCAH
tCLZ
-6
MAX
25
10,000
MIN
3
30
tRAC
13
ns
ns
tRAH
ns
ns
ns
tRCD
8
50
18
tRCS
MIN
3
35
50
tRAD
tRASP
-6
MAX
13
MAX
15
UNITS
ns
ns
60
ns
ns
15
10,000
10
60
20
125,000
ns
ns
ns
0
30
0
40
ns
ns
13
13
15
15
ns
ns
tWCS
8
0
10
0
ns
ns
tWP
8
10
ns
tRP
5
50
5
60
ns
ns
tRSH
13
8
0
15
10
0
ns
ns
ns
tWCH
tRWL
NOTE: 1. Do not drive data prior to tristate.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
EDO READ CYCLE
(with WE#-controlled disable)
RAS#
V IH
V IL
tCSH
tRCD
tCRP
CASL#/CASH#
tCAS
tCP
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
V IH
V IL
tASC
ROW
tCAH
tASC
COLUMN
COLUMN
tRCS
WE#
tRCH
tWPZ
tRCS
V IH
V IL
tAA
tRAC
tCAC
tCLZ
DQ
V OH
V OL
tWHZ
OPEN
VALID DATA
tOE
OE#
tCLZ
OPEN
tOD
V IH
V IL
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
tASC
tASR
MIN
tCAS
tCLZ
tCP
tCRP
tCSH
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
MIN
-5
38
45
0
0
0
0
ns
ns
tRAC
tRAD
9
12
ns
ns
ns
ns
ns
tRAH
9
11
0
10
14
0
ns
ns
ns
13
8
8
10,000
MAX
30
15
10
10
10,000
SYMBOL
tOD
tOE
tRCD
tRCH
MIN
0
-6
UNITS
ns
ns
tCAC
tCAH
-6
MAX
25
MIN
0
50
0
8
0
10
ns
ns
tRCS
tWHZ
0
0
5
38
5
45
ns
ns
tWPZ
10
26
MAX
12
12
12
0
0
10
MAX
15
15
UNITS
ns
ns
60
15
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
RAS#-ONLY REFRESH CYCLE 25
t RC
t RAS
RAS#
t RP
V IH
V IL
t RPC
t CRP
CAS#
V IH
V IL
t ASR
ADDR
V IH
V IL
t RAH
ROW
ROW
V
DQ V OH
OL
WE#
OPEN
V IH
V IL
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tASR
tCRP
tRAH (EDO)
tRAH (FPM)
tRAS
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
MIN
0
5
9
8
50
-6
MAX
10,000
MIN
0
5
10
10
60
-5
MAX
10,000
UNITS
ns
ns
ns
ns
ns
SYMBOL
tRC (FPM)
tRC (EDO)
tRP
tRPC (FPM)
tRPC (EDO)
27
MIN
90
84
30
0
5
-6
MAX
MIN
110
104
40
0
5
MAX
UNITS
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
SELF REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
RAS#
V IH
V IL
tRPS
((
))
tRPC
tCSR
NOTE 2
tRPC
((
))
tCP
CAS#
NOTE 1
tRASS
tRP
((
))
tCP
tCHD
((
))
((
))
V IH
V IL
V
DQ V OH
OL
((
))
tWRP
OPEN
tWRP
tWRH
tWRH
((
))
((
))
V
WE# V IH
IL
CBR REFRESH CYCLE 25
(Addresses = DON’T CARE)
tRP
RAS#
tRAS
tRP
tRAS
V IH
V IL
tRPC
tCP
CAS#
tCSR
tRPC
tCHR
tCHR
V IH
V IL
V OH
DQ V OL
OPEN
tWRP
WE#
tCSR
tWRH
tWRP
tWRH
V IH
V IL
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tCHD
tCHR
(FPM)
tCHR
(EDO)
tCP
tCSR
tRAS
tRASS
tRP
MIN
-6
MAX
MIN
-5
MAX
UNITS
SYMBOL
tRPC (FPM)
tRPC (EDO)
15
15
15
15
ns
ns
8
8
5
10
10
5
ns
ns
ns
tRPS
ns
µs
tWRN
50
100
30
10,000
60
100
40
10,000
tWRH
(EDO)
tWRP (EDO)
(FPM)
tWRP (FPM)
MIN
0
5
-6
MAX
MIN
0
5
MAX
UNITS
ns
ns
90
8
8
105
10
10
ns
ns
ns
10
10
10
10
ns
ns
ns
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
HIDDEN REFRESH CYCLE 20, 25
(WE# = HIGH)
tRC
tRAS
RAS#
tRAS
V IH
V IL
tCRP
CASL#/CASH#
tRP
tRSH
tRCD
tCHR
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
COLUMN
tAA
tRAC
tCAC
tCLZ
DQx
V IOH
V IOL
tOFF
OPEN
VALID DATA
OPEN
tOE
OE#
V IH
V IL
tOD
tORD
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR (EDO)
-5
-6
MIN
MAX
30
MAX
MIN
MAX
UNITS
tOFF
(FPM)
tOFF (EDO)
3
0
13
12
3
0
15
15
ns
ns
0
60
ns
ns
45
40
0
45
0
ns
ns
tORD
tASC
tASR
0
tRAD
(FPM)
(EDO)
tRAH (EDO)
13
9
9
8
50
8
10
tCHR
(FPM)
tCHR (EDO)
15
8
15
10
ns
ns
tRAH
tCLZ (FPM)
3
0
5
3
0
5
ns
ns
ns
tRC
tRCD
(FPM)
15
15
ns
ns
tRCD
(EDO)
15
15
ns
ns
tCRP
tOD
(FPM)
tOD (EDO)
tOE (EDO)
tOE (FPM)
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
13
3
0
13
12
12
13
15
3
0
tRAD
(FPM)
tRAS
(FPM)
15
12
10
10,000
10
60
ns
ns
ns
10,000
ns
ns
90
84
18
110
104
20
ns
ns
ns
tRP
11
30
14
40
ns
ns
tRSH
13
15
ns
tRC (EDO)
29
0
50
tCAH
tCLZ (EDO)
0
tRAC
ns
ns
ns
tCAC
-6
MIN
38
(FPM)
MAX
25
SYMBOL
UNITS
ns
ns
tAR
MIN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
SPD EEPROM
tF
t HIGH
tR
t LOW
SCL
t HD:STA
t SU:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
t DH
t AA
t BUF
SDA OUT
UNDEFINED
SPD EEPROM
TIMING PARAMETERS
SYMBOL
tAA
tBUF
tDH
tF
tHD:DAT
tHD:STA
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
MIN
0.3
4.7
300
MAX
3.5
300
0
4
UNITS
µs
µs
ns
ns
µs
µs
SYMBOL
tHIGH
tLOW
tR
tSU:DAT
tSU:STA
tSU:STO
30
MIN
4
4.7
MAX
1
250
4.7
4.7
UNITS
µs
µs
µs
ns
µs
µs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
144-PIN SODIMM
DG-7 (32MB)
FRONT VIEW
2.667 (67.75)
2.656 (67.45)
.150 (3.80)
MAX
.079 (2.00) R
(2X)
1.006 (25.55)
.071 (1.80)
(2X)
0.994 (25.25)
.787 (20.00)
TYP
.236 (6.00)
.157 (4.00)
.100 (2.55)
.043 (1.10)
.035 (0.90)
.079 (2.00)
.130 (3.30)
(2X)
PIN 1
.059 (1.50) .024 (.60)
TYP
TYP
.0315 (.80)
TYP
PIN 143 (PIN 144 ON BACKSIDE)
2.386 (60.60)
2.504 (63.60)
144-PIN SODIMM
DG-8 (64MB)
FRONT VIEW
.150 (3.80)
MAX
2.667 (67.75)
2.656 (67.45)
.079 (2.00) R
(2X)
1.006 (25.55)
0.994 (25.25)
.071 (1.80)
(2X)
.787 (20.00)
TYP
.236 (6.00)
.157 (4.00)
.100 (2.55)
.079 (2.00)
.130 (3.30)
(2X)
PIN 1
.059 (1.50) .024 (.60)
TYP
TYP
.0315 (.80)
TYP
.043 (1.10)
.035 (0.90)
PIN 143 (PIN 144 ON BACKSIDE)
2.386 (60.60)
2.504 (63.60)
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
4, 8 MEG x 64
DRAM SODIMMs
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.