MT90840 Distributed Hyperchannel Switch Advance Information Features ISSUE 1 June 1995 • Time-slot interchange function between 8 pairs of ST-BUS/GCI/MVIP streams (512 channels) and a Parallel Data Port (PDP) • Supports star, point to point connections and unidirectional or bidirectional ring topologies for distributed systems • Input to Output Bypass function with minimum delay for shared ring applications • Special diagnostic alarm functions for statistical analysis • Provides an internal latency adjustment buffer for ring applications • JTAG boundary scan • • Parallel port data rates up to 19.44Mbyte/s Programmable data rates on the serial port side (2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s) Applications • Unidirectional Parallel switching mode for up to 2430 channels non-blocking Ordering Information MT90840AK 100 Pin PQFP MT90840AP 84 Pin PLCC -40°C to 85°C • Bridging ST-BUS/MVIP buses to high speed Time Division Multiplex backplanes at SONET rates (STS-1/3) • High speed isochronous backbones for distributed PBX and Local Area Network systems • Per-channel direction control on the serial port side • Per-channel message mode and highimpedance control on both parallel and serial port sides • Switch platforms of up to 2430 channels with guaranteed frame integrity for wideband channels • 8-bit multiplexed port compatible with Intel and Motorola microcontrollers • Serial bus control and monitoring • Data multiplexer Guarantees frame integrity when switching wideband channels such as ISDN H0 channel Provides external control lines allowing the fast parallel interface to be shared with other devices • High speed communications interface • Isochronous switching/multiplexing to support IEEE 802.9 standards • • C4OUT C4REF1 C4REF2 FO SERIAL PORT TIMING CONTROL RECEIVE PATH DATA & CONN MEMORIES Serial Data Port DSo[0:7] DSi[0:7] TCK TMS TDI TDO S-P & P-S PARALLEL PORT TIMING CONTROL RECEIVE LATENCY BUFFER PPFRo PCKT PPFRi PCKR PDi0-7 PARALLEL PORT INTERFACE PDo0-7 Parallel Data Port TRANSMIT PATH DATA & CONN MEMORIES EXTERNAL CONTROL JTAG Microprocessor Interface RESET AD[0:7] ALE WR/ RD/ CS R/W DS CT0 CT1 CT2 CT3 DTACK INT Figure 1 - Functional Block Diagram 2-189 MT90840 Functional Description Real time multimedia applications require the transmission of mixed voice and data transmission into the same integrated network and transmission media. The network must simultaneously ensure that data (at N x 64 kbit/s) maintains time slot sequence integrity and provide constant delay through the switch. The MT90840 device bridges existing Mitel ST-BUS components into a new networking environment. Mixed data, voice and video signals can be timeinterchanged or multiplexed from serial PCM streams onto a serial high speed Time Division Multiplex (TDM) isochronous backbone operating at SONET rates such as 51 (STS-1) or 155 Mb/s (STS3). Figure 1 shows the MT90840 functional block diagram. Today, transmission links operating at SONET rates utilize Serial-to-Parallel and Parallel-to-Serial converter devices (or framers) which perform embedded framing functions and give the user the access to the payload of the high speed frame. The MT90840 device provides an 8-bit bidirectional parallel data port (PDP) which directly interfaces to the user data interface of typical high speed framers, allowing designers to build distributed networking systems with interconnection speeds up to 155 Mb/s. Figure 2 depicts an example of distributed networking application in Computer Telephony Integration (CTI) systems. Figure 3 shows an example of interconnection between the MT90840 and high speed S/P & P/S framers used when implementing 155 Mb/s transmission links. The MT90840 device is designed to switch 64 kbit/s or wideband N x 64 kb/s channels from a Serial Data Port (SDP) to the Parallel Data Port (connected to high speed framers) and vice versa. The MT90840 Parallel Data Port is designed to accept data rates up to 19.44 Mbyte/s and the Serial Data Port can be programmed to connect to PCM serial streams at 2.048, 4.096 and 8.192 Mb/s. Since the parallel and serial ports of the MT90840 device operate at different rates, an internal rate converter circuit associated with a multiple buffer time interchange block is employed to achieve the rate adaptation between the two ports. 2-190 Advance Information The internal time interchange block allows the switching of 512 64 kb/s channels on the serial interface in a flexible connection scheme. This is accomplished by a feature called "per channel direction control" available on the 16 serial streams. For example, in some applications up to 512 channels from the serial port can be time interchanged to the parallel port side. In the opposite direction up to 512 channels coming from the parallel port can be dropped or time interchanged to the serial port side. The device's clock synchronization and reference options allow many applications and topologies when isochronous TDM backbones are required. Two major clock synchronization schemes provided by the MT90840 allow the serial port interface (ST-BUS) to provide the master clock and frame reference signals for the distributed high speed backbone (master operation) or to derive the entire ST-BUS clock and frame reference signals from the high speed backbone (slave operation). Figure 3 depicts an example of Master Operation. This type of synchronization scheme may be used in applications such as MVIP multi-chassis level 3 interface (MC-3 system) utilizing point to point or point to multipoint switching connections. When the MT90840 device operates in a ring type of application like the system depicted in Figure 2, a special mode called Parallel Data Bypass is provided to allow all or part of the received input parallel data to be bypassed to the output parallel port feeding the ring back with the data which is not destined (to be dropped) to the local station. The selection of the data destined (dropped) for the local station can be done through CPU programming. In this mode, the CPU has the full control on managing the outgoing bandwidth (from the serial interface to the high speed link) so that it does not contend with the bypassed data. For CPU access to the serial channels, the MT90840 device can be programmed using message mode with fast memory access times. By using the Mitel message mode, the microprocessor can access serial input and output TDM data on a per channel basis to control devices such as the Mitel’s digital transceivers like MT8972B, MT8930/1, MT8910 and T1/CEPT trunks through the ST-BUS interface. MT90840 Advance Information Application Examples CTI SERVER 24 / 30B + D M T90810 F M IC STBUS M T 8 9 7 7 /9 0 7 9 T 1 & E 1 I/f CTI SERVER C a ll P r o c e s s in g 1 5 5 M b /s F R A M IN G & O P T IC S M T90840 M T 90810 F M IC STBUS PSTN AA AA AA A A U p to 4 8 0 0 c h a n n e ls o f u s e r d a ta MT896x F ilte r /C O D E C F ilt e r/ C O D E C POTS M T 8 9 8 5 /6 EDX STBUS M T 8 9 3 0 /7 1 (2 B + D )In te r fa c e Is o E th e r n e t M ux 2B +D A AA AA A AAA AA AA AAA AA 1 6 M b /s AA CTI SERVER LA N AD A P TE R C A R D IN T E R C H A S S IS S IG N A L L IN G (e .g ; M ite l’s C o n n e c tio n M a s te r) Figure 2 - CTI Multichassis Connection using 155 Mb/s S T -B U S / P C M H ig h w a y 4 .0 9 6 M H z PLL S E R IA L D A T A IN 155 M b /s MMF OR SM F (8 K H z) 1 9 .4 4 M H z tx re f CLO CK R EC O V. + M U L T IP L IE R (4 .0 9 6 M H z ) DATA 8 IN 8 OUT 155M Hz TX 155M Hz RX S E R IA L D A T A IN RX CLK 1 9 .4 4 M H z P A R . D A T A IN O /E & E /O S E R IA L D A T A O U T O F F -T H E -S H E L F 1 5 5 M b /s S /P & P /S CON VERTER TX 8 KH z M T90840 d e v ic e P A R .D A T A OU T TX C LK 1 9 .4 4 M H z AD c o n t ro l HO ST B us Figure 3 - Example of a 155 Mb/s Backbone Access Module 2-191 MT90840 Notes: 2-192 Advance Information