MOSEL VITELIC V53C16126H HIGH PERFORMANCE 128K X 16 BIT FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE 30 35 40 45 50 Max. RAS Access Time, (tRAC) 30 ns 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (tCAA) 16 ns 18 ns 20 ns 22 ns 24 ns Min. Fast Page Mode Cycle Time, (tPC) 19 ns 21 ns 23 ns 25 ns 28 ns Min. Read/Write Cycle Time, (tRC) 65 ns 70 ns 75 ns 80 ns 90 ns Features Description ■ 128K x 16-bit organization ■ Fast Page Mode for a sustained data rate of 53 MHz ■ RAS access time: 30, 35, 40, 45, 50ns ■ Dual CAS Inputs ■ Low Power Dissipation ■ Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh ■ Refresh Interval: 512 cycles/8 ms ■ Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages ■ Single +5V±10% Power Supply ■ TTL Interface The V53C16126H is a 131,072 x 16 bit high performance CMOS dynamic random access memory. The V53C16126H offers Fast Page mode with dual CAS inputs. The V53C16126H has asymmetric address, 9-bit row and 8-bit column. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256 x 16 bits, within a page, with cycle times as short as 19ns. The V53C16126H is ideally suited for a wide variety of high performance computer systems and peripheral applications. Device Usage Chart Operating Temperature Range 0°C to 70°C Package Outline Access Time (ns) Power K T 30 35 40 45 50 Std. Temperature Mark • • • • • • • • Blank V53C16126H Rev. 1.3 February 1998 1 V53C16126H MOSEL VITELIC V 5 3 C 16 1 FAMILY Description Pkg. Pin Count SOJ K 40 TSOP-II T 40/44L 40-Pin Plastic SOJ PIN CONFIGURATION Top View 2 6 H DEVICE PKG SPEED ( t RAC) K (SOJ) T (TSOP-II) TEMP. PWR. BLANK (0°C to 70°C) BLANK (NORMAL) 30 35 40 45 50 (30 ns) (35 ns) (40 ns) (45 ns) (50 ns) 16126H-01 40/44L-Pin Plastic TSOP-II PIN CONFIGURATION Top View Pin Names Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss 16126H-02 Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss A0–A8 Address Inputs RAS Row Address Strobe UCAS Column Address Strobe/Upper Byte Control LCAS Column Address Strobe/Lower Byte Control WE Write Enable OE Output Enable I/O1–I/O16 Data Input, Output VCC +5V Supply VSS 0V Supply NC No Connect 16126H-03 Absolute Maximum Ratings* Capacitance* TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V Ambient Temperature Under Bias ................................ –10°C to +80°C Storage Temperature (plastic) ..... –55°C to +125°C Voltage Relative to VSS .................–1.0 V to +7.0 V Data Output Current ..................................... 50 mA Power Dissipation .......................................... 1.0 W Parameter Typ. Max. Unit CIN1 Address Input 3 4 pF CIN2 RAS, CAS, WE, OE 4 5 pF COUT Data Input/Output 5 7 pF *Note: Capacitance is sampled and not 100% tested *Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. V53C16126H Rev. 1.3 February 1998 Symbol 2 V53C16126H MOSEL VITELIC Block Diagram 128K x 16 OE WE UCAS LCAS RAS RAS CLOCK GENERATOR CAS CLOCK GENERATOR WE CLOCK GENERATOR OE CLOCK GENERATOR VCC VSS I/O 1 DATA I/O BUS I/O2 COLUMN DECODERS Y0–Y7 I/O3 I/O BUFFER I/O4 I/O 5 SENSE AMPLIFIERS I/O6 REFRESH COUNTER I/O7 I/O8 I/O 9 256 x 16 A1 • • • A7 A8 V53C16126H Rev. 1.3 February 1998 I/O10 I/O11 X0– X8 ROW DECODERS A0 ADDRESS BUFFERS AND PREDECODERS 9 I/O12 I/O 13 512 MEMORY ARRAY I/O14 I/O15 I/O16 512 x 256 x 16 16126H-04 3 V53C16126H MOSEL VITELIC DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified. Symbol Parameter Access Time V53C16126H Min. Typ. Max. Unit Test Conditions Notes ILI Input Leakage Current (any input pin) –10 10 µA VSS ≤ VIN ≤ VCC ILO Output Leakage Current (for High-Z State) –10 10 µA VSS ≤ VOUT ≤ VCC RAS, CAS at VIH ICC1 VCC Supply Current, Operating 30 200 mA tRC = tRC (min.) 35 190 40 180 45 170 50 160 2 mA RAS, CAS at VIH, other inputs ≥ VSS 30 200 mA tRC = tRC (min.) 2 35 190 40 180 45 170 50 160 30 190 mA Minimum Cycle 1, 2 35 180 40 170 45 160 50 150 ICC2 VCC Supply Current, TTL Standby ICC3 VCC Supply Current, RAS-Only Refresh ICC4 VCC Supply Current, Fast Page Mode Operation 1, 2 ICC5 VCC Supply Current, Standby Output Enable other inputs ≥ VSS 2 mA RAS = VIH CAS = VIL ICC6 VCC Supply Current, CMOS Standby 1 mA RAS ≥ VCC – 0.2 V, CAS ≥ VCC – 0.2 V, All other inputs ≥ VSS VCC Supply Voltage 4.5 5.5 V VIL Input Low Voltage –1 0.8 V 3 VIH Input High Voltage 2.4 VCC + 1 V 3 VOL Output Low Voltage 0.4 V IOL = 4.2 mA VOH Output High Voltage 2.4 V IOH = –5 mA V53C16126H Rev. 1.3 February 1998 2.4 4 1 V53C16126H MOSEL VITELIC AC Characteristics TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V 30 35 40 45 50 # Symbol Parameter 1 tRAS RAS Pulse Width 30 2 tRC Read or Write Cycle Time 65 70 75 80 90 ns 3 tRP RAS Precharge Time 25 25 25 25 30 ns 4 tCSH CAS Hold Time 30 35 40 45 50 ns 5 tCAS CAS Pulse Width 5 6 7 8 9 ns 6 tRCD RAS to CAS Delay 15 7 tRCS Read Command Setup Time 0 0 0 0 0 ns 8 tASR Row Address Setup Time 0 0 0 0 0 ns 9 tRAH Row Address Hold Time 5 6 7 8 9 ns 10 tASC Column Address Setup Time 0 0 0 0 0 ns 11 tCAH Column Address Hold Time 5 5 5 6 7 ns 12 tRSH (R) RAS Hold Time (Read Cycle) 10 10 10 10 10 ns 13 tCRP CAS to RAS Precharge Time 5 5 5 5 5 ns 14 tRCH Read Command Hold Time Referenced to CAS 0 0 0 0 0 ns 5 15 tRRH Read Command Hold Time Referenced to RAS 0 0 0 0 0 ns 5 16 tROH RAS Hold Time Referenced to OE 6 7 8 9 10 ns 17 tOAC Access Time from OE 10 11 12 13 14 ns 12 18 tCAC Access Time from CAS 10 11 12 13 14 ns 6,7,14 19 tRAC Access Time from RAS 30 35 40 45 50 ns 6, 8, 9 20 tCAA Access Time from Column Address 16 18 20 22 24 ns 6,7,10 21 tLZ OE or CAS to Low-Z Output 0 ns 16 22 tHZ OE or CAS to High-Z Output 0 ns 16 23 tAR Column Address Hold Time from RAS 26 24 tRAD RAS to Column Address Delay Time 10 25 tRSH (W) RAS or CAS Hold Time in Write Cycle 10 10 10 10 10 ns 26 tCWL Write Command to CAS Lead Time 10 11 12 13 14 ns 27 tWCS Write Command Setup Time 0 0 0 0 0 ns 28 tWCH Write Command Hold Time 5 5 5 6 7 ns V53C16126H Rev. 1.3 February 1998 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes 75K 20 35 16 75K 24 0 5 0 11 5 17 75K 28 0 6 28 14 40 0 12 18 75K 32 0 6 30 17 45 0 13 19 75K 36 0 7 35 20 50 0 8 40 23 14 ns ns 4 ns 26 ns 11 12, 13 V53C16126H MOSEL VITELIC AC Characteristics (Cont’d) 30 35 40 45 50 # Symbol Parameter 29 tWP Write Pulse Width 5 5 5 6 7 ns 30 tWCR Write Command Hold Time from RAS 26 28 30 35 40 ns 31 tRWL Write Command to RAS Lead Time 10 11 12 13 14 ns 32 tDS Data in Setup Time 0 0 0 0 0 ns 14 33 tDH Data in Hold Time 5 5 5 6 7 ns 14 34 tWOH Write to OE Hold Time 5 5 6 7 8 ns 14 35 tOED OE to Data Delay Time 5 5 6 7 8 ns 14 36 tRWC Read-Modify-Write Cycle Time 100 105 110 115 130 ns 37 tRRW Read-Modify-Write Cycle RAS Pulse Width 65 70 75 80 87 ns 38 tCWD CAS to WE Delay 26 28 30 32 34 ns 12 39 tRWD RAS to WE Delay in ReadModify-Write Cycle 50 54 58 62 68 ns 12 40 tCRW CAS Pulse Width (RMW) 44 46 48 50 52 ns 41 tAWD Col. Address to WE Delay 32 35 38 41 42 ns 42 tPC Fast Page Mode Read or Write Cycle Time 19 21 23 25 28 ns 43 tCP CAS Precharge Time 3 4 5 6 7 ns 44 tCAR Column Address to RAS Setup Time 16 18 20 22 24 ns 45 tCAP Access Time from Column Precharge 46 tDHR Data in Hold Time Referenced to RAS 26 28 30 35 40 ns 47 tCSR CAS Setup Time CAS- beforeRAS Refresh 10 10 10 10 10 ns 48 tRPC RAS to CAS Precharge Time 0 0 0 0 0 ns 49 tCHR CAS Hold Time CAS-beforeRAS Refresh 7 8 8 10 12 ns 50 tPCM Fast Page Mode Read-ModifyWrite Cycle Time 56 58 60 65 70 ns 51 tT Transition Time (Rise and Fall) 1.5 52 tREF Refresh Interval (512 Cycles) V53C16126H Rev. 1.3 February 1998 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes 19 50 21 1.5 8 50 8 6 23 1.5 50 8 25 1.5 50 8 27 1.5 ns 12 7 50 ns 15 8 ms 17 V53C16126H MOSEL VITELIC Notes: 1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in Fast Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to one TTL input and 100 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD ≥ tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. V53C16126H Rev. 1.3 February 1998 7 V53C16126H MOSEL VITELIC Truth Table RAS LCAS UCAS WE OE ADDRESS Standby H H H X X X Read: Word L L L H L ROW/COL Data Out Read: Lower Byte L L H H L ROW/COL Lower Byte, Data-Out Upper Byte, High-Z Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z Upper Byte, Data-Out Write: Word (Early-Write) L L L L X ROW/COL Data-In Write: Lower Byte (Early) L L H L X ROW/COL Lower Byte, Data-In Upper Byte, High-Z Read: Upper Byte (Early) L H L L X ROW/COL Lower Byte, High-Z Upper Byte, Data-In Read-Write L L L H→L L→H ROW/COL Data-Out, Data-In Page-Mode Read L H→L H→L H L COL Data-Out 2 Page-Mode Write L H→L H→L L X COL Data-In 2 Page-Mode Read-Write L H→L H→L H→L L→H COL Data-Out, Data-In L→H→L L L H L ROW/COL L H H X X ROW High-Z H→L L L X X X High-Z Function Hidden Refresh Read RAS-Only Refresh CBR Refresh Notes: 1. Byte Write cycles LCAS or UCAS active. 2. Byte Read cycles LCAS or UCAS active. 3. Only one of the two CAS must be active (LCAS or UCAS). V53C16126H Rev. 1.3 February 1998 8 I/O Notes High-Z Data-Out 1,2 1,2 2 3 V53C16126H MOSEL VITELIC Waveforms of Read Cycle t RC (2) t RAS (1) RAS t RP (3) t AR (23) VIH VIL t CSH (4) t CRP (13) UCAS, LCAS t RCD (6) VIL t CRP (13) t RAD (24) t RAH (9) t ASR (8) ADDRESS t RSH (R)(12) t CAS (5) VIH VIH ROW ADDRESS VIL t CAH (11) t ASC (10) COLUMN ADDRESS t RCH (14) t CAR (44) t RCS (7) WE t RRH (15) VIH VIL t ROH (16) t CAA (20) OE t OAC (17) VIH VIL t CAC (18) t RAC (19) I/O t HZ (22) t HZ (22) VOH VALID DATA-OUT VOL t LZ (21) 16126H-05 Waveforms of Early Write Cycle t RC (2) t RAS (1) RAS t RP (3) t AR (23) V IH V IL t CSH (4) t CRP (13) UCAS, LCAS t RCD (6) t RSH (W)(25) t CAS (5) V IH V IL t CAR (44) t CAH (11) t RAH (9) t ASR (8) ADDRESS t CRP (13) V IH V IL t ASC (10) ROW ADDRESS COLUMN ADDRESS t WCH (28) t RAD (24) t CWL (26) WE t WP (29) t WCS (27) V IH V IL t WCR (30) t RWL (31) OE V IH V IL t DHR (46) t DS (32) I/O V IH V IL t DH (33) VALID DATA-IN HIGH-Z 16126H-06 Don’t Care V53C16126H Rev. 1.3 February 1998 9 Undefined V53C16126H MOSEL VITELIC Waveforms of OE-Controlled Write Cycle t RC (2) t RAS (1) RAS t RP (3) t AR (23) VIH V IL t CSH (4) t CRP (13) t RCD (6) t RSH (W)(12) t CAS (5) V IH UCAS, LCAS V IL t RAD (24) t RAH (9) t ASR (8) ADDRESS t CRP (13) V IH t ASC (10) ROW ADDRESS V IL t CAR (44) t CAH (11) COLUMN ADDRESS t CWL (26) t RWL (31) t WP (29) WE V IH V IL t WOH (34) OE V IH V IL t OED (35) I/O t DH (33) t DS (32) V IH VALID DATA-IN V IL 16126H-07 Waveforms of Read-Modify-Write Cycle t RWC (36) tRRW (37) RAS t RP (3) t AR (23) VIH VIL t CSH (4) t CRP (13) t RCD (6) t RSH (W)(25) t CRW (40) VIH UCAS, LCAS VIL t t RAH (9) VIH VIL ROW ADDRESS COLUMN ADDRESS t AWD (41) t CWD (38) t RAD (24) t RWD (39) WE OE CAH (11) t ASC (10) t ASR (8) ADDRESS t CRP (13) t RWL (31) t WP (29) VIH VIL t CAA (20) t OAC (17) VIH VIL t OED (35) t CAC (18) t RAC (19) I/O t CWL (26) t DH (33) t HZ (22) t DS (32) VIH VOH VALID DATA-OUT VIL VOL VALID DATA-IN t LZ (21) 16126H-08 Don’t Care V53C16126H Rev. 1.3 February 1998 10 Undefined V53C16126H MOSEL VITELIC Waveforms of Fast Page Mode Read Cycle RAS t PC (42) t CP (43) t CSH (4) t RAH (9) t ASC (10) V IH ROW ADDRESS t CAR (44) t ASC (10) t CAH (11) t CAH (11) COLUMN ADDRESS COLUMN ADDRESS t RCH (14) t CAH (11) t RCS (7) COLUMN ADDRESS t RCS (7) t RCS (7) V IL t CAA (20) t CAA (20) t CAP (45) t OAC (17) t RRH (15) t OAC (17) V IH V IL t HZ (22) t RAC (19) t CAC (18) t LZ (21) t CAC (18) t CAC (18) t LZ (21) t HZ (22) t LZ (21) I/O t RCH (14) V IH t OAC (17) OE t CRP (13) t CAS (5) t CAS (5) V IL V IL WE t RSH (R)(12) t CAS (5) V IH t ASR (8) ADDRESS RP (3) V IL t RCD (6) t CRP (13) UCAS, LCAS t t RASP (37) t AR (23) V IH V OH VALID DATA OUT V OL t HZ (22) t HZ (22) t HZ (22) t HZ (22) VALID DATA OUT VALID DATA OUT 16126H-09 Waveforms of Fast Page Mode Write Cycle t RP (3) t AR (23) RAS t RASP (37) V IH V IL t CRP (13) t RCD (6) UCAS, LCAS t PC (42) t CP (43) t CAS (5) V IH t CSH (4) t ASC (10) t ASR (8) V IH ROW ADD V IL t ASC (10) t CAH (11) t CRP (13) COLUMN ADDRESS t CWL (26) t WCS (27) t CAR (44) t CAH (11) COLUMN ADDRESS t RAD (24) t WCS (27) t WCH (28) t CAH (11) COLUMN ADDRESS t CWL (26) t WCS (27) t CWL (26) t WCH (28) t RWL (31) t WCH (28) t WP (29) t WP (29) t WP (29) WE t CAS (5) t CAS (5) V IL t RAH (9) ADDRESS t RSH (W)(25) V IH V IL OE VIH V IL I/O V IH V IL t DS (32) t DH (33) t DS (32) t DH (33) t DS (32) VALID DATA IN VALID DATA IN OPEN t DH (33) VALID DATA IN OPEN 16126H-10 Don’t Care V53C16126H Rev. 1.3 February 1998 11 Undefined V53C16126H MOSEL VITELIC Waveforms of Fast Page Mode Read-Write Cycle RAS t RASP (37) VIH V IL t CSH (4) t RCD (6) t PCM (50) IH V t RSH (W)(25) t CRP (13) t CAS (5) t CP (43) t CAS (5) V UCAS, LCAS t RP (3) t CAS (5) t RAD (24) IL t RAH (9) t ASC (10) t ASR (8) V ADDRESS IH IL t CAH (11) COLUMN ADDRESS t CAH (11) COLUMN ADDRESS t RWD (39) t RCS (7) t CAR (44) t ASC (10) t CAH (11) ROW ADD V t ASC (10) t CWL (26) t CWD (38) COLUMN ADDRESS t CWD (38) t CWD (38) t RWL (31) t CWL (26) t CWL (26) V WE IH V IL t CAA (20) t OAC (17) t AWD (41) t AWD (41) t AWD (41) t WP (29) t WP (29) t WP (29) t OAC (17) t OAC (17) V OE IH V IL t CAA (20) t OED (35) t CAC (18) t RAC (19) t CAP (43) t CAP (43) t CAA (20) t OED (35) t CAC (18) t HZ (22) t HZ (22) t DH (33) t DH (33) t DS (32) t DS (32) I/O V I/OH OUT V I/OL OUT IN t LZ (21) t LZ (21) t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32) OUT IN t LZ (21) IN 16126H-11 Waveforms of RAS-Only Refresh Cycle t RC (2) RAS t RAS (1) V IH t RP (3) V IL t CRP (13) UCAS, LCAS V IH V IL t ASR (8) ADDRESS V IH t RAH (9) ROW ADDR V IL 16126H-12 NOTE: WE, OE = Don’t care Don’t Care V53C16126H Rev. 1.3 February 1998 12 Undefined V53C16126H MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Counter Test Cycle t RAS (1) RAS t RP (3) V IH V IL t CSR (47) t CHR (49) t RSH (W)(25) t CAS (5) t CP (43) V IH UCAS, LCAS V IL ADDRESS V IH V IL READ WE t RRH (15) t RCH (14) t RCS (7) V IH V IL t ROH (16) t OAC (17) OE V IH V IL t HZ (22) t HZ (22) t LZ (21) I/O V IH D OUT V IL t RWL (31) t CWL (26) WRITE WE t WCH (28) t WCS (27) V IH V IL OE V IH V IL t I/O t DH (33) DS (32) V IH D IN V IL 16126H-13 Waveforms of CAS-before-RAS Refresh Cycle t RC (2) t RP (3) RAS t RAS (1) t RP (3) VIH VIL t RPC (48) t CP (43) t CHR (49) t CSR (47) CAS VIH V IL t HZ (22) I/O VOH VOL 16126H-14 NOTE: WE, OE, A 0 –A 8 = Don’t care Don’t Care V53C16126H Rev. 1.3 February 1998 13 Undefined V53C16126H MOSEL VITELIC Waveforms of Hidden Refresh Cycle (Read) t RC (2) RAS t RC (2) tRP (3) t RAS (1) t AR (23) V IH t RP (3) t RAS (1) V IL t RCD (6) t CRP (13) UCAS, LCAS t CRP (13) V IL V IH t RAD (24) t ASC (10) t CAH (11) COLUMN ADDRESS ROW ADD V IL t RCS (7) WE t CHR (49) V IH t ASR (8) t RAH (9) ADDRESS t RSH (R)(12) t RRH (15) V IH V IL t CAA (20) t OAC (17) OE V IH V IL t CAC (18) t LZ (21) t RAC (19) t HZ (22) t HZ (22) V OH I/O VALID DATA V OL 16126H-15 Waveforms of Hidden Refresh Cycle (Write) t RC (2) V IH RAS t RAS (1) t RP (3) V IL t RCD (6) t CRP (13) UCAS, LCAS t RC (2) t RP (3) t RAS (1) t AR (23) t RSH (12) t CHR (49) t CRP (13) V IH V IL t RAD (24) t ASC (10) t ASR (8) t RAH (9) ADDRESS V IH V IL t CAH (11) ROW ADD COLUMN ADDRESS t WCH (28) t WCS (27) WE V IH V IL V IH OE V IL t DS (32) V IH I/O V IL t DH (33) VALID DATA-IN t DHR (46) 16126H-16 Don’t Care V53C16126H Rev. 1.3 February 1998 14 Undefined V53C16126H MOSEL VITELIC Functional Description whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAS-controlled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied. The V53C16126H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C16126H reads and writes data by multiplexing an 17-bit address into a 9-bit row and a 8-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address “flows through” an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time. Refresh Cycle To retain data, 512 Refresh Cycles are required in each 8 ms period. There are two ways to refresh the memory: Memory Cycle A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP /t CP has elapsed. 1. By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any Read, Write, Read-Modify-Write or RASonly cycle refreshes the addressed row. 2. Using a CAS-before-RAS Refresh Cycle. If CAS makes a transition from low to high to low after the previous cycle and before RAS falls, CASb e f o r e -R A S r e f r e s h i s a c t i v a t e d . T h e V53C8256H uses the output of an internal 9-bit counter as the source of row addresses and ignore external address inputs. Read Cycle A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC , t RAC , t CAA and t CAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied. CAS-before-RAS is a “refresh-only” mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. A CAS-before-RAS counter test mode is provided to ensure reliable operation of the internal refresh counter. Write Cycle A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on V53C16126H Rev. 1.3 February 1998 15 V53C16126H MOSEL VITELIC Fast Page Mode Operation also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied. Fast Page Mode operation permits all 256 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flowthrough latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer and acts as an output enable. During Fast Page Mode operation, Read, Write, Read-ModifyWrite or Read-Write-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Fast Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA . In both cases, the falling edge of CAS latches the address and enables the output. Fast Page Mode provides sustained data rates up to 53 MHz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C16126H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ID D will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges. Table 1. V53C16126H Data Output Operation for Various Cycle Types 256 Data Rate = ---------------------------------------t RC + 255 × t PC Data Output Operation The V53C16126H Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal has no effect on any data stored in the output latches. A WE low level can V53C16126H Rev. 1.3 February 1998 16 Cycle Type I/O State Read Cycles Data from Addressed Memory Cell CAS-Controlled Write Cycle (Early Write) High-Z WE-Controlled Write Cycle (Late Write) OE Controlled. High OE = High-Z I/Os Read-Modify-Write Cycles Data from Addressed Memory Cell Fast Page Mode Read Data from Addressed Memory Cell Fast Page Mode Write Cycle (Early Write) High-Z Fast Page Mode Read-ModifyWrite Cycle Data from Addressed Memory Cell RAS-only Refresh High-Z CAS-before-RAS Refresh Cycle Data remains as in previous cycle CAS-only Cycles High-Z V53C16126H MOSEL VITELIC Package Outlines 40-Pin Plastic SOJ Unit in inches [mm] 20 0.026 MIN [0.660 MIN] +0.004 0.025 –0.002 +0.102 0.635 –0.051 0.368 ± 0.010 [9.35 ± 0.254] 1 0.010 0.144 MAX [3.66 MAX] 21 0.400 ±0.005 [10.16 ± 0.127] 40 0.440 ±0.005 [11.18 ± 0.127] 1.025 TYP. (1.035 MAX.) [26.04 TYP. (26.29 MAX.)] + 0.004 – 0.002 +0.102 0.254 –0.051 0.04 [0.1] 0.050 ± 0.006 [1.27 ± 0.152] 0.018 +0.004 –0.002 +0.102 0.457 –0.051 40/44L-Pin TSOP-II 40 21 1 20 0°–5° 0.0315 BSC [.8001 BSC] 0.012 – 0.016 [0.305 – 0.406] 0.039 – 0.047 [0.991 – 1.193] 0.002 – 0.008 [0.051 – 0.203] BASE PLANE SEATING PLANE 0.721 – 0.729 [18.31 – 18.52] V53C16126H Rev. 1.3 February 1998 17 Unit in inches [mm] 0.017 – 0.023 [0.432 – 0.584] 0.396 – 0.404 [10.06 – 10.26] 0.462 – 0.470 [11.73 – 11.94] 0.0047 – 0.0083 [0.119 – .211] MOSEL VITELIC WORLDWIDE OFFICES V53C16126H U.S.A. TAIWAN JAPAN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 011-886-2-545-1213 FAX: 011-886-2-545-1209 RM.302 ANNEX-G HIGASHI-NAKANO NAKANO-KU, TOKYO 164 PHONE: 011-81-03-3365-2851 FAX: 011-81-03-3365-2836 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 011-852-665-4883 FAX: 011-852-664-7535 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 011-886-35-783344 FAX: 011-886-35-792838 NORTHWESTERN SOUTHWESTERN CENTRAL & SOUTHEASTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 310-498-3314 FAX: 310-597-2174 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 © Copyright 1998, MOSEL VITELIC Inc. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC 2/98 Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461