MOSEL V53C318165A60

V53C318165A
3.3 VOLT 1M X 16 EDO PAGE MODE
CMOS DYNAMIC RAM
MOSEL VITELIC
HIGH PERFORMANCE
50
60
70
Max. RAS Access Time, (tRAC)
50 ns
60 ns
70 ns
Max. Column Address Access Time, (tCAA)
25 ns
30 ns
35 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC)
20 ns
25 ns
30 ns
Min. Read/Write Cycle Time, (tRC)
84 ns
104 ns
124 ns
Features
Description
■ 1M x 16-bit organization
■ EDO Page Mode for a sustained data rate
of 50 MHz
■ RAS access time: 50, 60, 70 ns
■ Dual CAS Inputs
■ Low power dissipation
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh, and
Self Refresh.
■ Refresh Interval: 1024 cycles/16 ms
■ Available in 42-pin 400 mil SOJ and 50/44-pin
400 mil TSOP-II
■ Single +3.3 V ±0.3 V Power Supply
■ TTL Interface
The V53C318165A is a 1048576 x 16 bit highperformance CMOS dynamic random access memory. The V53C318165A offers Page mode operation with Extended Data Output. The V53C318165A
has an symmetric address, 10-bit row and 10-bit
column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 16
bits, within a page, with cycle times as short as
20ns.
These features make the V53C318165A ideally
suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
0°C to 70 °C
V53C318165A Rev. 1.0 January 1998
Access Time (ns)
Power
K
T
50
60
70
Std.
Temperature
Mark
•
•
•
•
•
•
Blank
1
V53C318165A
MOSEL VITELIC
42-Pin Plastic SOJ
PIN CONFIGURATION
Top View
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
42
2
41
3
40
4
39
5
38
6
37
7
36
8
35
9
34
10
33
11
32
12
31
13
30
14
29
15
28
16
27
17
26
18
25
19
24
20
23
21
22
50/44-Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
311816500-02
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
NC
1
50
2
49
3
48
4
47
5
46
6
45
7
44
8
43
9
42
10
41
11
40
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
15
36
16
35
17
34
18
33
19
32
20
31
21
22
30
29
23
28
24
27
25
26
311816500-03
Pin Names
A0–A9
Row, Column Address Inputs
Description
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE
Write Enable
OE
Output Enable
I/O1–I/O16
Data Input, Output
VCC
+3.3V Supply
VSS
0V Supply
NC
No Connect
V53C318165A Rev. 1.0 January 1998
2
Pkg.
Pin Count
SOJ
K
42
TSOP-II
T
50
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
V53C318165A
MOSEL VITELIC
Absolute Maximum Ratings*
Capacitance*
Operating temperature range ..................0 to 70 °C
Storage temperature range ............... -55 to 150 °C
Soldering temperature ..................................260 °C
Soldering time...................................................10 s
Input/output voltage .... -0.5 to min (VCC+0.5, 4.6) V
Power supply voltage ........................-0.5V to 4.6 V
Power dissipation .......................................... 0.5 W
Data out current (short circuit) ...................... 50 mA
TA = 25°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V, f = 1 MHz
Symbol
Parameter
Min.
Max.
Unit
CIN1
Address Input
—
5
pF
CIN2
RAS, UCAS, LCAS,
WE, OE
—
7
pF
COUT
Data Input/Output
—
7
pF
*Note: Capacitance is sampled and not 100% tested.
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Block Diagram
1024 x 16
OE
WE
UCAS
LCAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
I/O 1
DATA I/O BUS
I/O2
I/O3
COLUMN DECODERS
I/O4
I/O 5
Y0–Y9
SENSE AMPLIFIERS
I/O6
REFRESH
COUNTER
I/O7
1024 x 16
A1
•
•
•
A8
A9
V53C318165A Rev. 1.0 January 1998
I/O8
I/O 9
I/O10
I/O11
X0– X9
ROW
DECODERS
A0
ADDRESS BUFFERS
AND PREDECODERS
12
I/O
BUFFER
1024
MEMORY
ARRAY
1024 x 1024 x 16
I/O12
I/O 13
I/O14
I/O15
I/O16
311816500-04
3
V53C318165A
MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V, tT = 2ns, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C318165A
Min.
Typ.
Max.
Unit
Test Conditions
Notes
ILI
Input Leakage Current
(any input pin)
–10
10
µA
VSS ≤ VIN ≤ VCC + 0.3V
1
ILO
Output Leakage Current
(for High-Z State)
–10
10
µA
VSS ≤ VOUT ≤ VCC + 0.3V
RAS, CAS at VIH
1
ICC1
VCC Supply Current,
Operating
50
200
mA
tRC = tRC (min.)
60
180
70
160
2
mA
RAS, CAS at VIH
other inputs ≥ VSS
50
200
mA
tRC = tRC (min.)
2, 4
60
180
70
160
50
90
mA
Minimum Cycle
2, 3, 4
60
75
70
60
RAS ≥ VCC – 0.2 V,
CAS ≥ VCC – 0.2 V
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
ICC4
VCC Supply Current,
EDO Page Mode
Operation
ICC5
VCC Supply Current,
CMOS Standby
1.0
mA
ICC6
Average Self Refresh Current
CBR cycle with tRAS > tRASS min.,
(L-version only)
CAS held low, WE = VCC – 0.2V,
Address and DIN = VCC – 0.2V
or 0.2V
1.0
mA
ICC7
VCC Supply Current,
during CAS-before-RAS Refresh
50
200
mA
60
180
70
160
tRC = tRC (min)
2, 3, 4
1
2, 4
VIL
Input Low Voltage
–0.5
0.8
V
1
VIH
Input High Voltage
2
VCC+0.5
V
1
VOL
Output Low Voltage
0.4
V
IOL = 2 mA
1
VOH
Output High Voltage
V
IOH = –2 mA
1
V53C318165A Rev. 1.0 January 1998
2.4
4
V53C318165A
MOSEL VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 3.3 V ±0.3 V, VSS = 0V, tT = 2ns unless otherwise noted
50
60
70
#
JEDEC
Symbol Symbol
Parameter
1
tRL1RH1
tRAS
RAS Pulse Width
50
2
tRL2RL2
tRC
Read or Write Cycle Time
84
104
124
ns
3
tRH2RL2
tRP
RAS Precharge Time
30
40
50
ns
4
tRL1CH1
tCSH
CAS Hold Time
40
50
60
ns
5
tCL1CH1
tCAS
CAS Pulse Width
8
10K
10
10K
12
10K
ns
6
tRL1CL1
tRCD
RAS to CAS Delay
12
37
14
45
14
53
ns
7
tWH2CL2
tRCS
Read Command Setup Time
0
0
0
ns
8
tAVRL2
tASR
Row Address Setup Time
0
0
0
ns
9
tRL1AX
tRAH
Row Address Hold Time
8
10
10
ns
10
tAVCL2
tASC
Column Address Setup Time
0
0
0
ns
11
tCL1AX
tCAH
Column Address Hold Time
8
10
12
ns
12
tCL1RH1(R) tRSH
RAS Hold Time
13
15
17
ns
13
tCH2RL2
tCRP
CAS to RAS Precharge Time
5
5
5
ns
14
tCH2WX
tRCH
Read Command Hold Time
Referenced to CAS
0
0
0
ns
9
15
tRH2WX
tRRH
Read Command Hold Time
Referenced to RAS
0
0
0
ns
9
16
tCL1
tCOH
Output Hold after CAS LOW
5
5
5
ns
17
tGL1QV
tOAC
Access Time from OE
13
15
17
ns
18
tCL1QV
tCAC
Access Time from CAS
13
15
17
ns
7, 12
19
tRL1QV
tRAC
Access Time from RAS
50
60
70
ns
7, 12
20
tAVQV
tCAA
Access Time from Column Address
25
30
35
ns
7, 13
21
tCL1QX
tCLZ
CAS to Low-Z Output
0
ns
7
22
tCH2QX
tOFF
Output Buffer Turnoff Delay
0
23
tCL1QZ
tDZC
Data to CAS Low Delay
0
24
tRL1AV
tRAD
RAS to Column Address Delay Time
10
25
12
30
12
35
ns
25
tGL2QZ
tOEZ
Output Buffer Turnoff Delay from OE
0
13
0
15
0
17
ns
26
tWL1CH1
tCWL
Write Command to CAS Lead Time
13
15
17
ns
27
tWL1CL2
tWCS
Write Command Setup Time
0
0
0
ns
28
tCL1WH1
tWCH
Write Command Hold Time
8
10
10
ns
29
tWL1WH1
tWP
Write Pulse Width
8
10
10
ns
30
tGL1QZ
tDEO
Data to OE Delay
0
0
0
ns
31
tWL1RH1
tRWL
Write Command to RAS Lead Time
13
15
17
ns
32
tDVWL2
tDS
Data in Setup Time
0
0
0
ns
V53C318165A Rev. 1.0 January 1998
Min. Max. Min. Max. Min. Max. Unit Notes
5
10K
60
10K
0
13
0
70
10K
0
15
0
0
17
0
ns
ns
ns
15
8
11
15
10
V53C318165A
MOSEL VITELIC
AC Characteristics (Cont’d)
50
60
70
#
JEDEC
Symbol Symbol
Parameter
33
tWL1DX
tDH
Data in Hold Time
8
10
12
ns
10
34
tWL1GL2
tWOH
Write to OE Hold Time
10
13
15
ns
10
35
tCH2RH2
tPRWC
EDO Page Mode Read-Write Cycle Time
58
68
77
ns
36
tRL2RL2
(RMW)
tRWC
Read-Modify-Write Cycle Time
113
138
162
ns
38
tCL1WL2
tCWD
CAS to WE Delay
27
32
36
ns
10
39
tRL1WL2
tRWD
RAS to WE Delay in Read-Modify-Write
Cycle
64
77
89
ns
10
40
tAVWL2
tAWD
Column Address to WE Delay
39
47
54
ns
10
41
tCL2CL2
tPC
EDO Page Mode Read or Write Cycle Time
20
25
30
ns
42
tCH2CL2
tCP
CAS Precharge Time
8
10
10
ns
43
tAVRH1
tCAR
Column Address to RAS Setup Time
25
30
35
ns
44
tCH2QV
tCAP
Access Time from Column Precharge
46
tCL1RL2
tCSR
CAS Setup Time CAS-before-RAS
Refresh
10
10
10
ns
47
tRH2CL2
tRPC
RAS to CAS Precharge Time
5
5
5
ns
48
tRL1CH1
tCHR
CAS Hold Time CAS-before-RAS Refresh
10
10
10
ns
50
tRH2CL2
tRASP
RAS Pulse Width (EDO Mode)
50
51
tRH2CL2
tRHCP
CAS Precharge Time to RAS Delay
27
32
37
ns
52
tRH2CL2
tCPWD
CAS Precharge Time to WE
41
49
56
ns
53
tRH2CL2
tCPT
CAS Precharge Time (CBR Counter Test)
35
40
40
ns
54
tRH2CL2
tWRP
Write to RAS Precharge time (CRB Cycle)
10
10
10
ns
55
tRH2CL2
tWRH
Write Hold time reference to RAS
(CRB Cycle)
10
10
10
ns
56
tRH2CL2
tCDD
CAS High to Data delay
10
13
15
ns
16
57
tRH2CL2
tODD
OE High to Data delay
10
13
15
ns
16
58
tT
tT
Transition Time (Rise and Fall)
1
tREF
Refresh Interval (1024 Cycles)
59
Min. Max. Min. Max. Min. Max. Unit Notes
27
200K
50
32
60
1
16
200K
50
37
70
1
16
200K
ns
6
ns
50
ns
16
ms
Self Refresh AC Characteristics
60
tRASS
RAS Pulse Width During Self Refresh
100K
100K
100K
ns
17
61
tRPS
RAS Precharge Time During Self Refresh
95
110
130
ns
17
62
tCHS
CAS Hold Time Width During Self Rerfresh
50
50
50
ns
17
V53C318165A Rev. 1.0 January 1998
6
V53C318165A
MOSEL VITELIC
Notes:
1. All voltage are referenced to VSS.
2. ICC1, ICC3, ICC4, and ICC7 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during an
EDO cycle (tHPC).
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of
8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL.
7. Measured with a load equivalent to 2 TTL gates and 50 pF (VOL = 0.8V and VOH = 2.0V).
8. tOFF (max.) and tOEZ (max.) define the time at which the outputs acheive the open-circuit condition and are not referenced to output voltage levels.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in
read-write cycles.
11. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain opencircuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.), and
tCPWD > tCPWD (min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If
neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
12. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only: if tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
13. Operation within the tRAD (max) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only: if tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA.
14. AC measurements assume tT = 2 ns.
15. Either tDZC or tDEO must be satisfied.
16. Either tCDD or tODD must be satisfied.
17. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR – Distributed/Burst; or CBR – Burst) over the refresh
interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit
from Self Refresh.
18. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
V53C318165A Rev. 1.0 January 1998
7
V53C318165A
MOSEL VITELIC
Waveforms of Read Cycle
tRC
tRAS
RAS
tRP
tAR
VIH
VIL
tCSH
tCRP
UCAS, LCAS
tRSH
tCAS
tRCD
VIH
VIL
tRAD
tRAH
tCAH
tASR
ADDRESS
tCRP
VIH
tASC
ROW ADDRESS
VIL
COLUMN ADDRESS
tCAR
tRCH
tRRH
tRCS
WE
OE
VIH
VIL
tCAA
tOAC
VIH
VIL
tDZC
tCDD
tCAC
tRAC
tDZO
I/O
tOFF
tOFZ
VOH
VALID DATA-IN
VALID DATA-OUT
VOL
tLZ
311816500-05
Waveforms of Early Write Cycle
tRC
tRAS
RAS
VIL
t CSH (4)
tCRP
UCAS, LCAS
t RCD (6)
VIH
tRSH
tCAS
tCRP
VIL
tCAR
tRAH
tCAH
tASR
ADDRESS
tRP
tAR
VIH
VIH
VIL
tASC
ROW ADDRESS
COLUMN ADDRESS
tRAD
tWCH
tCWL
tWP
WE
VIH
VIL
tWCR
tRWL
OE
VIH
VIL
tDHR
tDS
I/O
VIH
VIL
tDH
VALID DATA-IN
HIGH-Z
311816500-06
Don’t Care
V53C318165A Rev. 1.0 January 1998
8
Undefined
V53C318165A
MOSEL VITELIC
Waveforms of Write Cycle (OE Controlled Write)
tRC
tRAS
RAS
tRP
tAR
VIH
VIL
tCSH
tRCD
tCRP
UCAS, LCAS
tRSH
tCAS
VIH
VIL
tRAD
tRAH
tCAR
tCAH
tASR
ADDRESS
tCRP
VIH
tASC
ROW ADDRESS
VIL
ROW
ADDRESS
COLUMN ADDRESS
tCWL
tRWL
tWP
WE
VIH
VIL
tWOH
OE
VIH
VIL
tOED
tDH
tDS
I/O
VIH
VALID DATA-IN
VIL
311816500-07
Waveforms of Read-Modify-Write Cycle
tRWC
tRAS
RAS
tRP
tAR
VIH
VIL
tCSH
tCRP
UCAS, LCAS
tRCD
tRSH
tCAS
VIH
VIL
tRAH
tCAH
tASR
ADDRESS
VIH
tASC
ROW
ADDRESS
VIL
ROW
ADDRESS
COLUMN
ADDRESS
tAWD
tCWD
tRWD
tRAD
WE
OE
tCWL
tRWL
tWP
tDZO
VIH
tCAA
VIL
tOAC
VIH
VIL
tDZC
tOEZ
tRAC
VIH
VOH
VIL
VOL
tDH
tOED
tCAC
I/O
tCRP
tDS
VALID
DATA-OUT
VALID
DATA-IN
tLZ
311816500-08
Don’t Care
V53C318165A Rev. 1.0 January 1998
9
Undefined
V53C318165A
MOSEL VITELIC
Waveforms of EDO Page Mode Read Cycle
tRASP
RAS
VIL
tRCD
tRHCP
tPC
tCAS
VIH
tCAS
tCAS
VIL
tCSH
tCAR
tASC
tRAH
tASC
tASR
ADDRESS
VIH
tCAH
ROW
ADDRESS
VIL
COLUMN
ADDRESS
tRCH
tCAH
COLUMN
ADDRESS
tRCS
tRCH
tRCS
VIH
VIL
tCAA
tCAA
tCAP
tOAC
tOAC
OE
tCAH
COLUMN
ADDRESS
tRCS
WE
tCRP
tRSH(R)
tCP
tCRP
UCAS, LCAS
tRP
tAR
VIH
tRRH
tOAC
VIH
VIL
tHZ
tCAC
tRAC
tCAC
tCLZ
tCAC
tOFF
tOEZ
tLZ
tOEZ
tCOH
I/O
VOH
tOEZ
VALID
DATA OUT
VOL
VALID
DATA OUT
VALID
DATA OUT
311816500-09
Waveforms of EDO Page Mode Write Cycle
tRP
tAR
RAS
tRASP
VIH
VIL
tCRP
tRCD
UCAS, LCAS
tPC
tRSH
tCP
tCRP
tCAS
VIH
tCAS
tCAS
VIL
tCSH
tRAH
tCAR
tASC
tRAH
ADDRESS
VIH
ROW
ADD
VIL
tASC
tCAH
tCAH
COLUMN
ADDRESS
tRAD
COLUMN
ADDRESS
tCWL
COLUMN
ADDRESS
tCWL
tCWL
tWCS
tWCS
tWCS
tWCH
tWCH
tWP
WE
OE
tRWL
tWCH
tWP
tWP
VIH
VIL
VIH
VIL
tDS
tDS
tDS
I/O
tCAH
VIH
VIL
tDH
VALID
DATA IN
tDH
VALID
DATA IN
OPEN
tDH
VALID
DATA IN
OPEN
311816500-10
Don’t Care
V53C318165A Rev. 1.0 January 1998
10
Undefined
V53C318165A
MOSEL VITELIC
Waveforms of EDO Page Mode Read-Modify-Write Cycle
RAS
tRASP
VIH
VIL
tCSH
tRP
tRCD
tPCM
tRSH
tCRP
tCP
VIH
UCAS, LCAS
VIL
tCAS
tCAS
tCAS
tRAD
tRAH
tCAS
tASC
tASC
tASR
ADDRESS
VIH
tCAH
ROW
ADD
VIL
tASC
tCAH
COLUMN
ADDRESS
tCAH
COLUMN
ADDRESS
COLUMN
ADDRESS
tCPWD
tRWD
tCWD
tCWD
tCWL
tRCS
tRWD
tRWL
tCWL
tCWL
VIH
WE
VIL
tAWD
tWP
tOAC
OE
tAWD
tAWD
tCAA
tWP
tOAC
tWP
tOAC
VIH
VIL
tCAP
tCAP
tCAA
tODD
tCAA
tODD
tCAC
tODD
tCAC
tRAC
tCAC
tOEZ
tOEZ
tDH
tDS
I/O
VI/OH
OUT
VI/OL
tLZ
tOEZ
tDH
tDH
tDS
OUT
IN
tLZ
tDS
OUT
IN
tLZ
IN
311816500-11
Waveforms of RAS Only Refresh Cycle
tRC
tRP
RAS
tRAS
VIH
VIL
tCRP
UCAS, LCAS
VIH
VIL
tASR
ADDRESS
VIH
tRAH
ROW ADDR
VIL
I/O
VOH
HIGH-Z
VOL
311816500-12
NOTE:
WE, OE = Don’t care
Don’t Care
V53C318165A Rev. 1.0 January 1998
11
Undefined
V53C318165A
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
tRP
tRAS
RAS
VIH
VIL
tCHR
tRSH
tCAS
tCP
tCSR
VIH
UCAS, LCAS
ADDRESS
VIL
VIH
VIL
READ CYCLE
WE
tRRH
tRCH
tRCS
tWRP
VIH
VIL
tWRH
tOAC
OE
VIH
VIL
tCHZ
tOEZ
tLZ
I/O
VIH
DOUT
VIL
tRWL
tCWL
WRITE CYCLE
tWCS
tWRP
WE
tWCH
VIH
VIL
tWRH
OE
VIH
VIL
tDS
I/O
tDH
VIH
D IN
VIL
311816500-13
Waveforms of CAS-before-RAS Refresh Cycle
tRC
tRAS
tRP
RAS
tRP
VIH
VIL
tRPC
tCP
tCHR
tCSR
UCAS, LCAS
VIH
VIL
tOFF
I/O
VOH
VOL
311816500-14
NOTE: WE, OE, A0–A9 = Don’t care
Don’t Care
V53C318165A Rev. 1.0 January 1998
12
Undefined
V53C318165A
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
tRC
RAS
VIH
tRP
tRCD
tCHR
tRSH(R)
tCRP
VIL
tRAD
tASC
tRAH
VIH
tCAH
ROW
ADD
VIL
COLUMN
ADDRESS
tRCS
WE
tRP
VIH
tASR
ADDRESS
tRAS
VIL
tCRP
UCAS, LCAS
tRC
tRAS
tAR
tRRH
VIH
VIL
tCAA
tOAC
OE
VIH
VIL
tCAC
tCHZ
tLZ
tOEZ
tRAC
VOH
I/O
VALID DATA
VOL
311816500-15
Waveforms of Hidden Refresh Cycle (Write)
tRC
VIH
RAS
tRC
tRAS
tAR
tRP
tRAS
tRP
VIL
tRCD
tRSH(R)
tCHR
tCRP
tCRP
VIH
UCAS, LCAS
VIL
tRAD
tASC
tASR
tCAH
tRAH
ADDRESS
VIH
VIL
ROW
ADD
COLUMN
ADDRESS
tWCS
WE
OE
tWCH
VIH
VIL
VIH
VIL
tDS
tDH
VIH
I/O
VIL
VALID DATA-IN
311816500-16
tDHR
Don’t Care
V53C318165A Rev. 1.0 January 1998
13
Undefined
V53C318165A
MOSEL VITELIC
Waveforms of Self Refresh Cycle (optional)
tRP
RAS
VIH
VIL
tRASS
tRPS
tRPC
tCSR
tCP
UCAS, LCAS
ADDRESS
I/O
WE
OE
tRPC
tCHS
VIH
VIL
VIH
VIL
VOH
OPEN
VOL
VIH
VIL
VIH
VIL
311816500-17
Don’t Care
Undefined
Functional Description
Read Cycle
The V53C318165A is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional
dynamic RAM. The V53C318165A reads and writes
data by multiplexing an 20-bit address into a 10-bit
row and a 10-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only
when tOAC, tRAC, tCAA and tCAC are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For example, the access time is limited by tCAA when tRAC,
tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
V53C318165A Rev. 1.0 January 1998
14
V53C318165A
MOSEL VITELIC
Extended Data Output Page Mode
The Self Refresh mode is terminated by returning
the RAS clock to a high level for a specified (tRPS)
minimum time. After termination of the Self Refresh
cycle normal accesses to the device may be initiated immediately, poviding that subsequest refresh
cycles utilize the CAS before RAS (CBR) mode of
operation.
EDO Page operation permits all 1024 columns
within a selected row of the device to be randomly
accessed at a high data rate. Maintaining RAS low
while performing successive CAS cycles retains the
row address internally and eliminates the need to
reapply it for each cycle. The column address buffer
acts as a transparent or flow-through latch while
CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the
falling edge of CAS, eliminating tASC and tT from the
critical timing path. CAS latches the address into the
column address buffer. During EDO operation,
Read, Write, Read-Modify-Write or Read-WriteRead cycles are possible at random addresses
within a row. Following the initial entry cycle into
EDO Mode, access is tCAA or tCAP controlled. If the
column address is valid prior to the rising edge of
CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is
timed from the occurrence of a valid address and is
specified by tCAA. In both cases, the falling edge of
CAS latches the address and enables the output.
EDO provides a sustained data rate of 50 MHz for
applications that require high bandwidth such as
bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate
the maximum data rate:
Data Output Operation
The V53C318165A Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected
row address in the Memory Array. A RAS high transition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(tDS) to be satisfied.
1024
Data Rate = -------------------------------------------t RC + 1023 × t PC
Power-On
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C318165A is dependent on the input levels
of RAS and CAS. If RAS is low during Power-On,
the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS
and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
Self Refresh
Self Refresh mode provides internal refresh control signals to the DRAM during extended periods of
inactivity. Device operation in this mode provides
additional power savings and design ease by elimination of external refresh control signals. Self Refresh mode is initialed with a CAS before RAS
(CBR) Refresh cycle, holding both RAS low (tRASS)
and CAS low (tCHD) for a specified period. Both of
these parameters are specified with minimum values to guarantee entry into Self Refresh operation.
Once the device has been placed in to Self Refresh
mode the CAS clock is no longer required to maintain Self Refresh operation.
V53C318165A Rev. 1.0 January 1998
15
V53C318165A
MOSEL VITELIC
Table 1. V53C318165A Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write Cycle
(Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled. High
OE = High-Z I/Os
Read-Modify-Write Cycles
Data from Addressed
Memory Cell
EDO Read Cycle
Data from Addressed
Memory Cell
EDO Write Cycle (Early Write)
High-Z
EDO Read-Modify-Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
High-Z
CAS-only Cycles
High-Z
V53C318165A Rev. 1.0 January 1998
16
V53C318165A
MOSEL VITELIC
Package Diagrams
42-Pin 400 mil SOJ
0.017±0.004
[0.43 ±0.1]
.441 –0.006 [11.2 –0.15](1)
0.370±0.010 [9.4±0.25]
+0.005
0.008 –0.002
+0.12
0.2 –0.05
0.145 [3.68] MAX
0.045 [1.15] MIN
0.81 [.032] MAX
.406 –0.012(1)
[10.3 – 0.3]
21
0.088 ±0.004
[2.24 ±0.1]
1
.406 –0.012 [10.3 –0.3]
22
.441 ±0.006 [11.2 ±0.15]
1.08 –0.010 [27.41 –0.25]
42
0.004 [0.1]
0.05 [1.27]
1.0 [25.4]
(1) Does not include plastic or metal protrusion of 0.010 [0.25] max per side.
Unit in inches [mm]
50/44-Pin 400 mil TSOP-II
0.039 ± 0.002
[1 ± 0.05]
0.004±0.002
[0.1±0.05]
0.031 [0.8]
0.016 +0.002
–0.004
0.004 [0.1]
0.008 [0.2] M 44x
50
40
36
1
11
15
+0.08
0.15 –0.03
0.020±0.004
[0.5 ± 0.1]
26
25
1
Unit in inches [mm]
0.825±0.005
[20.95±0.13]
Does not include plastic or metal protrusion of 0.010 [0.25] max. per side
V53C318165A Rev. 1.0 January 1998
+0.003
0.006 –0.001
0.463±0.008
[11.76 ± 0.2]
0.4 +0.05
–0.1
1
0.047 Max
[1.2 Max]
0.4 ± 0.005
[10.16 ± 0.13]
17
MOSEL VITELIC
WORLDWIDE OFFICES
V53C318165A
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7F, NO. 102
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© Copyright 1998, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
1/98
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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