MOSEL V53C816H50

PRELIMINARY
MOSEL VITELIC
V53C816H
512K X 16 FAST PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
40
45
50
60
Max. RAS Access Time, (tRAC)
40 ns
45 ns
50 ns
60 ns
Max. Column Address Access Time, (tCAA)
20 ns
22 ns
24 ns
30 ns
Min. Fast Page Mode Cycle Time, (tPC)
23 ns
25 ns
28 ns
35 ns
Min. Read/Write Cycle Time, (tRC)
75 ns
80 ns
90 ns
110 ns
Features
Description
■ 512K x 16-bit organization
■ RAS access time: 40, 45, 50, 60 ns
■ Fast Page Mode for a sustained data rate
of 43 MHz
■ Dual CAS Inputs
■ Pin-to-Pin compatible with 256Kx16
■ Low power dissipation
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
■ Refresh Interval: 512 cycles/8 ms
■ Available in 40-pin 400 mil SOJ
■ Single +5V Power Supply
■ TTL Interface
The V53C816H is a 524,288 x 16 bit high-performance CMOS dynamic random access memory.
The V53C816H offers Fast Page mode with dual
CAS inputs. An address, CAS and RAS input capacitances are reduced to one half when the
256Kx16 DRAM is used to construct the same
memory density. The V53C816H has asymmetric
address, 10-bit row and 9-bit column.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512K x 16
bits, within a page, with cycle times as short as
23ns.
The V53C816H is best suited for graphics, and
buffer memory applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
K
40
45
50
60
Std.
Temperature
Mark
0°C to 70 °C
•
•
•
•
•
•
Blank
V53C816H Rev. 1.3 February 1999
Access Time (ns)
1
Power
V53C816H
MOSEL VITELIC
V 53
C
8
16
MOSEL-VITELIC
MANUFACTURED
H
K
HIGH
PERFORMANCE
53 = DRAM
C = CMOS PROCESS
SPEED
40 ns
45 ns
50 ns
60 ns
BLANK = 5V
8 = 8M-BIT
Description
SOJ
Pkg.
Pin Count
K
40
DATA WIDTH:
16 = 16-BIT FP
PACKAGE
TYPE
K = SOJ
816H-01
40-Pin SOJ
PIN CONFIGURATION
Top View
Vcc
I/O0
I/O1
I/O2
I/O3
Vcc
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
A9
A0
A1
A2
A3
Vcc
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
Pin Names
Vss
I/O15
I/O14
I/O13
I/O12
Vss
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
816H-02
V53C816H Rev. 1.3 February 1999
2
A0–A9
Address Inputs, A9 is effective with RAS
RAS
Row Address Strobe
UCAS
Column Address Strobe Upper Byte Control
LCAS
Column Address Strobe Lower Byte Control
WE
Write Enable
OE
Output Enable
I/O0–I/O15
Data Input, Output
VCC
+5V Supply
VSS
0V Supply
NC
No Connect
V53C816H
MOSEL VITELIC
Absolute Maximum Ratings*
Capacitance*
Ambient Temperature
Under Bias .............................. –10°C to +80°C
Storage Temperature (plastic) ..... –55°C to +125°C
Voltage Relative to VSS .................–1.0 V to +7.0 V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.4 W
TA = 25°C, VCC = 5 V ± 10%, f = 1 MHz
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Symbol
Parameter
Typ.
Max.
Unit
CIN1
Address Input
3
4
pF
CIN2
RAS, CAS, WE, OE
4
5
pF
COUT
Data Input/Output
5
7
pF
* Note: Capacitance is sampled and not 100% tested
Block Diagram
512K x16
OE
WE
UCAS
LCAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
I/O 0
DATA I/O BUS
I/O 1
I/O 2
COLUMN DECODERS
I/O 3
I/O 4
Y0 -Y 8
SENSE AMPLIFIERS
REFRESH
COUNTER
512 x 16
I/O 5
I/O
BUFFER
A1
•
•
•
A7
A8
A9
V53C816H Rev. 1.3 February 1999
I/O 7
I/O 8
I/O 9
I/O 10
X 0 -X 9
ROW
DECODERS
A0
ADDRESS BUFFERS
AND PREDECODERS
10
I/O 6
I/O 11
I/O 12
1024
MEMORY
ARRAY
512K x 16
I/O 13
I/O 14
I/O 15
816H-03
3
V53C816H
MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 5 V ± 5%, VSS = 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C816H
Min.
Typ.
Max.
Unit
Test Conditions
Notes
ILI
Input Leakage Current
(any input pin)
–10
10
µA
VSS ≤ VIN ≤ VCC
ILO
Output Leakage Current
(for High-Z State)
–10
10
µA
VSS≤ VOUT ≤ VCC
RAS, CAS at VIH
ICC1
VCC Supply Current, Operating
40
220
mA
tRC = tRC (min.)
45
210
50
200
60
190
4
mA
RAS, CAS at VIH
other inputs ≥ VSS
40
220
mA
tRC = tRC (min.)
2
45
210
50
200
60
190
40
210
mA
Minimum Cycle
1, 2
45
200
50
190
60
180
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
ICC4
VCC Supply Current,
Fast Page Mode Operation
1, 2
ICC5
VCC Supply Current,
Standby, Output Enabled
other inputs ≥ VSS
2.0
mA
RAS=VIH, CAS=VIL
ICC6
VCC Supply Current,
CMOS Standby
2.0
mA
RAS ≥ VCC – 0.2 V,
CAS ≥ VCC– 0.2 V,
All other inputs ≥ VSS
VCC
Supply Voltage
4.5
5.5
V
VIL
Input Low Voltage
–1
0.8
V
3
VIH
Input High Voltage
2.4
VCC+1
V
3
VOL
Output Low Voltage
0.4
V
IOL = 2.0 mA
VOH
Output High Voltage
V
IOH = –2.0 mA
V53C816H Rev. 1.3 February 1999
5.0
2.4
4
1
V53C816H
MOSEL VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
40
Parameter
45
50
60
#
Symbol
1
tRAS
RAS Pulse Width
40
2
tRC
Read or Write Cycle Time
75
80
90
110
ns
3
tRP
RAS Precharge Time
25
25
30
40
ns
4
tCSH
CAS Hold Time
40
45
50
60
ns
5
tCAS
CAS Pulse Width
12
13
14
15
ns
6
tRCD
RAS to CAS Delay
17
7
tRCS
Read Command Setup Time
0
0
0
0
ns
8
tASR
Row Address Setup Time
0
0
0
0
ns
9
tRAH
Row Address Hold Time
7
8
9
10
ns
10
tASC
Column Address Setup Time
0
0
0
0
ns
11
tCAH
Column Address Hold Time
5
6
7
10
ns
12
tRSH (R)
RAS Hold Time (Read Cycle)
12
13
14
15
ns
13
tCRP
CAS to RAS Precharge Time
5
5
5
5
ns
14
tRCH
Read Command Hold Time Referenced to
CAS
0
0
0
0
ns
5
15
tRRH
Read Command Hold Time Referenced to
RAS
0
0
0
0
ns
5
16
tROH
RAS Hold Time Referenced to OE
8
9
10
10
ns
17
tOAC
Access Time from OE
12
13
14
15
ns
18
tCAC
Access Time from CAS
12
13
14
15
ns
6, 7
19
tRAC
Access Time from RAS
40
45
50
60
ns
6, 8, 9
20
tCAA
Access Time from Column Address
20
22
24
30
ns
6, 7, 10
21
tLZ
OE or CAS to Low-Z Output
0
ns
16
22
tHZ
OE or CAS to High-Z Output
0
ns
16
23
tAR
Column Address Hold Time from RAS
30
24
tRAD
RAS to Column Address Delay Time
12
25
tRSH (W)
RAS or CAS Hold Time in Write Cycle
12
13
14
15
ns
26
tCWL
Write Command to CAS Lead Time
12
13
14
15
ns
27
tWCS
Write Command Setup Time
0
0
0
0
ns
28
tWCH
Write Command Hold Time
5
6
7
10
ns
29
tWP
Write Pulse Width
5
6
7
10
ns
30
tWCR
Write Command Hold Time from RAS
30
35
40
50
ns
31
tRWL
Write Command to RAS Lead Time
12
13
14
15
ns
V53C816H Rev. 1.3 February 1999
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
5
75
28
45
18
75K
32
0
6
0
13
19
75K
36
0
7
35
20
50
0
14
20
75K
45
0
8
40
23
60
0
10
50
26
15
ns
ns
4
ns
30
ns
11
12, 13
V53C816H
MOSEL VITELIC
AC Characteristics (Cont’d)
40
Parameter
45
50
60
#
Symbol
32
tDS
Data in Setup Time
0
0
0
0
ns
14
33
tDH
Data in Hold Time
5
6
7
10
ns
14
34
tWOH
Write to OE Hold Time
6
7
8
10
ns
14
35
tOED
OE to Data Delay Time
6
7
8
10
ns
14
36
tRWC
Read-Modify-Write Cycle Time
110
115
130
155
ns
37
tRRW
Read-Modify-Write Cycle RAS Pulse Width
75
80
87
105
ns
38
tCWD
CAS to WE Delay
30
32
34
40
ns
12
39
tRWD
RAS to WE Delay in Read-Modify-Write
Cycle
58
62
68
85
ns
12
40
tCRW
CAS Pulse Width (RMW)
48
50
52
65
ns
41
tAWD
Col. Address to WE Delay
38
41
42
58
ns
42
tPC
Fast Page Mode Read or Write Cycle Time
23
25
28
35
ns
43
tCP
CAS Precharge Time
5
6
7
10
ns
44
tCAR
Column Address to RAS Setup Time
20
22
24
30
ns
45
tCAP
Access Time from Column
Precharge
46
tDHR
Data in Hold Time Referenced to RAS
30
35
40
50
ns
47
tCSR
CAS Setup Time CAS-before-RAS
Refresh
10
10
10
10
ns
48
tRPC
RAS to CAS Precharge Time
0
0
0
0
ns
49
tCHR
CAS Hold Time CAS-before-RAS
Refresh
8
10
12
15
ns
50
tPCM
Fast Page Mode Read-Modify-Write Cycle
Time
60
65
70
85
ns
51
tT
Transition Time (Rise and Fall)
3
52
tREF
Refresh Interval (512 Cycles)
8
V53C816H Rev. 1.3 February 1999
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
22
6
50
24
3
8
50
27
3
8
50
34
3
16
50
ns
12
7
ns
15
8
17
V53C816H
MOSEL VITELIC
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is
measured with the output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a
maximum of two transitions per address cycle in Fast Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL input and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD
exceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C816H Rev. 1.3 February 1999
7
V53C816H
MOSEL VITELIC
Truth Table
Function
RAS
LCAS
UCAS
WE
OE
Standby
H
H
H
X
X
Read: Word
L
L
L
H
L
ROW/COL
Data Out
Read: Lower Byte
L
L
H
H
L
ROW/COL
Lower Byte, Data-Out
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, Data-Out
Write: Word (Early-Write)
L
L
L
L
X
ROW/COL
Data-In
Write: Lower Byte (Early)
L
L
H
L
X
ROW/COL
Lower Byte, Data-In
Upper Byte, High-Z
Read: Upper Byte (Early)
L
H
L
L
X
ROW/COL
Lower Byte, High-Z
Upper Byte, Data-In
Read-Write
L
L
L
H→L
L→H
ROW/COL
Data-Out, Data-In
Fast Page-Mode Read
L
H→L
H→L
H
L
COL
Data-Out
2
Fast Page-Mode Write
L
H→L
H→L
L
X
COL
Data-In
2
Fast Page-Mode Read-Write
L
H→L
H→L
H→L
L→H
COL
Data-Out, Data-In
L→H→L
L
L
H
L
ROW/COL
L
H
H
X
X
ROW
H→L
L
L
X
X
Hidden Refresh Read
RAS-Only Refresh
CBR Refresh
Notes:
1. Byte write cycles LCAS or UCAS active.
2. Byte Read cycles LCAS or UCAS active.
3. Only one of the two CAS must be active (LCAS or UCAS).
V53C816H Rev. 1.3 February 1999
8
ADDRESS I/O
Notes
High-Z
Data-Out
1, 2
1, 2
2
High-Z
High-Z
3
V53C816H
MOSEL VITELIC
Waveforms of Read Cycle
t RC (2)
RAS
t RAS (1)
tAR (23)
VIH
t RP (3)
V IL
t CSH (4)
t CRP (13)
CAS
tRCD (6)
V IL
t CRP (13)
t RAD (24)
t RAH (9)
t ASR (8)
ADDRESS
t RSH (R)(12)
t CAS (5)
V IH
V IH
ROW ADDRESS
V IL
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t RCH (14)
t CAR (44)
t RCS (7)
WE
t RRH (15)
V IH
V IL
t ROH (16)
t CAA (20)
OE
t OAC (17)
V IH
V IL
t CAC (18)
tRAC (19)
I/O
tHZ (22)
t HZ (22)
VOH
VALID DATA-OUT
VOL
t LZ (21)
816H-04
Waveforms of Early Write Cycle
t RC (2)
t RAS (1)
RAS
t RP (3)
tAR (23)
VIH
V IL
t CSH (4)
t CRP (13)
CAS
tRCD (6)
tRSH (W)(25)
t CAS (5)
VIH
V IL
t CAR (44)
t CAH (11)
t RAH (9)
t ASR (8)
ADDRESS
VIH
V IL
tASC (10)
ROW ADDRESS
COLUMN ADDRESS
t RAD (24)
WE
t CRP (13)
t CWL (26)
t WCH (28)
t WP(29)
t WCS (27)
VIH
V IL
t WCR (30)
t RWL (31)
OE
VIH
V IL
t DHR (46)
t DS (32)
I/O
VIH
V IL
t DH (33)
VALID DATA-IN
HIGH-Z
816H-05
Don’t Care
V53C816H Rev. 1.3 February 1999
9
Undefined
V53C816H
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
t RC (2)
t RAS (1)
RAS
V IL
t CSH (4)
t CRP (13)
CAS
t RCD (6)
t RSH (W)(12)
t CAS (5)
V IH
t CRP (13)
V IL
t RAD (24)
t RAH (9)
t CAR (44)
t CAH (11)
t ASR (8)
ADDRESS
t RP (3)
t AR (23)
VIH
t ASC (10)
V IH
ROW ADDRESS
V IL
COLUMN ADDRESS
t CWL (26)
t RWL (31)
t WP (29)
WE
V IH
V IL
t WOH (34)
OE
V IH
V IL
t OED (35)
I/O
t DH (33)
t DS (32)
V IH
VALID DATA-IN
V IL
816H-06
Waveforms of Read-Modify-Write Cycle
t RWC (36)
tRRW (37)
RAS
t RP (3)
t AR (23)
VIH
VIL
t CSH (4)
t CRP (13)
CAS
t RCD (6)
t RSH (W)(25)
t CRW (40)
VIH
VIL
t
t RAH (9)
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
t RAD (24)
t RWD (39)
WE
OE
CAH (11)
t ASC (10)
t ASR (8)
ADDRESS
t CRP (13)
t AWD (41)
t CWD (38)
t RWL (31)
t WP (29)
VIH
VIL
t CAA (20)
t OAC (17)
VIH
VIL
t OED (35)
t CAC (18)
t RAC (19)
I/O
t CWL (26)
t DH (33)
t HZ (22)
t DS (32)
VIH VOH
VALID
DATA-OUT
VIL VOL
VALID
DATA-IN
t LZ (21)
816H-07
Don’t Care
V53C816H Rev. 1.3 February 1999
10
Undefined
V53C816H
MOSEL VITELIC
Waveforms of Fast Page Mode Read Cycle
RAS
V IH
t PC (42)
t CP (43)
t CSH (4)
t RAH (9)
ROW
ADDRESS
t CAR (44)
t ASC (10)
t CAH (11)
t ASC (10)
V IH
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RCH (14)
t CAH (11)
t RCS (7)
COLUMN
ADDRESS
t RCS (7)
t RCS (7)
V IL
t CAA (20)
t CAA (20)
t CAP (45)
t OAC (17)
t RRH (15)
t OAC (17)
V IH
V IL
t HZ (22)
t RAC (19)
t CAC (18)
t LZ (21)
t CAC (18)
t CAC (18)
t LZ (21)
t HZ (22)
t LZ (21)
I/O
t RCH (14)
V IH
t OAC (17)
OE
t CRP (13)
t CAS (5)
t CAS (5)
V IL
V IL
WE
t RSH (R)(12)
t CAS (5)
V IH
t ASR (8)
ADDRESS
RP (3)
V IL
t RCD (6)
t CRP (13)
CAS
t
t RAS (1)
t AR (23)
V OH
VALID
DATA OUT
V OL
t HZ (22)
t HZ (22)
t HZ (22)
t HZ (22)
VALID
DATA OUT
VALID
DATA OUT
816H-08
Waveforms of Fast Page Mode Write Cycle
t RP (3)
t AR (23)
RAS
t RAS (1)
V IH
V IL
t CRP (13)
t RCD (6)
CAS
t PC (42)
t CP (43)
t CAS (5)
V IH
t CSH (4)
t ASC (10)
t ASR (8)
V IH
ROW
ADD
V IL
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WCS (27)
t WCH (28)
t WCS (27)
t CWL (26)
t WCH (28)
t RWL (31)
t WCH (28)
t WP (29)
t WP (29)
V IH
V IL
VIH
V IL
V IH
V IL
t DS (32)
t DH (33)
t DS (32)
t DH (33)
t DS (32)
I/O
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WP (29)
OE
t CRP (13)
t CAR (44)
t CAH (11)
COLUMN
ADDRESS
t RAD (24)
WE
t CAS (5)
t CAS (5)
V IL
t RAH (9)
ADDRESS
t RSH (W)(25)
VALID
DATA IN
VALID
DATA IN
OPEN
t DH (33)
VALID
DATA IN
OPEN
816H-09
Don’t Care
V53C816H Rev. 1.3 February 1999
11
Undefined
V53C816H
MOSEL VITELIC
Waveforms of Fast Page Mode Read-Write Cycle
RAS
t RAS (1)
VIH
V
IL
t CSH (4)
t RCD (6)
t PCM (50)
IH
V
t RSH (W)(25)
t CRP (13)
t CAS (5)
t CP (43)
t CAS (5)
V
CAS
t RP (3)
t CAS (5)
t RAD (24)
IL
t RAH (9)
t ASC (10)
t ASR (8)
V
ADDRESS
IH
IL
t CAH (11)
COLUMN
ADDRESS
t CAH (11)
COLUMN
ADDRESS
t RWD (39)
t RCS (7)
t CAR (44)
t ASC (10)
t CAH (11)
ROW
ADD
V
t ASC (10)
t CWL (26)
t CWD (38)
COLUMN
ADDRESS
t CWD (38)
t CWD (38)
t RWL (31)
t CWL (26)
t CWL (26)
V
WE
IH
V
IL
t CAA (20)
t OAC (17)
t AWD (41)
t AWD (41)
t AWD (41)
t WP (29)
t WP (29)
t WP (29)
t OAC (17)
t OAC (17)
V
OE
IH
V
IL
t CAA (20)
t OED (35)
t CAC (18)
t RAC (19)
t CAP (45)
t CAP (45)
t CAA (20)
t OED (35)
t CAC (18)
t HZ (22)
t HZ (22)
t DH (33)
t DH (33)
t DS (32)
t DS (32)
I/O
V I/OH
OUT
V I/OL
OUT
IN
t LZ (21)
t LZ (21)
t OED (35)
t CAC (18)
t HZ (22)
t DH (33)
t DS (32)
OUT
IN
t LZ (21)
IN
816H-10
Waveforms of RAS-Only Refresh Cycle
tRC (2)
RAS
t RAS (1)
VIH
tRP (3)
V IL
t CRP (13)
CAS
VIH
V IL
tASR (8)
ADDRESS
VIH
V IL
tRAH (9)
ROW ADDR
816H-11
NOTE: WE, OE = Don’t care
Don’t Care
V53C816H Rev. 1.3 February 1999
12
Undefined
V53C816H
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1)
RAS
VIH
V IL
t CSR (47)
CAS
ADDRESS
t RP (3)
t CHR (49)
t RSH (W)(25)
tCAS (5)
t CP(43)
VIH
V IL
VIH
V IL
READ CYCLE
WE
t RRH (15)
t RCH (14)
t RCS (7)
VIH
V IL
t ROH (16)
t OAC (17)
OE
VIH
V IL
t HZ (22)
t HZ (22)
t LZ (21)
I/O
VIH
DOUT
V IL
t RWL (31)
t CWL (26)
WRITE CYCLE
WE
OE
t WCH (28)
t WCS (27)
VIH
V IL
VIH
V IL
tDS (32)
I/O
t DH (33)
VIH
D IN
V IL
816H-12
Waveforms of CAS-before-RAS Refresh Cycle
t RC (2)
t RP (3)
RAS
t RP (3)
V IH
V IL
t CP (43)
CAS
t RAS (1)
t RPC (48)
t CSR (47)
t CHR (49)
V IH
V IL
t HZ (22)
I/O
V OH
V OL
816H-13
NOTE: WE, OE, A0–A8 = Don’t care
Don’t Care
V53C816H Rev. 1.3 February 1999
13
Undefined
V53C816H
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2)
RAS
V IH
t RSH (R)(12)
t CRP (13)
V IL
V IH
t RAD (24)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
ROW
ADD
V IL
t RCS (7)
WE
t CHR (49)
V IH
t ASR (8)
t RAH (9)
ADDRESS
t RP (3)
t RAS (1)
V IL
t RCD (6)
t CRP (13)
CAS
t RC (2)
tRP (3)
t RAS (1)
t AR (23)
t RRH (15)
V IH
V IL
t CAA (20)
t OAC (17)
OE
V IH
V IL
t CAC (18)
t LZ (21)
t RAC (19)
t HZ (22)
t HZ (22)
V OH
I/O
VALID DATA
V OL
816H-14
Waveforms of Hidden Refresh Cycle (Write)
t RC (2)
RAS
V IH
t RSH (12)
V IH
t CAH (11)
ROW
ADD
COLUMN
ADDRESS
t WCH (28)
V IH
V IL
V IH
V IL
t DS (32)
V IH
I/O
t CRP (13)
t RAD (24)
t ASC (10)
t WCS (27)
OE
t CHR (49)
V IL
V IL
WE
t RP (3)
V IH
t ASR (8)
t RAH (9)
ADDRESS
t RAS (1)
V IL
t RCD (6)
t CRP (13)
CAS
t RC (2)
t RP (3)
t RAS (1)
t AR (23)
V IL
t DH (33)
VALID DATA-IN
t DHR (46)
816H-15
Don’t Care
V53C816H Rev. 1.3 February 1999
14
Undefined
V53C816H
MOSEL VITELIC
Functional Description
Fast Page Mode Operation
The V53C816H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional
dynamic RAM. The V53C816H reads and writes
data by multiplexing an 19-bit address into a 10-bit
row and a 9-bit column address. The row address is
latched by the Row Address Strobe (RAS). The column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
Fast Page Mode operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining
RAS low while performing successive CAS cycles
retains the row address internally and eliminates the
need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through
latch while CAS is high. Thus, access begins from
the occurrence of a valid column address rather
than from the falling edge of CAS, eliminating tASC
and tT from the critical timing path. CAS latches the
address into the column address buffer and acts as
an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or ReadWrite-Read cycles are possible at random addresses within a row. Following the initial entry cycle into
Fast Page Mode, access is tCAA or tCAP controlled.
If the column address is valid prior to the rising edge
of CAS, the access time is referenced to the CAS
rising edge and is specified by tCAP. If the column
address is valid after the rising CAS edge, access
is timed from the occurrence of a valid address and
is specified by tCAA. In both cases, the falling edge
of CAS latches the address and enables the output.
Fast Page Mode provides a sustained data rate of
43 MHz for applications that require high data rates
such as bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only
when tOAC, tRAC, tCAA and tCAC are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For example, the access time is limited by tCAA when tRAC,
tCAC and tOAC are all satisfied.
512
Data Rate = ---------------------------------------t RC + 511 × t PC
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
V53C816H Rev. 1.3 February 1999
Data Output Operation
The V53C816H Input/Output is controlled by OE,
CAS, WE and RAS. A RAS low transition enables
the transfer of data to and from the selected row address in the Memory Array. A RAS high transition
disables data transfer and latches the output data if
the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition
or CAS low level enables the internal I/O path. A
CAS high transition or a CAS high level disables the
I/O path and the output driver if it is enabled. A CAS
low transition while RAS is high has no effect on the
I/O data path or on the output drivers. The output
drivers, when otherwise enabled, can be disabled
by holding OE high. The OE signal has no effect on
15
V53C816H
MOSEL VITELIC
Table 1. V53C816H Data Output
any data stored in the output latches. A WE low level can also disable the output drivers when CAS is
low. During a Write cycle, if WE goes low at a time
in relationship to CAS that would normally cause the
outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition
to allow Data In Setup Time (tDS) to be satisfied.
Operation for Various Cycle Types
Cycle Type
Power-On
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C816H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and ICC will exhibit
current transients. It is recommended that RAS and
CAS track with VCC or be held at a valid VIH during
Power-On to avoid current surges.
V53C816H Rev. 1.3 February 1999
16
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled. High
OE = High-Z I/Os
Read-Modify-Write Cycles
Data from Addressed
Memory Cell
Fast Page Mode Read
Data from Addressed
Memory Cell
Fast Page Mode Write
Cycle (Early Write)
High-Z
Fast Page Mode ReadModify-Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS Refresh
Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
V53C816H
MOSEL VITELIC
Package Diagram
40-Pin Plastic SOJ
Unit in inches [mm]
20
0.050 ± 0.006
[1.27 ± 0.152]
V53C816H Rev. 1.3 February 1999
0.026 MIN
[0.660 MIN]
+0.004
0.025 –0.002
+0.102
0.635 –0.051
0.04 [0.1]
0.018
+0.004
–0.002
+0.102
0.457 –0.051
17
0.368 ± 0.010
[9.35 ± 0.254]
1
0.144 MAX
[3.66 MAX]
21
0.400 ±0.005
[10.16 ± 0.127]
40
0.440 ±0.005
[11.18 ± 0.127]
1.025 TYP. (1.035 MAX.)
[26.04 TYP. (26.29 MAX.)]
0.010
+ 0.004
– 0.002
+0.102
0.254 –0.051
MOSEL VITELIC
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V53C816H
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© Copyright 1999, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
2/99
Printed in U.S.A.
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sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
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