MOSEL VITELIC PRELIMINARY V62C1164096 256K x 16, CMOS STATIC RAM Features Description ■ ■ ■ ■ ■ ■ ■ ■ The V62C1164096 is a 4,194,304-bit static random-access memory organized as 262,144 words by 16 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. High-speed: 85, 100 ns Ultra low CMOS standby current of 2µA (max.) Fully static operation All inputs and outputs directly TTL compatible Three state outputs Ultra low data retention current (VCC = 1.0V) Operating voltage: 1.8V – 2.3V Packages – 48-Ball CSP BGA (8mm x 10mm) Functional Block Diagram A0 VCC A6 Row Decoder GND 1024 x 4096 Memory Array A7 A8 A9 I/O1 Column I/O Input Data Circuit Column Decoder I/O16 A10 UBE LBE OE WE CE1 CE2 A17 Control Circuit Device Usage Chart Package Outline Operating Temperature Range Access Time (ns) Power B 85 100 L LL Temperature Mark 0°C to 70°C • • • • • Blank –40°C to +85°C • • • • I V62C1164096 Rev. 1.0 November 2001 1 MOSEL VITELIC V62C1164096 UBE, LBE Byte Enable Active low inputs. These inputs are used to enable the upper or lower data byte. Pin Descriptions A 0–A17 Address Inputs These 18 address inputs select one of the 256K x 16 bit segments in the RAM. Write Enable Input WE The write enable input is active LOW and controls read and write operations. With the chip enabled, when WE is HIGH and OE is LOW, output data will be present at the I/O pins; when WE is LOW and OE is HIGH, the data present on the I/O pins will be written into the selected memory locations. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. I/O1–I/O16 Data Input and Data Output Ports These 16 bidirectional ports are used to read data from and write data into the RAM. OE Output Enable Input The output enable input is active LOW. With the chip enabled, when OE is Low and WE High, data will be presented on the I/O pins. The I/O pins will be in the high impedance state when OE is High. VCC Power Supply GND Ground Pin Configurations (Top View) 48 BGA 1 2 3 4 A B C D E 5 6 1 2 3 4 5 A BLE OE A0 A1 A2 B I/O9 BHE A3 A4 CE1 I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCC I/O13 NC A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 F G I/O16 G H H NC WE I/O8 A10 A11 NC NC A12 A13 A8 A9 Note: NC means no connect. TOP VIEW TOP VIEW V62C1164096 Rev. 1.0 November 2001 2 6 CE2 MOSEL VITELIC V62C1164096 Part Number Information V MOSEL-VITELIC MANUFACTURED 62 C 18 16 4096 – TEMP. SRAM FAMILY OPERATING VOLTAGE DENSITY 4096K 62 = STANDARD SPEED PKG BLANK = 0°C to 70°C I = -40°C to +85°C PWR. 85 ns 100 ns C = CMOS PROCESS B = BGA 18 = 1.8V – 2.3V ORGANIZATION L = LOW POWER LL = DOUBLE LOW POWER 16 = 16-bit Absolute Maximum Ratings (1) Symbol Parameter Commercial Industrial Units VCC Supply Voltage -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V VN Input Voltage -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V V DQ Input/Output Voltage Applied VCC + 0.3 VCC + 0.3 V TBIAS Temperature Under Bias -10 to +125 -65 to +135 °C TSTG Storage Temperature -55 to +125 -65 to +150 °C NOTE: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance* TA = 25°C, f = 1.0MHz Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = 0V 6 pF COUT Output Capacitance VI/O = 0V 8 pF NOTE: 1. This parameter is guaranteed and not tested. Truth Table Mode CE1 CE2 OE WE UBE LBE I/O9-16 Operation I/O1-8 Operation Standby H X X X X X High Z High Z Standby X L X X X X High Z High Z Output Disable L H X X H H High Z High Z Output Disable L H H H X X High Z High Z Read L H L H L L DOUT DOUT Read L H L H L H DOUT High Z Read L H L H H L High Z DOUT Write L H X L L L DIN DIN Write L H X L L H DIN High Z Write L H X L H L High Z DIN NOTE: X = Don’t Care, L = LOW, H = HIGH V62C1164096 Rev. 1.0 November 2001 3 MOSEL VITELIC V62C1164096 DC Electrical Characteristics (over all temperature ranges, VCC = 1.8V – 2.3V) Symbol Parameter Min. Typ. Max. Units VIL Input LOW Voltage(1,2) -0.3 — 0.4 V VIH Input HIGH Voltage(1) 1.6 — VCC + 0.3 V IIL Input Leakage Current VCC = Max, VIN = 0V to VCC -1 — 1 µA IOL Output Leakage Current VCC = Max, CE = VIH, VOUT = 0V to VCC -1 — 1 µA VOL Output LOW Voltage VCC = Min, IOL = 2.1mA — — 0.4 V V OH Output HIGH Voltage VCC = Min, IOH = -0. 1mA VCC – 0.4 — — V Ind.(3) Units mA Symbol ICC1 Test Conditions Parameter Power Com.(3) Average Operating Current, CE1 = VIL, CE2 = VCC – 0.2V, Output Open, V CC = Max. f = fmax 25 30 f = 1 MHz 2 3 L 0.4 0.5 LL 0.3 0.3 L 5 7 LL 2 3 TTL Standby Current CE ≥ VIH, VCC = Max., f = 0 ISB CMOS Standby Current, CE1 ≥ VCC – 0.2V, CE2 < 0.2V V IN ≥ VCC – 0.2V or VIN ≤ 0.2V, VCC = Max., f = 0 ISB1 NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VIL (Min.) = -3.0V for pulse width < 20ns. 3. Maximum values. AC Test Conditions Key to Switching Waveforms Input Pulse Levels 0 to 1.6V WAVEFORM Input Rise and Fall Times 5 ns Timing Reference Levels 0.9V Output Load INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGING FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGING FROM L TO H DON'T CARE: ANY CHANGE PERMITTED CHANGING: STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE “OFF” STATE see below AC Test Loads and Waveforms TTL CL* * Includes scope and jig capacitance CL = 30 pF + 1 TTL Load V62C1164096 Rev. 1.0 November 2001 4 mA µA MOSEL VITELIC V62C1164096 Data Retention Characteristics Symbol Parameter VDR VCC for Data Retention CE1 ≥ VCC – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V ICCDR Data Retention Current CE1 ≥ VDR – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, VDR = 1.0V Com’l Ind. tCDR tR Min. Typ.(2) Max. Units 1.0 — 2.3 V L — 1 3 µA LL — 0.5 1.5 L — — 5 LL — — 2 0 — — ns — — ns Power Chip Deselect to Data Retention Time Operation Recovery Time (see Retention Waveform) tRC NOTES: 1. tRC = Read Cycle Time 2. TA = +25°C. Low VCC Data Retention Waveform (CE Controlled) Data Retention Mode VCC 1.8V VDR ≥ 1V tCDR CE1 V62C1164096 Rev. 1.0 November 2001 1.6V CE1 ≥ VCC – 0.2V 5 1.8V tR 1.6V (1) MOSEL VITELIC V62C1164096 AC Electrical Characteristics (over all temperature ranges) Read Cycle 85 Parameter Name Parameter tRC 100 Min. Max. Min. Max. Unit Read Cycle Time 85 — 70 — ns tAA Address Access Time — 85 — 100 ns tACS Chip Enable Access Time — 85 — 100 ns tBA UBE, LBE Access Time — 85 — 100 ns tOE Output Enable to Output Valid — 35 — 40 ns tCLZ Chip Enable to Output in Low Z 10 — 15 — ns tBLZ UBE, LBE to Output in Low Z 10 — 15 — ns tOLZ Output Enable to Output in Low Z 10 — 10 — ns tCHZ Chip Disable to Output in High Z 0 30 0 35 ns tOHZ Output Disable to Output in High Z 0 30 0 35 ns tBHZ UBE, LBE to Output in High Z 0 30 0 35 ns tOH Output Hold from Address Change 10 — 10 — ns Write Cycle 85 Parameter Name Parameter tWC 100 Min. Max. Min. Max. Unit Write Cycle Time 85 — 100 — ns tCW Chip Enable to End of Write 70 — 80 — ns tAS Address Setup Time 0 — 0 — ns tAW Address Valid to End of Write 70 — 80 — ns tWP Write Pulse Width 60 — 70 — ns tWR Write Recovery Time 0 — 0 — ns tWHZ Write to Output High-Z 0 25 0 35 ns tDW Data Setup to End of Write 40 — 45 — ns tDH Data Hold from End of Write 0 — 0 — ns tBW UBE, LBE to End of Write 70 — 80 — ns V62C1164096 Rev. 1.0 November 2001 6 MOSEL VITELIC V62C1164096 Switching Waveforms (Read Cycle) Read Cycle 1(1, 2) tRC ADDRESS tAA OE tOE tOLZ tOHZ(5) tBHZ tBLZ UBE, LBE tBA I/O Read Cycle 2(1, 2, 4, 6) tRC ADDRESS tOH tAA tOH I/O Read Cycle 3(1, 3, 4, 6) ADDRESS tACS CE1 CE2 tCLZ(5) tCHZ(5) I/O NOTES: 1. WE = VIH. 2. CE1 = VIL. CE2 = VIH. 3. Address valid prior to or coincident with CE transition LOW. 4. OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. 6. UBE = VIL, LBE = VIL. V62C1164096 Rev. 1.0 November 2001 7 MOSEL VITELIC V62C1164096 Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) tWC ADDRESS tWR(2) (6) tCW CE1 tAW CE2 tCW(6) tAS WE tWP(1) OUTPUT tDW tWHZ tDH INPUT Write Cycle 2 (CE Controlled)(4) tWC ADDRESS tWR(2) tCW(6) (4) CE1 tAW tCW(6) CE2 tAS WE OUTPUT High-Z tDW tDH (5) INPUT NOTES: 1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tWR is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE1 going low or CE2 going HIGH to the end of write. V62C1164096 Rev. 1.0 November 2001 8 MOSEL VITELIC V62C1164096 Package Diagrams 48 Ball—8x10 BGA D D1 e 6 E1 4 E 5 3 2 SYMBOL UNIT.MM A 1.05+0.15 A1 0.25±0.05 b 0.35±.0.05 c 0.30(TYP) D 10.00±0.10 D1 5.25 E 8.00±0.10 E1 3.75 e 0.75TYP aaa 0.10 1 A B C D E F H b SOLDER BALL aaa SIDE VIEW V62C1164096 Rev. 1.0 November 2001 9 A1 C A BOTTOM VIEW G MOSEL VITELIC WORLDWIDE OFFICES V62C1164096 U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 © Copyright , MOSEL VITELIC Inc. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC CENTRAL, NORTHEASTERN & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029 Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461