MOSEL VITELIC PRELIMINARY V62C1804096 512K X 8, CMOS STATIC RAM Features Description ■ ■ ■ ■ ■ ■ ■ ■ The V62C1804096 is a very low power CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, and active HIGH CE2, an active LOW OE, and three static I/O’s. This device has an a u to m a tic p o w e r -d o w n mo d e f e a tu r e w h e n deselected. High-speed: 85, 100 ns Ultra low standby current of 2µA (max.) Fully static operation All inputs and outputs directly compatible Three state outputs Ultra low data retention current (VCC = 1.0V) Operating voltage: 1.8V–2.3V Packages – 36-Ball CSP BGA (8mm x 10mm) Functional Block Diagram Input Buffer I/O8 Sense Amp Row Decoder A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1024 x 4096 I/O1 Column Decoder OE WE CE1 CE2 Control Circuit A10 A11 A12 A13 A14 A15 A16 A17 A18 Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Power B 85 100 L LL Temperature Mark 0°C to 70 °C • • • • • Blank –40°C to +85°C • • • • I V62C1804096 Rev. 1.0 October 2001 1 MOSEL VITELIC V62C1804096 WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip enabled, when WE is HIGH and OE is LOW, output data will be present at the I/O pins; when WE is LOW and OE is HIGH, the data present on the I/O pins will be written into the selected memory locations. Pin Descriptions A 0–A18 Address Inputs These 19 address inputs select one of the 512K x 8 bit segments in the RAM. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. I/O1–I/O8 Data Input and Data Output Ports These 8 bidirectional ports are used to read data from and write data into the RAM. OE Output Enable Input The Output Enable input is active LOW. With chip enabled, when OE is LOW and WE HIGH, data of the selected memory location will be available on the I/O pins. When OE is HIGH, the I/O pins will be in the high impedance state. VCC Power Supply GND Ground Pin Configurations (Top View) 36 BGA 1 2 3 4 5 6 A B C D E 1 2 3 4 5 A A0 A1 CE2 A3 A6 6 A8 B I/O5 A2 WE A4 A7 I/O1 C I/O6 NB NC A5 NB I/O2 D VSS NB NB NB NB VCC E VCC NB NB NB NB VSS F I/O7 NB A18 A17 NB I/O3 F G I/O8 OE CE1 A16 A15 I/O4 G H A9 A10 A11 A12 A13 A14 Note: NC means no connect. NB means no ball. H TOP VIEW TOP VIEW V62C1804096 Rev. 1.0 October 2001 2 MOSEL VITELIC V62C1804096 Part Number Information V MOSEL-VITELIC MANUFACTURED 62 1 18 C 80 8 4096 – TEMP. SRAM FAMILY OPERATING VOLTAGE PKG DENSITY PWR. 4096K 62 = STANDARD BLANK = 0°C to 70°C I = -40°C to +85°C SPEED 85 ns 100 ns C = CMOS PROCESS T = TSOP STANDARD B = BGA 18 1 = 1.8V–2.3V ORGANIZATION L = LOW POWER LL = LOW LOW POWER 80 8 = 8-bit Absolute Maximum Ratings (1) Symbol Parameter Commercial Industrial Units VCC Supply Voltage -0.5 to + VCC + 0.5 -0.5 to + VCC + 0.5 V VN Input Voltage -0.5 to + VCC + 0.5 -0.5 to + VCC + 0.5 V V DQ Input/Output Voltage Applied VCC + 0.3 VCC + 0.3 V TBIAS Temperature Under Bias -10 to +125 -65 to +135 °C TSTG Storage Temperature -55 to +125 -65 to +150 °C NOTE: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance* Truth Table TA = 25°C, f = 1.0MHz Symbol Parameter C IN Input Capacitance C OUT Output Capacitance Max. Unit Mode CE 1 CE2 OE WE I/O Operation VIN = 0V 6 pF Standby H X X X High Z VI/O = 0V 8 pF Standby X L X X High Z Output Disable L H H H High Z Read L H L H DOUT Write L H X L DIN Conditions NOTE: 1. This parameter is guaranteed and not tested. NOTE: X = Don’t Care, L = LOW, H = HIGH V62C1804096 Rev. 1.0 October 2001 3 MOSEL VITELIC V62C1804096 DC Electrical Characteristics (over all temperature ranges, VCC = 1.8V–2.3V) Symbol Min. Typ. Max. Units VIL Input LOW Voltage(1,2) -0.3 — 0.4 V VIH Input HIGH Voltage(1) 1.6 — VCC+0.3 V IIL Input Leakage Current VCC = Max, VIN = 0V to VCC — — 1 µA IOL Output Leakage Current VCC = Max, CE1 = VIH , VOUT = 0V to VCC — — 1 µA VOL Output LOW Voltage VCC = Min, IOL = 2mA — — 0.4 V V OH Output HIGH Voltage VCC = Min, IOH = -0.5mA VCC –0.4 — — V Symbol ICC1 ISB ISB1 Parameter Test Conditions Comm.(3) Ind.(3) Units f = fmax 25 30 mA f = 1 MHz 2 3 L 0.4 0.5 LL 0.3 0.3 L 5 7 LL 2 3 Parameter Average Operating Current, CE1 = VIL, CE2 = VCC – 0.2, Output Open, V CC = Max. TTL Standby Current CE1 >=VIH , CE2 <= VIL, VCC = Max., f = 0 CMOS Standby Current, CE1 Š VCC – 0.2V, CE2 ð 0.2V, V IN>= VCC – 0.2V or VIN <=0.2V, VCC = Max., f = 0 NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VIL (Min.) = -3.0V for pulse width < tRC /2. 3. Maximum value. AC Test Conditions Input Pulse Levels AC Test Loads and Waveforms 0 to 1.6V Input Rise and Fall Times 5 ns Timing Reference Levels 0.9V Output Load CL* TTL see below CL = 30pF + 1TTL Load * Includes scope and jig capacitance V62C1804096 Rev. 1.0 October 2001 4 mA µA MOSEL VITELIC V62C1804096 Data Retention Characteristics Symbol Parameter VDR VCC for Data Retention CE1 ≥ VCC – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V ICCDR Data Retention Current CE1 ≥ VDR – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, VDR = 1.0V Com’l Ind. tCDR tR Min. Typ.(2) Max. Units 1.0 — 2.3 V L — 1 3 µA LL — 0.5 1.5 L — — 5 LL — — 2 0 — — ns — — ns Power Chip Deselect to Data Retention Time Operation Recovery Time (see Retention Waveform) tRC NOTES: 1. tRC = Read Cycle Time 2. TA = +25°C. Low VCC Data Retention Waveform (1) (CE1 Controlled) Data Retention Mode VCC VDR ≥ 1V 1.8V tCDR CE1 1.6V CE1 ≥ VCC – 0.2V 1.8V tR 1.6V Key to Switching Waveforms WAVEFORM V62C1804096 Rev. 1.0 October 2001 INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGING FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGING FROM L TO H DON'T CARE: ANY CHANGE PERMITTED CHANGING: STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE “OFF” STATE 5 (1) MOSEL VITELIC V62C1804096 AC Electrical Characteristics (over all temperature ranges) Read Cycle Parameter Name 85 Parameter 100 Min. Max. Min. Max. Unit tRC Read Cycle Time 85 — 100 — ns tAA Address Access Time — 85 — 100 ns tACS1 Chip Enable Access Time — 85 — 100 ns tACS2 Chip Enable Access Time — 85 — 100 ns Output Enable to Output Valid — 85 — 40 ns tCLZ1 Chip Enable to Output in Low Z 10 — 15 — ns tCLZ2 Chip Enable to Output in Low Z 10 — 15 — ns tOLZ Output Enable to Output in Low Z 5 — 10 — ns tCHZ Chip Disable to Output in High Z — 30 — 35 ns tOHZ Output Disable to Output in High Z — 30 — 35 ns tOH Output Hold from Address Change 10 — 10 — ns tOE Write Cycle Parameter Name 85 Parameter 100 Min. Max. Min. Max. Unit tWC Write Cycle Time 85 — 70 — ns tCW Chip Enable to End of Write 70 — 60 — ns tAS Address Setup Time 0 — 0 — ns tAW Address Valid to End of Write 70 — 60 — ns tWP Write Pulse Width 60 — 50 — ns tWR Write Recovery Time 5 — 5 — ns tWHZ Write to Output High-Z — 25 — 30 ns tDW Data Setup to End of Write 40 — 45 — ns tDH Data Hold from End of Write 0 — 0 — ns V62C1804096 Rev. 1.0 October 2001 6 MOSEL VITELIC V62C1804096 Switching Waveforms (Read Cycle) Read Cycle 1(1, 2) tRC ADDRESS tAA OE tOE tOLZ tOH tOHZ(5) I/O Read Cycle 2(1, 2, 4) tRC ADDRESS tAA tOH tOH I/O Read Cycle 3(1, 3, 4) ADDRESS CE1 tACS1 CE2 I/O tACS2 tCHZ(5) tCLZ1(5) tCLZ2(5) NOTES: 1. WE = VIH. 2. CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition LOW and/or CE2 transition HIGH. 4. OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. V62C1804096 Rev. 1.0 October 2001 7 MOSEL VITELIC V62C1804096 Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) tWC ADDRESS tWR(2) (6) tCW CE1 tAW CE2 tCW(6) tAS WE tWP(1) OUTPUT tDW tWHZ tDH INPUT Write Cycle 2 (CE Controlled)(4) tWC ADDRESS tWR(2) tCW(6) (4) CE1 tAW tCW(6) CE2 tAS WE OUTPUT High-Z tDW tDH (5) INPUT NOTES: 1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tWR is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE1 going low or CE2 going HIGH to the end of write. V62C1804096 Rev. 1.0 October 2001 8 MOSEL VITELIC V62C1804096 Package Diagrams 36 Ball—8x10 BGA D D1 e 6 E1 4 E 5 3 2 SYMBOL UNIT.MM A 1.05+0.15 A1 0.25±0.05 b 0.35±.0.05 c 0.30(TYP) D 10.00±0.10 D1 5.25 E 8.00±0.10 E1 3.75 e 0.75TYP aaa 0.10 1 A B C D E F H b SOLDER BALL aaa SIDE VIEW V62C1804096 Rev. 1.0 October 2001 9 A1 C A BOTTOM VIEW G MOSEL VITELIC WORLDWIDE OFFICES V62C1804096 U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 © Copyright , MOSEL VITELIC Inc. The information in this document is subject to change without notice. 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