TLC59108F
www.ti.com .................................................................................................................................................................................................. SLDS162 – MARCH 2009
8-BIT FM+ I2C BUS LED DRIVER
FEATURES
1
•
•
•
•
•
•
•
•
•
•
Eight LED Drivers (Each Output Programmable
at OFF, ON, Programmable LED Brightness,
Programmable Group Dimming/Blinking Mixed
With Individual LED Brightness)
Eight Open-Drain Output Channels
256-Step (8-Bit) Linear Programmable
Brightness Per LED Output Varying From Fully
Off (Default) to Maximum Brightness Using a
97-kHz PWM Signal
256-Step Group Brightness Control Allows
General Dimming [Using a 190-Hz PWM Signal
From Fully Off to Maximum Brightness
(Default)]
256-Step Group Blinking With Frequency
Programmable From 24 Hz to 10.73 s and Duty
Cycle From 0% to 99.6%
Four Hardware Address Pins Allow 14
TLC59108F Devices to be Connected to the
Same I2C Bus
Four Software Programmable I2C Bus
Addresses (One LED Group Call Address and
Three LED Sub Call Addresses) Allow Groups
of Devices to be Simultaneously Addressed
Any Combination (For Example, One Register
Used for ‘All Call’ so That All the TLC59108Fs
on the I2C Bus Can be Simultaneously
Addressed and the Second Register Used for
Three Different Addresses so That One Third
of All Devices on the Bus Can be
Simultaneously Addressed)
Software Enable and Disable for I2C Bus
Address
Software Reset Feature (SWRST Call) Allows
the Device to be Reset Through the I2C Bus
Up to 14 Possible Hardware Adjustable
Individual I2C Bus Addresses Per Device so
That Each Device Can be Programmed
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Output State Change Programmable on the
Acknowledge or the STOP Command to
Update Outputs Byte-by-Byte or All at the
Same Time (Default to 'Change on STOP')
Maximum Output Current: 120 mA
Maximum Output Voltage: 17 V
25-MHz Internal Oscillator Requires No
External Components
1-MHz Fast-Mode Plus (FM+) Compatible I2C
Bus Interface With 30 mA High Drive
Capability on SDA Output for Driving High
Capacitive Buses
Internal Power-On Reset
Noise Filter on SCL/SDA Inputs
No Glitch on Power Up
Active-Low Reset (RESET)
Supports Hot Insertion
Low Standby Current
3.3-V or 5-V Supply Voltage
5.5-V Tolerant Inputs
Packages Offered: 20-Pin Thin Shrink
Small-Outline Package (TSSOP) (PW), 20-Pin
Quad Flatpack No Lead (QFN) (RGY)
–40°C to 85°C Operation
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TLC59108F
SLDS162 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com
PW PACKAGE
(TOP VIEW)
N.C.
A0
A1
A2
A3
OUT0
OUT1
GND
OUT2
OUT3
RGY PACKAGE
(TOP VIEW)
1
20
VCC
SDA
SCL
RESET
GND
OUT7
OUT6
GND
OUT5
OUT4
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
N.C. – No internal connection
N.C.
VCC
1
20
A0
2
19
SDA
A1
3
18
SCL
A2
4
17
RESET
A3
5
16
GND
OUT0
6
15
OUT7
OUT1
7
14
OUT6
GND
8
13
GND
OUT2
9
12
OUT5
10
11
OUT3
OUT4
DESCRIPTION/ORDERING INFORMATION
The TLC59108F is an I2C bus controlled 8-bit LED driver optimized for red/green/blue/amber (RGBA) color
mixing applications. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM
controller that operates at 97 kHz with a duty cycle that is adjustable from 0% to 99.6% to allow the LED to be
set to a specific brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both a
fixed frequency of 190 Hz and an adjustable frequency between 24 Hz to once every 10.73 seconds with a duty
cycle that is adjustable from 0% to 99.6% that is used to either dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller value or at both individual
and group PWM controller values. The TLC59108F operates with a supply voltage range of 3 V to 5.5 V and the
outputs are 17 V tolerant. LEDs can be directly connected to the TLC59108F device outputs.
Software programmable LED group and three sub call I2C bus addresses allow all or defined groups of
TLC59108F devices to respond to a common I2C bus address, allowing for example, all the same color LEDs to
be turned on or off at the same time or marquee chasing effect, thus minimizing I2C bus commands.
Four hardware address pins allow up to 14 devices on the same bus.
The software reset (SWRST) call allows the master to perform a reset of the TLC59108F through the I2C bus,
identical to the power-on reset (POR) that initializes the registers to their default state causing the outputs to be
set high (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition.
ORDERING INFORMATION
PACKAGE (1) (2)
TA
–40°C to 85°C
(1)
(2)
2
ORDERABLE PART NUMBER
TOP-SIDE MARKING
QFN – RGY
Reel of 3000
TLC59108FIRGYR
Y59108F
TSSOP – PW
Reel of 3000
TLC59108FIPWR
Y59108F
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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BLOCK DIAGRAM
A0
SCL
SDA
INPUT FILTER
A1 A2
A3
2
I C BUS CONTROL
OUT0
OUT7
OUTPUT DRIVER AND
ERROR DETECTION
LED STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
97 kHz
OUT6
NOTE:
All 8 FETs
are present
POWER-ON
RESET CONTROL
RESET
OUT1
24.3 kHz
25 MHz
OSCILLATOR
GRPFREQ
REGISTER
GRPPWM
REGISTER
190 Hz
‘0’ – Permanently OFF
‘1’ – Permanently ON
VCC
GND
NOTE: Only one PWM shown for clarity.
TERMINAL FUNCTIONS
TERMINAL
(1)
NAME
PW/RGY
PIN NO.
I/O (1)
N.C.
1
I
No internal connection
A0
2
I
Address input 0
A1
3
I
Address input 1
A2
4
I
Address input 2
DESCRIPTION
A3
5
I
Address input 3
OUT0, OUT1,
OUT2, OUT3,
OUT4, OUT6,
OUT6, OUT7
6, 7,
9, 10,
11, 12,
14, 15
O
Constant current output 0 to 7, LED ON at low
GND
8, 13, 16
–
Ground
RESET
17
I
Active-low reset input
Serial clock input
SCL
18
I
SDA
19
I/O
VCC
20
–
Serial data input/output
Power supply
I = input, O = output
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
0
7
V
Input voltage range
–0.4
7
V
VO
Output voltage range
–0.5
IO
Continuous output current
PD
Power dissipation, TA = 25 °C, JESD 51-7
TJ
Junction temperature range
–40
150
°C
Tstg
Storage temperature range
–55
150
°C
VCC
Supply voltage range
VI
(1)
UNIT
20
V
120
mA
PW package
1.2
RGY package
2.2
W
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL IMPEDANCE
UNIT
θJA
(1)
Package thermal impedance (1)
PW package
83
RGY package
47
°C/W
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
TEST CONDITIONS
VCC
Supply voltage
VIH
High-level input voltage
SCL, SDA, RESET, A0, A1, A2, A3
VIL
Low-level input voltage
SCL, SDA, RESET, A0, A1, A2, A3
VO
Output voltage
OUT0 to OUT7
IOL
Low-level output current
SDA
IO
Output current
OUT0 to OUT7
TA
Operating free-air temperature
(1)
4
MIN
MAX
3
5.5
V
0.7 × VCC
5.5
V
0
0.3 × VCC
V
17
V
VCC = 3 V
20
VCC = 4.5 V
30
UNIT
mA
5
120
mA
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
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ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
II
TEST CONDITIONS
Input/output leakage
current
SCL, SDA, A0,
A1, A2, A3,
VI = VCC or GND
RESET
Output leakage
current
OUT0 to OUT7 VO = 17 V, TJ = 25°C
VPOR
Power-on reset voltage
IOL
Low-level output
current
SDA
VOL
Low-level output
voltage
OUT0 to OUT7
rON
ON-state resistance
OUT0 to OUT7
TSD
Overtemperature shutdown (2)
THYS
Restart hysteresis
TYP (1)
MAX
UNIT
±0.3
µA
0.5
µA
2.5
Ci
Input capacitance
SCL, A0, A1,
A2, A3,
RESET
Cio
Input/output
capacitance
SDA
ICC
Supply current
(1)
(2)
MIN
VCC = 3 V, VOL = 0.4 V
20
VCC = 5 V, VOL = 0.4 V
30
V
mA
VCC = 3 V, IOL = 120 mA
230
450
VCC = 4.5 V, IOL = 120 mA
200
400
VCC = 3 V, IOL = 120 mA
1.92
3.75
VCC = 4.5 V, IOL = 120 mA
1.64
3.3
175
200
150
mV
Ω
°C
15
°C
VI = VCC or GND
5
pF
VI = VCC or GND
8
pF
VCC = 3 V
VCC = 4.5 V
OUT0 to OUT7 =
OFF
6
9
mA
All typical values are at TA = 25°C.
Specified by design, not production tested.
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I2C INTERFACE TIMING REQUIREMENTS
TA = –40°C to 85°C
STANDARD-MODE
I2C BUS
FAST-MODE
I2C BUS
FAST-MODE PLUS
I2C BUS
MIN
MAX
MIN
MAX
MIN
MAX
0
100
0
400
0
1000
UNIT
I2C Interface
fSCL
SCL clock frequency
tBUF
I2C bus free time between Stop and
Start
tHD;STA
Hold time (repeated) for Start
condition
tSU;STA
Set-up time (repeated) for Start
condition
tSU;STO
tHD;DAT
kHz
4.7
1.3
0.5
µs
4
0.6
0.26
µs
4.7
0.6
0.26
µs
Set-up time for Stop condition
4
0.6
0.26
µs
Data hold time
0
0
0
ns
tVD;ACK
Data valid acknowledge time
0.3
3.45
0.1
0.9
0.05
0.45
µs
tVD;DAT
Data valid time (2)
0.3
3.45
0.1
0.9
0.05
0.45
µs
tSU;DAT
Data set-up time
250
100
50
ns
tLOW
Low period of the SCL clock
4.7
1.3
0.5
µs
tHIGH
High period of the SCL clock
4
0.6
0.26
µs
tf
Fall time of both SDA and SCL
signals (3) (4)
300
tr
Rise time of both SDA and SCL
signals
1000
tSP
Pulse width of spikes that must be
suppressed by the input filter (6)
(1)
(5)
300
120
ns
20+0.1Cb (5)
300
120
ns
50
50
ns
20+0.1Cb
50
Reset
tW
Reset pulse width
tREC
Reset recovery time
tRESET
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
6
Time to reset
(7) (8)
10
10
10
ns
0
0
0
ns
400
400
400
ns
tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low.
tVD;DAT = minimum time for SDA data out to be valid following SCL low.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of SCLs falling edge.
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified
at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
Cb = total capacitance of one bus line in pF.
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns
Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.
Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.
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PARAMETER MEASUREMENT INFORMATION
START
SCL
ACK OR READ CYCLE
SDA
30%
tRESET
50%
RESET
tREC
tW
OUTn
50%
tRESET
Figure 1. Definition of Reset Timing
SDA
tBUF
tHD;STA
tr
tSP
tf
tLOW
SCL
tHD;STA
P
tHD;DAT
S
tHIGH
tSU;DAT
tSU;DAT
tSU;STO
Sr
P
Figure 2. Definition of Timing
Protocol
Start
Condition
(S)
tSU;STA
Bit 7
MSB
(A7)
tLOW
Bit 6
(A6)
tHIGH
Bit 7
(D1)
Bit 8
(D0)
Acknowledge
(A)
Stop
Condition
(P)
1/fSCL
SCL
tr
tf
tBUF
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
NOTE: Rise and fall times refer to VIL and VIH.
Figure 3. I2C Bus Timing
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
Pulse
Generator
VI
DUT
RT
VO
RL
VCC
Open
GND
CL
NOTE: RL = Load resistance for SDA and SCL; should be >1 kΩ at 3-mA or lower current.
CL = Load capacitance; includes jig and probe capacitance.
RT = Termination resistance; should be equal to the output impedance (ZO) of the pulse generator.
Figure 4. Test Circuit for Switching Characteristics
8
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APPLICATION INFORMATION
Functional Description
Device Address
Following a Start condition, the bus master must output the address of the slave it is accessing.
Regular I2C Bus Slave Address
The I2C bus slave address of the TLC59108F is shown in Figure 5. To conserve power, no internal pullup
resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. For
buffer management purpose, a set of sector information data should be stored.
Slave Address
1
0
Fixed
0
A3
A2
A1
A0 R/W
Hardware Selectable
Figure 5. Slave Address
The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is
selected. When set to logic 0, a write operation is selected.
LED All Call I2C Bus Address
• Default power-up value (ALLCALLADR address register): 90h or 1001 000
• Programmable through I2C bus (volatile programming)
• At power-up, LED All Call I2C bus address is enabled. TLC59108F sends an ACK when 90h (R/W = 0) or 91h
(R/W = 1) is sent by the master.
NOTE:
2
The LED All Call I C bus address (90h or 1001 000) must not be used as a regular
I2C bus slave address since this address is enabled at power-up. All the TLC59108Fs
on the I2C bus will acknowledge the address if sent by the I2C bus master.
LED Sub Call I2C Bus Address
•
•
•
•
Three different I2C bus address can be used
Default power-up values:
– SUBADR1 register: 92h or 1001 001
– SUBADR2 register: 94h or 1001 010
– SUBADR3 register: 98h or 1001 100
Programmable through I2C bus (volatile programming)
At power-up, Sub Call I2C bus address is disabled. TLC59108F does not send an ACK when 92h (R/W = 0)
or 93h (R/W = 1) or 94h (R/W = 0) or 95h (R/W = 1) or 98h (R/W = 0) or 99h (R/W = 1) is sent by the master.
NOTE:
The default LED Sub Call I2C bus address may be used as a regular I2C bus slave
address as long as they are disabled.
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Software Reset I2C Bus Address
The address shown in Figure 6 is used when a reset of the TLC59108F needs to be performed by the master.
The software reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59108F does not
acknowledge the SWRST. See Software Reset for more detail.
R/W
1
0
0
0
1
1
1
0
Figure 6. Software Reset Address
NOTE:
The Software Reset I2C bus address is a reserved address and cannot be use as a
regular I2C bus slave address.
Control Register
Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address,
the bus master will send a byte to the TLC59108F, which will be stored in the Control register. The lowest 5 bits
are used as a pointer to determine which register will be accessed (D[4:0]). The highest 3 bits are used as
Auto-Increment flag and Auto-Increment options (AI[2:0]).
Auto-Increment
Flag
AI2 AI1 AI0
Register Address
D4
D3
D2
D1
D0
Auto-Increment Options
Figure 7. Control Register
When the Auto-Increment flag is set (AI2 = logic 1), the five low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the registers sequentially. Four
different types of Auto-Increment are possible, depending on AI1 and AI0 values.
Table 1. Auto-Increment Options (1)
(1)
AI2
AI1
AI0
DESCRIPTION
0
0
0
No auto-increment
1
0
0
Auto-increment for all registers. D[4:0] roll over to '0 0000' after the last register ('1 0001') is
accessed.
1
0
1
Auto-increment for individual brightness registers only. D[4:0] roll over to '0 0010' after the last
register ('0 1001') is accessed.
1
1
0
Auto-increment for global control registers only. D[4:0] roll over to '0 1010' after the last register
('0 1011') is accessed.
1
1
1
Auto-increment for individual and global control registers only. D[4:0] roll over to '0 0010' after
the last register ('0 1011') is accessed.
Other combinations not shown in Table 1 (A1[2:0] = 001, 010, and 011) are reserved and must not be used for proper device operation.
AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C bus
communication, for example, changes the brightness of a single LED. Data is overwritten each time the register
is accessed during a write operation.
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the
same I2C bus communication, for example, changing color setting to another color setting.
10
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AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same
I2C bus communication, for example, global brightness or blinking change.
AI[2:0] = 111 is used when individually and global changes must be performed during the same I2C bus
communication, for example, changing color and global brightness at the same time.
Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.
When Control register is written, the register entry point determined by D[4:0] is the first register that will be
addressed (read or write operation), and can be anywhere between 0 0000 and 1 0001 (as defined in Table 2).
When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register
increment stops and goes to the next one is determined by AI[2:0]. See Table 1 for rollover values. For example,
if the Control register = 1110 1100 (ECh), then the register addressing sequence will be (in hex):
04 → … → 11 → 02 → ... → 11 → 02 → … as long as the master keeps sending or reading data.
Register Descriptions
Table 2 describes the registers in the TLC59108F.
Table 2. Register Descriptions
REGISTER
NUMBER
(HEX)
(1)
NAME
ACCESS (1)
DESCRIPTION
00
MODE1
R/W
Mode register 1
01
MODE2
R/W
Mode register 2
02
PWM0
R/W
Brightness control LED0
03
PWM1
R/W
Brightness control LED1
04
PWM2
R/W
Brightness control LED2
05
PWM3
R/W
Brightness control LED3
06
PWM4
R/W
Brightness control LED4
07
PWM5
R/W
Brightness control LED5
08
PWM6
R/W
Brightness control LED6
09
PWM7
R/W
Brightness control LED7
0A
GRPPWM
R/W
Group duty cycle control
0B
GRPFREQ
R/W
Group frequency
0C
LEDOUT0
R/W
LED output state 0
0D
LEDOUT1
R/W
LED output state 1
0E
SUBADR1
R/W
I2C bus sub-address 1
0F
SUBADR2
R/W
I2C bus sub-address 2
10
SUBADR3
R/W
I2C bus sub-address 3
11
ALLCALLADR
R/W
LED all call I2C bus address
R = read, W = write
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Mode Register 1 (MODE1)
Table 3 describes Mode Register 1.
Table 3. MODE1 – Mode Register 1 (Address 00h) Bit Description
BIT
7
6
5
4
3
2
(1)
(2)
(3)
(4)
SYMBOL
ACCESS (1)
AI2
R
AI1
R
AI0
R
SLEEP
R/W
SUB1
R/W
SUB2
R/W
1
SUB3
R/W
0
ALLCALL
R/W
VALUE
DESCRIPTION
0 (2)
Register auto-increment disabled
1
Register auto-increment enabled
0 (2)
Auto-increment bit 1 = 0
1
Auto-increment bit 1 = 1
0 (2)
Auto-increment bit 0 = 0
1
Auto-increment bit 0 = 1
0
Normal mode (3)
1 (2)
Low power mode. Oscillator off (4).
(2)
Device does not respond to I2C bus sub-address 1.
1
Device responds to I2C bus sub-address 1.
(2)
Device does not respond to I2C bus sub-address 2.
1
Device responds to I2C bus sub-address 2.
(2)
Device does not respond to I2C bus sub-address 3.
1
Device responds to I2C bus sub-address 3.
0
Device does not respond to LED All Call I2C bus address.
(2)
Device responds to LED All Call I2C bus address.
0
0
0
1
R = read, W = write
Default value
It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set from logic 1 to 0. Timings on LEDn outputs are
not guaranteed if PWMx, GRPPWM, or GRPFREQ registers are accessed within the 500 µs window.
No LED control (on, off, blinking, or dimming) is possible when the oscillator is off. Write to a register cannot be accepted during SLEEP
mode. When you change the LED condition, SLEEP bit must be set to logic 0.
Mode Register 2 (MODE2)
Table 4 describes Mode Register 2.
Table 4. MODE2 – Mode Register 2 (Address 01h) Bit Description
BIT
SYMBOL
7:6
5
DMBLNK
4
3
2:0
(1)
(2)
(3)
12
ACCESS (1)
VALUE
R
0 (2)
Reserved
0 (2)
Group control = dimming
1
Group control = blinking
(2)
Reserved
R/W
R
OCH
R/W
R
0
0 (2)
1
000
DESCRIPTION
Outputs change on Stop command (3).
Outputs change on ACK.
(2)
Reserved
R = read, W = write
Default value
Change of the outputs at the STOP command allows synchronizing outputs of more than one TLC59108F. Applicable to registers from
02h (PWM0) to 0Dh (LEDOUT) only.
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Individual Brightness Control Registers (PWM0–PWM7)
Table 5 describes the Individual Brightness Control Registers.
Table 5. PWM0–PWM7 – Individual Brightness Control Registers (Addresses 02h–09h) Bit Description
ADDRESS
REGISTER
BIT
SYMBOL
ACCESS (1)
VALUE
02h
PWM0
7:0
IDC0[7:0]
R/W
0000 0000 (2)
PWM0 individual duty cycle
(2)
PWM1 individual duty cycle
(1)
(2)
DESCRIPTION
03h
PWM1
7:0
IDC1[7:0]
R/W
0000 0000
04h
PWM2
7:0
IDC2[7:0]
R/W
0000 0000 (2)
PWM2 individual duty cycle
05h
PWM3
7:0
IDC3[7:0]
R/W
0000 0000 (2)
PWM3 individual duty cycle
06h
PWM4
7:0
IDC4[7:0]
R/W
0000 0000 (2)
PWM4 individual duty cycle
(2)
PWM5 individual duty cycle
07h
PWM5
7:0
IDC5[7:0]
R/W
0000 0000
08h
PWM6
7:0
IDC6[7:0]
R/W
0000 0000 (2)
PWM6 individual duty cycle
09h
PWM7
7:0
IDC7[7:0]
R/W
0000 0000 (2)
PWM7 individual duty cycle
R = read, W = write
Default value
A 97-kHz fixed-frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from
00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable
to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 and LEDOUT1 registers).
duty cycle =
IDCx[7:0]
256
Group Duty Cycle Control Register (GRPPWM)
Table 6 describes the Group Duty Cycle Control Register .
Table 6. GRPPWM – Group Duty Cycle Control Register (Address 0Ah) Bit Description
ADDRESS
REGISTER
BIT
SYMBOL
ACCESS (1)
VALUE
0Ah
GRPPWM
7:0
GDC0[7:0]
R/W
1111 1111 (2)
(1)
(2)
DESCRIPTION
GRPPWM register
R = read, W = write
Default value
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed frequency signal is
superimposed with the 97 kHz individual brightness control signal. GRPPWM is then used as a global brightness
control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘Don’t
care’.
General brightness for the 8 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED output
off) to FFh (99.6% duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx = 11
(LEDOUT0 and LEDOUT1 registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking
pattern, where GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains
the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
duty cycle =
GDC[7:0]
256
Group Frequency Register (GRPFREQ)
Table 7 describes the Group Frequency Register.
Table 7. GRPFREQ – Group Frequency Register (Address 0Bh) Bit Description
ADDRESS
REGISTER
BIT
SYMBOL
ACCESS (1)
VALUE
0Bh
GRPFREQ
7:0
GFRQ[7:0]
R/W
0000 0000 (2)
(1)
(2)
DESCRIPTION
GRPFREQ register
R = read, W = write
Default value
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GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1.
Value in this register is a ‘Don’t care’ when DMBLNK = 0. Applicable to LED output programmed with LDRx = 11
(LEDOUT0 and LEDOUT1 registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).
globalblinkingperiod =
GFRQ[7:0] + 1
(s)
24
LED Driver Output State Registers (LEDOUT0, LEDOUT1)
Table 8 describes the LED Driver Output State Registers.
Table 8. LEDOUT0 and LEDOUT1 – LED Driver Output State Registers (Address 0Ch and 0Dh) Bit
Descriptions
ADDRESS
0Ch
LEDOUT0
0Dh
(1)
(2)
REGISTER
LEDOUT1
ACCESS (1)
BIT
SYMBOL
7:6
LDR3[1:0]
00 (2)
LED3 output state control
5:4
LDR2[1:0]
(2)
LED2 output state control
3:2
LDR1[1:0]
00 (2)
LED1 output state control
1:0
LDR0[1:0]
00 (2)
LED0 output state control
7:6
LDR7[1:0]
00 (2)
LED7 output state control
5:4
LDR6[1:0]
(2)
LED6 output state control
3:2
LDR4[1:0]
00 (2)
LED5 output state control
1:0
LDR4[1:0]
00 (2)
LED4 output state control
R/W
R/W
VALUE
00
00
DESCRIPTION
R = read, W = write
Default value
LDRx = 00 : LED driver x is off (default power-up state).
LDRx = 01 : LED driver x is fully on (individual brightness and group dimming/blinking not controlled).
LDRx = 10 : LED driver x is individual brightness can be controlled through its PWMx register.
LDRx = 11 : LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx
register and the GRPPWM registers.
I2C Bus Sub-Address Registers 1 to 3 (SUBADR1–SUBADR3)
Table 9 describes the Output Gain Control Register.
Table 9. SUBADR1–SUBADR3 – I2C Bus Sub-Address Registers 1 to 3 (Addresses 0Eh–10h) Bit
Descriptions
ADDRESS
0Eh
0Fh
10h
REGISTER
SUBADR1
SUBADR2
SUBADR3
BIT
SYMBOL
ACCESS (1)
VALUE
7:5
A1[7:5]
R
100 (2)
4:1
14
R/W
0
A1[0]
R
7:5
A2[7:5]
R
4:1
A2[4:1]
R/W
0
A2[0]
R
7:5
A3[7:5]
R
4:1
0
(1)
(2)
A1[4:1]
A3[4:1]
A3[0]
R/W
R
1001
0
(2)
(2)
100 (2)
1010
0
(2)
(2)
100 (2)
1100
0
(2)
(2)
DESCRIPTION
Reserved
I2C bus sub-address 1
Reserved
Reserved
I2C bus sub-address 2
Reserved
Reserved
I2C bus sub-address 3
Reserved
R = read, W = write
Default value
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Sub-addresses are programmable through the I2C bus. Default power-up values are 92h, 94h, 98h and the
device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1
register is equal to 0).
Once sub-addresses have been programmed to their right values, SUBx bits need to be set to 1 in order to have
the device acknowledging these addresses (MODE1 register).
Only the 7 MSBs representing the I2C bus sub-address are valid. The LSB in SUBADRx register is a read-only
bit (0).
When SUBx is set to 1, the corresponding I2C bus sub-address can be used during either an I2C bus read or
write sequence.
LED All Call I2C Bus Address Register (ALLCALLADR)
Table 10 describes the LED All Call I2C Bus Address Register.
Table 10. ALLCALLADR – LED All Call I2C Bus Address Register Addresses 11h) Bit Description
ADDRESS
11h
REGISTER
ALLCALLADR
BIT
SYMBOL
ACCESS (1)
VALUE
7:5
AC[7:5]
R
100 (2)
Reserved
4:1
AC[4:1]
R/W
1000 (2)
ALLCALL I2C bus address
0
(1)
(2)
AC[0]
R
0
(2)
DESCRIPTION
Reserved
R = read, W = write
Default value
The LED All Call I2C-bus address allows all the TLC59108Fs in the bus to be programmed at the same time
(ALLCALL bit in register MODE1 must be equal to 1 (power-up default state)). This address is programmable
through the I2C-bus and can be used during either an I2C-bus read or write sequence. The register address can
also be programmed as a Sub Call.
Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in ALLCALLADR register is a
read-only bit (0).
If ALLCALL bit = 0 (MODE1 register), the device does not acknowledge the address programmed in register
ALLCALLADR.
Power-On Reset
When power is applied to VCC, an internal power-on reset holds the TLC59108F in a reset condition until VCC has
reached VPOR. At this point, the reset condition is released and the TLC59108F registers and I2C bus state
machine are initialized to their default states causing all the channels to be deselected. Thereafter, VCC must be
lowered below 0.2 V to reset the device.
External Reset
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TLC59108F registers and
I2C state machine will be held in their default state until the RESET input is once again high.
This input requires a pull-up resistor to VCC if no active connection is used.
Software Reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C bus to be reset to the power-up state
value through a specific I2C bus command. To be performed correctly, the I2C bus must be functional and there
must be no device hanging the bus.
The SWRST Call function is defined as the following:
1. A Start command is sent by the I2C bus master.
2. The reserved SWRST I2C bus address 1001 011 with the R/W bit set to 0 (write) is sent by the I2C bus
master.
3. The TLC59108F device(s) acknowledge(s) after seeing the SWRST Call address 1001 0110 (9Eh) only. If
the R/W bit is set to 1 (read), no acknowledge is returned to the I2C bus master.
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4. Once the SWRST Call address has been sent and acknowledged, the master sends two bytes with two
specific values (SWRST data byte 1 and byte 2):
a. Byte1 = A5h: the TLC59108F acknowledges this value only. If byte 1 is not equal to A5h, the TLC59108F
does not acknowledge it.
b. Byte 2 = 5Ah: the TLC59108F acknowledges this value only. If byte 2 is not equal to 5Ah, the
TLC59108F does not acknowledge it.
If more than two bytes of data are sent, the TLC59108F does not acknowledge any more.
5. Once the correct two bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly
acknowledged, the master sends a Stop command to end the SWRST Call. The TLC59108F then resets to
the default value (power-up value) and is ready to be addressed again within the specified bus free time
(tBUF).
The I2C bus master may interpret a non-acknowledge from the TLC59108F (at any time) as a SWRST Call
Abort. The TLC59108F does not initiate a reset of its registers. This happens only when the format of the Start
Call sequence is not correct.
Individual Brightness Control With Group Dimming/Blinking
A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually
the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED
outputs):
• A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a
global brightness control.
• A programmable frequency signal from 24 Hz to 1/10.73 s (8 bits, 256 steps) is used to provide a global
blinking control.
1 2
3
4
5
6
7
8
9 10 11 12
507
508
510
512 508
510
512
508
511 507
508
511
1 2
3
4
5
6
7
8
3
4
5
6
7
8
9 10 11
N X 40 ns with
N = (0 to 255)
(PWMx Register)
M X 256 X 2 X 40 ns
with M = (0 to 255)
(GRPPWM Register)
256 X 40 ns = 10.24 µs
(97.6 kHz)
Group Dimming Signal
256 X 2 X 256 X 40 ns = 5.24 ms (190.7 Hz)
1 2
3
4
5
6
7
8
1 2
Resulting Brightness + Group Dimming Signal
A.
Minimum pulse width for LEDn brightness control is 40 ns.
B.
Minimum pulse width for group dimming is 20.48 µs.
C.
When M = 1 (GRPPWM register value), the resulting LEDn brightness control and group dimming signal will have two
pulses of the LED brightness control signal (pulse width = N × 40 ns,w ith N defined in the PWMx register).
D.
The resulting brightness plus group dimming signal shown above demonstrate a resulting control signal with M = 4 (8
pulses).
Figure 8. Brightness + Group Dimming Signals
16
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Characteristics of the I2C Bus
The I2C bus is for two-way two-line communication between different devices or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a
pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus
is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see
Figure 9).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 9. Bit Transfer
Start and Stop Conditions
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the Stop condition (P) (see Figure 10).
SDA
SCL
SDA
S
P
SCL
Stop Condition
Start Condition
Figure 10. Start and Stop Conditions
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System Configuration
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master and the devices which are controlled by the master are the slaves (see Figure 11).
SDA
SCL
Master
Transmitter/
Receiver
Slave Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
2
I C Bus
Multiplexer
Slave
Figure 11. System Configuration
Acknowledge
The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on
the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and
hold time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable
the master to generate a Stop condition.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Condition
Clock Pulse for
Acknowledgment
Figure 12. Acknowledge on I2C Bus
18
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Control Register
Slave Address
S
1
0
0
A3
A2
0
A0
A1
A
X
X
X
D3
D4
D2
Auto-Increment Options
Auto-Increment Flag
Acknowledge
From Slave
START Condition
D1
D0
A
A
P
STOP
Condition
Acknowledge
From Slave
R/W
Acknowledge
From Slave
Figure 13. Write to a Specific Register
1
S
0
0
A3
MODE1 Register
Control Register
Slave Address
A2
0
A0
A1
START Condition
1
A
0
0
0
0
Auto-Increment on
All Registers
R/W
0
0
0
A
MODE1 Register
Selection
Acknowledge
From Slave
Acknowledge
From Slave
MODE2 Register
(cont.)
A
A
Acknowledge
From Slave
Acknowledge
From Slave
Auto-Increment On
ALLCALLADR Register
SUBADR3 Register
(cont.)
A
A
P
Acknowledge
From Slave
Acknowledge
From Slave
STOP
Condition
Figure 14. Write to All Registers Using Auto-Increment
S
1
0
0
A3
A2
START Condition
PWM0 Register
Control Register
Slave Address
A1
A0
0
1
A
R/W
Acknowledge
From Slave
0
1
0
0
0
1
0
PWM1 Register
A
A
Auto-Increment on
PWM Register
Brightness Registers
Selection
Only
Acknowledge
From Slave
(cont.)
A
Acknowledge
From Slave
Acknowledge
From Slave
Auto-Increment On
(cont.)
PWM0 Register
PWM7 Register
PWM6 Register
A
Acknowledge
From Slave
A
Acknowledge
From Slave
PWMx Register
A
A
Acknowledge
From Slave
P
Acknowledge
From Slave
STOP
Condition
Figure 15. Multiple Writes to Individual Brightness Registers Only Using the Auto-Increment Feature
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S
1
0
0
A3
A2
Slave Address
Control Register
Slave Address
0
A0
A1
START Condition
1
A
0
0
0
0
Auto-Increment
on All Registers
R/W
0
0
0
MODE1Register
Selection
1
Sr
A
0
A3
0
Data from MODE1 Register
A2
A1
A0
Repeated Start
A
A
(cont.)
Acknowledge
From Master
R/W
Acknowledge
From Slave
Acknowledge
From Slave
1
Acknowledge
From Slave
Auto-Increment On
Data from ALLCALLADR Register
Data from PWM0 Register
Data from MODE2 Register
(cont.)
Data from MODE1 Register
A
A
A
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
A
(cont.)
Acknowledge
From Master
Data from Last Read Byte
(cont.)
P
A
Not Acknowledge
From Master
STOP
Condition
Figure 16. Read All Registers With the Auto-Increment Feature
Sequence A
S
1
0
0
A3
A2
New LED All-Call I2C Address(B)
Control Register
Slave Address
A1
A0
START Condition
0
A
X
X
1
X
0
0
0
1
A
1
0
0
1
1
0
1
ALLCALLADR
Register Selection
R/W
X
P
Acknowledge
From Slave
STOP
Condition
Acknowledge
From Slave
Acknowledge
From Slave
A
Auto-Increment Flag
Sequence B
S
1
0
0
1
1
0
START Condition
The 16 LEDs are ON at Acknowledge
LEDOUT0 Register (LED0–LED3 Fully ON)(C)
Control Register
LED All-Call I2C Address
1
0
A
X
X
0
X
1
1
0
0
A
0
1
LEDOUT0 Register Selection
R/W
Acknowledge
From Slave
0
1
0
1
0
1
A
P
Acknowledge
From Slave
Acknowledge
From the 4 Devices
STOP
Condition
Auto-Increment Flag
A.
In this example, four TLC59108Fs are used with the same sequence sent to each.
B.
ALLCALL bit in MODE1 register is equal to 1 for this example.
C.
OCH bit in MODE2 register is equal to 1 for this example.
Figure 17. LED All-Call I2C Bus Address Programming and LED All-Call Sequence Example
20
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PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC59108FIPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
TLC59108FIRGYR
VQFN
RGY
20
3000
180.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC59108FIPWR
TLC59108FIRGYR
TSSOP
PW
20
2000
346.0
346.0
33.0
VQFN
RGY
20
3000
190.5
212.7
31.8
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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