SN74AS230A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SDAS213B – DECEMBER 1982 – REVISED DECEMBER 1994 • • • • • DW OR N PACKAGE (TOP VIEW) True and Complementary Outputs 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers High Capacitive-Drive Capability Current-Sinking Capability Up to 64 mA Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND description 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 This octal buffer/driver is designed specifically to 10 11 improve the performance of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. When used together, multiples of this device provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE) inputs, and complementary OE and OE inputs. The SN74AS230A is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each buffer) INPUTS OUTPUT Y OE A L H L L L H H X Z logic symbol† 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 EN 2 18 4 16 6 14 8 12 19 1Y1 1Y2 1Y3 1Y4 EN 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AS230A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SDAS213B – DECEMBER 1982 – REVISED DECEMBER 1994 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 2 18 4 16 6 14 8 12 1Y1 1Y2 1Y3 1Y4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions VCC VIH Supply voltage VIL IOH Low-level input voltage IOL TA Low-level output current 2 High-level input voltage MIN NOM MAX 4.5 5 5.5 2 High-level output current Operating free-air temperature 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V – 15 mA 64 mA 70 °C SN74AS230A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SDAS213B – DECEMBER 1982 – REVISED DECEMBER 1994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS TYP† MIN MAX UNIT – 1.2 V VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VCC = 4 4.5 5V IOH = – 3 mA IOH = – 15 mA VOL IOZH VCC = 4.5 V, VCC = 5.5 V, IOL = 64 mA VO = 2.7 V IOZL II VCC = 5.5 V, VCC = 5.5 V, VO = 0.4 V VI = 7 V IIH VCC = 5.5 V, VI = 2.7 V VCC = 5 5.5 5V V, VI = 0 0.4 4V IO‡ VCC = 5.5 V, VO = 2.25 V Outputs high 16 25 ICC VCC = 5.5 V Outputs low 55 87 Outputs disabled 29 46 VOH IIL 2A inputs All other inputs VCC – 2 2.4 V 3.4 2.4 0.31 0.55 V 50 µA – 50 µA 0.1 mA 20 µA –1 – 0.5 – 50 – 150 mA mA mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL 1A 1Y tPLH tPHL 2A 2Y tPZH tPZL 1OE 1Y tPHZ tPLZ 1OE 1Y tPZH tPZL 2OE 2Y tPHZ tPLZ 2OE 2Y VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX§ MIN MAX 2 6.5 1 5.7 2 6.2 1 6.2 2 6.4 2 8.5 2 6 2 9.5 2 9 2 7.5 2 6 2 9 UNIT ns ns ns ns ns ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74AS230A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SDAS213B – DECEMBER 1982 – REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated