TI SN54HC193

SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MAY 1997
D
D
D
D
D
Look-Ahead Circuitry Enhances Cascaded
Counters
Fully Synchronous in Count Modes
Parallel Asynchronous Load for Modulo-N
Count Lengths
Asynchronous Clear
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
SN54HC193 . . . J OR W PACKAGE
SN74HC193 . . . D OR N PACKAGE
(TOP VIEW)
B
QB
QA
DOWN
UP
QC
QD
GND
description
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of either count
(clock) input (UP or DOWN). The direction of
counting is determined by which count input is
pulsed while the other count input is high.
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
A
CLR
BO
CO
LOAD
C
D
QB
B
NC
VCC
A
SN54HC193 . . . FK PACKAGE
(TOP VIEW)
QA
DOWN
NC
UP
QC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
CLR
BO
NC
CO
LOAD
QD
GND
NC
D
C
The ’HC193 are 4-bit synchronous, reversible,
up/down binary counters. Synchronous operation
is provided by having all flip-flops clocked
simultaneously so that the outputs change
coincidentally with each other when so instructed
by the steering logic. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple-clock)
counters.
1
NC – No internal connection
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on
the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the
data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The
clear function is independent of the count and LOAD inputs.
These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output
produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)
output produces a low-level pulse while the count is maximum (9 or 15) and UP is low. The counters can then
be easily cascaded by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter.
The SN54HC193 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC193 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MAY 1997
logic symbol†
CLR
UP
DOWN
LOAD
A
B
C
D
14
5
4
11
15
1
CT=0
CTRDIV16
2+
G1
1CT=15
1–
G2
2CT=0
3D
[1]
[2]
3
2
6
[4]
[8]
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
2
13
CO
BO
C3
10
9
12
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• DALLAS, TEXAS 75265
7
QA
QB
QC
QD
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MAY 1997
logic diagram (positive logic)
12
13
CLR
UP
DOWN
LOAD
A
CO
BO
14
5
4
S
11
R
15
S
3
QA
C1
1D
R
B
1
S
2
QB
C1
1D
R
C
10
S
6
QC
C1
1D
R
D
9
S
7
QD
C1
1D
R
Pin numbers shown are for the D, J, N, and W packages.
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3
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MAY 1997
typical clear, load, and count sequence
The following sequence is illustrated below:
1. Clear outputs to 0
2. Load (preset) to binary 13
3. Count up to 14, 15, carry, 0, 1, and 2
4. Count down to 1, 0, borrow, 15, 14, and 13
CLR
LOAD
A
Data
Inputs
B
C
D
UP
DOWN
QA
Data
Outputs
QB
QC
QD
CO
BO
0
13
Clear
Preset
14
0
15
Count Up
1
2
1
0
15
14
Count Down
NOTES: A. CLR overrides LOAD, data, and count inputs.
B. When counting up, count-down input must be high; when counting down, count-up input must be high.
4
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13
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HC193
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
Low-level input voltage
VI
VO
Input voltage
Output voltage
tt‡
Input transition (rise and fall) time
SN74HC193
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
V
V
0
0.5
0
0.5
0
1.35
0
1.35
0
1.8
0
1.8
0
0
0
VCC
VCC
0
VCC
VCC
VCC = 2 V
VCC = 4.5 V
0
1000
0
1000
0
500
0
500
VCC = 6 V
0
400
0
400
VCC = 4.5 V
VCC = 6 V
UNIT
V
V
V
ns
TA
Operating free-air temperature
–55
125
–40
85
°C
‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
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5
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
IOL = 20 µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
VI = VCC or 0
VI = VCC or 0,
IO = 0
VCC
MIN
TA = 25°C
TYP
MAX
MIN
MAX
SN74HC193
MIN
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
µA
3
10
10
10
pF
6V
Ci
SN54HC193
2 V to 6 V
V
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
CLR high
tw
Pulse duration
LOAD low
UP or DOWN high or low
Data before LOAD inactive
tsu
Setup time
CLR inactive before UP↑
↑ or DOWN↑
↑
LOAD inactive before UP↑
↑ or DOWN↑
↑
th
6
Hold time
Data after LOAD inactive
POST OFFICE BOX 655303
TA = 25°C
MIN
MAX
SN54HC193
SN74HC193
MIN
MAX
MIN
MAX
2V
0
4.2
0
2.8
0
3.3
4.5 V
0
21
0
14
0
17
6V
0
24
0
16
0
19
2V
120
180
150
4.5 V
24
36
30
6V
21
31
26
2V
120
180
150
4.5 V
24
36
30
6V
21
31
26
2V
120
180
150
4.5 V
24
36
30
6V
21
31
26
2V
110
165
140
4.5 V
22
33
28
6V
19
28
24
2V
110
165
140
4.5 V
22
33
28
6V
19
28
24
2V
110
165
140
4.5 V
22
33
28
6V
19
28
24
2V
5
5
5
4.5 V
5
5
5
6V
5
5
5
• DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
UP
DOWN
CO
BO
tpd
d
UP or DOWN
LOAD
tPHL
CLR
tt
Any Q
Any Q
Any Q
Any
MIN
TA = 25°C
TYP
MAX
2V
4.2
8
2.8
3.3
4.5 V
21
55
14
17
6V
24
60
16
19
VCC
SN54HC193
MIN
MAX
SN74HC193
MIN
MAX
UNIT
MHz
2V
75
165
250
205
4.5 V
24
33
50
41
6V
20
28
43
35
2V
75
165
250
205
4.5 V
24
33
50
41
6V
20
28
43
35
2V
190
250
375
315
4.5 V
40
50
75
63
6V
35
43
64
54
2V
190
260
390
325
4.5 V
40
52
78
65
6V
35
44
66
55
2V
170
240
360
300
4.5 V
36
48
72
60
6V
31
41
61
51
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load
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TYP
50
UNIT
pF
7
SN54HC193, SN74HC193
4-BIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122B – DECEMBER 1982 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
VCC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL = 50 pF
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
VCC
50%
50%
0V
tPLH
Reference
Input
VCC
50%
In-Phase
Output
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
90%
90%
tr
th
90%
50%
10%
tPHL
Out-of-Phase
Output
90%
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
tPLH
50%
10%
tf
tf
VOH
50%
10%
VOL
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
8
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Copyright  1998, Texas Instruments Incorporated