RHL (QFN) D-8 (SOIC) www.ti.com D-14 (SOIC) SN65HVD30 – SN65HVD39 SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 3.3 V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS FEATURES 1 • • • • • • • • • • (1) 1/8 Unit-Load Option Available (Up to 256 Nodes on the Bus) Bus-Pin ESD Protection Exceeds 15 kV HBM Optional Driver Output Transition Times for Signaling Rates(1) of 1 Mbps, 5 Mbps and 26 Mbps Low-Current Standby Mode: < 1 µA Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications 5-V Tolerant Inputs Bus Idle, Open, and Short Circuit Failsafe Driver Current Limiting and Thermal Shutdown Meets or Exceeds the Requirements of ANSI TIA/EIA-485-A and RS-422 Compatible 5-V Devices available, SN65HVD50-59 Line Signaling Rate is the number of voltage transitions made per second expressed in units of bps (bits per second). APPLICATIONS • • • • Utility Meters DTE/DCE Interfaces Industrial, Process, and Building Automation Point-of-Sale (POS) Terminals and Networks DESCRIPTION Each driver and receiver has separate input and output pins for full-duplex bus communication designs. They are designed for balanced transmission lines and inter-operation with ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11 and ISO 8482:1993 standard-compliant devices. The SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36 and SN65HVD37 are fully enabled with no external enabling pins. The SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38, and SN65HVD39 have active-high driver enables and active-low receiver enables. A low, less than 1µA, standby current can be achieved by disabling both the driver and receiver. All devices are characterized for ambient temperatures from –40°C to 85°C. Low power dissipation allows operation at temperatures up to 105°C or 125°C, depending on package option. The preview devices SN65HVD36 and SN65HVD38 implement receiver equalization technology for improved jitter performance on differential bus applications with data rates up to 20 Mbps at cable lengths up to 160 meters. The preview devices SN65HVD37 and SN65HVD39 implement receiver equalization technology for improved jitter performance on differential bus applications with data rates in the range of 1 to 5 Mbps at cable lengths up to 1000 meters. The SN65HVD3X devices are 3-state differential line drivers and differential-input line receivers that operate with 3.3-V power supply. IMPROVED REPLACEMENT FOR: Part Number Replace with xxx3491 xxx3490 SN65HVD33: SN65HVD30: Better ESD protection (15kV vs 2kV or not specified) Higher Signaling Rate (26Mbps vs 20Mbps) Fractional Unit Load (64 Nodes vs 32) MAX3491E MAX3490E SN65HVD33: SN65HVD30: Higher Signaling Rate (26Mbps vs 12Mbps) Fractional Unit Load (64 Nodes vs 32) MAX3076E MAX3077E SN65HVD33: SN65HVD30: Higher Signaling Rate (26Mbps vs 16Mbps) Lower Standby Current (1 µA vs 10 µA) MAX3073E MAX3074E SN65HVD34: SN65HVD31: Higher Signaling Rate (5Mbps vs 500kbps) Lower Standby Current (1 µA vs 10 µA) MAX3070E MAX3071E SN65HVD35: SN65HVD32: Higher Signaling Rate (1Mbps vs 250kbps) Lower Standby Current (1 µA vs 10 µA) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2008, Texas Instruments Incorporated SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36, SN65HVD37 SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38, SN65HVD39 D PACKAGE (TOP VIEW) VCC R D GND R D 1 8 2 7 3 6 4 5 8 2 A 7 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC VCC A B Z Y NC NC - No internal connection B 5 3 NC R RE DE D GND GND A B Z Y Y 6 Z SN65HVD33 RHL PACKAGE (TOP VIEW) VCC NC 2 1 VCC 20 19 NC R 3 18 A RE 4 17 B NC 5 16 NC DE 6 15 Z D 7 14 Y NC 8 13 NC NC 9 12 NC 10 11 GND GND R RE DE D 18 3 17 4 A B 6 14 7 15 Y Z NC - No internal connection 2 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 AVAILABLE OPTIONS SIGNALING RATE UNIT LOADS RECEIVER EQUALIZATION ENABLES BASE PART NUMBER SOIC MARKING 26 Mbps No No SN65HVD30 VP30 5 Mbps 1/8 No No SN65HVD31 VP31 1 Mbps 1/8 No No SN65HVD32 VP32 26 Mbps No Yes SN65HVD33 65HVD33 5 Mbps 1/8 No Yes SN65HVD34 65HVD34 1 Mbps 1/8 No Yes SN65HVD35 65HVD35 Yes No SN65HVD36 PREVIEW Yes No SN65HVD37 PREVIEW Yes Yes SN65HVD38 PREVIEW Yes Yes SN65HVD39 PREVIEW 26 Mbps 5 Mbps 1/8 26 Mbps 5 Mbps 1/8 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) (2) UNIT VCC Supply voltage range –0.3 V to 6 V V(A), V(B), V(Y), V(Z) Voltage range at any bus terminal (A, B, Y, Z) –9 V to 14 V V(TRANS) Voltage input, transient pulse through 100 Ω. See Figure 12 (A, B, Y, Z) (3) –50 to 50 V VI Input voltage range (D, DE, RE) PD(cont) Continuous total power dissipation IO Output current (receiver output only, R) (1) (2) (3) (4) -0.5 V to 7 V Internally limited (4) 11 mA Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. This tests survivability only and the output state of the receiver is not specified. The thermal shutdown protection circuit internally limits the continuous total power dissipation. Thermal shutdown typically occurs when the junction temperature reaches 165°C. DISSIPATION RATINGS PACKAGE SOIC (D) 8 pin SOIC (D) 14 pin QFN (RHL) 20 pin JEDEC THERMAL MODEL TA < 25°C RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C RATING Low k 625 mW 5 mW/°C 325 mW High k 1000 mW 8 mW/°C 520 mW 360 mW Low k 765 mW 6.1 mW/°C 400 mW 275 mW High k 1350 mW 10.8 mW/°C 705 mW 485 mW 270 mW High k 1710 mW 13.7 mW/°C 890 mW 6150 mW 340 mW Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 TA = 105°C RATING TA = 125°C RATING Submit Documentation Feedback 3 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range unless otherwise noted MIN VCC Supply voltage VI or VIC Voltage at any bus terminal (separately or common mode) 1/tUI Signaling rate NOM MAX 3 3.6 –7 (1) 12 SN65HVD30, SN65HVD33, SN65HVD36, SN65HVD38 26 SN65HVD31, SN65HVD34, SN65HVD37, SN65HVD39 5 SN65HVD32, SN65HVD35 1 Differential load resistance VIH High-level input voltage D, DE, RE 2 VCC VIL Low-level input voltage D, DE, RE 0 0.8 VID Differential input voltage –12 12 High-level output current IOL Low-level output current TJ Junction temperature (1) Driver 60 –60 Receiver V Mbps Ω RL IOH 54 UNIT V mA –8 Driver 60 Receiver 8 –40 150 mA °C The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. ELECTROSTATIC DISCHARGE PROTECTION PARAMETER Human body model Bus terminals and GND Human body model (2) Charged-device-model (1) (2) (3) 4 MIN TYP (1) TEST CONDITIONS (3) MAX UNIT ±16 All pins ±4 All pins ±1 kV All typical values at 25°C with 3.3-V supply. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER VI(K) |VOD(SS)| TEST CONDITIONS Input clamp voltage II = –18 mA Steady-state differential output voltage 2.5 RL = 54 Ω, See Figure 1 (RS-485) 1.5 2 2 2.3 RL = 100 Ω, See Figure 1 , (2) (RS-422) Change in magnitude of steady-state differential output voltage between states RL = 54 Ω, See Figure 1 and Figure 2 VOD(RING) Differential Output Voltage overshoot and undershoot RL = 54 Ω, CL = 50 pF, See Figure 5 and Figure 3 VOC(PP) Peak-to-peak common-mode output voltage ΔVOC(SS) Change in steady-state common-mode output voltage HVD30, HVD31, HVD32, HVD36, HVD37 IZ(Z) or IY(Z) High-impedance state output current HVD33, HVD34, HVD35, HVD38, HVD39 IZ(S) or IY(S) Short Circuit output Current II Input current C(OD) Differential output capacitance (1) (2) (3) VCC V 1.5 –0.2 HVD30, HVD33, HVD36, HVD38 Steady-state common-mode output voltage UNIT V IO = 0 Δ|VOD(SS)| HVD31, HVD34, HVD37, HVD39, HVD32, HVD35 MAX –1.5 Vtest = –7 V to 12 V, See Figure 2 VOC(SS) MIN TYP (1) 0.2 V 10% (3) V 0.5 See Figure 4 V 0.25 1.6 2.3 –0.05 0.05 See Figure 4 V VCC = 0 V, VZ or VY = 12 V, Other input at 0 V 90 VCC = 0 V, VZ or VY = –7 V, Other input at 0 V VCC = 3 V or 0 V, DE = 0 V VZ or VY = 12 V VCC = 3 V or 0 V, DE = 0 V VZ or VY = –7 V VZ or VY = –7 V VZ or VY = 12 V –10 µA Other input at 0 V Other input at 0 V D, DE VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 90 –10 –250 250 –250 250 0 100 16 mA µA pF All typical values are at 25°C and with a 3.3-V supply. VCC is 3.3 Vdc ± 5% 10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485 Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 Submit Documentation Feedback 5 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER Propagation delay time, low-to-high-level output tPLH TEST CONDITIONS HVD30, HVD33, HVD36, HVD38 4 10 18 HVD31, HVD34, HVD37, HVD39 25 38 65 HVD32, HVD35 Propagation delay time, high-to-low-level output tPHL Differential output signal rise time tr Differential output signal fall time tf 120 175 305 HVD30, HVD33, HVD36, HVD38 4 9 18 HVD31, HVD34, HVD37, HVD39 25 38 65 HVD32, HVD35 120 175 305 HVD30, HVD33, HVD36, HVD38 2.5 5 12 20 37 60 HVD32, HVD35 120 185 300 HVD30, HVD33, HVD36, HVD38 2.5 5 12 HVD31, HVD34, HVD37, HVD39 20 35 60 120 180 300 HVD31, HVD34, HVD37, HVD39 RL = 54 Ω, CL = 50 pF, See Figure 5 HVD32, HVD35 tsk(p) tPZH1 tPZL1 Propagation delay time, high-impedance-to-low-level output Propagation delay time, low-level-to-high-impedance output tPLZ tPZH2 tPZL2 6 Propagation delay time, high-impedance-to-high-level output Propagation delay time, high-level-to-high-impedance output tPHZ (1) Pulse skew (|tPHL – tPLH|) MIN TYP (1) MAX HVD30, HVD33, HVD36, HVD38 0.6 HVD31, HVD34, HVD37, HVD39 2.0 HVD32, HVD35 5.1 45 HVD34, HVD39 235 HVD33, HVD38 HVD34, HVD39 RL = 110 Ω, RE at 0 V, D = 3 V and S1 = Y, or D = 0 V and S1 = Z See Figure 6 HVD35 HVD35 HVD33, HVD38 HVD34, HVD39 ns ns ns ns 490 25 65 ns 165 HVD33, HVD38 HVD34, HVD39 ns ns HVD33, HVD38 HVD35 UNIT 35 RL = 110 Ω, RE at 0 V, D = 3 V and S1 = Z, or D = 0 V and S1 = Y See Figure 7 HVD35 190 ns 490 30 120 ns 290 Propagation delay time, standby-to-high-level output RL = 110 Ω, RE at 3 V, D = 3 V and S1 = Y, or D = 0 V and S1 = Z See Figure 6 4000 ns Propagation delay time, standby-to-low-level output RL = 110 Ω, RE at 3 V, D = 3 V and S1 = Z, or D = 0 V and S1 = Y See Figure 7 4000 ns All typical values are at 25°C and with a 3.3-V supply. Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER VIT+ Positive-going differential input threshold voltage IO = –8 mA VIT- Negative-going differential input threshold voltage IO = 8 mA Vhys Hysteresis voltage (VIT+ - VIT-) VIK Enable-input clamp voltage Output voltage IO(Z) High-impedance-state output current V II = –18 mA V 2.4 0.4 VO = 0 or VCC, RE at VCC –1 1 VA or VB = 12 V 0.05 0.1 VA or VB = 12 V, VCC = 0 V 0.06 0.1 VA or VB = -7 V Other input at 0V VA or VB = -7 V, VCC = 0 V HVD30, HVD33, HVD36, HVD38 mV –1.5 VID = –200 mV, IO = 8 mA, See Figure 8 Bus input current UNIT –0.20 50 HVD31, HVD32, HVD34, HVD35, HVD37, HVD39 –0.10 –0.04 –0.10 –0.03 VA or VB = 12 V 0.20 0.35 VA or VB = 12 V, VCC = 0 V 0.24 0.4 VA or VB = -7 V Other input at 0V VA or VB = -7 V, VCC = 0 V IIH Input current, RE VIH = 0.8 V or 2 V CID Differential input capacitance VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V (1) MAX –0.02 VID = 200 mV, IO = –8 mA, See Figure 8 VO IA or IB MIN TYP (1) TEST CONDITIONS –0.35 –0.18 –0.25 –0.13 V µA mA mA µA –60 15 pF All typical values are at 25°C and with a 3.3-V supply. SUPPLY CURRENT CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER MIN TYP (1) TEST CONDITIONS HVD30 D at 0 V or VCC and No Load 6.4 HVD36, HVD37 mA 7.9 HVD33 1.8 RE at 0 V, D at 0 V or VCC, DE at 0 V, No load (Receiver enabled and driver disabled) HVD34, HVD35 2.2 HVD38, HVD39 mA 3.8 HVD33, HVD34, HVD35, HVD38, HVD39 Supply current RE at VCC, D at VCC, DE at 0 V, No load (Receiver disabled and driver disabled) 0.022 HVD33 1 µA 2.1 HVD34, HVD35 RE at 0 V, D at 0 V or VCC, DE at VCC, No load (Receiver enabled and driver enabled) HVD38 6.5 3.5 HVD39 8 HVD33 1.8 HVD34, HVD35 RE at VCC, D at 0 V or VCC, DE at VCC No load (Receiver disabled and driver enabled) HVD38 HVD39 (1) UNIT 2.1 HVD31, HVD32 ICC MAX mA 6.2 2.5 7 All typical values are at 25°C and with a 3.3-V supply. Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 Submit Documentation Feedback 7 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted MIN TYP (1) MAX HVD30, HVD33, HVD36, HVD38 26 45 HVD31, HVD32, HVD34, HVD35, HVD37, HVD39 47 70 HVD30, HVD33, HVD36, HVD38 29 45 49 70 PARAMETER tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew (|tPHL – tPLH|) TEST CONDITIONS HVD31, HVD32, HVD34, HVD35, HVD37, HVD39 HVD30, HVD33, HVD36, HVD37, HVD38, HVD39 VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 9 7 HVD31, HVD34, HVD32, HVD35 tr Output signal rise time tf Output signal fall time tPHZ Output disable time from high level tPZH1 Output enable time to high level tPZH2 Propagation delay time, standby-to-high-level output tPLZ Output disable time from low level tPZL1 Output enable time to low level tPZL2 Propagation delay time, standby-to-low-level output (1) UNIT 10 5 ns 6 20 DE at 3 V CL = 15 pF, See Figure 10 20 DE at 0 V 4000 20 DE at 3 V CL = 15 pF, See Figure 11 20 DE at 0 V 4000 All typical values are at 25°C and with a 3.3-V supply RECEIVER EQUALIZATION CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS DEVICE 0m 100 m 25 Mbps 150 m 200 m 200 m tj(pp) Peak-to-peak eye-pattern jitter Pseudo-random NRZ code with a bit pattern length of 216–1, Belden 3105A cable 10 Mbps 250 m 300 m 5 Mbps 3 Mbps 1 Mbps (1) (2) 8 500 m 500 m 1000 m MIN TYP (1) HVD36, HVD38 PREVIEW HVD33 (2) PREVIEW HVD36, HVD38 PREVIEW HVD33 (2) PREVIEW HVD33 (2) PREVIEW HVD36, HVD38 PREVIEW HVD33 (2) PREVIEW HVD36, HVD38 PREVIEW HVD33 (2) PREVIEW HVD36, HVD38 PREVIEW HVD33 (2) PREVIEW HVD36, HVD38 PREVIEW (2) ns PREVIEW HVD37, HVD39 PREVIEW HVD33 (2) PREVIEW (2) PREVIEW HVD34 UNIT PREVIEW HVD36, HVD38 HVD34 MAX HVD36, HVD38 PREVIEW HVD37, HVD39 PREVIEW HVD34 (2) PREVIEW HVD37, HVD39 PREVIEW All typical values are at VCC = 5 V, and temperature = 25°C. The HVD33 and the HVD34 do not have receiver equalization but are specified for comparison. Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 DEVICE POWER DISSIPATION – PD PARAMETER TEST CONDITIONS SOIC-8 θJA θJB Junction-to-Ambient Thermal Resistance SOIC-14 Junction-to- Board Thermal Resistance VALUE JEDEC Low-K model 231 JEDEC High-K model 135 JEDEC Low-K model 163 JEDEC High-K model 92 QFN-20 73 SOIC-8 44 SOIC-14 61 UNITS °C/W °C/W QFN-20 θJC Junction-to-Case Thermal Resistance SOIC-8 43 SOIC-14 59 QFN-20 PD Power Dissipation Driver and receiver enabled, 50% duty cycle square-wave signal at signaling rate: HVD30,33 at 25 Mbps, HVD31,34 at 5 Mbps, HVD32,35 at 1 Mbps HVD30,33 Typical HVD31,34 HVD32,35 HVD30,33 Worst-case HVD31,34 HVD32,35 TSD °C/W 14 VCC = 3.3V, TJ = 25°C, RL = 60 Ω, CL = 50 pF (driver), CL = 15 pF (receiver) VCC = 3.6V, TJ = 140°C, RL = 54 Ω, CL = 50 pF (driver), CL = 15 pF (receiver) Thermal Shut-down Junction Temperature Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 mW 197 213 mW 248 170 Submit Documentation Feedback °C 9 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 PARAMETER MEASUREMENT INFORMATION VCC DE II IY Y VOD 0 or 3 V Z RL IZ VI VZ VY Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions 375 Ω ±1% VCC DE D Y VOD 0 or 3 V 60 Ω ±1% + _ −7 V < V(test) < 12 V Z 375 Ω ±1% Figure 2. Driver VOD With Common-Mode Loading Test Circuit VOD(SS) VOD(RING) 0 V Differential VOD(RING) -VOD(SS) Figure 3. VOD(RING) Waveform and Definitions VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the VOD(H) and VOD(L) steady state values. VCC DE Input D 27 Ω ± 1% Y Y VY Z VZ VOC(PP) Z 27 Ω ± 1% CL = 50 pF ±20% VOC ∆VOC(SS) VOC CL Includes Fixture and Instrumentation Capacitance Input: PRR = 500 kHz, 50% Duty Cycle,t r <6ns, t f <6ns, ZO = 50 Ω Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 10 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 PARAMETER MEASUREMENT INFORMATION (continued) Y W » W Z » W Figure 5. Driver Switching Test Circuit and Voltage Waveforms D 3V 0V 3V S1 Y Z Y VI S1 D VO Z 1.5 V 1.5 V 0.5 V t PZH(1 & 2) 0V V OH DE Input Generator VI RL = 110 W ±1% CL = 50 pF ±20% 50 W VO 2.3 V ~0V tPHZ Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W CL Includes Fixture and Instrumentation Capacitance Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms D 3V 0V VCC S1 Z Y Y D VI S1 3V VI 1.5 V 1.5 V VO DE Input Generator RL = 110 Ω ± 1% 0V Z t PZL(1&2) t PLZ VCC CL = 50 pF ±20% 50 Ω 0.5 V VO 2.3 V VOL Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W CL Includes Fixture and Instrumentation Capacitance Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 Submit Documentation Feedback 11 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 PARAMETER MEASUREMENT INFORMATION (continued) IA VIC VA + VB A IO R VA VID B VB IB 2 VO RE II VI Figure 8. Receiver Voltage and Current Definitions A R Input Generator VI 50 Ω 1.5 V B 0V 3V VO RE 1.5 V VI 1.5 V 0V CL = 15 pF ±20% t PLH VO CL Includes Fixture and Instrumentation Capacitance Generator: PRR = 500 kHz, 50% Duty Cycle, t r <6 ns, t f <6 ns, Zo = 50 Ω t PHL 90% 90% 1.5 V 10% tr VOH 1.5 V 10% V OL tf Figure 9. Receiver Switching Test Circuit and Voltage Waveforms 1.5 V V CC A R 0V B VI 1 k W ±1% 3V A S1 VI C L = 15 pF ±20% RE Input Generator VO 1.5V 1.5V B 0V t PHZ t PZH(1 & 2) V OH 50 W C L Includes Fixture and Instrumentation Capacitance 1.5 V VO 0.5V ~0 V Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms 0V V CC A R 1.5 V B RE Input VI Generator V O 1 k W ±1% S1 C L = 15 pF ±20% 50 W C L Includes Fixture and Instrumentation Capacitance 3V A VI 1.5V 1.5V 0V B tPZL(1 & 2) tPLZ 1.5 V VO V CC 0.5V V OL Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W Figure 11. Receiver Enable Time From Standby (Driver Disabled) 12 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 PARAMETER MEASUREMENT INFORMATION (continued) 0 V or 3 V DE A Y D R Z 100 W ±1% + - Pulse Generator 15 ms duration 1% Duty Cycle tr, tf £ 100 ns 100 W ±1% B RE 0 V or 3 V + - Figure 12. Test Circuit, Transient Over Voltage Test Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 Submit Documentation Feedback 13 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 DEVICE INFORMATION LOW-POWER STANDBY MODE When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. 12 R RE 2 11 A B 3 Low-Power Standby DE 4 9 D 5 10 Y Z Figure 13. Low-Power Standby Logic Diagram If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature. If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation section. If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid. 14 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 FUNCTION TABLES SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38, SN65HVD39 DRIVER INPUTS OUTPUTS D DE Y H H H Z L L H L H X L or open Z Z Open H L H SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38, SN65HVD39 RECEIVER DIFFERENTIAL INPUTS VID = V(A) - V(B) ENABLE RE OUTPUT R VID ≤ −0.2 V L L −0.2 V < VID < −0.02 V L ? −0.02 V ≤ VID L H X H or open Z Open Circuit L H Idle circuit L H Short Circuit, V(A) = V(B) L H SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36, SN65HVD37 DRIVER OUTPUTS INPUT D Y Z H H L L L H Open L H SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36, SN65HVD37 RECEIVER DIFFERENTIAL INPUTS VID = V(A) - V(B) OUTPUT R VID ≤ −0.2 V L −0.2 V < VID < −0.02 V ? −0.02 V ≤ VID H Open Circuit H Idle circuit H Short Circuit, V(A) = V(B) H Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 Submit Documentation Feedback 15 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS D and DE Input RE Input VCC VCC 130 kW Input 470 W Input 470 W 9V 9V 125 kW A Input B Input VCC VCC R1 22 V R1 22 V R3 R3 Input Input 22 V R2 22 V R2 R Output Y and Z Outputs VCC VCC 16 V 5W Output 16 V 16 9V R1/R2 R3 SN65HVD30, SN65HVD33, SN65HVD36, SN65HVD38 9 kΩ 45 kΩ SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35 SN65HVD37, SN65HVD38, SN65HVD39 36 kΩ 180 kΩ Submit Documentation Feedback Output Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS HVD30, HVD33 RMS SUPPLY CURRENT vs SIGNALING RATE HVD31, HVD34 RMS SUPPLY CURRENT vs SIGNALING RATE 55 60 TA =25°C RL = 54 W RE = VCC CL = 50 pF DE = VCC 55 ICC - RMS Supply Current - mA 50 ICC - RMS Supply Current - mA TA =25°C RL = 54 W RE = VCC CL = 50 pF DE = VCC 45 VCC = 3.3 V 40 35 50 VCC = 3.3 V 45 40 35 30 30 0 5 10 15 20 25 0 1 2 3 Signaling Rate - Mbps Signaling Rate - Mbps Figure 14. Figure 15. 4 5 HVD32, HVD35 RMS SUPPLY CURRENT vs SIGNALING RATE 60 TA =25°C RL = 54 W RE = VCC CL = 50 pF DE = VCC ICC - RMS Supply Current - mA 55 50 VCC = 3.3 V 45 40 35 30 0 0.2 0.4 0.6 0.8 1 Signaling Rate - Mbps Figure 16. Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 Submit Documentation Feedback 17 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) HVD30, HVD33 BUS INPUT CURRENT vs INPUT VOLTAGE HVD31, HVD32, HVD34, HVD35 BUS INPUT CURRENT vs INPUT VOLTAGE 250 60 TA = 25°C RE = 0 V DE = 0 V 200 TA = 25°C RE = 0 V DE = 0 V 40 100 II - Bus Input Current - uA II - Bus Input Current - uA 150 50 VCC = 3.3 V 0 -50 -100 20 0 VCC = 3.3 V -20 -40 -150 -200 -60 -7 -4 -1 2 5 8 11 -7 14 -4 -1 VI - Bus Input Voltage - V 8 11 Figure 18. DRIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE DRIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 14 0.01 VCC = 3.3 V DE = VCC D=0V 0.12 VCC = 3.3 V DE = VCC D=0V -0.01 0.1 IOH - High-level Output Current - A IOL - Low-level Output Current - A 5 Figure 17. 0.14 0.08 0.06 0.04 0.02 0 -0.02 -0.03 -0.05 -0.07 -0.09 -0.11 -0.13 0 0.5 1 1.5 2 2.5 VOL - Low-Level Output Voltage - V 3 3.5 0 0.5 1 Submit Documentation Feedback 1.5 2 2.5 3 3.5 VOH - High-Level Output Voltage - V Figure 19. 18 2 VI - Bus Input Voltage - V Figure 20. Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE 2.5 40 TA = 25°C RL = 54 W D = VCC DE = VCC 2.4 3.6 V 35 RL = 60 W IO - Driver Output Current - mA VOD - Differential Output Voltage - V 2.3 2.2 3.3 V 2.1 2 1.9 3V 1.8 30 25 20 15 10 1.7 5 1.6 1.5 0 -60 -40 -20 0 20 40 60 80 90 0 0.5 1 1.5 2 2.5 TA − Free-Air Temperature − oC VCC Supply Voltage - V Figure 21. Figure 22. HVD30, HVD33 DRIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE HVD30, HVD33 DRIVER RISE/FALL TIME vs FREE-AIR TEMPERATURE 3 3.5 5 14 13 4.5 Driver Rise/Fall Time - ns Driver Propagation Delay - ns 12 3V 11 3.6 V 10 9 3V 4 3.6 V 3.5 3 8 2.5 7 2 6 -60 -40 -20 0 20 40 TA − Free-Air Temperature − oC 60 80 90 -60 -40 -20 0 20 40 60 80 90 o TA − Free-Air Temperature − C Figure 23. Figure 24. Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 Submit Documentation Feedback 19 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) RECEIVER THRESHOLD vs COMMON-MODE VOLTAGE 0.00 0.00 −0.02 −0.02 −0.04 −0.04 VIT+ −0.06 Receiver Threshold − V Receiver Threshold − V RECEIVER THRESHOLD vs AMBIENT TEMPERATURE −0.08 −0.10 VIT− −0.12 −0.14 −0.08 −0.10 −0.14 −0.16 −0.18 −0.18 −25 0 25 50 75 100 VIT− −0.12 −0.16 −0.20 −50 VIT+ −0.06 −0.20 −7 125 TA − Ambient Temperature − °C −5 −3 3 5 7 9 Figure 26. SUPPLY CURRENT vs FREE-AIR TEMPERATURE ENABLE TIME vs COMMON-MODE VOLTAGE (SEE Figure 29) 1.4 800 1.2 700 11 HVD35 600 1 3V Enable Time − ns ICC - Supply Current - mA 1 Figure 25. 3.6 V 0.8 0.6 500 HVD34 400 300 0.4 Static, No Load 200 HVD33 0.2 0 -60 100 0 -40 -20 0 20 40 60 80 90 -7 -2 3 8 TA − Free-Air Temperature − C V(TEST) − Common-Mode Voltage − V Figure 27. Figure 28. o 20 −1 VCM − Common-Mode Voltage − V Submit Documentation Feedback 13 Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 SN65HVD30 – SN65HVD39 www.ti.com SLLS665E – SEPTEMBER 2005 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) 375 W ± 1% Y D 0 or 3 V -7 V < V(TEST) < 12 V VOD 60 W ± 1% Z DE 375 W ± 1% Input Generator V 50 W 50% tpZH(diff) VOD (high) 1.5 V 0V tpZL(diff) -1.5 V VOD (low) Figure 29. Driver Enable Time From DE to VOD The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V. Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 – SN65HVD39 Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 12-Feb-2008 PACKAGING INFORMATION (1) Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65HVD30D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 12-Feb-2008 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65HVD30DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD31DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD32DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD33DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN65HVD34DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN65HVD35DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD30DR SOIC D 8 2500 346.0 346.0 29.0 SN65HVD31DR SOIC D 8 2500 346.0 346.0 29.0 SN65HVD32DR SOIC D 8 2500 346.0 346.0 29.0 SN65HVD33DR SOIC D 14 2500 346.0 346.0 33.0 SN65HVD34DR SOIC D 14 2500 346.0 346.0 33.0 SN65HVD35DR SOIC D 14 2500 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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