NEC 2SK3482-Z

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK3482
SWITCHING
N-CHANNEL POWER MOS FET
ORDERING INFORMATION
DESCRIPTION
The 2SK3482 is N-channel MOS Field Effect Transistor
designed for high current switching applications.
PART NUMBER
PACKAGE
2SK3482
TO-251 (MP-3)
2SK3482-Z
TO-252 (MP-3Z)
FEATURES
• Low on-state resistance
RDS(on)1 = 33 mΩ MAX. (VGS = 10 V, ID = 18 A)
RDS(on)2 = 39 mΩ MAX. (VGS = 4.5 V, ID = 18 A)
• Low Ciss: Ciss = 3600 pF TYP.
• Built-in gate protection diode
• TO-251/TO-252 package
(TO-251)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
100
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
V
Drain Current (DC)
ID(DC)
±36
A
ID(pulse)
±100
A
Total Power Dissipation (TC = 25°C)
PT
50
W
Total Power Dissipation (TA = 25°C)
PT
1.0
W
Channel Temperature
Tch
150
°C
Drain Current (Pulse)
Note1
Storage Temperature
Tstg
–55 to +150
°C
Single Avalanche Current
Note2
IAS
30
A
Single Avalanche Energy
Note2
EAS
90
mJ
(TO-252)
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, RG = 25 Ω, VGS = 20 → 0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D15064EJ2V0DS00 (2nd edition)
Date Published August 2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2001
2SK3482
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = 100 V, VGS = 0 V
10
µA
Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
µA
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
2.0
2.5
V
| yfs |
VDS = 10 V, ID = 18 A
12
23
RDS(on)1
VGS = 10 V, ID = 18 A
27
33
mΩ
RDS(on)2
VGS = 4.5 V, ID = 18 A
29
39
mΩ
Gate Cut-off Voltage
Forward Transfer Admittance
Note
Drain to Source On-state Resistance
Note
S
Input Capacitance
Ciss
VDS = 10 V
3600
pF
Output Capacitance
Coss
VGS = 0 V
360
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
190
pF
Turn-on Delay Time
td(on)
VDD = 50 V, ID = 18 A
15
ns
VGS = 10 V
10
ns
RG = 0 Ω
68
ns
6
ns
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
VDD = 80 V
72
nC
Gate to Source Charge
QGS
VGS = 10 V
10
nC
QGD
ID = 36 A
19
nC
VF(S-D)
IF = 36 A, VGS = 0 V
1.0
V
Reverse Recovery Time
trr
IF = 36 A, VGS = 0 V
70
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/µs
180
nC
Gate to Drain Charge
Body Diode Forward Voltage
Note
Note Pulsed
TEST CIRCUIT 2 SWITCHING TIME
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
PG.
50 Ω
VDD
VGS = 20 → 0 V
RG
PG.
VGS
VGS
Wave Form
0
90%
ID
VGS
0
ID
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
2
IG = 2 mA
RL
50 Ω
VDD
10%
0 10%
Wave Form
τ
VDD
PG.
90%
BVDSS
VDS
ID
90%
VDD
ID
IAS
VGS
10%
Data Sheet D15064EJ2V0DS
td(on)
tr
ton
td(off)
tf
toff
2SK3482
TYPICAL CHARACTERISTICS (TA = 25°C)
FORWARD
BIAS
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
120
60
100
50
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
DERATING FACTOR OF
SAFE OPERATING AREA
80
60
40
20
40
30
20
10
0
0
0
25
50
75
100
125
150
175
0
25
TC - Case Temperature - °C
50
75
100
125
150
175
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
1000
10
d
ite V)
im 10
L
)
=
on
S( GS
RDat V
(
10
0
ID(DC) = 36 A
DC
10
1
PW
µs
=
10
µs
m
s
m
s
Po
Lim we
ite r Di
d s
1
sip
at
ion
TC = 25˚C
Single Pulse
0.1
0.1
1
10
100
VDS - Drain to Source Voltage - V
1000
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
rth(t) - Transient Thermal Resistance - °C/W
ID - Drain Current - A
ID(pulse) = 100 A
100
Rth(ch-A) = 125˚C/W
100
Channel to Ambient
10
Rth(ch-C) = 2.5˚C/W
Channel to Case
1
0.1
Single Pulse
0.01
10 µ
100 µ
1m
10 m
100 m
1
PW - Pulse Width - s
Data Sheet D15064EJ2V0DS
10
100
1000
3
2SK3482
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
100
90
Pulsed
80
VGS = 10 V
10
ID - Drain Current - A
ID - Drain Current - A
70
60
4.5 V
50
40
30
20
TA = 150°C
75°C
-25°C
-40°C
1
0.1
VDS = 10 V
Pulsed
10
0.01
0
0
1
2
3
4
0
5
1
VDS - Drain to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
3.5
| yfs | - Forward Transfer Admittance - S
VGS(off) – Gate Cut-off Voltage - V
4
5
100
V SD = 10 V
ID = 1mA
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-50
-25
0
25
50
75
100 125 150
10
T A= 15 0 °C
7 5°C
2 5 °C
-4 0 ° C
1
0 .1
V DS= 10V
P u ls e d
0 .0 1
0 .0 1
0 .1
Tch - Channel Temperature - °C
60
50
40
V G S = 4 .5 V
10 V
10
0
0 .1
1
10
100
RDS(on) - Drain to Source On-state Resistance - mΩ
P u ls e d
20
10
100
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
70
30
1
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
RDS(on) - Drain to Source On-state Resistance - mΩ
3
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
4.0
ID - Drain Current - A
4
2
VGS - Gate to Source Voltage - V
50
Pulsed
45
40
ID = 36 A
18 A
35
30
25
7.2 A
20
15
10
5
0
0
2
4
6
8
10
12
14
16
VGS - Gate to Source Voltage - V
Data Sheet D15064EJ2V0DS
18
20
2SK3482
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
80
10000
Pulsed
C iss
60
50
V GS = 4.5 V
40
10 V
30
20
10
C oss
1000
C rss
100
V GS = 0 V
f = 1 MHz
0
-50
-25
0
25
50
75
10
0.01
100 125 150
Tch - Channel Temperature - °C
SWITCHING CHARACTERISTICS
100
t d(off)
td(on)
10
tr
10
ID = 36 A
90
VDS - Drain to Source Voltage - V
td(on), tr, td(off), tf - Switching Time - ns
100
V DD = 80 V
50 V
20 V
80
8
V GS
70
60
6
50
40
4
30
20
2
VDS
10
1
0
0.1
1
10
100
0
0
10
20
30
40
50
60
70
80
ID - Drain Current - A
QG - Gate Charge - nC
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
REVERSE RECOVERY TIME vs. DRAIN CURRENT
1000
100
di/dt = 100 A/ µ s
VGS = 0 V
trr - Reverse Recovery Time - ns
V GS = 10 V
ISD - Diode Forward Current - A
10
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
V DD = 50 V
V G S = 10 V
RG = 0 Ω
100
1
VDS - Drain to Source Voltage - V
1000
tf
0.1
10
0V
1
0.1
100
10
Pulsed
0.01
0.0
1
0.5
1.0
1.5
VSD - Source to Drain Voltage - V
0.1
1
10
100
IF - Drain Current - A
Data Sheet D15064EJ2V0DS
5
VGS - Gate to Drain Voltage - V
70
Ciss, Coss, Crss - Capacitance - pF
RDS(on) - Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
2SK3482
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
SINGLE AVALANCHE ENERGY
DERATING FACTOR
120
V D D = 50 V
V G S = 20 → 0 V
R G = 25 Ω
100
I AS = 30 A
E AS = 90 m J
10
1
0.001
80
60
40
20
0
25
0.01
0.1
1
50
75
100
125
150
10
Starting Tch - Starting Channel Temperature - °C
L - Inductive Load - mH
6
V D D = 50 V
V G S = 20 → 0 V
R G = 25 Ω
I A S ≤ 30 A
100
Energy Derating Factor - %
IAS - Single Avalanche Current - A
1000
Data Sheet D15064EJ2V0DS
2SK3482
PACKAGE DRAWINGS (Unit: mm)
2) TO-252 (MP-3Z)
1.1 ±0.2
+0.2
0.5 −0.1
+0.2
0.5 −0.1
0.75
2.3 2.3
1. Gate
2. Drain
3. Source
4. Fin (Drain)
1
2
3
1.5 −0.1
2.3 ±0.2
1.0 MIN.
1.8TYP.
0.5 ±0.1
0.9
0.8
2.3 2.3 MAX. MAX.
0.8
1. Gate
2. Drain
3. Source
4. Fin (Drain)
0.7
0.8 4.3 MAX.
1.1 ±0.2
13.7 MIN.
3
7.0 MIN.
2
5.5 ±0.2
1.6 ±0.2
1
4
5.5 ±0.2
10.0 MAX.
6.5 ±0.2
5.0 ±0.2
0.5 ±0.1
4
+0.2
2.3 ±0.2
2.0
MIN.
5.0 ±0.2
1.5 −0.1
6.5 ±0.2
+0.2
1) TO-251 (MP-3)
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
Data Sheet D15064EJ2V0DS
7
2SK3482
• The information in this document is current as of August, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
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M8E 02. 11-1