TI TMS320UC5405

TMS320UC5405 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS199B
October 2002 − Revised October 2004
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2004, Texas Instruments Incorporated
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS199A device-specific data
sheet to make it an SPRS199B revision.
Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the
specified release date with the following changes.
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
Global:
Added “ZQW” mechanical data package device-specific information.
Moved “Package Thermal Resistance Characteristics” section (was page 42 in SPRS199A) to the Mechanical Data section
18
Signal Descriptions table, TEST PINS:
Added “EMU0 should be pulled up to DVDD with a separate 4.7-kΩ resistor” to the EMU0 pin DESCRIPTION column
Added “EMU1/OFF should be pulled up to DVDD with a separate 4.7-kΩ resistor” to the EMU1/OFF pin DESCRIPTION
column
39
Device Support section:
Added new section
Added associated figure
74
Mechanical Data section:
Deleted the “GQW (S−PBGA−N143)” mechanical data package diagram; now an automated merge process
Added lead-in sentences for the thermal resistance characteristics table(s) and the “merged” mechanical data packages
Added “for GQW” to the Thermal Resistance Characteristics table
Added Thermal Resistance Characteristics table for the “ZQW” package
October 2002 − Revised October 2004
SPRS199B
3
Revision History
This page intentionally left blank
4
SPRS199B
October 2002 − Revised October 2004
Contents
Contents
Section
Page
1
TMS320UC5405 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Terminal Assignments for the GQW and ZQW Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
13
15
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
On-Chip ROM With Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4
Implications of 6-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5
Relocatable Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
Software-Programmable Wait-State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1
IFR and IMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
20
21
21
22
23
23
26
28
28
30
33
33
34
35
35
37
38
4
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
5
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Electrical Characteristics Over Recommended Operating Case Temperature Range . . . . . . .
6.4
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.1
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.2
Divide-By-Two Clock Option (PLL disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.3
Multiply-By-N Clock Option (PLL Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
42
42
43
44
45
45
46
47
October 2002 − Revised October 2004
SPRS199B
5
Contents
Section
6.6
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.1
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.2
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.3
I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.4
I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Timing for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Flag (XF) and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.1
McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.2
McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.3
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host-Port Interface Timing (HPI8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
48
50
52
53
54
57
58
60
61
62
62
65
66
70
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
6
Page
SPRS199B
October 2002 − Revised October 2004
Figures
List of Figures
Figure
Page
2−1
143-Terminal GQW and ZQW Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
3−10
Block Diagram of the TMS320UC5405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320UC5405 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320UC5405 External Memory Paging Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Mode Status (PMST) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] . . .
Software Wait-State Control Register (SWCR) [MMR Address 002Bh] . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) [MMR Address 0029h] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI8 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFR and IMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
21
22
22
23
24
25
26
30
38
4−1
TMS320UC5405 DSP Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
6−1
6−2
6−3
6−4
6−5
6−6
6−7
6−8
6−9
6−10
6−11
6−12
6−13
6−14
6−15
6−16
6−17
6−18
6−19
6−20
6−21
6−22
6−23
6−24
1.8-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Divide-by-Two Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiply-by-One Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timings (HM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset and BIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MP/MC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IACK Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
43
45
46
47
49
51
52
53
54
55
55
56
57
58
59
59
60
61
61
64
64
65
66
67
October 2002 − Revised October 2004
SPRS199B
7
Figures
Figure
6−25
6−26
6−27
6−28
6−29
6−30
8
Page
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
Using HDS to Control Accesses (HCS Always Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using HCS to Control Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIOx Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRS199B
68
69
72
73
73
73
October 2002 − Revised October 2004
Tables
List of Tables
Table
Page
2−1
2−2
Terminal Assignments (143-Terminal GQW and ZQW Packages) . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
15
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
3−10
3−11
3−12
3−13
3−14
Standard On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Control Register (SWCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode Settings at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFR and IMR Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
24
24
25
29
32
32
32
33
34
35
36
37
38
6−1
6−2
6−3
6−4
6−5
6−6
6−7
6−8
6−9
6−10
6−11
6−12
6−13
6−14
6−15
6−16
6−17
6−18
6−19
6−20
6−21
6−22
6−23
6−24
6−25
6−26
6−27
6−28
Divide-By-2 and Divide-by-4 Clock Options Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Timing Requirements for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Acknowledge (IACK) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Flag (XF) and TOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .
46
46
47
47
48
48
50
52
52
53
54
57
57
58
60
61
62
63
65
65
66
66
67
67
68
68
69
69
October 2002 − Revised October 2004
SPRS199B
9
Tables
Table
Page
6−29
6−30
HPI8 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI8 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
71
7−1
7−2
Thermal Resistance Characteristics for GQW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance Characteristics for ZQW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
74
10
SPRS199B
October 2002 − Revised October 2004
Features
1
TMS320UC5405 Features
D Advanced Multibus Architecture With Three
D
D
D
D
D
D
D
D
D
D
D
D
D
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Simplified External Memory Interface
(6-Bit Address Available, A0−A5)
Data Bus With a Bus-Holder Feature
4K x 16-Bit On-Chip ROM
16K x 16-Bit On-Chip Dual-Access RAM
(DARAM)
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for
Efficient Program and Data Management
Instructions With a 32-Bit-Long Word
Operand
Instructions With Two- or Three-Operand
Reads
D Arithmetic Instructions With Parallel Store
and Parallel Load
D Conditional Store Instructions
D Fast Return From Interrupt
D On-Chip Peripherals
D
D
D
D
D
D
D
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
− Two Multichannel Buffered Serial Ports
(McBSPs)
− Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
− Two 16-Bit Timers
− Six-Channel Direct Memory Access
(DMA) Controller
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic
12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS)
1.8-V Core Power Supply
1.8-V to 3.6-V I/O Power Supply Enables
Operation With a Single 1.8-V Supply or
With Dual Supplies
Available in a 143-Ball MicroStar Junior
Ball Grid Array (BGA) (GQW/ZQW Suffixes)
MicroStar Junior is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
October 2002 − Revised October 2004
SPRS199B
11
Introduction
2
Introduction
This section describes the main features of the TMS320UC5405, lists the pin assignments, and describes the
function of each pin. This data manual also provides a detailed description section, electrical specifications,
parameter measurement information, and mechanical data about the available packaging.
NOTE: This data manual is designed to be used in conjunction with theTMS320C54x DSP Functional
Overview (literature number SPRU307).
2.1
Description
The TMS320UC5405 fixed-point, digital signal processor (DSP) (hereafter referred to as the UC5405 unless
otherwise specified) is ideal for low-power, high-performance applications. This processor offers very low
power consumption and the flexibility to support various system voltage configurations. The wide range of I/O
voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed-voltage
systems. This feature eliminates the need for external level-shifting and reduces power consumption in
emerging sub-3V systems.
The TMS320UC5405 is essentially similar to a TMS320UC5402 DSP. The main differences are listed below:
•
Simplified external memory interface. There are six address lines (A0−A5) and 16 data lines (D0−D15)
available.
•
MSC and IAQ signals are not available.
•
Significantly reduced package size.
Texas Instrument (TI) DSPs do not require specific power sequencing between the core supply and the I/O
supply. However, systems should be designed to ensure that neither supply is powered up for extended
periods of time if the other supply is below the proper operating voltage. Excessive exposure to these
conditions can adversely affect the long-term reliability of the device.
System-level concerns such as bus contention may require supply sequencing to be implemented. In this
case, the core supply should be powered up at the same time as, or prior to, the I/O buffers and powered down
after the I/O buffers.
The UC5405 is based on an advanced modified Harvard architecture that has one program memory bus and
three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
2.2
Pin Assignments
Figure 2−1 illustrates the ball locations for the 143-terminal GQW and ZQW ball grid array (BGA) packages
and is used in conjunction with Table 2−1 to locate signal names and ball grid numbers. DVDD is the power
supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O
pins and the core CPU.
TMS320C54x is a trademark of Texas Instruments.
12
SPRS199B
October 2002 − Revised October 2004
Introduction
2.3
Terminal Assignments for the GQW and ZQW Packages
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12
Figure 2−1. 143-Terminal GQW and ZQW Ball Grid Array (Bottom View)
October 2002 − Revised October 2004
SPRS199B
13
Introduction
Table 2−1. Terminal Assignments (143-Terminal GQW and ZQW Packages)†
BGA BALL #
SIGNAL
NAME
BGA BALL #
SIGNAL
NAME
BGA BALL #
SIGNAL
NAME
BGA BALL #
SIGNAL
NAME
A1
VSS
D1
BDR1
G1
DVDD
K1
INT1
A2
VSS
D2
BFSR1
G2
VSS
K2
INT0
A3
MP/MC
D3
BFSR0
G3
HRDY
K3
INT3
A4
HOLDA
D4
NC
G4
NC
K4
EMU0
A5
IOSTRB
D5
NC
G5
NC
K5
TDI
A6
IS
D6
NC
G6
NC
K6
TMS
A7
READY
D7
NC
G7
NC
K7
CVDD
A8
CVDD
D8
NC
G8
NC
K8
X1
A9
VSS
D9
NC
G9
NC
K9
D0
A10
HD7
D10
A1
G10
D14
K10
D3
A11
VSS
D11
DVDD
G11
HD4
K11
DVDD
A12
CVDD
D12
A0
G12
D13
K12
D6
B1
BCLKR1
E1
VSS
H1
BDX0
L1
CVDD
B2
HCNTL0
E2
BCLKX1
H2
HD0
L2
HD1
B3
BIO
E3
HINT/TOUT1
H3
BDX1
L3
CLKMD2
B4
XF
E4
HCNTL1
H4
INT2
L4
HD2
B5
MSTRB
E5
NC
H5
NC
L5
EMU1/OFF
B6
DS
E6
NC
H6
NC
L6
TRST
B7
HR/W
E7
NC
H7
NC
L7
VSS
B8
NC
E8
NC
H8
NC
L8
CLKOUT
B9
HAS
E9
NC
H9
NC
L9
X2/CLKIN‡
B10
DVDD
E10
HDS2
H10
D12
L10
D1
B11
A5
E11
HDS1
H11
D10
L11
D5
B12
A4
E12
VSS
H12
D11
L12
VSS
C1
BDR0
F1
BFSX0
J1
HBIL
M1
VSS
C2
BCLKR0
F2
CVDD
J2
IACK
M2
VSS
C3
DVDD
F3
BFSX1
J3
NMI
M3
CLKMD3
C4
HOLD
F4
BCLKX0
J4
DVDD
M4
TOUT0
C5
NC
F5
NC
J5
CLKMD1
M5
TDO
C6
R/W
F6
NC
J6
NC
M6
TCK
C7
PS
F7
NC
J7
NC
M7
HPIENA
C8
HCS
F8
NC
J8
NC
M8
HD3
C9
NC
F9
NC
J9
NC
M9
RS
C10
HD6
F10
D15
J10
D9
M10
D2
C11
A2
F11
CVDD
J11
D7
M11
D4
C12
A3
F12
HD5
J12
D8
M12
VSS
†
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core
CPU.
‡ If an external clock source is used, the CLKIN signal level should not exceed CV
DD + 0.3 V.
NOTE: NC = No connection
14
SPRS199B
October 2002 − Revised October 2004
Introduction
2.4
Signal Descriptions
Table 2−2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2−2. Signal Descriptions
TERMINAL
NAME
TYPE†
DESCRIPTION
DATA SIGNALS
A5
A4
A3
A2
A1
A0
(MSB)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
O/Z
Parallel address bus A5 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. These pins are placed
in the high-impedance state when the hold mode is enabled, or when EMU1/OFF is low.
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer
data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the
high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when EMU1/OFF is low.
(LSB)
The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus
holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven
by the UC5405, the bus holders keep the pins at the previous logic level. The data bus holders on the UC5405
are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).
(LSB)
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A5−A0. IACK also goes into the high-impedance state when EMU1/OFF
is low.
INT0
INT1
INT2
INT3
I
External user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register (IMR) and
the interrupt mode bit. INT0 −INT3 can be polled and reset by way of the interrupt flag register (IFR).
NMI
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM bit (in the ST1
register) or the IMR. When NMI is activated, the processor traps to the appropriate vector location.
RS
I
Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the
CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
I
Microprocessor/microcomputer mode select. If active (low) at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
that is selected at reset.
MP/MC
†
‡
I = input, O = output, Z = high impedance, S = supply
If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
October 2002 − Revised October 2004
SPRS199B
15
Introduction
Table 2−2. Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
MULTIPROCESSING SIGNALS
BIO
XF
I
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the
pipeline; all other instructions sample BIO during the read phase of the pipeline.
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when EMU1/OFF
is low, and is set high at reset.
MEMORY CONTROL SIGNALS
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing
a particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are
placed in the high-impedance state in the hold mode; the signals also go into the high-impedance state when
EMU1/OFF is low.
MSTRB
O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when EMU1/OFF is low.
I
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
R/W
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the
high-impedance state in hold mode; it also goes into the high-impedance state when EMU1/OFF is low.
IOSTRB
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when EMU1/OFF is low.
I
Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the
C54x, these lines go into the high-impedance state.
O/Z
Hold acknowledge. HOLDA indicates that the UC5405 is in a hold state and that the address, data, and control
lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices.
HOLDA also goes into the high-impedance state when EMU1/OFF is low.
READY
HOLD
HOLDA
PLL/TIMER SIGNALS
O/Z
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF
is low.
CLKMD1
CLKMD2
CLKMD3
I
Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The
logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized
to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select
signals have no effect until the device is reset again.
X2/CLKIN‡
I
Clock/PLL input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.
TOUT0
O/Z
Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF is low.
HINT/TOUT1
O/Z
Timer1 output. TOUT1 signals a pulse when the on-chip timer 1 counts down past zero. The pulse is one
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when
the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF is low.
CLKOUT
†
‡
I = input, O = output, Z = high impedance, S = supply
If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
C54x is a trademark of Texas Instruments.
16
SPRS199B
October 2002 − Revised October 2004
Introduction
Table 2−2. Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
BCLKR0
BCLKR1
I/O/Z
Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BDR0
BDR1
I
BFSR0
BFSR1
I/O/Z
Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.
BCLKX0
BCLKX1
I/O/Z
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when
EMU1/OFF goes low.
BDX0
BDX1
O/Z
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when EMU1/OFF is low.
BFSX0
BFSX1
I/O/Z
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX
can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the
high-impedance state when EMU1/OFF is low.
I/O/Z
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0−HD7 is placed in the
high-impedance state when not outputting data or when EMU1/OFF is low. The HPI data bus includes bus
holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not
being driven by the UC5405, the bus holders keep the pins at the previous logic level. The HPI data bus holders
are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.
HCNTL0
HCNTL1
I
Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have
internal pullup resistors that are only enabled when HPIENA = 0.
HBIL
I
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup
resistor that is only enabled when HPIENA = 0.
HCS
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
HDS1
HDS2
I
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs
have internal pullup resistors that are only enabled when HPIENA = 0.
HAS
I
Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA
register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.
HR/W
I
Read/write. HR/W controls the direction of an HPI transfer. HR/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
HRDY
O/Z
Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the
high-impedance state when EMU1/OFF is low.
HINT/TOUT1
O/Z
Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can also
be configured as the timer 1 output (TOUT1) when the HPI is disabled. The signal goes into the high-impedance
state when EMU1/OFF is low.
I
HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor
is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the UC5405
is reset.
Serial data receive input
HOST-PORT INTERFACE SIGNALS
HD0−HD7
HPIENA
SUPPLY PINS
CVDD
S
+VDD. Dedicated power supply for the core CPU
DVDD
S
+VDD. Dedicated power supply for the I/O pins
VSS
S
Ground
†
I = input, O = output, Z = high impedance, S = supply
‡ If an external clock source is used, the CLKIN signal level should not exceed CV
DD + 0.3 V.
October 2002 − Revised October 2004
SPRS199B
17
Introduction
Table 2−2. Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
MISCELLANEOUS SIGNAL
NC
No connection
TCK
I
IEEE standard 1149.1 (JTAG) test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The
changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller,
instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal
(TDO) occur on the falling edge of TCK.
TDI
I
IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when EMU1/OFF is low.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TRST
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode,
and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
EMU0
I/O/Z
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way
of the IEEE standard 1149.1 scan system. EMU0 should be pulled up to DVDD with a separate 4.7-kΩ resistor.
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST
is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active (low), puts all output drivers
into the high-impedance state. EMU1/OFF should be pulled up to DVDD with a separate 4.7-kΩ resistor. Note
that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore,
for the OFF feature, the following apply:
TRST = low
EMU0 = high
EMU1/OFF = low
TEST PINS
EMU1/OFF
†
‡
18
I = input, O = output, Z = high impedance, S = supply
If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
SPRS199B
October 2002 − Revised October 2004
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3−1.
54x Core
16K Dual-Access RAM
Program/Data
Dbus
Cbus
Pbus
Ebus
Dbus
Cbus
Pbus
Ebus
Dbus
Pbus
Cbus
P, C, D, E Buses and Control Signals
4K ROM Program/Data
JTAG
Peripheral Bus
GPIO
Limited External
Memory Interface
McBSP0
HPI8 Module
McBSP1
DMA Controller
6 Channels
Timer0
Timer1
APLL
DMA Bus
Figure 3−1. Block Diagram of the TMS320UC5405
3.1
Memory
The UC5405 device provides both on-chip ROM and RAM to aid in system performance and integration.
3.1.1 On-Chip Dual-Access RAM (DARAM)
The UC5405 device contains 16K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed
of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and
a write in one cycle. The DARAM is located in the address range 0080h−3FFFh in data space, and can be
mapped into program/data space by setting the OVLY bit to 1.
October 2002 − Revised October 2004
SPRS199B
19
Functional Overview
3.1.2 On-Chip ROM With Bootloader
The UC5405 features 4K × 16-bit of on-chip maskable ROM. Customers can arrange to have the ROM of the
UC5405 programmed with contents unique to any particular application. A security option is available to
protect a custom ROM. This security option is described in the TMS320C54x DSP Reference Set, Volume 1:
CPU and Peripherals (literature number SPRU131). Note that only the ROM security option, and not the
ROM/RAM option, is available on the UC5405 .
A bootloader is available in the standard UC5405 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC
pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program. The standard UC5405 bootloader
provides different ways to download the code to accomodate various system requirements:
•
•
Serial boot from serial ports 8-bit or 16-bit mode
Host-port interface boot
The standard on-chip ROM layout is shown in Table 3−1.
Table 3−1. Standard On-Chip ROM Layout†
ADDRESS RANGE
†
20
SPRS199B
DESCRIPTION
F000h − F7FFh
Reserved
F800h − FBFFh
Bootloader
FC00h − FCFFh
µ-law expansion table
FD00h − FDFFh
A-law expansion table
FE00h − FEFFh
Sine look-up table
FF00h − FF7Fh
Reserved
FF80h − FFFFh
Interrupt vector table
In the UC5405 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
October 2002 − Revised October 2004
Functional Overview
3.1.3 Memory Map
Hex Page 0 Program
0000
Page 0 Program
Hex
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
0080
005F
0060
Scratch-Pad
RAM
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
3FFF
4000
Memory
Mapped
Registers
007F
0080
007F
0080
On-Chip DARAM
(OVLY = 1)
External
(OVLY = 0)
Data
Hex
0000
On-Chip DARAM
(16K x 16-bit)
3FFF
4000
3FFF
4000
External†
External†
EFFF
F000
EFFF
F000
External†
FEFF
FF00
FF7F
FF80
Reserved
FF7F
FF80
†
Reserved
(DROM=1)
or External
(DROM=0)
FFFF
FFFF
MP/MC= 1
(Microprocessor Mode)
FEFF
FF00
Interrupts
(On-Chip)
Reserved
FFFF
ROM (DROM=1)
or External†
(DROM=0)
On-Chip ROM
(4K x 16-bit)
MP/MC= 0
(Microcomputer Mode)
Only six of the 16 total TMS320UC5405 address bits are available to the external interface; therefore, only 64 unique external addresses are
available, regardless of the actual 16-bit address generated internally. These 64 addresses are those resulting from the truncation of the upper
address bits (A6 and above). This results in these 64 addresses being repeated throughout all of the external address space.
Figure 3−2. TMS320UC5405 Memory Map
3.1.4 Implications of 6-Bit Addressing
TMS320UC5405 provides only six of the 16 total address bits to the external interface. Therefore, only
64 unique external addresses are available, regardless of the actual 16-bit address generated internally.
These 64 addresses are those resulting from the truncation of the upper address bits (A6 through A15). This
results in these 64 addresses being repeated throughout all of the external address space.
If more than 64 external locations need to be addressed, a paging scheme can be used to expand the
addressing capability as necessary. In this paging scheme, an external register is used to supply the upper
addresses (A6 through A15) for the memory reach greater than six bits. The external register is loaded by
having the 5405 write to a location in I/O space whose data lines are the higher address bits as shown in
Figure 3−3. This scheme can be implemented using either a simple external latch, or can be included in a
FPGA. This paging scheme can be implemented without any decoding required and shares the same bus
with the SRAM and the DSP.
October 2002 − Revised October 2004
SPRS199B
21
Functional Overview
Register
EN
Q0 − Q9
D0 − D9
TMS320UC5405
SRAM
IS
A6 − A15
D15 − D0
D15 − D0
A5 − A0
A5 − A0
PS or DS
CS
Figure 3−3. TMS320UC5405 External Memory Paging Scheme
3.1.5 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see
Figure 3−4) with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or
trap vector is mapped to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
15
8
IPTR
R/W
7
6
5
4
3
2
1
0
IPTR
MP/MC
OVLY
AVIS
DROM
CLKOFF
SMUL
SST
R/W
R/W
R/W
R
R
R
R/W
R/W
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−4. Processor Mode Status (PMST) Register
22
SPRS199B
October 2002 − Revised October 2004
Functional Overview
3.2
On-Chip Peripherals
The UC5405 device supports the following on-chip peripherals:
•
•
•
•
•
•
Software-programmable wait-state generator with programmable bank-switching wait states
An enhanced 8-bit host-port interface (HPI8)
Two multichannel buffered serial ports (McBSPs)
Two hardware timers
A clock generator with a phase-locked loop (PLL)
A direct memory access (DMA) controller
3.2.1 Software-Programmable Wait-State Generator
The software wait-state generator of the UC5405 can extend external bus cycles by up to 14 machine cycles.
Devices that require more than 14 wait states can be interfaced using the hardware READY line. When all
external accesses are configured for zero wait states, the internal clocks to the wait-state generator are
automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the
UC5405.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 15 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to
5 separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 3−5 and described in Table 3−2.
15
14
12
11
9
8
XPA
I/O
DATA
DATA
R/W-0
R/W-111
R/W-111
R/W-111
2
0
7
6
5
3
DATA
PROGRAM
PROGRAM
R/W-111
R/W-111
R/W-111
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
October 2002 − Revised October 2004
SPRS199B
23
Functional Overview
Table 3−2. Software Wait-State Register (SWWSR) Bit Fields
BIT
NO.
NAME
RESET
VALUE
15
XPA
0
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for the program space wait states.
14−12
I/O
1
I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
11−9
Data
1
Upper data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
8−6
Data
1
Lower data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
FUNCTION
Upper program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
5−3
Program
1
-
XPA = 0: x8000 − xFFFFh
-
XPA = 1: The upper program space bit field has no effect on wait states.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
2−0
Program
1
-
XPA = 0: x0000−x7FFFh
-
XPA = 1: 00000−FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
The software wait-state multiplier bit (SWSM) of the software wait-state control register (SWCR) is used to
extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3−6
and described in Table 3−3.
15
8
Reserved
R/W-0
7
1
0
Reserved
SWSM
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3−3. Software Wait-State Control Register (SWCR) Bit Fields
BIT
NO.
NAME
RESET
VALUE
15−1
Reserved
0
FUNCTION
These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
0
24
SWSM
SPRS199B
0
-
SWSM = 0: wait-state base values are unchanged (multiplied by 1).
-
SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.
October 2002 − Revised October 2004
Functional Overview
3.2.1.1
Programmable Bank-Switching Wait States
The programmable bank-switching logic of the UC5405 is functionally equivalent to that of the 548/549
devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within
program or data memory space. A bank-switching wait state can also be automatically inserted when
accesses cross the data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 3−7
shows the BSCR and its bits are described in Table 3−4.
15
12
11
10
8
BNKCMP
PS−DS
Reserved
R/W-1111
R/W-1
R-0
7
3
2
1
0
Reserved
HBH
BH
EXIO
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3−7. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
Table 3−4. Bank-Switching Control Register (BSCR) Bit Fields
NO.
BIT
NAME
RESET
VALUE
FUNCTION
1111
Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of
an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12−15) are compared, resulting in a
bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
PS - DS
1
Program read − data read access. Inserts an extra cycle between consecutive accesses of program read
and data read or data read and program read.
PS-DS = 0
No extra cycles are inserted by this feature.
PS-DS = 1
One extra cycle is inserted between consecutive data and program reads.
Reserved
0
These bits are reserved and are unaffected by writes.
2
HBH
0
HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset.
HBH = 0
The bus holder is disabled.
HBH = 1
The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the
previous logic level.
1
BH
0
Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0
The bus holder is disabled.
BH = 1
The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the
previous logic level.
0
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0
The external bus interface functions as usual.
EXIO = 1
The address bus, data bus, and control signals become inactive after completing the
current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM
bit of ST1 cannot be modified when the interface is disabled.
15−12
11
10−3
0
BNKCMP
EXIO
October 2002 − Revised October 2004
SPRS199B
25
Functional Overview
3.2.2 Parallel I/O Ports
The UC5405 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The UC5405 can
interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding
circuits.
3.2.2.1
Enhanced 8-Bit Host-Port Interface (HPI8)
The UC5405 host-port interface, also referred to as the HPI8, is an enhanced version of the standard 8-bit
HPI found on earlier 54x DSPs (542, 545, 548, and 549). The HPI8 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8 include:
Standard features:
•
•
•
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and 54x interrupt capability
Multiple data strobes and control pins for interface flexibility
Enhanced features of the UC5405 HPI8:
•
•
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
Hex
0000
Reserved
001F
0020
0023
0024
McBSP
Registers
Reserved
005F
0060
Scratch-Pad
RAM
007F
0080
(16K x 16-bit)
On-Chip DARAM
3FFF
4000
Reserved
FFFF
Figure 3−8. HPI8 Memory Map
The HPI8 functions as a slave and enables the host processor to access the on-chip memory of the UC5405.
A major enhancement to the UC5405 HPI over previous versions is that it allows host access to the entire
on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times
and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to
the same location, the host has priority, and the DSP waits for one HPI8 cycle. Note that since host accesses
are always synchronized to the UC5405 clock, an active input clock (CLKIN) is required for HPI8 accesses
during IDLE states, and host accesses are not allowed while the UC5405 reset pin is asserted.
26
SPRS199B
October 2002 − Revised October 2004
Functional Overview
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an
HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC
register is accessible by both the host and the UC5405.
3.2.2.2
Multichannel Buffered Serial Ports
The UC5405 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that
allow direct interface to other C54x/LC54x DSPs, codecs, and other devices in a system. The McBSPs are
based on the standard serial port interface found on other 54x devices. Like its predecessors, the McBSP
provides:
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
•
•
•
•
•
•
Direct interface to:
−
T1/E1 framers
−
MVIP switching compatible and ST-BUS compliant devices
−
IOM-2 compliant devices
−
Serial peripheral interface devices
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
•
•
•
•
•
•
BCLKX
BDX
BFSX
BCLKR
BDR
BFSR
Transmit reference clock
Transmit data
Transmit frame synchronization
Receive reference clock
Receive data
Receive frame synchronization
The six pins listed are functionally equivalent to the previous serial port interface pins in the TMS320C5000
platform of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX
and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit
register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This
structure allows DXR to be loaded with the next word to be sent while the transmission of the current word
is in progress.
On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,
respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received
on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register
(RBR). If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until
the DRR is available. This structure allows storage of the two previous words while the reception of the current
word is in progress.
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP
interrupts, event signals, and status flags. The DMA is capable of handling data movement between the
McBSPs and memory with no intervention from the CPU.
TMS320C5000 is a trademark of Texas Instruments.
October 2002 − Revised October 2004
SPRS199B
27
Functional Overview
In addition to the standard serial port functions, the McBSP provides programmable clock and frame
synchronization generation. Among the programmable functions are:
•
•
•
•
•
•
Frame synchronization pulse width
Frame period
Frame synchronization delay
Clock reference (internal vs. external)
Clock division
Clock and frame synchronization polarity
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmit data is encoded according to specified companding law and received
data is decoded to 2s complement format.
The McBSP allows multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus
bandwidth, multichannel selection allows independent enabling of particular channels for transmission and
reception. Up to 32 channels in a stream of up to 128 channels can be enabled.
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)
protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes
supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP
is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or
as a slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU
clock frequency divided by 2.
3.2.3 Hardware Timer
The UC5405 device features two 16-bit timing circuits with 4-bit prescalers. The main counter of each timer
is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timers can be stopped, restarted, reset, or disabled by specific control bits.
3.2.4 Clock Generator
The clock generator provides clocks to the UC5405 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external reference clock source. The
reference clock input is then divided by two or four (DIV mode) to generate clocks for the UC5405 device, or
the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock
frequency by a scale factor. This allows the use of a clock source with a lower frequency than that of the
CPU.The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the
UC5405 device.
28
SPRS199B
October 2002 − Revised October 2004
Functional Overview
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
•
•
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the UC5405 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to the PLL clocking mode of the device until lock is achieved. Devices that have
a built-in software-programmable PLL can be configured in one of two clock modes:
•
•
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon
reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the
CLKMD1 − CLKMD3 pins as shown in Table 3−5.
Table 3−5. Clock Mode Settings at Reset
CLKMD1
CLKMD2
CLKMD3
CLKMD
RESET VALUE
0
0
0
E007h
PLL x 15
0
0
1
9007h
PLL x 10
0
1
0
4007h
PLL x 5
1
0
0
1007h
PLL x 2
1
1
0
F007h
PLL x 1
1
1
1
0000h
1/2 (PLL disabled)
1
0
1
F000h
1/4 (PLL disabled)
0
1
1
—
October 2002 − Revised October 2004
CLOCK MODE
Reserved (bypass mode)
SPRS199B
29
Functional Overview
3.2.5 DMA Controller
The UC5405 direct memory access (DMA) controller transfers data between points in the memory map
without intervention by the CPU. The DMA controller allows movements of data to and from internal
program/data memory or internal peripherals (such as the McBSPs) to occur in the background of CPU
operation. The DMA has six independent programmable channels, allowing six different contexts for DMA
operation.
3.2.5.1
Features
The DMA has the following features:
•
•
•
•
•
•
•
•
3.2.5.2
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be postincremented,
postdecremented, or be adjusted by a programmable value.
Each read or write transfer may be initialized by selected events.
Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to
the CPU.
The DMA can perform doubleword transfers (a 32-bit transfer of two 16-bit words).
DMA Memory Map
The DMA memory map allows DMA transfers to be unaffected by the status of the MP/MC, DROM, and OVLY
bits. The DMA memory map (see Figure 3−9) is identical to that of the HPI8 controller.
Hex
0000
Reserved
001F
0020
0023
0024
McBSP
Registers
Reserved
005F
0060
Scratch-Pad
RAM
007F
0080
(16K x 16-bit)
On-Chip DARAM
3FFF
4000
Reserved
FFFF
Figure 3−9. DMA Memory Map
3.2.5.3
DMA Priority Level
Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
30
SPRS199B
October 2002 − Revised October 2004
Functional Overview
3.2.5.4
DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be postincremented, postdecremented, or postincremented with a specified index offset.
3.2.5.5
DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
•
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfer; but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
•
Repetitive operation: The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
3.2.5.6
DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
•
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon
the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is
reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count
of 0 (default value) means the block transfer contains a single frame.
•
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is
reloaded with the DMA global count reload register (DMGCR).
3.2.5.7
DMA Transfers in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
3.2.5.8
DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode
control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and
DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is
the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame is determined
by the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
•
Element index: For all except the last transfer in the frame, the element index determines the amount to
be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as
selected by the SIND/DIND bits.
•
Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as
selected by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.
3.2.5.9
DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA mode control register (DMMCRx). The available modes
are shown in Table 3−6.
October 2002 − Revised October 2004
SPRS199B
31
Functional Overview
Table 3−6. DMA Interrupts
MODE
DINM
INTERRUPT
ABU (non-decrement)
1
0
At full buffer only
ABU (non-decrement)
1
1
At half buffer and full buffer
Multi-Frame
1
0
At block transfer complete (DMCTRx = DMSEFCx[7:0] = 0)
Multi-Frame
1
1
At end of frame and end of block (DMCTRx = 0)
Either
0
X
No interrupt generated
Either
0
X
No interrupt generated
3.2.5.10 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN
bit field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization
event for a channel. The list of possible events and the DSYN values are shown in Table 3−7.
Table 3−7. DMA Synchronization Events
DSYN VALUE
DMA SYNCHRONIZATION EVENT
0000b
No synchronization used
0001b
McBSP0 receive event
0010b
McBSP0 transmit event
0011−0100b
Reserved
0101b
McBSP1 receive event
0110b
McBSP1 transmit event
0111b−0110b
Reserved
1101b
Timer0 interrupt
1110b
External interrupt 3
1111b
Timer1 interrupt
3.2.5.11 DMA Channel Interrupt Selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources
for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt
line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an
interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with a reserved
interrupt source. When the UC5405 is reset, the interrupts from these four DMA channels are deselected. The
INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these
interrupts, as shown in Table 3−8.
Table 3−8. DMA Channel Interrupt Selection
INTSEL Value
IMR/IFR[6]
IMR/IFR[7]
IMR/IFR[10]
IMR/IFR[11]
00b (reset)
Reserved
TINT1
BRINT1
BXINT1
01b
Reserved
TINT1
DMAC2
DMAC3
10b
DMAC0
DMAC1
DMAC2
DMAC3
11b
32
SPRS199B
Reserved
October 2002 − Revised October 2004
Functional Overview
3.3
Memory-Mapped Registers
The UC5405 has a set of memory-mapped registers associated with the CPU, on-chip peripherals, the
McBSPs, and the DMA.
3.3.1 CPU Memory-Mapped Registers
The UC5405 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses
0h to 1Fh. Table 3−9 gives a list of the CPU memory-mapped registers (MMRs) available on UC5405.
Table 3−9. CPU Memory-Mapped Registers
ADDRESS
NAME
DESCRIPTION
DEC
HEX
IMR
0
0
Interrupt mask register
IFR
1
1
Interrupt flag register
Reserved for testing
–
2−5
2−5
ST0
6
6
Status register 0
ST1
7
7
Status register 1
AL
8
8
Accumulator A low word (15−0)
AH
9
9
Accumulator A high word (31−16)
AG
10
A
Accumulator A guard bits (39−32)
BL
11
B
Accumulator B low word (15−0)
BH
12
C
Accumulator B high word (31−16)
BG
13
D
Accumulator B guard bits (39−32)
TREG
14
E
Temporary register
TRN
15
F
Transition register
AR0
16
10
Auxiliary register 0
AR1
17
11
Auxiliary register 1
AR2
18
12
Auxiliary register 2
AR3
19
13
Auxiliary register 3
AR4
20
14
Auxiliary register 4
AR5
21
15
Auxiliary register 5
AR6
22
16
Auxiliary register 6
AR7
23
17
Auxiliary register 7
SP
24
18
Stack pointer register
BK
25
19
Circular buffer size register
BRC
26
1A
Block-repeat counter
RSA
27
1B
Block-repeat start address
REA
28
1C
Block-repeat end address
PMST
29
1D
Processor mode status (PMST) register
XPC
30
1E
Extended program page register
–
31
1F
Reserved
October 2002 − Revised October 2004
SPRS199B
33
Functional Overview
3.3.2 Peripheral Memory-Mapped Registers
The UC5405 has a set of memory-mapped registers associated with peripherals as shown in Table 3−10.
Table 3−10. Peripheral Memory-Mapped Registers
NAME
ADDRESS
DESCRIPTION
TYPE
DRR20
20h
McBSP0 data receive register 2
McBSP #0
DRR10
21h
McBSP0 data receive register 1
McBSP #0
DXR20
22h
McBSP0 data transmit register 2
McBSP #0
DXR10
23h
McBSP0 data transmit register 1
McBSP #0
TIM
24h
Timer0 register
Timer0
PRD
25h
Timer0 period counter
Timer0
TCR
26h
Timer0 control register
Timer0
–
27h
Reserved
SWWSR
28h
Software wait-state register
External Bus
BSCR
29h
Bank-switching control register
External Bus
–
2Ah
Reserved
SWCR
2Bh
Software wait-state control register
HPIC
2Ch
HPI control register
–
2Dh−2Fh
External Bus
HPI
Reserved
TIM1
30h
Timer1 register
Timer1
PRD1
31h
Timer1 period counter
Timer1
32h
Timer1 control register
Timer1
TCR1
–
33h−37h
SPSA0
SPSD0
–
38h
39h
3Ah−3Bh
GPIOCR
GPIOSR
–
Reserved
McBSP0 subbank address register†
McBSP0 subbank data
register†
McBSP #0
McBSP #0
Reserved
3Ch
General-purpose I/O pins control register
GPIO
3Dh
General-purpose I/O pins status register
GPIO
3Eh−3Fh
Reserved
DRR21
40h
McBSP1 data receive register 2
McBSP #1
DRR11
41h
McBSP1 data receive register 1
McBSP #1
DXR21
42h
McBSP1 data transmit register 2
McBSP #1
43h
McBSP1 data transmit register 1
McBSP #1
DXR11
–
44h−47h
Reserved
SPSA1
48h
McBSP1 subbank address register†
McBSP #1
SPSD1
49h
McBSP1 subbank data register†
McBSP #1
–
4Ah−53h
Reserved
DMPREC
54h
DMA channel priority and enable control register
DMA
DMSA
55h
DMA subbank address register‡
DMA
autoincrement‡
DMSDI
56h
DMA subbank data register with
DMSDN
57h
DMA subbank data register‡
DMA
CLKMD
58h
Clock mode register
PLL
–
59h−5Fh
DMA
Reserved
†
See Table 3−11 for a detailed description of the McBSP control registers and their subaddresses.
‡ See Table 3−12 for a detailed description of the DMA subbank addressed registers.
34
SPRS199B
October 2002 − Revised October 2004
Functional Overview
3.3.3 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The serial port subbank address (SPSA) register is used as a pointer to select a particular register
within the subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected
register. Table 3−11 shows the McBSP control registers and their corresponding subaddresses.
Table 3−11. McBSP Control Registers and Subaddresses
McBSP0
NAME
ADDRESS
NAME
McBSP1
ADDRESS
SUBADDRESS
DESCRIPTION
SPCR10
39h
SPCR11
49h
00h
Serial port control register 1
SPCR20
39h
SPCR21
49h
01h
Serial port control register 2
RCR10
39h
RCR11
49h
02h
Receive control register 1
RCR20
39h
RCR21
49h
03h
Receive control register 2
XCR10
39h
XCR11
49h
04h
Transmit control register 1
XCR20
39h
XCR21
49h
05h
Transmit control register 2
SRGR10
39h
SRGR11
49h
06h
Sample rate generator register 1
SRGR20
39h
SRGR21
49h
07h
Sample rate generator register 2
MCR10
39h
MCR11
49h
08h
Multichannel register 1
MCR20
39h
MCR21
49h
09h
Multichannel register 2
RCERA0
39h
RCERA1
49h
0Ah
Receive channel enable register partition A
RCERB0
39h
RCERB1
49h
0Bh
Receive channel enable register partition B
XCERA0
39h
XCERA1
49h
0Ch
Transmit channel enable register partition A
XCERB0
39h
XCERB1
49h
0Dh
Transmit channel enable register partition B
PCR0
39h
PCR1
49h
0Eh
Pin control register
3.3.4 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular
register within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register
with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access affects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 3−12 shows the DMA
controller subbank addressed registers and their corresponding subaddresses.
October 2002 − Revised October 2004
SPRS199B
35
Functional Overview
Table 3−12. DMA Subbank Addressed Registers
ADDRESS†
SUBADDRESS
DMSRC0
56h/57h
00h
DMA channel 0 source address register
DMDST0
56h/57h
01h
DMA channel 0 destination address register
DMCTR0
56h/57h
02h
DMA channel 0 element count register
DMSFC0
56h/57h
03h
DMA channel 0 sync select and frame count register
DMMCR0
56h/57h
04h
DMA channel 0 transfer mode control register
DMSRC1
56h/57h
05h
DMA channel 1 source address register
DMDST1
56h/57h
06h
DMA channel 1 destination address register
DMCTR1
56h/57h
07h
DMA channel 1 element count register
DMSFC1
56h/57h
08h
DMA channel 1 sync select and frame count register
DMMCR1
56h/57h
09h
DMA channel 1 transfer mode control register
DMSRC2
56h/57h
0Ah
DMA channel 2 source address register
DMDST2
56h/57h
0Bh
DMA channel 2 destination address register
DMCTR2
56h/57h
0Ch
DMA channel 2 element count register
DMSFC2
56h/57h
0Dh
DMA channel 2 sync select and frame count register
DMMCR2
56h/57h
0Eh
DMA channel 2 transfer mode control register
DMSRC3
56h/57h
0Fh
DMA channel 3 source address register
DMDST3
56h/57h
10h
DMA channel 3 destination address register
DMCTR3
56h/57h
11h
DMA channel 3 element count register
DMSFC3
56h/57h
12h
DMA channel 3 sync select and frame count register
DMMCR3
56h/57h
13h
DMA channel 3 transfer mode control register
DMSRC4
56h/57h
14h
DMA channel 4 source address register
DMDST4
56h/57h
15h
DMA channel 4 destination address register
DMCTR4
56h/57h
16h
DMA channel 4 element count register
DMSFC4
56h/57h
17h
DMA channel 4 sync select and frame count register
DMMCR4
56h/57h
18h
DMA channel 4 transfer mode control register
DMSRC5
56h/57h
19h
DMA channel 5 source address register
DMDST5
56h/57h
1Ah
DMA channel 5 destination address register
DMCTR5
56h/57h
1Bh
DMA channel 5 element count register
DMSFC5
56h/57h
1Ch
DMA channel 5 sync select and frame count register
DMMCR5
56h/57h
1Dh
DMA channel 5 transfer mode control register
DMSRCP
56h/57h
1Eh
DMA source program page address (common channel)
DMDSTP
56h/57h
1Fh
DMA destination program page address (common channel)
DMIDX0
56h/57h
20h
DMA element index address register 0
DMIDX1
56h/57h
21h
DMA element index address register 1
DMFRI0
56h/57h
22h
DMA frame index register 0
DMFRI1
56h/57h
23h
DMA frame index register 1
DMGSA
56h/57h
24h
DMA global source address reload register
DMGDA
56h/57h
25h
DMA global destination address reload register
DMGCR
56h/57h
26h
DMA global count reload register
DMGFR
56h/57h
27h
DMA global frame count reload register
NAME
†
DESCRIPTION
Address 56h is used to access DMA subbank data registers with autoincrement (DMSDI) while address 57h is used to access DMA subbank
data register without autoincrement (DMSDN).
36
SPRS199B
October 2002 − Revised October 2004
Functional Overview
3.4
Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−13.
Table 3−13. Interrupt Locations and Priorities
NAME
LOCATION
DECIMAL
HEX
RS, SINTR
0
00
NMI, SINT16
4
SINT17
8
SINT18
PRIORITY
FUNCTION
1
Reset (hardware and software reset)
04
2
Nonmaskable interrupt
08
—
Software interrupt #17
12
0C
—
Software interrupt #18
SINT19
16
10
—
Software interrupt #19
SINT20
20
14
—
Software interrupt #20
SINT21
24
18
—
Software interrupt #21
SINT22
28
1C
—
Software interrupt #22
SINT23
32
20
—
Software interrupt #23
SINT24
36
24
—
Software interrupt #24
SINT25
40
28
—
Software interrupt #25
SINT26
44
2C
—
Software interrupt #26
SINT27
48
30
—
Software interrupt #27
SINT28
52
34
—
Software interrupt #28
SINT29
56
38
—
Software interrupt #29
SINT30
60
3C
—
Software interrupt #30
INT0, SINT0
64
40
3
External user interrupt #0
INT1, SINT1
68
44
4
External user interrupt #1
INT2, SINT2
72
48
5
External user interrupt #2
TINT0, SINT3
76
4C
6
Timer0 interrupt
BRINT0, SINT4
80
50
7
McBSP #0 receive interrupt
BXINT0, SINT5
84
54
8
McBSP #0 transmit interrupt
Reserved(DMAC0), SINT6
88
58
9
Reserved (default) or DMA channel 0
interrupt. The selection is made in the
DMPREC register.
TINT1(DMAC1), SINT7
92
5C
10
Timer1 interrupt (default) or DMA channel 1
interrupt. The selection is made in the
DMPREC register.
INT3, SINT8
96
60
11
External user interrupt #3
HPINT, SINT9
100
64
12
HPI interrupt
BRINT1(DMAC2), SINT10
104
68
13
McBSP #1 receive interrupt (default) or DMA
channel 2 interrupt. The selection is made in
the DMPREC register.
BXINT1(DMAC3), SINT11
108
6C
14
McBSP #1 transmit interrupt (default) or DMA
channel 3 interrupt. The selection is made in
the DMPREC register.
DMAC4,SINT12
112
70
15
DMA channel 4 interrupt
DMAC5,SINT13
116
74
16
DMA channel 5 interrupt
120−127
78−7F
—
Reserved
Reserved
October 2002 − Revised October 2004
SPRS199B
37
Functional Overview
3.4.1 IFR and IMR Registers
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in
Figure 3−10.
15
14
Reserved
13
12
11
10
9
8
DMAC5
DMAC4
BXINT1/
DMAC3
BRINT1/
DMAC2
HPINT
INT3
7
6
5
4
3
2
1
0
TINT1/
DMAC1
Reserved/
DMAC0
BXINT0
BRINT0
TINT0
INT2
INT1
INT0
Figure 3−10. IFR and IMR Registers
Table 3−14. IFR and IMR Register Bit Fields
BIT
NUMBER
38
FUNCTION
NAME
15−14
−
13
DMAC5
Reserved for future expansion
DMA channel 5 interrupt flag/mask bit
12
DMAC4
DMA channel 4 interrupt flag/mask bit
11
BXINT1/DMAC3
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
10
BRINT1/DMAC2
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
9
HPINT
8
INT3
7
TINT1/DMAC1
This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
6
Reserved or DMAC0
This bit can be configured either as reserved or as the DMA channel 0 interrupt flag/mask bit. The
selection is made in the DMPREC register.
Host−to-C54x interrupt flag/mask
External interrupt 3 flag/mask
5
BXINT0
McBSP0 transmit interrupt flag/mask bit
4
BRINT0
McBSP0 receive interrupt flag/mask bit
3
TINT0
2
INT2
External interrupt 2 flag/mask bit
1
INT1
External interrupt 1 flag/mask bit
0
INT0
External interrupt 0 flag/mask bit
SPRS199B
Timer 0 interrupt flag/mask bit
October 2002 − Revised October 2004
Device Support
4
Device Support
4.1
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with against the following
disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, GQW or ZQW) and temperature range (for example, “Blank” is the default temperature
range). Figure 4−1 provides a legend for reading the complete device name for the TMS320UC5405 device.
For device part numbers and further ordering information for TMS320UC5405 in the GQW and ZQW package
types, see the TI website (http://www.ti.com) or contact your TI sales representative.
TMS320 is a trademark of Texas Instruments.
October 2002 − Revised October 2004
SPRS199B
39
Device and Development-Support Tool Nomenclature
TMS
320 UC 5405
PREFIX
TMX = Experimental device
TMP = Prototype device
TMS = Qualified device
GQW
(
)
(R)
PACKAGING
R = Tape and Reel
TEMPERATURE RANGE
Blank = −40°C TO 100°C (default)
DEVICE FAMILY
320 = TMS320 Family
TECHNOLOGY
C = CMOS
E = CMOS EPROM
F = CMOS Flash EEPROM
LC = Low-Voltage CMOS (3.3 V)
VC = Low Voltage CMOS [3 V (2.5 V Core)]
UC= Ultra-Low Voltage CMOS [1.8-V to 3.6-V I/O (1.8-v Core)]
†
‡
PACKAGE TYPE†
GQW = 143-pin plastic PBGA
ZQW = 143-pin plastic BGA with Pb-free soldered balls
DEVICE‡
C54x DSP:
5405
BGA = Ball Grid Array
For actual part numbers (P/Ns) and ordering information, see the TI website (www.ti.com).
Figure 4−1. TMS320UC5405 DSP Device Nomenclature
40
SPRS199B
October 2002 − Revised October 2004
Documentation Support
5
Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000 platform of DSPs:
•
•
•
•
•
TMS320C54x DSP Functional Overview (literature number SPRU307)
Device-specific data sheets
Complete user’s guides
Development support tools
Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set consists of:
•
•
•
•
•
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x DSP products currently available and the hardware
and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320 and C5000 are trademarks of Texas Instruments.
October 2002 − Revised October 2004
SPRS199B
41
Electrical Specifications
6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320UC5405 DSP.
6.1
Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 6.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to VSS. Figure 6−1 provides the test load circuit
values for a 1.8-V device.
Supply voltage I/O range, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.0 V
Supply voltage core range, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.0 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
6.2
Recommended Operating Conditions
MIN
DVDD
Device supply voltage, I/O
1.71
CVDD
Device supply voltage, core
1.71
VSS
Supply voltage, GND
DVDD = 1.71 V to 1.89 V
DVDD = 1.90 V to 2.99 V
VIH
High-level input
voltage
DVDD = 3.0 V to 3.6 V
VIL
Low-level input
voltage
DVDD = 1.90 V to 3.6 V
1.8
MAX
UNIT
3.6
V
1.98
V
0
V
X2/CLKIN
1.35
CVDD + 0.3
All other inputs
1.35
DVDD + 0.3
X2/CLKIN
1.35
CVDD + 0.3
All other inputs
1.7
DVDD + 0.3
X2/CLKIN
1.35
CVDD + 0.3
RS, INTn, NMI, BIO,
BCLKR0, BCLKR1, BCLKX0,
BCLKX1, HCS, HDS1,
HDS2, TDI, TMS, CLKMDn
2.2
DVDD + 0.3
TCK, TRST
2.5
DVDD + 0.3
2
DVDD + 0.3
X2/CLKIN
−0.3
0.6
All other inputs
−0.3
0.6
X2/CLKIN
−0.3
0.6
RS, INTn, NMI, BIO,
BCLKR0, BCLKR1, BCLKX0,
BCLKX1, HCS, HDS1,
HDS2, TCK, CLKMDn
−0.3
0.6
All other inputs
−0.3
0.8
All other inputs
DVDD = 1.71 V to 1.89 V
NOM
V
V
IOH
High-level output current
−300
µA
IOL
Low-level output current
1.5
mA
TC
Operating case temperature
100
°C
42
SPRS199B
−40
October 2002 − Revised October 2004
Electrical Specifications
6.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level
voltage
IIZ
output
Input current for
outputs in high
impedance
TEST CONDITIONS
MIN
IOH = MAX
Input current
0.4
All other outputs
0.35
All outputs
0.4
IOL = MAX
DVDD = 1.9 to 3.6 V
IOL = MAX
D[15:0], HD[7:0]
Bus holders enabled, DVDD = MAX,
VI = VSS to DVDD
All other inputs
DVDD = MAX, VO = VSS to DVDD
IDDP
−175
175
−5
5
−40
40
TRST
With internal pulldown
−5
300
HPIENA
With internal pulldown
−5
300
TMS, TCK, TDI, HPI}
With internal pullups,
HPIENA = 0
−300
5
−5
5
(VI = VSS
to DVDD)
Supply current, core CPU
CVDD = 1.8 V, fclock = 80 MHz,w
TC = 25°C
Supply current, pins
fclock = 80 MHz,w
TC = 25°C
35
DVDD = 1.71 to
1.89 V
12
DVDD = 1.9 to
3.6 V
27
IDLE2
PLL × 1 mode,
IDLE3
Divide-by-two mode, CLKIN stopped
UNIT
V
CLKOUT
DVDD = 1.71 to 1.89 V
All other input-only
pins
IDDC
MAX
DVDD − 0.3
X2/CLKIN
II
TYP†
V
µA
µA
A
mA
mA
1.6
mA
20
µA
Input capacitance
5
pF
Output capacitance
5
pF
IDD
Supply current,
standby
Ci
Co
80 MHz input
†
All values are typical unless otherwise specified.
HPI input signals except for HPIENA.
§ Clock mode: PLL × 1 with external source
‡
IOL
50 Ω
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where:
IOL
IOH
VLoad
CT
=
=
=
=
1.5 mA (all outputs)
300 µA (all outputs)
0.855 V
40 pF typical load circuit capacitance
Figure 6−1. 1.8-V Test Load Circuit
October 2002 − Revised October 2004
SPRS199B
43
Electrical Specifications
6.4
Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
44
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
dis
disable time
Z
High impedance
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
X
Unknown, changing, or don’t care level
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.5
Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
6.5.1 Internal Oscillator With External Crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT
is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD
register. The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30 Ω and power dissipation of 1 mW. The circuit shown in Figure 6−2 represents
fundamental-mode operation.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 6−2.
The load capacitors, C1 and C2, should be chosen such that the equation below is satisfied. CL in the equation
is the load specified for the crystal.
CL +
C 1C 2
(C 1 ) C 2)
MIN
fclock
Input clock frequency
10
X1
MAX
UNIT
20
MHz
X2/CLKIN
Crystal
C1
C2
Figure 6−2. Internal Oscillator With External Crystal
October 2002 − Revised October 2004
SPRS199B
45
Electrical Specifications
6.5.2 Divide-By-Two Clock Option (PLL disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate
the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 6−1.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
Table 6−1 and Table 6−2 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 6−3).
Table 6−1. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
†
MIN
MAX
6.25
†
UNIT
ns
tc(CI)
Cycle time, X2/CLKIN
tf(CI)
Fall time, X2/CLKIN
8
ns
tr(CI)
Rise time, X2/CLKIN
8
ns
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
Table 6−2. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
PARAMETER
MIN
TYP
12.5‡
2tc(CI)
7
12
MAX
UNIT
†
ns
20
ns
tc(CO)
Cycle time, CLKOUT
td(CIH-CO)
Delay time, X2/CLKIN high to CLKOUT high/low
tf(CO)
Fall time, CLKOUT
tr(CO)
Rise time, CLKOUT
tw(COL)
Pulse duration, CLKOUT low
H−2
H+2
ns
tw(COH)
Pulse duration, CLKOUT high
H−2
H+2
ns
4
ns
4
ns
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
†
tr(CI)
tf(CI)
tc(CI)
X2/CLKIN
tc(CO)
td(CIH-CO)
tw(COH)
tf(CO)
tr(CO)
tw(COL)
CLKOUT
Figure 6−3. External Divide-by-Two Clock Timing
46
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.5.3 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in the
clock generator section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 6−3.
NOTE: If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.
Table 6−3 and Table 6−4 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 6−4).
Table 6−3. Multiply-By-N Clock Option Timing Requirements†
tc(CI)
†
Cycle time, X2/CLKIN
MIN
MAX
Integer PLL multiplier N (N = 1−15)
12.5N
400N
PLL multiplier N = x.5
12.5N
200N
PLL multiplier N = x.25, x.75
12.5N
100N
UNIT
ns
tf(CI)
Fall time, X2/CLKIN
8
ns
tr(CI)
Rise time, X2/CLKIN
8
ns
N = Multiplication factor
Table 6−4. Multiply-By-N Clock Option Switching Characteristics
PARAMETER
†
MIN
TYP
12.5
tc(CI)/N†
7
10
MAX
UNIT
tc(CO)
Cycle time, CLKOUT
td(CI-CO)
Delay time, X2/CLKIN high/low to CLKOUT high/low
ns
tf(CO)
Fall time, CLKOUT
4
tr(CO)
Rise time, CLKOUT
4
tw(COL)
Pulse duration, CLKOUT low
H−2
H+2
ns
tw(COH)
Pulse duration, CLKOUT high
H−2
H+2
ns
tp
Transitory phase, PLL lock up time
30
ms
20
ns
ns
ns
N = Multiplication factor
tf(CI)
tr(CI)
tc(CI)
X2/CLKIN
td(CI-CO)
tc(CO)
tp
tw(COH)
tf(CO)
tw(COL)
tr(CO)
Unstable
CLKOUT
Figure 6−4. External Multiply-by-One Clock Timing
October 2002 − Revised October 2004
SPRS199B
47
Electrical Specifications
6.6
Memory and Parallel I/O Interface Timing
6.6.1 Memory Read
Table 6−5 and Table 6−6 assume testing over recommended operating conditions with MSTRB = 0 and
H = 0.5tc(CO) (see Figure 6−5).
Table 6−5. Memory Read Timing Requirements†
MIN
†
MAX
UNIT
ta(A)M
Access time, read data access from address valid
2H−14
ns
ta(MSTRBL)
Access time, read data access from MSTRB low
2H−14
ns
tsu(D)R
Setup time, read data before CLKOUT low
7
ns
th(D)R
Hold time, read data after CLKOUT low
0
ns
th(A-D)R
Hold time, read data after address invalid
0
ns
th(D)MSTRBH
Hold time, read data after MSTRB high
0
ns
Address, PS, and DS timings are all included in timings referenced as address.
Table 6−6. Memory Read Switching Characteristics†
PARAMETER
valid‡
MIN
MAX
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address
0
8
ns
td(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
0
8
ns
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
0
8
ns
0
7
ns
0
5
ns
low‡
th(CLKL-A)R
Hold time, address valid after CLKOUT
th(CLKH-A)R
Hold time, address valid after CLKOUT high§
†
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory read preceded by a memory read
§ In the case of a memory read preceded by a memory write
‡
48
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
CLKOUT
td(CLKL-A)
th(CLKL-A)R
A[5:0]
th(A-D)R
tsu(D)R
ta(A)M
th(D)R
D[15:0]
th(D)MSTRBH
td(CLKL-MSL)
td(CLKL-MSH)
ta(MSTRBL)
MSTRB
R/W
PS, DS
Figure 6−5. Memory Read
October 2002 − Revised October 2004
SPRS199B
49
Electrical Specifications
6.6.2 Memory Write
Table 6−7 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5tc(CO) (see
Figure 6−6).
Table 6−7. Memory Write Switching Characteristics†
td(CLKH-A)
PARAMETER
MIN
MAX
Delay time, CLKOUT high to address valid‡
0
5
ns
0
8
ns
0
8
ns
valid§
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address
td(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
td(CLKL-D)W
Delay time, CLKOUT low to data valid
0
17
ns
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
0
8
ns
td(CLKH-RWL)
Delay time, CLKOUT high to R/W low
−1
5
ns
td(CLKH-RWH)
Delay time, CLKOUT high to R/W high
−2
5
ns
td(RWL-MSTRBL)
Delay time, R/W low to MSTRB low
H−4
H+2
ns
5
ns
H+14
ns
high‡
th(A)W
Hold time, address valid after CLKOUT
th(D)MSH
Hold time, write data valid after MSTRB high
0
tw(SL)MS
Pulse duration, MSTRB low
2H−5
tsu(A)W
Setup time, address valid before MSTRB low
2H−4
tsu(D)MSH
Setup time, write data valid before MSTRB high
ten(D−RWL)
Enable time, data bus driven from R/W low
tdis(RWH−D)
Disable time, data bus high impedance from R/W high
H−3
2H−14
ns
ns
2H+5
H−5
ns
ns
0
ns
†
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory write preceded by a memory write
§ In the case of a memory write preceded by an I/O cycle
‡
50
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
CLKOUT
td(CLKH-A)
td(CLKL-A)
th(A)W
A[5:0]
td(CLKL-D)W
th(D)MSH
tsu(D)MSH
D[15:0]
td(CLKL-MSL)
td(CLKL-MSH)
tsu(A)W
tdis(RWH-D)
MSTRB
td(CLKH-RWL)
ten(D-RWL)
td(CLKH-RWH)
tw(SL)MS
td(RWL-MSTRBL)
R/W
PS, DS
Figure 6−6. Memory Write
October 2002 − Revised October 2004
SPRS199B
51
Electrical Specifications
6.6.3 I/O Read
Table 6−8 and Table 6−9 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5tc(CO) (see Figure 6−7).
Table 6−8. I/O Read Timing Requirements
MIN
†
MAX
UNIT
ta(A)IO
Access time, read data access from address valid†
ta(ISTRBL)IO
Access time, read data access from IOSTRB low
tsu(D)IOR
Setup time, read data before CLKOUT high
9
ns
th(D)IOR
Hold time, read data after CLKOUT high
0
ns
th(ISTRBH-D)R
Hold time, read data after IOSTRB high
0
ns
3H−17
ns
3H−17
ns
Address and IS timings are included in timings referenced as address.
Table 6−9. I/O Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address
0
8
ns
td(CLKH-ISTRBL)
Delay time, CLKOUT high to IOSTRB low
−2
5
ns
td(CLKH-ISTRBH)
Delay time, CLKOUT high to IOSTRB high
−2
5
ns
0
8
ns
th(A)IOR
†
valid†
Hold time, address after CLKOUT
low†
Address and IS timings are included in timings referenced as address.
CLKOUT
th(A)IOR
td(CLKL-A)
A[5:0]
th(D)IOR
tsu(D)IOR
ta(A)IO
D[15:0]
th(ISTRBH-D)R
td(CLKH-ISTRBH)
ta(ISTRBL)IO
td(CLKH-ISTRBL)
IOSTRB
R/W
IS
Figure 6−7. Parallel I/O Port Read
52
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.6.4 I/O Write
Table 6−10 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5tc(CO) (see
Figure 6−8).
Table 6−10. I/O Write Switching Characteristics
PARAMETER
†
td(CLKL-A)
Delay time, CLKOUT low to address valid†
td(CLKH-ISTRBL)
Delay time, CLKOUT high to IOSTRB low
td(CLKH-D)IOW
Delay time, CLKOUT high to write data valid
td(CLKH-ISTRBH)
Delay time, CLKOUT high to IOSTRB high
td(CLKL-RWL)
Delay time, CLKOUT low to R/W low
td(CLKL-RWH)
Delay time, CLKOUT low to R/W high
low†
th(A)IOW
Hold time, address valid after CLKOUT
th(D)IOW
Hold time, write data after IOSTRB high
tsu(D)IOSTRBH
Setup time, write data before IOSTRB high
tsu(A)IOSTRBL
Setup time, address valid before IOSTRB low†
MIN
MAX
0
8
UNIT
ns
−2
5
ns
H−5
H+14
ns
−2
5
ns
0
8
ns
0
8
ns
0
8
ns
H−3
H+11
ns
H−11
H+1
ns
H−2
H+2
ns
Address and IS timings are included in timings referenced as address.
CLKOUT
tsu(A)IOSTRBL
th(A)IOW
td(CLKL-A)
A[5:0]
td(CLKH-D)IOW
th(D)IOW
D[15:0]
td(CLKH-ISTRBL)
td(CLKH-ISTRBH)
tsu(D)IOSTRBH
IOSTRB
td(CLKL-RWL)
td(CLKL-RWH)
R/W
IS
Figure 6−8. Parallel I/O Port Write
October 2002 − Revised October 2004
SPRS199B
53
Electrical Specifications
6.7
Ready Timing for Externally Generated Wait States
Table 6−11 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6−9
through Figure 6−12).
Table 6−11. Ready Timing Requirements for Externally Generated Wait States†
MIN
tsu(RDY)
Setup time, READY before CLKOUT low
th(RDY)
Hold time, READY after CLKOUT low
tv(RDY)MSTRB
Valid time, READY after MSTRB low‡
th(RDY)MSTRB
Hold time, READY after MSTRB
low‡
tv(RDY)IOSTRB
Valid time, READY after IOSTRB low‡
th(RDY)IOSTRB
Hold time, READY after IOSTRB low‡
MAX
7
ns
−2
ns
4H−11
4H−4
ns
ns
5H−11
5H−3
UNIT
ns
ns
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
CLKOUT
A[5:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
Wait State
Generated
by READY
Wait States
Generated Internally
Figure 6−9. Memory Read With Externally Generated Wait States
54
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
CLKOUT
A[5:0]
D[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
Wait States
Generated Internally
Wait State Generated
by READY
Figure 6−10. Memory Write With Externally Generated Wait States
CLKOUT
A[5:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
Wait State Generated
by READY
Wait
States
Generated
Internally
Figure 6−11. I/O Read With Externally Generated Wait States
October 2002 − Revised October 2004
SPRS199B
55
Electrical Specifications
CLKOUT
A[5:0]
D[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
Wait State Generated
by READY
Wait States
Generated
Internally
Figure 6−12. I/O Write With Externally Generated Wait States
56
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.8
HOLD and HOLDA Timings
Table 6−12 and Table 6−13 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 6−13).
Table 6−12. HOLD and HOLDA Timing Requirements
MIN
tw(HOLD)
Pulse duration, HOLD low
tsu(HOLD)
Setup time, HOLD low/high before CLKOUT low
MAX
UNIT
4H+7
ns
7
ns
Table 6−13. HOLD and HOLDA Switching Characteristics
PARAMETER
MIN
MAX
UNIT
tdis(CLKL-A)
Disable time, address, PS, DS, IS high impedance from CLKOUT low
3
ns
tdis(CLKL-RW)
Disable time, R/W high impedance from CLKOUT low
3
ns
tdis(CLKL-S)
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
3
ns
ten(CLKL-A)
Enable time, address, PS, DS, IS from CLKOUT low
2H+7
ns
ten(CLKL-RW)
Enable time, R/W enabled from CLKOUT low
2H+7
ns
ten(CLKL-S)
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
2H+7
ns
tv(HOLDA)
tw(HOLDA)
Valid time, HOLDA low after CLKOUT low
0
8
ns
Valid time, HOLDA high after CLKOUT low
0
8
ns
Pulse duration, HOLDA low duration
2H
ns
CLKOUT
tsu(HOLD)
tsu(HOLD)
tw(HOLD)
HOLD
tv(HOLDA)
HOLDA
tv(HOLDA)
tw(HOLDA)
tdis(CLKL-A)
ten(CLKL-A)
A[5:0]
PS, DS, IS
D[15:0]
tdis(CLKL-RW)
ten(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-S)
tdis(CLKL-S)
ten(CLKL-S)
R/W
MSTRB
IOSTRB
Figure 6−13. HOLD and HOLDA Timings (HM = 1)
October 2002 − Revised October 2004
SPRS199B
57
Electrical Specifications
6.9
Reset, BIO, Interrupt, and MP/MC Timings
Table 6−14 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6−14,
Figure 6−15, and Figure 6−16).
Table 6−14. Reset, BIO, Interrupt, and MP/MC Timing Requirements
MIN
MAX
UNIT
th(RS)
Hold time, RS after CLKOUT low
0
ns
th(BIO)
Hold time, BIO after CLKOUT low
−2
ns
−3
ns
0
ns
low†
th(INT)
Hold time, INTn, NMI, after CLKOUT
th(MPMC)
Hold time, MP/MC after CLKOUT low
tw(RSL)
Pulse duration, RS low‡§
4H+5
ns
tw(BIO)S
Pulse duration, BIO low, synchronous
2H+4
ns
tw(BIO)A
Pulse duration, BIO low, asynchronous
4H
ns
tw(INTH)S
Pulse duration, INTn, NMI high (synchronous)
2H−1
ns
tw(INTH)A
Pulse duration, INTn, NMI high (asynchronous)
4H
ns
tw(INTL)S
Pulse duration, INTn, NMI low (synchronous)
2H+1
ns
tw(INTL)A
Pulse duration, INTn, NMI low (asynchronous)
4H
ns
tw(INTL)WKP
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
8
ns
tsu(RS)
Setup time, RS before X2/CLKIN low¶
5
ns
tsu(BIO)
Setup time, BIO before CLKOUT low
7
12
ns
tsu(INT)
Setup time, INTn, NMI, RS before CLKOUT low
8
12
ns
tsu(MPMC)
Setup time, MP/MC before CLKOUT low
10
ns
†
The external interrupts (INT0−INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure synchronization
and lock-in of the PLL.
§ Note that RS may cause a change in clock frequency, therefore changing the value of H.
¶ Divide-by-two mode
X2/CLKIN
tsu(RS)
tw(RSL)
RS, INTn, NMI
tsu(INT)
th(RS)
CLKOUT
tsu(BIO)
th(BIO)
BIO
tw(BIO)S
Figure 6−14. Reset and BIO Timings
58
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
CLKOUT
tsu(INT)
tsu(INT)
th(INT)
INTn, NMI
tw(INTH)A
tw(INTL)A
Figure 6−15. Interrupt Timing
CLKOUT
RS
th(MPMC)
tsu(MPMC)
MP/MC
Figure 6−16. MP/MC Timing
October 2002 − Revised October 2004
SPRS199B
59
Electrical Specifications
6.10 Interrupt Acknowledge (IACK) Timings
Table 6−15 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6−17).
Table 6−15. Interrupt Acknowledge (IACK) Switching Characteristics
MIN
MAX
td(CLKL-IACKL)
Delay time, CLKOUT low to IACK low
PARAMETER
0
9
UNIT
ns
td(CLKL-IACKH)
Delay time , CLKOUT low to IACK high
1
6
ns
td(A)IACK
Delay time, address valid to IACK low
2
ns
th(A)IACK
Hold time, IACK high after address invalid
tw(IACKL)
Pulse duration, IACK low
−2
ns
2H−1
ns
CLKOUT
A[5:0]
td(CLKL-IACKH)
td(CLKL-IACKL)
th(A)IACK
td(A)IACK
tw(IACKL)
IACK
MSTRB
Figure 6−17. IACK Timings
60
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.11 External Flag (XF) and TOUT Timings
Table 6−16 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6−18 and
Figure 6−19).
Table 6−16. External Flag (XF) and TOUT Switching Characteristics
PARAMETER
td(XF)
MIN
MAX
Delay time, CLKOUT low to XF high
−1
8
Delay time, CLKOUT low to XF low
−1
8
UNIT
ns
td(TOUTH)
Delay time, CLKOUT low to TOUT high
0
11
ns
td(TOUTL)
Delay time, CLKOUT low to TOUT low
0
9
ns
tw(TOUT)
Pulse duration, TOUT
2H−1
ns
CLKOUT
td(XF)
XF
Figure 6−18. XF Timing
CLKOUT
td(TOUTH)
td(TOUTL)
TOUT
tw(TOUT)
Figure 6−19. TOUT Timing
October 2002 − Revised October 2004
SPRS199B
61
Electrical Specifications
6.12 Multichannel Buffered Serial Port (McBSP) Timing
6.12.1
McBSP Transmit and Receive Timings
Table 6−17 and Table 6−18 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 6−20 and Figure 6−21).
Table 6−17. McBSP Transmit and Receive Timing Requirements†
MIN
†
MAX
UNIT
tc(BCKRX)
Cycle time, BCLKR/X
BCLKR/X ext
4H
ns
tw(BCKRX)
Pulse duration, BCLKR/X high or BCLKR/X low
BCLKR/X ext
2H−1
ns
BCLKR int
20
BCLKR ext
0
BCLKR int
−3
BCLKR ext
4
BCLKR int
17
BCLKR ext
0
BCLKR int
0
BCLKR ext
8
BCLKX int
20
BCLKX ext
0
BCLKX int
−4
BCLKX ext
5
tsu(BFRH-BCKRL)
Setup time, external BFSR high before BCLKR low
ns
th(BCKRL-BFRH)
Hold time, external BFSR high after BCLKR low
tsu(BDRV-BCKRL)
Setup time, BDR valid before BCLKR low
th(BCKRL-BDRV)
Hold time, BDR valid after BCLKR low
tsu(BFXH-BCKXL)
Setup time, external BFSX high before BCLKX low
th(BCKXL-BFXH)
Hold time, external BFSX high after BCLKX low
tr(BCKRX)
Rise time, BCLKR/X
BCLKR/X ext
8
ns
tf(BCKRX)
Fall time, BCLKR/X
BCLKR/X ext
8
ns
ns
ns
ns
ns
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
62
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
Table 6−18. McBSP Transmit and Receive Switching Characteristics†
MIN
PARAMETER
MAX
UNIT
tc(BCKRX)
Cycle time, BCLKR/X
BCLKR/X int
4H
tw(BCKRXH)
Pulse duration, BCLKR/X high
BCLKR/X int
D − 3‡
D + 2‡
ns
BCLKR/X int
3‡
2‡
ns
tw(BCKRXL)
td(BCKRH-BFRV)
Pulse duration, BCLKR/X low
Delay time, BCLKR high to internal BFSR valid
td(BCKXH-BFXV)
Delay time, BCLKX high to internal BFSX valid
tdis(BCKXH-BDXHZ)
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
DXENA = 0§
C−
ns
C+
BCLKR int
−3
6
ns
BCLKR ext
7
13
ns
BCLKX int
0
6
BCLKX ext
5
19
BCLKX int
1
6
BCLKX ext
7
13
BCLKX int
0¶
6
BCLKX ext
5
19
Delay time, BFSX high to BDX valid
BFSX int
1¶
2
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
BFSX ext
7
18
td(BFXH-BDXV)
ns
ns
ns
ns
†
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the TMS320UC5405.
¶ Minimum delay times also represent minimum output hold times.
‡
October 2002 − Revised October 2004
SPRS199B
63
Electrical Specifications
tc(BCKRX)
tw(BCKRXH)
tr(BCKRX)
tw(BCKRXL)
BCLKR
td(BCKRH−BFRV)
tr(BCKRX)
td(BCKRH−BFRV)
BFSR (int)
tsu(BFRH−BCKRL)
th(BCKRL−BFRH)
BFSR (ext)
th(BCKRL−BDRV)
tsu(BDRV−BCKRL)
BDR
(RDATDLY=00b)
Bit (n−1)
(n−2)
tsu(BDRV−BCKRL)
(n−3)
(n−4)
th(BCKRL−BDRV)
BDR
(RDATDLY=01b)
Bit (n−1)
(n−2)
tsu(BDRV−BCKRL)
BDR
(RDATDLY=10b)
(n−3)
th(BCKRL−BDRV)
Bit (n−1)
(n−2)
Figure 6−20. McBSP Receive Timings
tc(BCKRX)
tw(BCKRXH)
tr(BCKRX)
tw(BCKRXL)
tf(BCKRX)
BCLKX
td(BCKXH−BFXV)
td(BCKXH−BFXV)
BFSX (int)
tsu(BFXH−BCKXL)
th(BCKXL−BFXH)
BFSX (ext)
td(BFXH−BDXV)
BDX
(XDATDLY=00b)
Bit 0
Bit (n−1)
td(BCKXH−BDXV)
(n−2)
(n−3)
(n−4)
td(BCKXH−BDXV)
BDX
(XDATDLY=01b)
Bit 0
Bit (n−1)
(n−3)
td(BCKXH−BDXV)
tdis(BCKXH−BDXHZ)
BDX
(XDATDLY=10b)
(n−2)
Bit 0
Bit (n−1)
(n−2)
Figure 6−21. McBSP Transmit Timings
64
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
6.12.2
McBSP General-Purpose I/O Timing
Table 6−19 and Table 6−20 assume testing over recommended operating conditions (see Figure 6−22).
Table 6−19. McBSP General-Purpose I/O Timing Requirements
MIN
†
high†
tsu(BGPIO-COH)
Setup time, BGPIOx input mode before CLKOUT
th(COH-BGPIO)
Hold time, BGPIOx input mode after CLKOUT high†
MAX
UNIT
9
ns
0
ns
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Table 6−20. McBSP General-Purpose I/O Switching Characteristics
PARAMETER
td(COH-BGPIO)
‡
Delay time, CLKOUT high to BGPIOx output mode‡
MIN
MAX
0
5
UNIT
ns
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
tsu(BGPIO-COH)
td(COH-BGPIO)
CLKOUT
th(COH-BGPIO)
BGPIOx Input
mode†
BGPIOx Output
mode‡
†
‡
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 6−22. McBSP General-Purpose I/O Timings
October 2002 − Revised October 2004
SPRS199B
65
Electrical Specifications
6.12.3
McBSP as SPI Master or Slave Timing
Table 6−21 to Table 6−28 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 6−23, Figure 6−24, Figure 6−25, and Figure 6−26).
Table 6−21. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)†
MASTER
MIN
†
tsu(BDRV-BCKXL)
Setup time, BDR valid before BCLKX low
th(BCKXL-BDRV)
Hold time, BDR valid after BCLKX low
tsu(BFXL-BCKXH)
Setup time, BFSX low before BCLKX high
tc(BCKX)
Cycle time, BCLKX
SLAVE
MAX
MIN
MAX
UNIT
16
− 12H
ns
4
12H + 5
ns
10
ns
32H
ns
12H
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 6−22. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)†
MASTER‡
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
th(BCKXL-BFXL)
Hold time, BFSX low after BCLKX low§
T−4
T+5
td(BFXL-BCKXH)
Delay time, BFSX low to BCLKX high¶
C−6
C+4
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
−3
7
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
C−2
C+3
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
2H+ 8
6H + 21
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H −3
8H + 21
ns
ns
ns
6H + 6
10H + 20
ns
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
‡
tsu(BFXL-BCKXH)
LSB
tc(BCKX)
MSB
BCLKX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
BFSX
tdis(BFXH-BDXHZ)
td(BFXL-BDXV)
td(BCKXH-BDXV)
tdis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
tsu(BDRV-BCKXL)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXL-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−23. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
66
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
Table 6−23. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)†
MASTER
MIN
†
tsu(BDRV-BCKXH)
Setup time, BDR valid before BCLKX high
th(BCKXH-BDRV)
Hold time, BDR valid after BCLKX high
tsu(BFXL-BCKXH)
Setup time, BFSX low before BCLKX high
tc(BCKX)
Cycle time, BCLKX
SLAVE
MAX
MIN
MAX
UNIT
16
− 12H
ns
4
12H + 5
ns
10
ns
32H
ns
12H
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 6−24. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)†
MASTER‡
PARAMETER
SLAVE
MIN
MAX
MIN
MAX
UNIT
th(BCKXL-BFXL)
Hold time, BFSX low after BCLKX low§
C −4
C+5
td(BFXL-BCKXH)
Delay time, BFSX low to BCLKX
high¶
T−6
T+4
td(BCKXL-BDXV)
Delay time, BCLKX low to BDX valid
−3
7
6H + 6
10H + 20
ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
0
6
6H +7
10H + 21
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
D−2
D+4
4H −3
8H + 21
ns
ns
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
tsu(BFXL-BCKXH)
LSB
tc(BCKX)
MSB
BCLKX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
BFSX
tdis(BCKXL-BDXHZ)
BDX
td(BCKXL-BDXV)
td(BFXL-BDXV)
Bit 0
Bit(n-1)
tsu(BDRV-BCKXH)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXH-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−24. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
October 2002 − Revised October 2004
SPRS199B
67
Electrical Specifications
Table 6−25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)†
MASTER
MIN
†
tsu(BDRV-BCKXH)
Setup time, BDR valid before BCLKX high
th(BCKXH-BDRV)
Hold time, BDR valid after BCLKX high
tsu(BFXL-BCKXL)
Setup time, BFSX low before BCLKX low
tc(BCKX)
Cycle time, BCLKX
SLAVE
MAX
MIN
MAX
UNIT
16
− 12H
ns
4
12H + 5
ns
10
ns
32H
ns
12H
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 6−26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)†
MASTER‡
PARAMETER
Hold time, BFSX low after BCLKX high§
th(BCKXH-BFXL)
low¶
SLAVE
MIN
MAX
T−4
T+5
D−6
D+4
−3
7
D−2
D+3
MIN
MAX
UNIT
ns
td(BFXL-BCKXL)
Delay time, BFSX low to BCLKX
td(BCKXL-BDXV)
Delay time, BCLKX low to BDX valid
ns
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
2H + 7
6H + 21
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H − 3
8H + 21
ns
6H + 6
10H + 20
ns
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
tsu(BFXL-BCKXL)
LSB
tc(BCKX)
MSB
BCLKX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
BFSX
td(BFXL-BDXV)
tdis(BFXH-BDXHZ)
td(BCKXL-BDXV)
tdis(BCKXH-BDXHZ)
BDX
Bit 0
Bit(n-1)
tsu(BDRV-BCKXH)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXH-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−25. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
68
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
Table 6−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)†
MASTER
MIN
†
tsu(BDRV-BCKXL)
Setup time, BDR valid before BCLKX low
th(BCKXL-BDRV)
Hold time, BDR valid after BCLKX low
tsu(BFXL-BCKXL)
Setup time, BFSX low before BCLKX low
tc(BCKX)
Cycle time, BCLKX
SLAVE
MAX
MIN
UNIT
MAX
16
− 12H
ns
4
12H + 5
ns
10
ns
32H
ns
12H
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 6−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)†
MASTER‡
PARAMETER
Hold time, BFSX low after BCLKX high§
th(BCKXH-BFXL)
SLAVE
MIN
MAX
MIN
UNIT
MAX
D−4
D+5
td(BFXL-BCKXL)
Delay time, BFSX low to BCLKX
low¶
ns
T−6
T+4
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
−3
7
6H + 6
10H + 20
ns
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
0
6
6H +7
10H + 21
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
C−2
C+4
4H − 3
8H + 21
ns
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
LSB
tsu(BFXL-BCKXL)
tc(BCKX)
MSB
BCLKX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
BFSX
tdis(BCKXH-BDXHZ)
BDX
td(BCKXH-BDXV)
td(BFXL-BDXV)
Bit 0
Bit(n-1)
tsu(BDRV-BCKXL)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXL-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−26. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
October 2002 − Revised October 2004
SPRS199B
69
Electrical Specifications
6.13 Host-Port Interface Timing (HPI8)
Table 6−29 and Table 6−30 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 6−27 through Figure 6−30). In the following tables, DS refers to the logical OR of HCS, HDS1, and
HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0, HCNTL1,
and HR/W. GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
NOTE: During all cycles, DS should not be driven high to complete the cycle until HRDY is
high. In the case of a read cycle, HDx should also be valid before rising DS.
Table 6−29. HPI8 Mode Timing Requirements
MIN
MAX
UNIT
tsu(HBV-DSL)
Setup time, HBIL valid before DS low
5
ns
th(DSL-HBV)
Hold time, HBIL valid after DS low
6
ns
tsu(HSL-DSL)
Setup time, HAS low before DS low
5
ns
tw(DSL)
Pulse duration, DS low
20
ns
tw(DSH)
Pulse duration, DS high
10
ns
tsu(HDV-DSH)
Setup time, HDx valid before DS high, HPI write
12
ns
th(DSH-HDV)W
Hold time, HDx valid after DS high, HPI write
8
ns
tsu(GPIO-COH)
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
9
ns
th(GPIO-COH)
Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input
−3
ns
70
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
Table 6−30. HPI8 Mode Switching Characteristics
PARAMETER
ten(DSL-HD)
td(DSL-HDV1)
Enable time, HD driven from DS low
Delay time, DS low to HDx valid for
first byte of an HPI read
MAX
UNIT
5
21
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) < 18H†
18H + 21 − tw(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) ≥ 18H†
21
Case 1c: Memory access when
DMAC is active in 32-bit mode and
tw(DSH) < 26H†
26H + 21 − tw(DSH)
Case 1d: Memory access when
DMAC is active in 32-bit mode and
tw(DSH) ≥ 26H†
21
ns
Case 2a: Memory accesses when
DMAC is inactive and tw(DSH) < 10H†
10H + 21 − tw(DSH)
Case 2b: Memory accesses when
DMAC is inactive and tw(DSH) ≥ 10H†
21
Case 3: Register accesses
21
td(DSL-HDV2)
Delay time, DS low to HDx valid for second byte of an HPI read
th(DSH-HDV)R
Hold time, HDx valid after DS high, for a HPI read
tv(HYH-HDV)
td(DSH-HYL)
td(DSH-HYH)
MIN
21
ns
9
ns
Valid time, HDx valid after HRDY high
12
ns
Delay time, DS high to HRDY low (see Note 1)
21
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode†
18H + 21
ns
Case 1b: Memory accesses when
DMAC is active in 32-bit mode†
26H + 21
ns
Case 2: Memory accesses when
DMAC is inactive†
10H + 21
Case 3: Write accesses to HPIC
register (see Note 2)
6H + 21
Delay time, DS high to HRDY high
5
ns
td(HCS-HRDY)
Delay time, HCS low/high to HRDY low/high
19
ns
td(COH-HYH)
Delay time, CLKOUT high to HRDY high
5
ns
td(COH-HTX)
Delay time, CLKOUT high to HINT change
5
ns
td(COH-GPIO)
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output.
9
ns
NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
2. This timing applies to the first byte of an access, when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes
to the HPIC occur asynchronously, and do not cause HRDY to be deasserted.
† DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
October 2002 − Revised October 2004
SPRS199B
71
Electrical Specifications
Second Byte
First Byte
Second Byte
HAS
tsu(HBV-DSL)
tsu(HSL-DSL)
HAD†
Valid
Valid
tsu(HBV-DSL)‡
th(DSL-HBV)‡
HBIL
HCS
tw(DSH)
tw(DSL)
HDS
td(DSH-HYH)
td(DSH-HYL)
HRDY
ten(DSL-HD)
td(DSL-HDV2)
th(DSH-HDV)R
HD READ
td(DSL-HDV1)
Valid
Valid
tsu(HDV-DSH)
Valid
tv(HYH-HDV)
th(DSH-HDV)W
HD WRITE
Valid
Valid
Valid
td(COH-HYH)
CLKOUT
†
‡
HAD refers to HCNTL0, HCNTL1, and HR/W.
When HAS is not used (HAS always high)
Figure 6−27. Using HDS to Control Accesses (HCS Always Low)
72
SPRS199B
October 2002 − Revised October 2004
Electrical Specifications
Second Byte
First Byte
Second Byte
HCS
HDS
td(HCS-HRDY)
HRDY
Figure 6−28. Using HCS to Control Accesses
CLKOUT
td(COH-HTX)
HINT
Figure 6−29. HINT Timing
CLKOUT
tsu(GPIO-COH)
th(GPIO-COH)
GPIOx Input Mode†
td(COH-GPIO)
GPIOx Output Mode†
†
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
Figure 6−30. GPIOx† Timings
October 2002 − Revised October 2004
SPRS199B
73
Mechanical Data
7
Mechanical Data
Table 7−1 and Table 7−2 show the thermal resistance characteristics for the GQW (PBGA) and ZQW (PBGA)
mechanical packages.
Table 7−1. Thermal Resistance Characteristics for GQW
†
PARAMETER
GQW PACKAGE
UNIT
RΘJA
36.24†
°C / W
RΘJC
17.93
°C / W
Based on a JEDEC 2s2p-style (high-k) board with 0 linear feet per minute (lfm) airflow.
Table 7−2. Thermal Resistance Characteristics for ZQW
†
PARAMETER
ZQW PACKAGE
UNIT
RΘJA
36.24†
°C / W
RΘJC
17.93
°C / W
Based on a JEDEC 2s2p-style (high-k) board with 0 linear feet per minute (lfm) airflow.
The following mechanical package diagram(s) reflect the most up-to-date mechanical data released for these
designated device(s).
74
SPRS199B
October 2002 − Revised October 2004
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
TMS320UC5405GQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GQW
143
250
TBD
SNPB
Level-3-220C-168HR
TMS320UC5405ZQW
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQW
143
250
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168HR
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1