[ /Title (CD74H C4094, CD74H CT4094 ) /Subject (High Speed CMOS Logic 8- CD54HC4094, CD74HC4094, CD74HCT4094 Data sheet acquired from Harris Semiconductor SCHS211D November 1997 - Revised October 2003 High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State Features Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge, provides a means for cascading these devices when the clock rise time is slow. • Buffered Inputs • Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges For Cascading • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times TEMP. RANGE (oC) PACKAGE CD54HC4094F3A -55 to 125 16 Ld CERDIP CD74HC4094E -55 to 125 16 Ld PDIP CD74HC4094M -55 to 125 16 Ld SOIC CD74HC4094MT -55 to 125 16 Ld SOIC CD74HC4094M96 -55 to 125 16 Ld SOIC CD74HC4094NSR -55 to 125 16 Ld SOP CD74HC4094PW -55 to 125 16 Ld TSSOP CD74HC4094PWR -55 to 125 16 Ld TSSOP CD74HC4094PWT -55 to 125 16 Ld TSSOP CD74HCT4094E -55 to 125 16 Ld PDIP CD74HCT4094M -55 to 125 16 Ld SOIC CD74HCT4094MT -55 to 125 16 Ld SOIC CD74HCT4094M96 -55 to 125 16 Ld SOIC PART NUMBER • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered three-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high. NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC4094 (CERDIP) CD74HC4094 (PDIP, SOIC, SOP, TSSOP) CD74HCT4094 (PDIP, SOIC) TOP VIEW 16 VCC STROBE 1 DATA 2 15 OE CP 3 14 Q4 Q0 4 13 Q5 Q1 5 12 Q6 Q2 6 11 Q7 Q3 7 10 QS2 GND 8 9 QS1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC4094, CD74HC4094, CD74HCT4094 Functional Diagram 2 DATA CP 3 1 STROBE 9 8-STAGE SHIFT REGISTER QS1 10 QS2 8-BIT STORAGE REGISTER 4 Q0 5 Q1 6 Q2 7 15 OE THREESTATE OUTPUT 14 13 12 11 Q3 Q4 Q5 Q6 Q7 GND = 8 VCC = 16 TRUTH TABLE INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS CP OE STR D Q0 Qn QS1 (NOTE 1) QS2 ↑ L X X Z Z Q’6 NC ↓ L X X Z Z NC Q7 ↑ H L X NC NC Q’6 NC ↑ H H L L Qn -1 Q’6 NC ↑ H H H H Qn -1 Q’6 NC ↓ H H H NC NC NC Q7 H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, NC = No charge, Z = High Impedance Off-state, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low. NOTE: 1. At the positive clock edge the information in the seventh register stage is transferred to the 8th register stage and QS1 output. 2 3 OE STR CP DATA 15 1 3 2 Q CP CP FFO D LO OE OE 4 Q0 Q STR STR FF1 L1 FF2 5 Q1 L2 FF3 6 Q2 L3 FF4 7 Q3 L4 FF5 14 Q4 L5 FF6 13 Q5 L6 FF7 12 Q6 D CP L7 L8 Q 11 Q7 CP QS2 QS1 10 9 CD54HC4094, CD74HC4094, CD74HCT4094 Logic Diagram CD54HC4094, CD74HC4094, CD74HCT4094 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 2): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature (Plastic Package) . . . . . . . . . 150o Maximum Storage Temperature Range . . . . . . . . . . . -65oC to 150o Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300o SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 4 CD54HC4094, CD74HC4094, CD74HCT4094 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 3) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS D 0.4 CP, OE 1.5 STR 1.0 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Prerequisite for Switching Specifications 25oC CHARACTERISTIC -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS tW 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns HC TYPES CP Pulse Width STR Pulse Width tWH 5 CD54HC4094, CD74HC4094, CD74HCT4094 Prerequisite for Switching Specifications (Continued) 25oC CHARACTERISTIC Data Set-up Time Data Hold Time STR Set-up Time STR Hold Time Maximum CP Frequency SYMBOL -40oC TO 85oC -55oC TO 125oC VCC (V) MIN MAX MIN MAX MIN MAX UNITS tSU tH tSU tH fCL (MAX) 2 50 - 65 - 75 - ns 4.5 10 - 13 - 15 - ns 6 9 - 11 - 13 - ns 2 3 - 3 - 3 - ns 4.5 3 - 3 - 3 - ns 6 3 - 3 - 3 - ns 2 100 - 125 - 150 - ns 4.5 20 - 25 - 30 - ns 6 17 - 21 - 26 - ns 2 0 - 0 - 0 - ns 4.5 0 - 0 - 0 - ns 6 0 - 0 - 0 - ns 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz HCT TYPES tW 4.5 16 - 20 - 24 - ns STR Pulse Width tWH 4.5 16 - 20 - 24 - ns Data Set-up Time tSU 4.5 10 - 13 - 15 - ns Data Hold Time tH 4.5 4 - 4 - 4 - ns STR Set-up Time tSU 4.5 20 - 25 - 30 - ns STR Hold Time tH 4.5 0 - 0 - 0 - ns fCL (MAX) 4.5 30 - 24 - 20 - MHz CP Pulse Width Maximum CP Frequency Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay Time (Figure 1) TEST SYMBOL CONDITIONS tPLH, tPHL CP to Qn STR to Qn tPLH, tPHL tPLH, tPHL tPLH, tPHL -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns CL =15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 26 - 33 - 38 ns CL = 50pF CP to QS1 CP to QS2 25oC VCC (V) CL = 50pF 2 - - 135 - 170 - 205 ns 4.5 - - 27 - 34 - 41 ns CL =15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 23 - 29 - 35 ns CL = 50pF 2 - - 195 - 245 - 295 ns 4.5 - - 39 - 49 - 59 ns 5 - 16 - - - - - ns 6 - - 33 - 42 - 50 ns 2 - - 180 - 225 - 270 ns 4.5 - - 36 - 45 - 54 ns 6 - - 31 - 38 - 46 ns CL = 50pF 6 CD54HC4094, CD74HC4094, CD74HCT4094 Switching Specifications Input tr, tf = 6ns PARAMETER Output Enable to Qn Output Disable to Qn Output Transition Time Output Disabling Time Maximum CP Frequency (Continued) TEST SYMBOL CONDITIONS tPZH, tPZL CL = 50pF tPHZ, tPLZ CL = 50pF tTLH, tTHL CL = 50pF tPHZ, tPLZ CL =15pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns 6 - - 30 - 37 - 45 ns 2 - - 125 - 155 - 190 ns 4.5 - - 25 - 31 - 38 ns 6 - - 21 - 26 - 32 ns 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns 5 - 10 - - - - - ns 5 - 60 - - - - - MHz fMAX CL =15pF Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL =15pF 5 - 90 - - - - - pF Three-State Output Capacitance CO CL = 50pF - - - 15 - 15 - 15 pF tPLH, tPHL CL = 50pF 4.5 - - 39 - - - - ns CL =15pF 5 - 16 - - - - - ns tPLH, tPHL CL = 50pF 4.5 - - 36 - - - - ns CL =15pF 5 - 15 - - - - - ns CP to Qn tPLH, tPHL CL = 50pF 4.5 - - 43 - - - - ns CL =15pF 5 - 18 - - - - - ns STR to Qn tPLH, tPHL CL = 50pF 4.5 - - 39 - - - - ns Output Enable to Qn tPZH, tPZL CL = 50pF 4.5 - - 35 - - - - ns Output Disable to Qn tPHZ, tPLZ CL = 50pF 4.5 - - 35 - - - - ns Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - - - - ns Output Disabling Time tPHZ, tPLZ CL =15pF HCT TYPES Propagation Delay Time (Figure 1) CP to QS1 CP to QS2 5 - 14 - - - - - ns fMAX CL =15pF 5 - 60 - - - - - MHz Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL =15pF 5 - 110 - - - - - pF Three-State Output Capacitance CO CL = 50pF - - - 15 - 15 - 15 pF Maximum CP Frequency NOTES: 4. CPD is used to determine the dynamic power consumption, per register. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 7 CD54/74HC4094, CD74HCT4094 Test Circuits and Waveforms 6ns 6ns 90% VS 10% INPUT LEVEL VS GND CLOCK tSU tH tW tW INPUT LEVEL SERIAL IN GND tPLH tPHL VOH VS Qn, QS1 VOL tPHL VOH tPLH VS VOL QS2 FIGURE 1. DATA PROPAGATION DELAYS, SET-UP AND HOLD TIMES INPUT LEVEL tr = 6ns SERIAL IN GND tSU tH VS CLOCK OE VOH VS VOL OUTPUT HIGH TO OFF OUTPUTS CONNECTED VOH VS VOL FIGURE 2. STROBE PROPAGATION DELAYS AND SET-UP AND HOLD TIMES VS 10% tPHZ tPLH, tPHL Qn OUTPUT LOW TO OFF 10% tPZL tPLZ GND STROBE 90% VS INPUT LEVEL VS tW tf = 6ns tPZH 90% OUTPUTS DISCONNECTED VS OUTPUTS CONNECTED FIGURE 3. ENABLE AND DISABLE TIMES 8 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type CD54HC4094F3A ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC CD74HC4094E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC4094M ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HC4094M96 ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HC4094MT ACTIVE SOIC D 16 250 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HC4094NSR ACTIVE SO NS 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HC4094PW ACTIVE TSSOP PW 16 90 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CD74HC4094PWR ACTIVE TSSOP PW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CD74HC4094PWT ACTIVE TSSOP PW 16 250 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CD74HCT4094E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT4094M ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HCT4094M96 ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HCT4094MT ACTIVE SOIC D 16 250 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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