DATA SHEET MOS INTEGRATED CIRCUIT MC-45V16AD641 16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE TM VirtualChannel Description The MC-45V16AD641 is a 16,777,216 words by 64 bits VirtualChannel synchronous dynamic RAM module on which 16 pieces of 64M VirtualChannel SDRAM : µPD4565821 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features • 16,777,216 words by 64 bits organization • Clock frequency and access time from CLK Part number Clock Read Access latency frequency Maximum supply current mA time Operating MHz from CLK (MAX.) ns (MAX.) 133 5.4 880 MC-45V16AD641KF-A10 100 6 MC-45V16AD641EF-A75 133 MC-45V16AD641EF-A10 100 MC-45V16AD641KF-A75 2 Prefetch Restore Refresh Channel Auto Self 720 1280 16 840 600 1120 5.4 880 720 1280 6 840 600 1120 read / write (Burst) • Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Dual internal banks controlled by BA0 (Bank Select) • Programmable Wrap sequence (Sequential / Interleave) • Programmable burst length (1, 2, 4, 8 and 16) ★ • Read latency (2) • Prefetch Read latency (4) • Auto precharge and without auto precharge • Auto refresh and Self refresh • Single 3.3 V ± 0.3 V power supply • Interface: LVTTL • Refresh cycle: 4K cycles / 64 ms • 168-pin dual in-line memory module (Pin pitch = 1.27 mm) • Unbuffered type • Serial PD The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M13823EJ6V0DS00 (6th edition) The mark • shows major revised points. Date Published June 2000 NS CP (K) Printed in Japan © 1998 MC-45V16AD641 ★ Ordering Information Part number Clock Read Prefetch frequency latency read MHz (MAX.) Package Mounted devices latency 168-pin Dual In-line 16 pieces of µPD4565821G5 100 Memory Module (Socket Type) (10.16 mm (400) TSOP (II)) (Rev.K) MC-45V16AD641EF-A75 133 Edge connector : Gold plated 16 pieces of µPD4565821G5 MC-45V16AD641EF-A10 100 34.93 mm height (10.16 mm (400) TSOP (II)) (Rev.E) MC-45V16AD641KF-A75 133 MC-45V16AD641KF-A10 2 2 4 Data Sheet M13823EJ6V0DS00 MC-45V16AD641 Pin Configuration 168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal. 85 86 87 88 89 90 91 92 93 94 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 NC NC VSS NC NC Vcc /CAS DQMB4 DQMB5 /CS1 /RAS VSS A1 A3 A5 A7 A9 BA0 (A13) A11 Vcc DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 NC NC VSS NC NC Vcc /WE DQMB0 DQMB1 /CS0 NC VSS A0 A2 A4 A6 A8 A10 A12 Vcc 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 CLK1 NC VSS CKE0 /CS3 DQMB6 DQMB7 NC Vcc NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL Vcc 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Data Sheet M13823EJ6V0DS00 A0 - A12 : Address Inputs [Row: A0 - A12, Column: A0 - A6] BA0 (A13) : VirtualChannel SDRAM Bank Select DQ0 - DQ63 : Data Inputs/Outputs CLK0 - CLK3 : Clock Input CKE0, CKE1 : Clock Enable Input /CS0 - /CS3 : Chip Select Input /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQMB0 - DQMB7 : DQ Mask Enable SA0 - SA2 : Address Input for EEPROM SDA : Serial Data I/O for PD SCL : Clock Input for PD VCC : Power Supply VSS : Ground WP : Write Protect NC : No Connection 3 MC-45V16AD641 Block Diagram /WE /CS0 /CS1 /CS2 DQMB0 /CS3 DQMB2 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D0 DQ 3 DQ 2 DQ 1 DQ 0 /WE DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D8 DQ 4 DQ 5 DQ 6 DQ 7 /WE DQ 7 DQM /WE /CS /WE DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D2 DQ 3 DQ 2 DQ 1 DQ 0 /WE DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D10 DQ 4 DQ 5 DQ 6 DQ 7 /WE DQ 4 DQM /CS DQ 7 DQ 6 DQ 5 D3 DQ 3 DQ 2 DQ 1 DQ 0 /WE DQ 3 DQM /CS DQ 0 DQ 1 DQ 2 D11 DQ 4 DQ 5 DQ 6 DQ 7 /WE DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D6 DQ 3 DQ 2 DQ 1 DQ 0 /WE DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D14 DQ 4 DQ 5 DQ 6 DQ 7 /WE DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D7 DQ 3 DQ 2 DQ 1 DQ 0 /WE DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D15 DQ 4 DQ 5 DQ 6 DQ 7 /WE DQMB3 DQMB1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 /CS D1 DQ 0 DQM DQ 1 DQ 2 DQ 3 D9 DQ 4 DQ 5 DQ 6 DQ 7 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 DQMB6 DQMB4 DQ 4 DQM /CS DQ 7 DQ 6 DQ 5 D4 DQ 3 DQ 2 DQ 1 DQ 0 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 /WE DQ 3 DQM /CS DQ 0 DQ 1 DQ 2 D12 DQ 4 DQ 5 DQ 6 DQ 7 /WE DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 DQMB7 DQMB5 DQ 5 DQM /CS DQ 7 DQ 6 DQ 4 D5 DQ 3 DQ 2 DQ 1 DQ 0 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 /WE DQ 2 DQM /CS DQ 0 DQ 1 DQ 3 D13 DQ 4 DQ 5 DQ 6 DQ 7 /WE CLK0 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 CLK: D0, D1, D4, D5 CLK2 CLK: D2, D3, D6, D7 3.3 pF SERIAL PD 3.3 pF SDA SCL A0 A1 A2 WP CLK1 CLK: D8, D9, D12, D13 CLK3 CLK: D10, D11, D14, D15 3.3 pF 3.3 pF 47 kΩ SA0 SA1 SA2 A0 - A12 A0 - A12: D0 - D15 BA0 VCC /RAS: D0 - D15 /CAS /CAS: D0 - D15 CKE0 CKE: D0 - D7 D0 - D15 Remarks 1. The value of all resistors is 10 Ω except CKE1 and WP. 2. D0 - D15: µPD4565821 (4M words × 8 bits × 2 banks) 4 10 CKE1 D0 - D15 C V SS /RAS A13: D0 - D15 Data Sheet M13823EJ6V0DS00 CKE: D8-D15 MC-45V16AD641 Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Voltage on power supply pin relative to GND Rating Unit VCC –0.5 to +4.6 V Voltage on input pin relative to GND VT –0.5 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 16 W Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg –55 to +125 °C Caution Condition Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 3.3 3.6 V Supply voltage VCC 3.0 High level input voltage VIH 2.0 VCC + 0.3 V Low level input voltage VIL −0.3 +0.8 V Operating ambient temperature TA 0 70 °C MAX. Unit pF Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Data input/output capacitance Symbol Test condition MIN. TYP. CI1 A0 - A12, BA0 (A13), /RAS, /CAS, /WE 58 94 CI2 CLK0 - CLK3 24 40 CI3 CKE0, CKE1 32 52 CI4 /CS0 - /CS3 17 29 CI5 DQMB0 - DQMB7 10 17 CI/O DQ0 - DQ63 11 19 Data Sheet M13823EJ6V0DS00 pF 5 MC-45V16AD641 DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter ★ Operating current (Prefetch Symbol ICC1P mode at one bank active) ★ Operating current (Restore ICC1R Test condition in power down mode Precharge standby current ICC2P ICC2PS ICC2N ICC2NS power down mode Active standby current in ICC3P ICC3PS ICC3N non power down mode Operating current Unit Notes mA 1 mA 1 -A75 880 Prefetch is executed one time during tRC. -A10 840 tRC ≥ tRC (MIN.) -A75 880 -A10 840 CKE ≤ VIL (MAX.), tCK = 15 ns 16 CKE ≤ VIL (MAX.), tCK = ∞ ICC4 (Burst mode) 8 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 400 CKE ≥ VIH (MIN.), tCK = ∞ , Input signals are stable. 128 CKE ≤ VIL (MAX.), tCK = 15 ns 80 CKE ≤ VIL (MAX.), tCK = ∞ 64 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 400 CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable. mA mA mA 160 tCK ≥ tCK (MIN.), IO = 0 mA -A75 720 Background : precharge standby -A10 600 ★ Auto refresh current ICC5 tRC ≥ tRC (MIN.) -A75 1,280 -A10 1,120 ★ Self refresh current ICC6 CKE ≤ 0.2 V -A75 16 -A10 16 Input leakage current mA Input signals are changed one time during 30 ns. ICC3NS ★ MAX. Input signals are changed one time during 30 ns. in non power down mode Active standby current in MIN. tRC ≥ tRC (MIN.) mode at one bank active) Precharge standby current Grade 2 mA 3 mA –16 +16 µA –500 +500 µA –1.5 +1.5 µA II (L) VI = 0 to 3.6 V, All other pins not under test = 0 V Output leakage current IO (L) DOUT is disabled, VO = 0 to 3.6 V High level output voltage VOH IO = – 4.0 mA 2.4 Low level output voltage VOL IO = + 4.0 mA Input leakage current (CKE1) mA V 0.4 V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). 6 Data Sheet M13823EJ6V0DS00 MC-45V16AD641 AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions • AC measurements assume tT = 1 ns. • Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. • If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.). • An access time is measured at 1.4 V. tCK tCK tCL tCH tCH tCL CLK tCKH tCKS CKE tS Command Address DQM (Input) tH Valid tDS Data (Input) tDH Valid Hi-Z tDH Valid tAC tAC tLZ Data (Output) tDS tOH Valid Data Sheet M13823EJ6V0DS00 tHZ Valid Hi-Z 7 MC-45V16AD641 ★ AC characteristics Parameter Symbol -A75 -A10 Unit MIN. MAX. MIN. MAX. Clock cycle time tCK 7.5 − 10 − ns Access time from CLK tAC − 5.4 − 6 ns CLK high level width tCH 2.5 − 3 − ns CLK low level width tCL 2.5 − 3 − ns Data-out hold time tOH 2.7 − 3 − ns Data-out low-impedance time tLZ 0 − 0 − ns Data-out high-impedance time tHZ 2.5 5.4 3 6 ns Data-in setup time tDS 1.5 − 2 − ns Data-in hold time tDH 0.8 − 1 − ns Address, Command, DQM setup time tS 1.5 − 2 − ns Address, Command, DQM hold time tH 0.8 − 1 − ns CKE setup time tCKS 1.5 − 2 − ns CKE hold time tCKH 0.8 − 1 − ns CKE setup time (Power down exit) tCKSP 1.5 − 2 − ns tT 0.5 30 1 30 ns Refresh time (4,096 refresh cycles) tREF − 64 − 64 ms Mode register set cycle time tRSC 2 − 2 − CLK Transition time Note 1. Output load. Z = 50 Ω Output 50 pF 8 Data Sheet M13823EJ6V0DS00 Note 1 1 MC-45V16AD641 ★ AC characteristics (Background to Background operation) Parameter Symbol -A 75 -A10 Unit MIN. MAX. MIN. MAX. Notes Same Bank Operation ACT to ACT/REF Command period tRC 67.5 − 80 − ns REF to REF/ ACT Command period tRCF 67.5 − 80 − ns ACT to PRE Command period tRAS 52 120,000 60 120,000 ns PRE to ACT / REF Command period tRP 20 − 20 − ns ACT to PFC/PFCA/ PPF/PPFA Command delay time tAPD 15 − 20 − ns ACT to PFR Command delay time (Prefetch Read Operation) tAPRD 20 − 20 − ns PFC to PRE Command delay time tPPL 22.5 − 30 − ns PFCA / PFR to ACT/REF Command delay time tPAL 45 − 50 − ns PPF to PRE Command delay time tPPP 45 − 60 − ns PPFA to ACT/REF Command delay time tPPA 67.5 − 80 − ns tRAD 7.5 30 10 40 ns tRPD 37.5 − 40 − ns PFC to PFC / PFCA Command delay time tPPD 22.5 − 30 − ns PPF to PPF / PPFA Command delay time tPPPD 45 − 60 − ns ACT to ACT/ACT(R) or ACT(R) to ACT Command delay time tRRD 15 − 20 − ns ACT(R) to ACT(R) Command delay time tRRDR 30 − 40 − ns PFC /PFCA to RST /RSTA Command delay time tPRD 22.5 − 30 − ns PPF /PPFA to RST /RSTA Command delay time tPPRD 45 − 60 − ns RST / RSTA to ACT(R) Note1 Command delay time 2 Same, Other Bank Operation ACT(R) Note1 to PFC/PFCA/PFR/ PPF/PPFA Command delay time Other Bank Operation Notes 1. ACT (R) command is ACT command after RST command. 2. The another background operation and same channel foreground operation are illegal while tRAD period. Data Sheet M13823EJ6V0DS00 9 MC-45V16AD641 ★ AC characteristics (Foreground to Foreground operation) Parameter Symbol READ/WRITE to READ/WRITE Command delay time ★ tCCD -A75 -A10 Unit MIN. MAX. MIN. MAX. 7.5 − 10 − Note ns AC characteristics (Background to Foreground operation) (after same channel Prefetch/Restore) Parameter PFC/PFCA/PPF/PPFA to READ/WRITE Symbol -A75 -A10 Unit MIN. MAX. MIN. MAX. tPCD 15 − 20 − ns tPPCD 37.5 − 50 − ns tRCD 30 − 40 − ns Note Command delay time PPF/PPFA to READ/WRITE Command delay time (2nd prefetch channel read write) ACT(R) to READ/WRITE Command delay time Note 1. ACT (R) command is ACT command after RST command. 10 Data Sheet M13823EJ6V0DS00 1 MC-45V16AD641 Serial PD Byte No. 0 (1/2) Function Described Defines the number of bytes written Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 80H 1 0 0 0 0 0 0 0 128 bytes 08H 0 0 0 0 1 0 0 0 256 bytes into serial PD memory 1 Total number of bytes of serial PD 2 Fundamental memory type 08H 0 0 0 0 1 0 0 0 VC SDRAM 3 Number of row addresses 0DH 0 0 0 0 1 1 0 1 13 rows 4 Number of column addresses 07H 0 0 0 0 0 1 1 1 7 columns 5 Number of banks 02H 0 0 0 0 0 0 1 0 2 banks 6 Data width 40H 0 1 0 0 0 0 0 0 64 bits 7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0 8 Voltage interface standard 01H 0 0 0 0 0 0 0 1 LVTTL 9 Read latency (/CAS latency) = 2 -A75 75H 0 1 1 1 0 1 0 1 7.5 ns cycle time -A10 A0H 1 0 1 0 0 0 0 0 10 ns Read latency (/CAS latency) = 2 -A75 54H 0 1 0 1 0 1 0 0 5.4 ns access time -A10 60H 0 1 1 0 0 0 0 0 6 ns memory ★ ★ • 10 11 DIMM configuration type 00H 0 0 0 0 0 0 0 0 None 12 Refresh rate / type 80H 1 0 0 0 0 0 0 0 Normal 13 VC SDRAM width 08H 0 0 0 0 1 0 0 0 ×8 14 Error checking SDRAM width 00H 0 0 0 0 0 0 0 0 None 15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock 16 Burst length supported 1FH 0 0 0 1 1 1 1 1 1, 2, 4, 8, 16 17 Number of banks on each VC SDRAM 02H 0 0 0 0 0 0 1 0 2 banks 18 Read latency (/CAS latency) supported 02H 0 0 0 0 0 0 1 0 2 19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0 20 /WE latency supported 01H 0 0 0 0 0 0 0 1 0 21 VC SDRAM module attributes 00H 0 0 0 0 0 0 0 0 22 VC SDRAM device attributes : general 0EH 0 0 0 0 1 1 1 0 00H 0 0 0 0 0 0 0 0 -A75 14H 0 0 0 1 0 1 0 0 20 ns -A10 14H 0 0 0 1 0 1 0 0 20 ns -A75 0FH 0 0 0 0 1 1 1 1 15 ns -A10 14H 0 0 0 1 0 1 0 0 20 ns -A75 0FH 0 0 0 0 1 1 1 1 15 ns -A10 14H 0 0 0 1 0 1 0 0 20 ns -A75 34H 0 0 1 1 0 1 0 0 52 ns -A10 3CH 0 0 1 1 1 1 0 0 60 ns • 23-26 • 27 • • • 28 29 30 tRP (MIN.) tRRD (MIN.) tAPD (MIN.) tRAS (MIN.) Data Sheet M13823EJ6V0DS00 11 MC-45V16AD641 (2/2) Byte No. • • Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 10H 0 0 0 1 0 0 0 0 64M bytes Address and command signal -A75 15H 0 0 0 1 0 1 0 1 1.5 ns input setup time -A10 20H 0 0 1 0 0 0 0 0 2 ns Address and command signal -A75 08H 0 0 0 0 1 0 0 0 0.8 ns input hold time -A10 10H 0 0 0 1 0 0 0 0 1 ns Data signal input setup time -A75 15H 0 0 0 1 0 1 0 1 1.5 ns -A10 20H 0 0 1 0 0 0 0 0 2 ns -A75 08H 0 0 0 0 1 0 0 0 0.8 ns -A10 10H 0 0 0 1 0 0 0 0 1 ns -A75 04H 0 0 0 0 0 1 0 0 4 clocks -A10 04H 0 0 0 0 0 1 0 0 4 clocks -A75 0FH 0 0 0 0 1 1 1 1 15 ns -A10 14H 0 0 0 1 0 1 0 0 20 ns 36 • Bit 6 32 35 • Bit 7 Module bank density 34 • Hex 31 33 • Function Described 37 Data signal input hold time Prefetch read latency tPCD (MIN.) 38 Number of segment addresses 02H 0 0 0 0 0 0 1 0 2 bits 39 Number of channels 04H 0 0 0 0 0 1 0 0 16 40 Depth of channels 07H 0 0 0 0 0 1 1 1 128 bits 62 SPD revision 02H 0 0 0 0 0 0 1 0 2.0 63 Checksum for bytes 0 - 62 -A75 3EH 0 0 1 1 1 1 1 0 -A10 B2H 1 0 1 1 0 0 1 0 41-61 • • 64-71 72 Manufacture’s JEDEC ID code Manufacturing location 73-90 Manufacture’s P/N 91-92 Revision code 93-94 Manufacturing date 95-98 Assembly serial number 99-125 Mfg specific Timing Charts Please refer to the µPD4565421, 4565821, 4565161 Data sheet (M13022E). 12 Data Sheet M13823EJ6V0DS00 MC-45V16AD641 Package Drawing 168 PIN DUAL IN-LINE MODULE (SOCKET TYPE) A (AREA B) Z1 Z2 Y1 Y2 R2 N F2 F1 Q R1 M L A J S (OPTIONAL HOLES) K C B I B H G U1 U2 T E D A1 (AREA A) M2 (AREA A) M1 (AREA B) detail of A part detail of B part D2 W V P X D1 ITEM A A1 B C D D1 D2 E F1 F2 G H I J K L M M1 M2 N P Q R1 R2 S T U1 U2 V W MILLIMETERS 133.35 133.35±0.13 11.43 36.83 6.35 2.0 3.125 54.61 2.44 3.18 6.35 1.27 (T.P.) 8.89 24.495 42.18 17.78 34.93±0.13 15.15 19.78 4.0 MAX. 1.0 R2.0 4.0±0.10 9.53 φ 3.0 X Y1 1.27±0.1 4.0 MIN. 4.0 MIN. 0.2±0.15 1.0±0.05 2.54±0.10 3.0 MIN. Y2 Z1 Z2 2.26 3.0 MIN. 2.26 M168S-50A78 Data Sheet M13823EJ6V0DS00 13 MC-45V16AD641 Revision History Edition / Date Page Description This Previous Type of edition edition revision 4th edition / p.1 p.1 Deletion Jun. 1999 p.2 p.2 p.3 p.3 p.6 p.6 p.8 p.8 Location -A70 Modification PIN No.53, No.63 Deletion -A70 Modification Note 1 p.9 p.9 Deletion -A70, tRCPD, tDAL Modification tAPD (Parameter), tRPD (Parameter) p.10 p.10 Deletion -A70 Modification tPCD (Parameter) p.11 p.11 Deletion -A70 p.12 p.12 p.14 p.14 Addition Revision History 5th edition / p.1 p.1 Addition MC-45V16AD641EF-A75, MC-45V16AD641EF-A10, MC-45V16AD641EF-A15 Dec. 1999 p.2 p.2 Addition MC-45V16AD641EF-A75, MC-45V16AD641EF-A10, MC-45V16AD641EF-A15 p.3 p.3 Modification Pin Configuration (WP) Deletion p.4 p.4 Note Modification Block Diagram (WP) Deletion Remarks 2 p.5 p.5 Modification Capacitance p.8 p.8 Modification tHZ (-A75 (MAX.), -A15 (MAX.)) p.13 p.13 Modification Package Drawing 6th edition / p.1 p.1 Jun. 2000 p.2 p.2 p.6 p.6 p.8 p.8 Deletion -A15 Modification tT (-A75(MIN.)) p.9 p.9 p.10 p.10 p.11 p.11 Deletion -A15 Modification Byte No. 18 p.12 Deletion Byte No. 23, 24 p.11, 12 Deletion -A15 p.12 Addition Byte No. 32-35, -A75 Modification Byte No. 63 14 Data Sheet M13823EJ6V0DS00 MC-45V16AD641 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M13823EJ6V0DS00 15 MC-45V16AD641 VirtualChannel is a trademark of NEC Corporation. CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. • The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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