DATA SHEET HYBRID INTEGRATED CIRCUIT MC-9400A 320 (240)-BIT AC- PDP DRIVER MODULE DESCRIPTION The MC-9400A is a PDP driver module that incorporates five 64-bit high breakdown voltage output (150 V, 40 mA) CMOS driver ICs. It supports 320 outputs in the case of 4-bit parallel input, and 240 outputs in the case of 3-bit parallel input. The integrated structure of the MC-9400A, which combines a COB with an aluminum heat sink and an output flexible printed circuit (FPC) board, enables the easy implementation of heat dissipation measures and high-density mounting. FEATURES • Incorporates five µPD16337s with four 16-bit bi-directional shift registers • Low thermal resistance realized by chip-on-metal structure • Provided with connector and capacitor for easy mounting on a panel • Supports output electrode with a narrow pitch through use of a flexible printed circuit board • Polarity of all driver outputs can be inverted through use of /PC pins • Supports custom modules Remark /XXX indicates active low. ORDERING INFORMATION Part Number Package MC-9400A COB The information in this document is subject to change without notice. Document No. S13787EJ2V0DS00 (2nd edition) Data Published October 1998 NS CP(K) Printed in Japan The mark ★ shows major revised points. © NEC Corporation 1998 MC-9400A BLOCK DIAGRAM (1/5 CIRCUIT) 74AC244 CN3 µ PD16337 /PC BLK LE R,/L A1 O1 O2 O3 O4 O5 O6 O7 A2 A3 A4 CN1,2 B1 B2 VDD1 (Logic power supply) B3 B4 VDD2 (Driver power supply) O60 O61 O62 O63 O64 /CLK Remark Five µPD16337s incorporated : 240 outputs at 3 ch and 320 outputs at 4 ch. See the following block diagram for the µPD16337. µPD16337 BLOCK DIAGRAM /PC BLK LE LE SR1 A1 /CLK R,/L S1 S5 A1 CLK S1 S2 S3 S4 Note /L1 O1 R,/L B1 B1 A2 A2 S61 SR2 S2 S6 CLK R,/L B2 B2 A3 A3 S62 SR3 S3 S7 CLK R,/L B3 B3 A4 A4 S63 SR4 S4 S8 CLK R,/L B4 B4 S64 S61 S62 S63 S64 S64 /L64 SRn : 16-bit shift register Note High breakdown voltage CMOS driver 150V, ±40 mA(MAX.). 2 MC-9400A ★ PIN CONFIGURATION (Top View) EPC CN3 B54 B53 B52 B51 A51 A52 A53 A54 B44 B43 B42 B41 A41 A42 A43 A44 GND /CLK GND LE GND R,/L GND /PC GND BLK B34 B33 B32 B31 A31 A32 A33 A34 B24 B23 B22 B21 A21 A22 A23 A24 B14 B13 B12 B11 A11 A12 A13 A14 O320 CN2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VDD2 GND VDD1 1 2 3 O257 O256 O194 O193 O129 O128 O65 O64 CN1 VDD2 GND VDD1 1 2 3 O1 Caution To prevent latch-up breakage, be sure to turn the power on in the order of VDD1, logic signal, and VDD2, and turn the power off in the reverse order. Keep this order also during a transition period. 3 MC-9400A PIN FUNCTIONS Pin Symbol /PC Pin Name Polarity inverted Pin No. I/O Description 27 CN3 /PC = L : Polarity of all outputs inverted input BLK Blanking input 25 CN3 BLK = H : All outputs = H or L LE Latch enable input 31 CN3 Automatically latches by a high level input at the rising edge of the clock A11 to A14, RIGHT data input 1 to 4 CN3 When R,/L = H A21 to A24, 9 to 12 A11 to A14, A21 to A24, A31 to A34, A41 to A44, A51 to A54 : Input A31 to A34, 17 to 20 B11 to B14, B21 to B24, B31 to B34, B41 to B44, B51 to B54 : Output A41 to A44, 35 to 38 When R,/L = L A51 to A54 46 A11 to A14, A21 to A24, A31 to A34, A41 to A44, A51 to A54 : Output B11 to B14, B21 to B24, B31 to B34, B41 to B44, B51 to B54 : Input B11 to B14, LEFT data input 5 to 8 B21 to B24, 13 to 16 B31 to B34, 21 to 24 B41 to B44, 39 to 42 B51 to B54 47 to 50 CN3 /CLK Clock input 33 CN3 Executes a shift at the rising edge R,/L Shift control input 29 CN3 Right shift mode by H SR1 : A1 → S1 ... S61 → B1 (SR2, SR3, and SR4 also same direction) Left shift mode by L SR1 : B1 → S61 ... S1 → A1 (SR2, SR3, and SR4 also same direction) O1 to O320 High breakdown 1 to 320 FPC 150 V, 40mA 1 CN1 5 V ± 10 % (MAX.) voltage output VDD1 Logic block power supply VDD2 Driver block power CN2 3 supply GND Ground CN1 CN2 2 CN1 CN2 26,28, 30,32, 34 4 30 V to 130 V CN3 Connected to system ground MC-9400A TRUTH TABLE 1. Shift register block Input Output Shift register R,/L /CLK H ↓ A B Output Note1 Execution of right shift Input H X L ↓ Output Output Note2 Retain Execution of left shift Input L X Output Retain Notes 1. On a clock rise, the data S57, S58, S59, and S60 are shifted to S61, S62, S63, and S64, and output from B1, B2, B3, and B4, respectively. 2. On a clock fall, the data S5, S6, S7, and S8 are shifted to S1, S2, S3, and S4, and output from A1, A2, A3, and A4, respectively. Remark X= H or L, H= High level, L= Low level 2. Latch block LE H L /CLK Output state of latch block (/Ln) ↓ Latches the data of Sn and retains the output data ↓ Retains the latch data X Retains the latch data Remark X= H or L, H= High level, L= Low level 3. Driver block /Ln BLK /PC Driver output state X H H H (all driver outputs : H) X H L L (all driver outputs : L) X L H Outputs latch data (/Ln) X L L Outputs latch data (/Ln) with polarity inverted Remark X= H or L, H= High level, L= Low level 5 MC-9400A ELECTRICAL CHARACTERISTICS Absolute maximum ratings (TA = +25°°C, VSS1 = VSS2 = 0 V) Parameter Symbol Ratings Unit Logic block supply voltage VDD1 − 0.5 to + 7.0 V Driver block supply voltage VDD2 − 0.5 to + 150 V Logic block input voltage V1 − 0.5 to VDD1 + 0.5 V Driver block output current IO2 40 mA Note Module allowable power dissipation PdMAX. 6 W Junction temperature TjMAX. 125 °C Operating ambient temperature TA − 10 to + 70 °C Storage temperature Tstg − 40 to + 85 °C Note The value when mounting this driver module on the aluminum frame by screw. Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended operating range (TA = −10 to + 70°°C, VSS1 = VSS2 = 0 V) Parameter Symbol MIN. TYP. MAX. Unit Logic block supply voltage VDD1 4.5 5.0 5.5 V Driver block supply voltage VDD2 30 130 V Input voltage high VIH 0.7 VDD1 VDD1 V Input voltage low VIL 0 0.2 VDD1 V Driver output current IOH2 −30 IOL2 6 mA +30 mA MC-9400A Electrical specifications (TA = +25°°C, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output voltage high VOH21 VDD2 = 130 V,IOH = −10 mA 123 V Output voltage high VOH22 VDD2 = 130 V,IOH = −30 mA 110 V Output voltage low VOL21 VDD2 = 130 V,IOH = 10 mA 5.0 V Output voltage low VOL22 VDD2 = 130 V,IOH = 30 mA 15.0 V Input leakage current (H1) PU ILIH1 VDD1 = 7.0 V,VDD2 = 30 V −4.0 +4.0 µA Input leakage current (H2) PC ILIH2 VDD1 = 7.0 V,VDD2 = 30 V −4.0 +4.0 µA Input leakage current (L2) PC ILIL2 VDD1 = 7.0 V,VDD2 = 30 V −4.0 +4.0 µA Input voltage high VIH VDD1 = 5.0 V,VDD2 = 30 V 3.5 Input voltage low VIL VDD1 = V 8 mA In : High Level 80 µA Out : ALL Low 500 µA IDD2 Out : ALL High 500 µA IDD2 Out :HLHLLHLH 500 µA IDD2 Out :LHLHHLHL 500 µA MAX. Unit IDD1 a1 Power supply current 1(Logic) IDD1 –1 Power supply current 2 V 1.0 Power supply current 1(Logic) IDD2 5.0 V,VDD2 = 30 V VDD1 = 7.0 V VDD1 = 5.0 V VDD2 =135 V (Driver) Power supply current 2 (Driver) Power supply current 2 (Driver) Power supply current 2 (Driver) Switching characteristics (TA = +25°°C, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. Propagation delay time tPLH2 VDD1 = 5.0 V, VDD2 = 130 V 187.5 ns Propagation delay time tPHL2 VDD1 = 5.0 V, VDD2 = 130 V 187.5 ns Propagation delay time tPLH3 VDD1 = 5.0 V, VDD2 = 130 V, 172.5 ns 172.5 ns 160.0 ns 160.0 ns BLK→OUT Propagation delay time tPHL3 VDD1 = 5.0 V, VDD2 = 130 V, BLK→OUT Propagation delay time tPLH4 VDD1 = 5.0 V, VDD2 = 130 V, PC→OUT Propagation delay time tPHL4 VDD1 = 5.0 V, VDD2 = 130 V, PC→OUT Rise time tTLH VDD1 = 5.0 V, VDD2 = 130 V 200.0 ns Fall time tTHL VDD1 = 5.0 V, VDD2 = 130 V 200.0 ns Maximum clock frequency fMAX. VDD1 = 4.0 V, VDD2 = 30 V 25.0 MHZ 7 MC-9400A Timing requirements (TA = +25°°C, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data setup time 1 tSETUP1 VDD1 = 4.5 V, VDD2 = 30 V 31.2 ns Data setup time 2 tSETUP2 VDD1 = 4.5 V, VDD2 = 30 V 12.0 ns Data hold time tHOLD VDD1 = 4.5 V, VDD2 = 30 V 8.5 ns Latch enable time 1 tLE1 VDD1 = 4.5 V, VDD2 = 30 V 27.5 ns Latch enable time 2 tLE2 VDD1 = 4.5 V, VDD2 = 30 V 17.5 ns Latch enable time 3 tLE3 VDD1 = 4.5 V, VDD2 = 30 V 27.5 ns Latch enable time 4 tLE4 VDD1 = 4.5 V, VDD2 = 30 V 17.5 ns 8 MC-9400A Timing chart (Right shift) /CLK A1 (B4) A2 (B3) A3 (B2) A4 (B1) S1 (S64) S2 (S63) S3 (S62) S4 (S61) S5 (S60) S6 (S59) S7 (S58) S8 (S57) LE BLK /PC O1 (O64) O2 (O63) O3 (O62) O4 (O61) O5 (O60) O6 (O59) O7 (O58) O8 (O57) Remark () applies when R,/L = L 9 MC-9400A Switching characteristics waveform Propagation delay time tPHL2, tPLH2 /CLK2 50 % 50% tPHL2 90 % On tPLH2 On 10% Propagation delay time (BLK → OUT) tPHL3, tPLH3 BLK 50 % 50% tPHL3 tPLH3 90 % On 10% 10 MC-9400A Propagation delay time (/PC → OUT) tPHL4, tPLH4 /PC 50% 50% tPHL4 tPLH4 90% On 10% Rise time, Fall time tTLH, tTHL tTHL tTLH On 90 % 90 % 10% 10% Maximum clock frequency FMAX. 1/fMAX. CLK2 50% 50% 11 MC-9400A Data setup time1, 2, and Data hold time tSETUP1, tSETUP2, tHOLD 50% /CLK1 tSETUP2 DATA tHOLD 50% tSETUP1 50% /CLK2 Latch enable time1, 2, 3, 4 tLE1, tLE2, tLE3, tLE4 /CLK2 50% tLE1 LE 12 50% 50% tLE2 50% tLE3 tLE4 50% MC-9400A PACKAGE DRAWING (unit : mm) COB with radiation board attached + FPC module 15 10 101.4 5 2-10 1.5 33.0 63 1.25 MC-9400A C2 10.95 35.05 35.05 10.95 C2 7 MAX. 92.0 13 MC-9400A [MEMO] 14 MC-9400A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 15 MC-9400A No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC’s Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5