TI DRV8800

DRV8800
DRV8801
www.ti.com ............................................................................................................................................................... SLVS855A – JULY 2008 – REVISED JULY 2008
DMOS FULL-BRIDGE MOTOR DRIVERS
•
•
FEATURES
1
•
•
•
•
•
•
•
•
2
Low ON-Resistance [Rds(ON)] Outputs
Overcurrent Protection
Motor Lead Short-to-Supply Protection
Short-to-Ground Protection
Low-Power Mode
Synchronous Rectification
Diagnostic Output
Internal Undervoltage Lockout (UVLO)
Crossover-Current Protection
16-Pin QFN With PowerPAD™ Package
APPLICATIONS
•
•
Printers
Industrial Automation
DESCRIPTION/ORDERING INFORMATION
Designed to control dc motors by using pulse width modulation (PWM), the DRV8800/DRV8801 is capable of
peak output currents up to ±2.8 A and operating voltages up to 36 V.
The PHASE and ENABLE inputs provide dc motor speed and direction control by applying external pulse-width
modulation (PWM) and control signals. Internal synchronous rectification control circuitry provides lower power
dissipation during PWM operation.
Internal circuit protection includes motor lead short-to-supply/short-to-ground, thermal shutdown with hysteresis,
undervoltage monitoring of VBB and VCP, and crossover-current protection.
The DRV8800/DRV8801 is supplied in a thin-profile 16-pin QFN (RTY) PowerPAD™ package, providing
enhanced thermal dissipation. The devices are lead free (Pb free).
ORDERING INFORMATION
TA
–20°C to 80°C
(1)
(2)
PACKAGE
(1) (2)
Plastic QFN 16 (S-PQFP-16) – RTY
ORDERABLE PART NUMBER
TOP-SIDE MARKING
DRV8800RTYR
DRV8800A0RTY
DRV8800RTYT
DRV8800A0RTY
DRV8801RTYR
DRV8801A0RTY
DRV8801RTYT
DRV8801A0RTY
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
DRV8800
DRV8801
SLVS855A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
DRV8801
RTY PACKAGE
(TOP VIEW)
nFAULT
VPROPI
VCP
14
13
VCP
13
15
VREG
14
MODE 1
nFAULT
15
16
MODE
16
DRV8800
RTY PACKAGE
(TOP VIEW)
CP2
nSLEEP
3
10
CP1
nSLEEP
3
10
CP1
ENABLE
4
9
OUT–
ENABLE
4
9
OUT–
MODE 2
8
11
VBB
2
7
GND
SENSE
CP2
6
11
OUT+
2
5
GND
8
GND
VBB
12
7
1
SENSE
PHASE
6
GND
OUT+
12
5
1
NC
PHASE
NC – Do not connect
TERMINAL FUNCTIONS
TERMINAL
NO.
2
NAME
DRV8800
DESCRIPTION
DRV8801
1
PHASE
PHASE
Phase logic input for direction control
2
GND
GND
Ground
3
nSLEEP
nSLEEP
Sleep logic input
4
ENABLE
ENABLE
Enable logic input
5
NC
MODE 2
No connect (DRV8800), Mode 2 logic input (DRV8801)
6
OUTA
OUTA
DMOS full-bridge output A
7
SENSE
SENSE
Sense power return
8
VBB
VBB
Load supply voltage
9
OUTB
OUTB
DMOS full-bridge output B
10
CP1
CP1
Charge-pump capacitor 1
11
CP2
CP2
Charge-pump capacitor 2
12
GND
GND
Ground
13
VCP
VCP
Reservoir capacitor
14
VREG
VPROPI
Regulated voltage (DRV8800), Winding current proportional voltage output (DRV8801)
15
nFAULT
nFAULT
Fault open-drain output
16
MODE
MODE 1
Mode logic input
PowerPAD
PowerPAD
Exposed pad for thermal dissipation connect to GND pins
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV8800 DRV8801
DRV8800
DRV8801
www.ti.com ............................................................................................................................................................... SLVS855A – JULY 2008 – REVISED JULY 2008
DRV8800 TYPICAL APPLICATION DIAGRAM
VDD
(Optional) VREG may be left disconnected
3.3K
.1 uf
50V
VCP
VREG
nFAULT
MODE
VDD
VBB
.22 uf
25V
3.3K
PHASE
GND
GND
CP2
.1 uf
50V
DRV8800
M
RSENSE
VBB
OUT-
SENSE
ENABLE
OUT+
CP1
NC
nSLEEP
.1 uf
50V
100 uf
50V
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3
DRV8800
DRV8801
SLVS855A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
DRV8801 TYPICAL APPLICATION DIAGRAM
100K
VDD
ANA_VPROPI
VBB
VDD
3.3K
.1 uf
50V
1000 pf
VCP
VPROPI
nFAULT
MODE 1
3.3K
PHASE
GND
GND
CP2
.1 uf
50V
DRV8801
4
M
RSENSE
VBB
OUT-
SENSE
ENABLE
OUT+
CP1
MODE 2
nSLEEP
.1 uf
50V
100 uf
50V
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV8800 DRV8801
DRV8800
DRV8801
www.ti.com ............................................................................................................................................................... SLVS855A – JULY 2008 – REVISED JULY 2008
DRV8800 FUNCTIONAL BLOCK DIAGRAM
.1 uf
CP1
CP2
VBB
VCP
.1 uf
Charge Pump
VREG
Optional
VBB
Low-Side
Gate Supply
.22 uf
Bias
Supply
MODE
100 uf
PHASE
.1 uf
OUT+
M
ENABLE
VDD
Control
Logic
OUT-
3.3K
3.3K
nSLEEP
SENSE
nFAULT
UVLO
STB
Motor lead
Protection
STG
TSD
VBB
OUTA
OUTB
SENSE
GND
GND
PAD
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5
DRV8800
DRV8801
SLVS855A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
DRV8801 FUNCTIONAL BLOCK DIAGRAM
.1 uf
VPROPI
X5
CP1
CP2
VBB
SENSE
VCP
.1 uf
Charge Pump
MODE 1
VBB
Bias
Supply
MODE 2
PHASE
100 uf
.1 uf
OUT+
M
Control
Logic
ENABLE
VDD
OUT3.3K
3.3K
nSLEEP
SENSE
nFAULT
UVLO
STB
Motor lead
Protection
STG
TSD
VBB
OUTA
OUTB
SENSE
GND
GND
PAD
6
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Product Folder Link(s): DRV8800 DRV8801
DRV8800
DRV8801
www.ti.com ............................................................................................................................................................... SLVS855A – JULY 2008 – REVISED JULY 2008
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
VBB
VSense
VDD
V
Output current
2.8
A
Sense voltage
±500
36
V
OUTx to SENSE
36
V
(2)
–0.3
Human-Body Model (HBM)
Charged-Device Model (CDM)
Continuous total power dissipation
Operating free-air temperature range
TJ
Maximum junction temperature
Tstg
Storage temperature range
(2)
mV
VBB to OUTx
TA
(1)
UNIT
40
Logic input voltage
ESD rating
MAX
Load supply voltage (2)
7
V
±2
kV
500
V
See Dissipation Rating Table
–20
–40
80
°C
190
°C
125
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
PACKAGE
θJA
TA = 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
RTY
41.6
3W
24 mW/C
RECOMMENDED OPERATING CONDITIONS
VIN
Input voltage, VBB
TA
Operating free-air temperature
MIN
NOM
MAX
8
32
38
V
–20
25
80
°C
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UNIT
7
DRV8800
DRV8801
SLVS855A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fPWM < 50 kHz
IBB
Motor supply current
TYP
Charge pump on, Outputs disabled
VIL
VIH
VIL
IIH
IIL
IIH
IIL
IIH
IIL
0.8
2.7
nSLEEP input voltage
PHASE, MODE input current 1
ENABLE input current
nSLEEP input current
0.8
VIN = 2 V
20
VIN = 2 V
40
100
VIN = 0.8 V
16
40
VIN = 2.7 V
27
50
VIN = 0.8 V
<1
10
0.4
V
12
13.8
V
mV
Isink = 1 mA
VBB nFAULT release
8 V < VBB < 40 V
VIHys
Input hysteresis, except nSLEEP
RSENSE/ISense voltage trip
Vf
Body diode forward voltage 1
tpd
Propagation delay time
tCOD
Crossover delay
DAGain
Differential AMP gain
V
≤–2.0
VIN = 0.8 V
nFAULT output voltage
VTRP
V
20
VBBNFR
Output ON resistance
µA
<1.0
VOL
Rds(ON)
10
2
PHASE, ENABLE,
MODE input voltage
UNIT
mA
3.2
Sleep mode
VIH
MAX
6
–20
500
800
Source driver, IOUT = –2.8 A, TJ = 25°C
100
0.35
0.48
Source driver, IOUT = –2.8 A, TJ = 125°C
0.55
0.8
0.3
0.43
Sink driver, IOUT = 2.8 A, TJ = 125°C
0.45
0.7
SENSE connected to ground through some
resistance
500
Sink driver, IOUT = 2.8 A, TJ = 25°C
1.4
Sink diode, If = 2.8 A
1.4
600
PWM, Change to source or sink OFF
100
Sense = 0.1 V to 0.4 V
µA
µA
Ω
mV
Source diode, If = –2.8 A
PWM, Change to source or sink ON
µA
V
ns
500
ns
5
V/V
Protection Circuitry
VUV
UVLO threshold
IOCP
Overcurrent threshold 2
tOCP
Overcurrent protection period
TJW
Thermal warning temperature
Temperature increasing
TJWHys
Thermal warning hysteresis
Recovery = TJW – TJWHys
TJTSD
Thermal shutdown temperature
Temperature increasing
TJTSDHys Thermal shutdown hysteresis
8
VBB increasing
6.5
3
Recovery = TJTSD – TJTSDHys
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8
V
A
1.2
ms
160
°C
15
°C
175
°C
15
°C
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV8800 DRV8801
DRV8800
DRV8801
www.ti.com ............................................................................................................................................................... SLVS855A – JULY 2008 – REVISED JULY 2008
SLEEP
ENABLE
PHASE
MODE
VBB
VOUTA
0
VBB
VOUTB
0
IOUTX
0
A
1
2
3
4
5
6
7
VIN
1
8
9
VIN
5
6
7
OUTA
OUTB
2
OUTA
4
3
OUTB
8
9
A
Charge Pump and VREG power on delay (~200 us)
Figure 1. PWM Control Timing
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9
DRV8800
DRV8801
SLVS855A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
VOUTA
VOUTB High-Z
IPEAK
IOUTx
IOCP
Enable,
Source
or Sink
BLANK
Charge Pump
Counter
tBLANK
tOCP
NFAULT
Motor Lead
Short Condition
Normal DC
Motor Capacitance
Figure 2. Overcurrent Control Timing
FUNCTIONAL DESCRIPTION
Device Operation
The DRV8800/DRV8801 is designed to drive one dc motor. The current through the output full-bridge switches
and all N-channel DMOS are regulated with a fixed off-time PWM control circuit.
Logic Inputs
It is recommended to use a high-value pullup resistor when logic inputs are pulled up to VDD. This resistor limits
the current to the input in case an overvoltage event occurs. Logic inputs are nSLEEP, MODE, PHASE, and
ENABLE. Voltages higher than 7 V on any logic input can cause damage to the input structure.
VREG (DRV8800 Only)
This output represents a measurement of the internal regulator voltage. This pin should be left disconnected. A
voltage of approximately 7.5 V can be measured at this pin.
VPROPI (DRV8801 Only)
This output offers an analog voltage proportional to the winding current. Voltage at this terminal is five times
greater than the motor winding current (VPROPI = 5×I). VPROPI is meaningful only if there is a resistor
connected to the SENSE pin. If SENSE is connected to ground, VPROPI measures 0 V. During slow decay,
VPROPI outputs 0 V. VPROPI can output a maximum of 2.5 V, since at 500 mV on SENSE, the H-bridge is
disabled.
10
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DRV8800
DRV8801
www.ti.com ............................................................................................................................................................... SLVS855A – JULY 2008 – REVISED JULY 2008
Charge Pump
The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-µF
ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-µF
ceramic monolithic capacitor, CStorage, should be connected between VCP and VBB to act as a reservoir to run
the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition,
the outputs of the device are disabled.
Shutdown
As a measure to protect the device, faults caused by very high junction temperatures or low voltage on VCP
disable the outputs of the device until the fault condition is removed. At power on, the UVLO circuit disables the
drivers.
Low-Power Mode
Control input nSLEEP is used to minimize power consumption when the DRV8800/DRV8801 is not in use. This
disables much of the internal circuitry, including the internal voltage rails and charge pump. nSLEEP is asserted
low. A logic high on this input pin results in normal operation. When switching from low to high, the user should
allow a 1-ms delay before applying PWM signals. This time is needed for the charge pump to stabilize.
• MODE 1 (MODE on the DRV8800)
Input MODE 1 is used to toggle between fast-decay mode and slow-decay mode. A logic high puts the device
in slow-decay mode.
• MODE 2 (DRV8801 only)
MODE 2 is used to select which set of drivers (high side versus low side) is used during the slow-decay
recirculation. MODE 2 is meaningful only when MODE 1 is asserted high. A logic high on MODE 2 has
current recirculation through the high-side drivers. A logic low has current recirculation through the low-side
drivers.
Braking
The braking function is implemented by driving the device in slow-decay mode (MODE 1 pin is high) and
deasserting the enable to low. Because it is possible to drive current in both directions through the DMOS
switches, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode
is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to ensure that the
maximum ratings of the device are not exceeded in worse-case braking situations – high-speed and high-inertia
loads.
Diagnostic Output
The nFAULT pin signals a problem with the chip via an open-drain output. A motor fault, undervoltage condition,
or TJ > 160°C drives the pin active low. This output is not valid when nSLEEP puts the device into minimum
power dissipation mode (i.e., nSLEEP is low). nFAULT stays asserted (nFAULT = L) until VBB reaches VBBNFR
to give the charge pump headroom to reach its undervoltage threshold. nFAULT is a status-only signal and does
not affect any device functionality. The H-bridge portion still operates normally down to VBB = 8 V with nFAULT
asserted.
Thermal Shutdown (TSD)
Two die-temperature monitors are integrated on the chip. As die temperature increases toward the maximum, a
thermal warning signal is triggered at 160°C. This fault drives the nFAULT low, but does not disable the
operation of the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs are
disabled until the internal temperature falls below a hysteresis of 15°C.
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11
DRV8800
DRV8801
SLVS855A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
Control Logic Table (1)
PINS
(1)
(2)
OPERATION
PHASE
ENABLE
MODE 1
MODE 2
nSLEEP
OUTA
OUTB
1
1
X
X
1
H
L
Forward
0
1
X
X
1
L
H
Reverse
X
0
1
0
1
L
L
Brake (slow decay)
1
0
0
1
1
L
H
Fast-decay synchronous
rectification (2)
0
0
0
X
1
H
L
Fast-decay synchronous
rectification (2)
X
X
X
X
0
Z
Z
Sleep mode
X = Don’t care, Z = high impedance
To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high-impedance state as the current
approaches 0 A.
Overcurrent Protection
The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not
shorted to supply or ground. If a short is detected, the full-bridge outputs are turned off, flag nFAULT is driven
low, and a 1.2-ms fault timer is started. After this 1.2-ms period, tOCP , the device is then allowed to follow the
input commands and another turnon is attempted (nFAULT becomes high again during this attempt). If there is
still a fault condition, the cycle repeats. If after tOCP expires it is determined the short condition is not present,
normal operation resumes and nFAULT is deasserted.
12
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Product Folder Link(s): DRV8800 DRV8801
DRV8800
DRV8801
www.ti.com ............................................................................................................................................................... SLVS855A – JULY 2008 – REVISED JULY 2008
APPLICATION INFORMATION
Power Dissipation
First-order approximation of power dissipation in the DRV8800/DRV8801 can be calculated by examining the
power dissipation in the full-bridge during each of the operation modes. DRV8800/DRV8801 utilize synchronous
rectification. During the decay cycle, the body diode is shorted by the low-Rds(ON) driver, which in turn reduces
power dissipation in the full-bridge. In order to prevent shoot through (high-side and low-side drivers on the same
side are ON at the same time), DRV8800/DRV8801 implement a 500-ns typical crossover delay time. During this
period, the body diode in the decay current path conducts the current until the DMOS driver turns on. High
current and high ambient temperature applications should take this into consideration. In addition, motor
parameters and switching losses can add power dissipation that could affect critical applications.
Drive Current
This current path is through the high-side sourcing DMOS driver, motor winding, and low-side sinking DMOS
driver. Power dissipation I2R loses in one source and one sink DMOS driver, as shown in Equation 1.
2
PD = I (RDS(on)Source + RDS(onSink))
(1)
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13
DRV8800
DRV8801
SLVS855A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
DRV8800
VBB
1
3
2
1 Drive Current
2 Fast decay with synchronous rectification (reverse)
3 Slow decay with synchronous rectification (brake)
DRV8801
VBB
4
1
3
2
1
Drive Current
2
Fast decay with synchronous rectification (reverse)
3
Slow decay with synchronous rectification (brake) Low Side
4
Slow decay with synchronous rectification (brake) High Side
Figure 3. Current Path
Fast Decay With Synchronous Rectification
This decay mode is equivalent to a phase change where the opposite drivers are switched on. When in fast
decay, the motor current is not allowed to go negative (direction change). Instead, as the current approaches
zero, the drivers turn off. The power calculation is the same as the drive current calculation (see Equation 1).
14
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Product Folder Link(s): DRV8800 DRV8801
DRV8800
DRV8801
www.ti.com ............................................................................................................................................................... SLVS855A – JULY 2008 – REVISED JULY 2008
Slow-Decay SR (Brake Mode)
In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the H-bridge’s
low side (two sink drivers) and the load. Power dissipation I2R loses in the two sink DMOS drivers:
2
PD = I (2 ´ RDS(on)Sink)
(2)
SENSE
A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes. To
minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor should have an
independent ground return to the star ground point. This trace should be as short as possible. For low-value
sense resistors, the IR drops in the PCB can be significant, and should be taken into account.
NOTE:
When selecting a value for the sense resistor, SENSE does not exceed the maximum
voltage of ±500 mV. The H-bridge is disabled and enters recirculation while motor
winding current is above a SENSE voltage equal or greater than 500 mV.
Ground
A ground power plane should be located as close to the DRV8800/DRV8801 as possible. The copper ground
plane directly under the PowerPAD package makes a good location. This pad can then be connected to ground
for this purpose.
Layout
The printed circuit board (PCB) should use a heavy ground plane. For optimum electrical and thermal
performance, the DRV8800/DRV8801 must be soldered directly onto the board. On the underside of the
DRV8800/DRV8801 is a PowerPAD package, which provides a path for enhanced thermal dissipation. The
thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer
heat to other layers of the PCB. For more information on this technique, please refer to document SLMA002.
The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 µF) in parallel with a
ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB,
connected to VREG, and between CP1 and CP2 should be as close to the pins of the device as possible, in
order to minimize lead inductance.
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Product Folder Link(s): DRV8800 DRV8801
15
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DRV8800RTYR
ACTIVE
QFN
RTY
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DRV8800RTYT
ACTIVE
QFN
RTY
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DRV8801RTYR
ACTIVE
QFN
RTY
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DRV8801RTYT
ACTIVE
QFN
RTY
16
250
CU NIPDAU
Level-3-260C-168 HR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DRV8800RTYR
QFN
RTY
16
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
4.3
4.3
1.5
8.0
12.0
Q1
DRV8800RTYT
QFN
RTY
16
250
180.0
12.4
4.3
4.3
1.5
8.0
12.0
Q1
DRV8801RTYR
QFN
RTY
16
3000
330.0
12.4
4.3
4.3
1.5
8.0
12.0
Q1
DRV8801RTYT
QFN
RTY
16
250
180.0
12.4
4.3
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8800RTYR
QFN
RTY
16
3000
346.0
346.0
29.0
DRV8800RTYT
QFN
RTY
16
250
190.5
212.7
31.8
DRV8801RTYR
QFN
RTY
16
3000
346.0
346.0
29.0
DRV8801RTYT
QFN
RTY
16
250
190.5
212.7
31.8
Pack Materials-Page 2
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