DATA SHEET MOS INTEGRATED CIRCUIT µ PD16340 96-BIT AC-PDP DRIVER DESCRIPTION The µ PD16340 is a high withstand voltage CMOS driver designed for use with a flat display panel such as a PDP, VFD, or EL panel. It consists of a 96-bit bi-directional shift register, 96-bit latch and high withstand voltage CMOS driver. The logic block operates with a 5-V power supply interface (CMOS level input) so that it can be directly connected to a gate array and microcontroller. The driver block provides a high withstand voltage output: 80 V, +50/– 75 mA MAX. The logic and driver blocks are made of CMOS circuits, consuming lower power. FEATURES • Circuit configuration switched by the IBS pin between three 32-bit bi-directional shift registers and six 16-bit bidirectional shift registers. • Data control with transfer clock (external) and latch • High-speed data transfer (fMAX. = 40 MHz MIN. at data latch) (fMAX. = 25 MHz MIN. at cascade connection) • High withstand output voltage (80 V, +50/–75 mA MAX.) • 5-V CMOS input interface • High withstand voltage CMOS structure • ORDERING INFORMATION Part Number Package µ PD16340 Module Caution Consult an NEC sales representative regarding the module. Since the module characteristics is based on the module specifications, there may be differences between the contents written in this document and real characteristics. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13685EJ1V0DS00 (1st edition) Date Published December 1999 NS CP (K) Printed in Japan The mark • shows major revised points. © 1998,1999 µ PD16340 BLOCK DIAGRAM 1 (IBS = H, 3-BIT INPUT, 32-BIT LENGTH SHIFT REGISTER) HZ /LBLK /HBLK VDD2 /LE SR1Note A1 A1 S1 S4 CLK CLK R,/L R,/L B1 LE S1 S2 S3 /L1 O1 VSS2 B1 CLR S94 /CLR SR2Note A2 A2 S2 CLK S5 R,/L B2 B2 CLR S95 SR3Note A3 A3 S3 VDD2 S6 CLK R,/L B3 B3 CLR S96 S94 S95 S96 /L96 O96 VSS2 Note SRn: 32-bit shift register Remark /xxx indicates active low signal. 2 Data Sheet S13685EJ1V0DS00 µ PD16340 BLOCK DIAGRAM 2 (IBS = L, 6-BIT INPUT, 16-BIT LENGTH SHIFT REGISTER) HZ /LBLK /HBLK VDD2 /LE A1 CLK R,/L B1 /CLR A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 SR1Note A1 S1 S7 CLK R,/L S91 B1 CLR SR2Note A2 S2 S8 CLK R,/L B2 CLR S92 S1 LE S2 /L1 S3 S4 S5 S6 O1 VSS2 SR3Note A3 S3 S9 CLK R,/L B3 CLR S93 SR4Note A4 S4 S10 CLK R,/L B4 CLR S94 SR5Note A5 S5 S11 CLK R,/L B5 CLR S95 SR6Note A6 S6 S12 CLK R,/L B6 CLR S96 VDD2 S93 S94 S95 S96 /L96 O96 VSS2 Note SRn: 16-bit shift register Data Sheet S13685EJ1V0DS00 3 µ PD16340 PIN FUNCTIONS Symbol Pin Name Description /LBLK Low blanking input /LBLK = L : All output = L /HBLK High blanking input /HBLK = L : All output = H /LE Latch enable input Latch on a falling edge HZ Output high impedance H: All output set to the high-impedance state /CLR Register clear input A1-A3(6) L: All shift register data cleared to the L level RIGHT data input/output Note R,/L = H, the parenthesized pins are used in 6-bit input mode. A1-A3(6) : Input, B1-B3(6) : Output B1-B3(6) LEFT data input/output Note R,/L = L, the parenthesized pins are used in 6-bit input mode. A1-A3(6) : Output, B1-B3(6) : Input CLK Clock input Shift on a rising edge R,/L Shift control input H: Right shift mode SR1 : A1 → S1.......S94 → B1 (SR2 and SR3 also shift in the same direction.) Left shift mode SR1 : B1 → S94.......S1 → A1 (SR2 and SR6 also shift in the same direction.) IBS Input mode switch H: 32-bit shift registers, 3-bit input mode L: 16-bit shift registers, 6-bit input mode O1 to O96 High withstand voltage output 80 V, +50/–75 mA MAX. VDD1 Logic power supply 5 V ± 10 % VDD2 Driver power supply 10 to 70 V VSS1 Logic ground Connect to system ground VSS2 Driver ground Connect to system ground Note In 3-bit input mode, unused I/O pins must be held at the L level. To use for module, the back side of IC chip must be held at the VSS (GND) level. 4 Data Sheet S13685EJ1V0DS00 µ PD16340 TRUTH TABLE Shift Register Block Input Output Shift Register R,/L CLK H ↑ H A B Output H or L ↑ L L Note1 Right shift operation performed Input Output Output Hold Note2 Left shift operation performed Input H or L Output Hold Notes 1. On the rising edge of the clock, the data of S91-S93 (S85-S90) is shifted to S94-S96 (S91-S96), and is output from B1-B3 (B1-B6) (The parenthesized pins are used in 6-bit input mode.). 2. On the rising edge of the clock, the data of S4-S6 (S7-S12) is shifted to S1-S3 (S1-S6), and is output from A1-A3 (A1-A6) (The parenthesized pins are used in 6-bit input mode.). Latch Block /LE Output State of Latch Section (/Ln) ↓ Latch Sn data H or L Hold latch (output) data Driver Block A (B) /HBLK /LBLK HZ Output State of Driver Block x L H L All driver output : H x x L L All driver output : L x x x H All driver output : High Impedance L H H L L H H H L H Remark x : H or L, H : High level, L : Low level Data Sheet S13685EJ1V0DS00 5 µ PD16340 TIMING CHART 1 (IBS = H, 3-BIT INPUT, RIGHT SHIFT) /CLR CLK A1 (B3) A2 (B2) A3 (B1) S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91) /LE (Latch on falling edge) /HBLK /LBLK HZ High-impedance O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91) Remark 6 Values in parentheses are when R,/L = L. Data Sheet S13685EJ1V0DS00 µ PD16340 TIMING CHART 2 (IBS = L, 6-BIT INPUT, RIGHT SHIFT) /CLR CLK A1 (B6) A2 (B5) A3 (B4) A4 (B3) A5 (B2) A6 (B1) S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91) S7 (S90) /LE (Latch on falling edge) /HBLK /LBLK HZ High-impedance O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91) O7 (O90) Remark Values in parentheses are when R,/L = L. Data Sheet S13685EJ1V0DS00 7 µ PD16340 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C, VSS1 = VSS2 = 0 V) Parameter Symbol Ratings Unit Logic Supply Voltage VDD1 –0.5 to +6.0 V Driver Supply Voltage VDD2 –0.5 to +80 V Logic Input Voltage VI –0.5 to VDD1 + 0.5 V Driver Output Current IO2 +50 / –75 mA Operating Junction Temperature TJ +125 °C Storage Temperature Tstg –65 to +150 °C Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range (TA = −40 to +85 °C, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 5.0 5.5 V Logic Supply Voltage VDD1 4.5 Driver Supply Voltage VDD2 15 70 V High-Level Input Voltage VIH 0.7 VDD1 VDD1 V Low-Level Input Voltage VIL 0 0.2 VDD1 V Driver Output Current IOH2 –60 mA IOL2 +40 mA 8 Data Sheet S13685EJ1V0DS00 µ PD16340 Electrical Characteristics (TA = 25 °C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V) Parameter Conditions MIN. TYP. MAX. Unit 0.9 VDD1 VDD1 V 0.1 VDD1 V High-Level Output Voltage VOH1 Logic, IOH1 = –1.0 mA Low-Level Output Voltage VOL1 Logic, IOL1 = 1.0 mA 0 High-Level Output Voltage VOH21 O1 to O96, IOH2 = –1.3 mA 69 V VOH22 O1 to O96, IOH2 = –13 mA 65 V VOL21 O1 to O96, IOL2 = 5 mA 1.0 V VOL22 O1 to O96, IOL2 = 40 mA 10 V ±1.0 µA Low-Level Output Voltage • Symbol Input Leakage Current IIL High-Level Intput Voltage VIH Low-Level Input Voltage VIL Static Current Dissipation IDD1 • IDD2 V1 = VDD1 or VSS1 0.7 VDD1 V 0.2 VDD1 V Logic, TA = –40 to +85 °C 500 µA Logic, TA = 25 °C 300 µA Driver, TA = –40 to +85 °C 1000 µA Driver, TA = 25 °C 100 µA Data Sheet S13685EJ1V0DS00 9 µ PD16340 Switching Characteristics (TA = 25 °C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V, Logic CL = 15 pF, Driver CL = 50 pF, tr = tf = 6.0 ns) Parameter Propagation Delay Time Symbol MAX. Unit 34 ns 34 ns 180 ns 180 ns 165 ns 165 ns 160 ns 160 ns 300 ns tPZH 180 ns tPLZ 300 ns tPZL 180 ns 120 ns tPHL1 Conditions MIN. CLK ↑ → A/B tPLH1 tPHL2 /LE ↓ → O1 to O96 tPLH2 tPHL3 /HBLK → O1 to O96 tPLH3 tPHL4 /LBLK → O1 to O96 tPLH4 tPHZ Rise Time HZ → O1 to O96, RL = 10 kΩ tTLH O1 to O96 tTLZ O1 to O96, RL = 10 kΩ tTZH Fall Time tTHL O1 to O96 tTHZ O1 to O96, RL = 10 kΩ tTZL Maximum Clock Frequency Input Capacitance 10 fMAX. TYP. 3 µs 120 ns 150 ns 3 µs 150 ns Data latch, duty = 50 % 40 MHz Cascade connection,Duty = 50 % 25 MHz CI 15 Data Sheet S13685EJ1V0DS00 pF µ PD16340 Timing Requirement (TA = –40 to +85 °C, VDD1 = 4.5 to 5.5 V, VSS1 = VSS2 = 0 V, tr = tf = 6.0 ns) Parameter Clock Pulse Width Symbol Conditions PWCLK(H) MIN. TYP. MAX. Unit 12 ns 12 ns PWCLK(L) Latch Enable Pulse Width PW/LE(H) PW/LE(L) • Blank Pulse Width PW/BLK /HBLK, /LBLK 200 ns HZ Pulse Width PWHZ RL = 10 kΩ 3.3 µs /CLR Pulse Width PW/CLR 12 ns Data Setup Time tSETUP 4 ns Data Hold Time tHOLD 6 ns Latch Enable Time t/LE1 12 ns t/LE2 12 ns t/CLR 6 ns /CLR Timing Data Sheet S13685EJ1V0DS00 11 µ PD16340 Switching Characteristics Waveform (1/3) 1/fMAX. PWCLK (H) PWCLK (L) VDD1 50% 50% 50% CLK VSS1 tSETUP An,Bn (Input) tHOLD VDD1 50% 50% VSS1 tPHL1 tPLH1 VOH1 Bn,An (Output) 50% 50% VOL1 VDD1 /LE 50% 50% VSS1 PW/LE (H) PW/LE (L) t/LE1 t/LE2 VDD1 50% 50% CLK VSS1 tTHL tPHL2 VOH2 90% On 10% tTLH tPLH2 90% 10% On 12 Data Sheet S13685EJ1V0DS00 VOL2 VOH2 VOL2 µ PD16340 • Switching Characteristics Waveform (2/3) PW/BLK VDD1 /LBLK 50% 50% VSS1 tPHL4 tPLH4 VOH2 90% On 10% VOL2 PW/BLK VDD1 /HBLK 50% 50% VSS1 tPHL3 tPLH3 VOH2 90% On 10% VOL2 PW/CLR VDD1 50% 50% /CLR VSS1 t/CLR VOH2 50% CLK VOL2 Clock rising edge for valid data Data Sheet S13685EJ1V0DS00 13 µ PD16340 Switching Characteristics Waveform (3/3) PWHZ VDD1 HZ 50% 50% VSS1 tPLZ tPZL tTLZ tTZL VO(H) 90% 90% On 10% 10% VOL2 VOH2 90% 90% On 10% tPHZ 14 tTHZ Data Sheet S13685EJ1V0DS00 10% tPZH VO(L) tTZH µ PD16340 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S13685EJ1V0DS00 15 µ PD16340 Reference Documents NEC Semiconductor Device Reliability/Quality Control System(C10983E) Quality Grades to NEC’s Semiconductor Devices(C11531E) • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8