DATA SHEET MOS INTEGRATED CIRCUIT µPD16454A The µPD16454A is a single-chip controller/driver for dot matrix LCD, enabling the display of up to 48 alphanumerical and kana characters and symbols (24 characters × 2 lines) each of which is composed of 5 × 7 dots. On-chip charge pump-type DC/DC converter that enables the µPD16454A to operate on a single 5-V power supply and the chip design aiming at tape carrier package (TCP) mounting make the µPD16454A ideal for portable equipment and all kinds of data terminals for which downsizing is an important consideration. FEATURES • 5 × 7 dot matrix LCD display controller/driver • 24 characters × 2 lines, 1/14 duty display • Interface with CPU 4 bits wise • On-chip ROM and RAM • Display data RAM (8 × 48 bits) • Character generator RAM (8 user-defined characters; 5 × 7 × 8 bits) • Character generator ROM (160 characters; 5 × 7 × 160 bits) • On-chip LCD driver • 120 segment signals • 14 common signals • Single 5-V power supply • Doubling DC/DC booster generating 10 V for driving LCDs • Total power dissipation: 2 mA max. • On-chip temperature compensation circuit • TCP mounting enabled ORDERING INFORMATION Part number Available as µPD16454AN-XXX TCP (TAB) µPD16454AP Chip TPC formats are created on a custom-made basis. For additional information, contact an NEC sales representative. For purchases of chips only, additional documents on quality are required. Contact an NEC sales representative. Document No. IC-3362A (2nd edition) (0. D. No. IC-8800) Date Published March 1997 P Printed in Japan © 1994 Timing circuit 6 6 Instruction register (IR) 8 8 6 6 Instruction decoder BLOCK DIAGRAM 2 Address counter (AC) 3 Disply data RAM (DDRAM) 8 × 48 bits 14-bit shift register 14 CLK Common signal driver COM1 14 COM14 RS E DB0 to DB3 8 4 I/O buffer 8 8 8 Data register (DR) RESET 8 6 8 8 3 3 TEST Character generator RAM (CGRAM) 5 × 7 × 8 bits BF Busy flag C (+) C (−) 120 Segment signal driver SEG1 120 SEG120 120 DC/DC converter 5 Serializer (parallel data → serial data) 5 120-bit shift register OP amp. VIN (+) VIN (−) V1 V2 V3 V4 V5 µPD16454A VDD VCC1 VCC2 GND1 GND2 12-bit latch Character generator ROM (CGROM) 5 × 7 × 160 bits µPD16454A PIN FUNCTION Symbol Pin No. Input/Output Connect to Function RS 138 Input CPU Register selection signal ‘0’ instruction register (IR) ‘1’ data register (DR) E 139 Input CPU Data reading signal TEST 140 Input BF 145 Output CPU When busy flag is ‘1’, indicates that internal part of LCD is currently operating. In test mode, functions as test output. DB0 to 3 141 to 144 Input/Output CPU Data input signals In test mode, function as output pin. RESET 137 Input CPU Reset is performed with reset signal ‘0’ CLK 146 Input CPU LCD-driving clock COM1 to 14 128 to 134, 7 to 1 Output LCD Common signals SEG1 to 120 127 to 68, 8 to 67 Output LCD Segment signal outputs Reads data at the falling edge. Test pin ‘1’ = test mode ‘0’ or open = normal operation V1 to 5 153 to 157 Power supply LCD-driving supply voltages VCC1 148 Power supply Power supply for logic circuits VCC2 136 Power supply Power supply for logic circuits VDD 135 Power supply Boosted power supply GND1 147 Power supply Ground for logic circuit GND2 158 Power supply Ground for high-voltage circuit VIN (+) 151 Power supply Reference voltage supply VIN (−) 152 C (+) 149 Capacitor Capacitor connection pin for booster C (−) 150 Capaditor Capacitor connection pin for booster LCD-driving supply voltage adjustment input 3 µPD16454A GND2 V5 V4 V3 V2 V1 VIN + VIN − C− C+ VCC1 GND1 CLK BF DB3 DB2 DB1 DB0 TEST E RS RESET VCC2 VDD PIN CONFIGURATION (Pad Configuration) COM14 158 1 135 134 COM7 COM8 SEG61 SEG62 COM1 SEG1 SEG2 4 68 SEG60 SEG59 SEG119 SEG120 67 µPD16454A BLOCK FUNCTIONS (1) Registers (IR, DR) This LCD contains both an 8-bit instruction register (IR) and an 8-bit data register (DR). The IR register stores display clear instruction codes and display data RAM (DDRAM) and character generaotor RAM (CGRAM) addresses. The DR register temporarily stores data to be transferred to DDRAM and CGRAM. The IR and DR registers are selected with the register selector (RS) bit. RS Register selector 0 IR 1 DR (2) Busy flag (BF) When BF = ‘1’, this indicates that the LCD’s internal circuit is currently operating. Therefore, after ascertaining that BF = ‘0’, it is necessary to read the next instruction or display data. (3) Address counter (AC) The AC is a counter that sets addresses in DDRAM and CGRAM. When an address-setting instruction is written to the IR, the address value is set from the IR to the address counter. At the same time, which of DDRAM and CGRAM is selected is also determined. After display data is written in DDRAM or CGRAM, the address counter’s address value is automatically incremented by 1. Nevertheless, since data in CGRAM consists of 7 bytes characters, the address value is incremented by 2 only when display data has been written to the 7th line. (4) Display data RAM (DDRAM) DDRAM is a RAM that stores display data consisting of 8-bit character codes. The capacity is 8 × 48 bits so that 48 characters can be stored. The correspondence between DDRAM addresses and display position on LCD is shown in Fig. 1. 5 µPD16454A Fig.1 Correspondence of DDRAM address and display position on LCD 1st digit 2 1st line 00 01 3 4 5 02 03 04 6 7 8 05 06 07 9 10 11 16 17 18 19 20 21 22 23 24 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 21 22 29 2A 2B 2C 2D 2E 2F 2nd line 18 19 1A 1B 1C 1D 1E 1F 20 12 23 13 14 24 25 15 26 27 28 DDRAM address (hexadecimal) (5) Character generator ROM (CGROM) CGROM is a ROM that generates 5 × 7-dot character patterns from 8-bit character codes, and can generate 160 different characters in total. The correspondence of CGROM addresses and character patterns to the ASCII code is shown in Fig.2. Fig.2 Correspondence of CGROM address data (character codes) and character patterns (00110010 → “2”) CGROM address A10 A9 A8 A7 A6 A5 A4 ROM output data A3 A2 Character code (DDRAM output data) 0 0 1 1 0 0 A1 04 03 02 01 00 Line position 1 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 1 0 1 1 1 1 1 Character code and character pattern correspondence is shown in Fig.3. 6 A0 µPD16454A Fig.3. Character Code and Character Pattern Correspondence Upper 4 bits Lower 4 bits XXXX0000 XXXX0001 XXXX0010 XXXX0011 XXXX0100 XXXX0101 XXXX0110 XXXX0111 XXXX1000 XXXX1001 XXXX1010 XXXX1011 XXXX1100 XXXX1101 XXXX1110 XXXX1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 CG RAM (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8) 7 µPD16454A (6) Character generator RAM (CGRAM) CGRAM is a RAM that the user can use to freely define character patterns. Eight types of 5 × 7-dot character pattern definitions are possible. The CGRAM address values (character codes) of A10 to A3 in Fig.2 are 00H to 17H (8 types). Other values (line position, output data, etc.) are the same as in Fig.2. (7) Timing circuit The timing circuit generates timing signals to activate internal circuits. Retrieve timing of RAM needed for display and internal operation timing through access from the CPU are performed on a time-share basis and thus do not interfere with each other. Therefore, to change display characters on the LCD panel, even if DDRAM has been accessed, characters other than those that have been accessed do not flicker. (8) LCD-related circuit The LCD driver circuit consists of 14 common signal drivers and 120 segment signal drivers. Each driver is automatically controlled by an internal control circuit, and outputs a driving waveform corresponding to the character pattern. Serial data is always sent from the character pattern of the display data corresponding to the last DDRAM address, and the character pattern of the display data corresponding to the first DDRAM address (00H) is latched when inpout in the 120-bit shift register. LCD display positions are shown in Fig.1 of section (4) Display data RAM (DDRAM). Interface with CPU (data transfer) This LSI interfaces (transfers data) with CPU in 4-bit units (DB0 to DB3), but the internal register circuits (IR and DR) have 8-bit paths, therefore making it necessary to transfer 4-bit data twice. Assuming that the 8 bits of data are numbered D0 to D7, this data is transferred in the following sequence: first the upper 4 bits (D4 to D7), then the lower 4 bits (D0 to D3). The busy flag check is performed before the upper 4 bits are transferred, and is not necessary before transferring the 4 lower bits. If data is transferred without checking BF, taking 10 CLK cycles or more is necessary between previous 8-bit data transfer and next transfer (CLK = 1/fc). 8 µPD16454A INSTRUCTIONS The instructions for this LSI are shown in Table 1 below. Table 1 Instruction List Code Instruction Description RS D7 D6 D5 D4 D3 D2 D1 D0 Display On/Off 0 0 0 0 0 1 D * * CGRAM Address Set 0 0 0 CGRAM address CGRAM address set. Transfer of subsequent data is of CGRAM. DDRAM Address Set 0 1 * DDRAM address DDRAM address set. Transfer of subsequent data is of DDRAM data. CGRAM/DDRAM Data Write 1 Remark Write data However, because CGRAM data occupies D0 to D4, D5 to D7 are ignored. Full display On/Off D : ‘1’ (ON), ‘0’ (OFF) Data is written in CGRAM or DDRAM. The internal address counter (AC) is automatically incremented by one following data write. * in the above table indicates that the value may be either 0 to 1. Initialization using the reset signal (RESET) When the reset signal (RESET) is activated (RESET = 0) for 10 CLK cycles (CLK = 1/fc) or more, initialization is performed as follows. (1) Display ON/OFF Set to OFF (D = 0) (2) DDRAM address set Set to DDRAM address 00H When data write is performed under this condition, data is written to DDRAM address 00H. 9 µPD16454A ABSOLUTE MAXIMUM RATINGS (Ta = +25 °C, GND1 = GND2 = 0 V) Parameter Symbol Ratings Unit Logic Supply Voltage VCC −0.3 to +7.0 V Driver Input Voltage VI −0.3 to VCC +0.3 V Logic Output Voltage VO1 −0.3 to VCC +0.3 V Driver Supply Voltage VDD −0.3 to +15 V V2 to V5 −0.3 to VDD +0.3 V Driver’s Driver Output Voltage V1 −0.3 to VDD +0.3 V Driver Output Voltage VO2 −0.3 to VDD +0.3 V Storage Temperature Tstg −40 to +125 °C Driver’s Driver Input Voltage RECOMMENDED OPERATING CONDITIONS Parameter Symbol MIN. TYP. MAX. Unit Logic Supply Voltage VCC 4.75 5 5.25 V Operating Ambient Temperature Topt −30 25 85 °C 10 µPD16454A DC CHARACTERISTICS (Ta = −30 to +85 °C, VCC = 5 V 5 ± 5%) Parameter Symbol Conditions High-Level Input Voltage 1 VIH1 Low-Level Input Voltage 1 VIL1 High-Level Input Voltage 2 VIH2 Low-Level Input Voltage 2 VIL2 Hysteresis voltage VH High-Level Output Voltage VOH IOH = −1 mA Low-Level Output Voltage VOL IOL = 1 mA High-Level Input Leak Current IIH1 High-Level Input Leak Current MIN. E, RESET, CLK, input excluded TYP. MAX. 0.7 VCC V 0.3 VCC E, RESET, CLK input Unit 0.8 VCC V V 0.2 VCC 0.1 V V 0.9 VDD V 0.1 VCC V TEST excluded, VIN = VCC 1 µA IIH2 TEST, VIN = VCC 6 mA Low-Level Input Lead Current IIL VIN = 0 V Common Output Impedance RCOM IO = 50 µA 1.5 58 kΩ Segment Output Impedance RSEG IO = 50 µA 1.5 76 kΩ 1 2 mA 2 VCC V Logic Supply Voltage (Total consumption) µA −1 R1 = 33 kΩ RP = 27 kΩ RB = 22 kΩ ICC fC = 250 kHz Driver Supply Voltage (Boosted voltage) VDD High-Level Output Voltage (V1 pin) VOH2 R1 = 33 kΩ RP = 27 kΩ RB = 22 kΩ External capacitor of 1 µF 1.9 VCC IOH = −1 mA V 0.9 VDD VIN (+) = VDD VIN (−) = 0 V Low-Level Output Voltage (V1 pin) IOL = 10 µA VOL2 0.1 VDD V VIN (+) = 0 V VIN (−) = VDD ∗ TYP. is reference value at Ta = +25 °C. + − VIN (−) VIN (+) V1 V2 RB V3 RB V5 V4 RB RB RB Rt +5 V R1 Rp Rt : Thermostat 11 µPD16454A AC CHARACTERISTICS (Ta = −30 to +85 °C, VCC = 5 V ± 5%) Parameter MIN. TYP. MAX. Unit fC 160 250 500 kHz Enable Cycle Time tCYCE 1 000 ns Enable Pulse Width PWE 450 ns RS • E Setup Time tRSES 100 ns RS • E Hold Time tRSEH 100 ns Data Setup Time tDS 100 ns Data Hold Time tDH 100 ns Operating Frequency Symbol Conditions ∗ TYP. is reference value at Ta = +25 °C. AC CHARACTERISTIC WAVEFORM Write Operation RS tRSES PWE tRSEH E tDH tDS DB0 to DB3 Valid Data tCYCE 12 µPD16454A OSCILLATION FREQUENCY and LCD FRAME FREQUENCY CORRESPONDENCE The correspondence between the oscillation frequency of 250 kHz and the LCD frame frequency is shown in Fig.4 below. Fig.4 Oscillation Frequency and LCD Frame Frequency Correspondence 120 Clocks 1 2 3 ∼ 14 1 2 3 ∼ 14 1 2 V1 V2 V3 COM1 V4 V5 GND2 1 frame = 4 µs × 120 × 14 = 6 720 µs = 6.72 ms Signal Display Mode + − COM Lit GND2 V1 Not lit V2 V5 Lit GND2 V1 Not lit V4 V3 SEG 13 µPD16454A MAX. 0.9 ,,,, 13.475 13.475 P0.5 = 0.01 × 48 = 24.0 ± 0.05 P0.4 ± 0.01 × 40 = 16.0 ± 0.035 W0.16 ± 0.03 1.42 ± 0.03 13.475 13.475 31.82 −0.07 +0.04 P0.5 = 0.01 × 48 = 24.0 ± 0.05 13.475 12.7 11.8 0.65 0.65 0.5 0.7 0.5 11.8 12.7 13.475 0.125 0.1 0.8 ± 0.015 3. This drawing is viewed from wire-patterned face. Test Pad and Alignment Pattern Details 0.6 ± 0.015 Note 1. Measurements between brackets are for referency only. 2. Non-specified tolerances are ± 0.05 mm. From center of tape P0.4 ± 0.01 × 40 = 16.0 ± 0.035 W0.16 ± 0.03 1.42 ± 0.03 4.75 (0.735) REFERENCE 1 : STANDARD TCP DRAWING (µPD16454AN-051) From center of tape 14 REFERENCE 2 : TCP SHIPPING RELL (φ 405 mm) A B C E W D W1 Symbol A W2 Size (mm) *:Tape width φ 405 ± 2.0 φ 105 C φ 25.9 ± 0.5 D φ 17.9 ± 0.5 E 50 +1.0 −0 W (35)* 37 ± 1.5 W (48)* 50 ± 1.5 W (70)* 72 ± 1.5 W1 3 ± 0.5 W2 W + 2W1 15 µPD16454A B µPD16454A [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. 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Anti-radioactive design is not implemented in this product. M4 96. 5