DATA SHEET MOS INTEGRATED CIRCUIT µ PD16655 240-OUTPUT TFT-LCD GATE DRIVER The µ PD16655 is a TFT-LCD gate driver equipped with 240-output lines. It can output a high-gate scanning voltage in response to 5 V/3.3 V CMOS level input because it provided with a level-shift circuit as a logic-input circuit. This gate driver is also provided with an output enable (OE) function, so that drivers can be installed at both sides. FEATURES • High-output voltage (VDD-VEE = amplitude: 31 V MAX.) • Shift-direction select function • Level shift of negative voltage VEE2(level shift range: VDD-VEE2 = 15 V) • 5 V/3.3 V CMOS level interface • Output enable function • As many as 240-output lines • Slim TCP ORDERING INFORMATION Part Number µ PD16655N-xxx Package TCP(TAB package) Remark The TCP’s external shape is custom model. To order your TCP’s external shape, please contact a NEC salesperson. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S11950EJ2V0DS00 (2nd edition) Date Published February 1999 NS CP(K) Printed in Japan The mark shows major revised points. © 1998 µ PD16655 1. BLOCK DIAGRAM R,/L LSNote CLK LSNote STVR LSNote OE LSNote 240-bit shift register SR1 SR2 SR3 SR238 SR239 SR240 LSNote VEE1 VEE2 O1 O2 O3 Note LS (level shifter): Shifts 5 V/3.3 V CMOS level and VDD2-VEE1 level. Remark /xxx indicates active low signal. 2 Data Sheet S11950EJ2V0DS00 O238 O239 O240 STVL µ PD16655 2. PIN CONFIGURATION (µ PD16655N-xxx) O240 O239 O238 VDD2 VDD1 STVL OE CLK R,/L Copper foil surface VCC VSS STVR VEE1 VEE2 O3 O2 O1 Remark This figure does not specify the TCP package. Data Sheet S11950EJ2V0DS00 3 µ PD16655 3. PIN FUNCTIONS SYMBOL PIN NAME O1 to O240 Driver Output STVR Start Pulse Input/Output I/O DESCRIPTION These pins output scan signals that drive the vertical direction (gate lines) of a TFT-LCD. The output signals change in synchronization with the rising edge of shift clock CLK. The driver output amplitude is VDD2 - VEE2. STVL VSS/VCC or VDD1/VEE1 (input) This is the input of the internal shift register. The input date is read at the rising edge of shift clock CLK, and scan signals are output from the O1 through O120 pins. The input level is a VCC/VSS or VDD1 - VEE1 level. VDD1/VEE1 (output) This pin outputs a start pulse to the µ PD16655 at the next stage when two or more µ PD16655s are connected in cascade. The pulse is output at the falling edge of the 240th clock of shift clock CLK, and is cleared at the falling edge of the 241st clock. R,/L Shift Direction Select Input VSS/VCC or VDD1/VEE1 R,/L = “H” (right shift): STVR → O1 → O240 → STVL R,/L = “L” (left shift): STVL → O240 → O1 → STVR CLK Shift Clock Input VSS/VCC This pin inputs a shift clock to the internal shift register. The shift operation is performed in synchronization with the rising edge of this input. OE Output Enable Input VSS/VCC When this pin goes “H”, the driver output is fixed to “L”. The shift register is not cleared, however. The internal logic operates even when OE = “H”. OE is in asynchronization with the clock. VDD1 Logic Positive Power Supply 10 V to 25 V VDD2 Driver Positive Power Supply 10 V to 25 V VCC Reference Positive Power Supply 3.0 to 5.5 V Reference voltage to level shifter LS. VSS Reference Negative Power Supply Connect this pin to the ground of the system. VEE1 Logic Negative Power Supply –21 V to –3 V VEE2 Driver Negative Power Supply –21 V to VDD2 – 15 V Cautions 1. To prevent latch up, turn on power to VCC, VEE1-VEE2, VDD1-VDD2, and logic input in this order. Turn off power in the reverse order. These power up/down sequence must be observed also during transition period. 2. Insert a capacitor of about 0.1 µ F between each power line, as shown below, to secure noise margin such as VIH and VIL, because the internal logic operates on a high voltage level. (VDD = VDD1 = VDD2) VDD VCC 0.1 F 0.1 F VSS 0.1 F VEE 4 Data Sheet S11950EJ2V0DS00 µ PD16655 3. In an application where the VEE power supply is not shifted, short-circuit VEE2 (driver power) and VEE1 (logic power) outside the TCP. Fix unused pins to the VEE level. 4. The level shift range of VEE2 must be VEE1 ≤ VEE2 ≤ VDD – 15 V. Note that, in this case, the guaranteed values of the output ON resistance and output fall time slightly change. (VDD = VDD1 = VDD2) 5. TIMING CHART 1 2 3 239 240 241 242 CLK STVR (STVL) O1 O2 O3 O239 O240 STVL (STVR) O1 of next stage O2 of next stage Caution Do not use a sequence in which the outputs change all at once because such a sequence may cause malfunctioning. Data Sheet S11950EJ2V0DS00 5 µ PD16655 6. ELECTRICAL SPECIFICATION Absolute Maximum Ratings (TA = 25°C, VSS = 0 V) Parameter Symbol Ratings Unit Logic Positive Supply Voltage VDD1 –0.5 to +28 V Driver Positive Supply Voltage VDD2 –0.5 to +28 V Reference Positive Power Supply Voltage VCC –0.5 to +7 V VDD1-VEE1 VDD2-VEE2 –0.5 to +33 V Logic Negative Supply Voltage VEE1 –23 to +0.5 V Driver Negative Supply Voltage VEE2 –23 to +0.5 V Input Voltage VI VEE1 – 0.5 to VDD1 + 0.5 V Input Current II ±10 mA Output Current IO ±10 mA Operating Temperature Range TA –30 to +85 °C Storage Temperature Range Tstg –55 to +125 °C Power Supply Voltage Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range (TA = –30 to 85°C, VSS = 0 V) Parameter Symbol MIN. Logic Positive Supply Voltage VDD1 Driver Positive Supply Voltage MAX. Unit 10 25 V VDD2 10 25 V Logic Negative Supply Voltage VEE1 –21 –3 V Driver Negative Supply Voltage VEE2 –21 VDD2 – 15 V VDD1-VEE1 VDD2-VEE2 15 31 V VCC 2.7 5.5 V Power Supply Voltage Reference Positive Power Supply Voltage TYP. Caution Observe the following condition when shifting VEE2 (driver power). Note that, in this case, the guaranteed values of the output ON resistance and output fall time slightly change. VEE1 ≤ VEE2 ≤ VDD – 15 V (VDD1 or VDD2) 6 Data Sheet S11950EJ2V0DS00 µ PD16655 ELECTRICAL CHARACTERISTICS (TA = –30 to +85 °C, VDD1 = VDD2 = 22 V, VEE1 = VEE2 = –9 V, VSS = 0 V, VCC = 2.7 V or 5.5 V) Parameter Symbol Condition MIN TYP. MAX. Unit High-Level Input Voltage VIH 0.7 VCC VDD1 V Low-Level Input Voltage VIL VEE1 0.3 VCC V High-Level Output Voltage VOH STVR-STVL, without load VDD1 – 0.05 VDD1 V Low-Level Output Voltage VOL STVR-STVL, without load VEE1 VEE1 + 0.05 V High-Level Output Driver Current IXOH Driver output, VO = VDD2 – 1.0 V –2.0 mA Low-Level Output Driver Current IXOL1 Driver output, VO = VEE2 + 1.0 V 2.0 mA IXOL2 Driver output, VO = VEE2 + 1.0 V, 1.5 mA VEE2 = VDD – 15 V LCD Driver Output ON Resistance RON1 VO = VEE2 + 1.0 V, VDD2 – 1.0 V 500 Ω RON2 VO = VEE2 + 1.0 V, VDD2 – 1.0 V, 700 Ω –2.0 mA VEE2 = VDD – 15 V High-Level Output Pulse Current IPOH STVR-STVL, VO = VDD1 – 1.0 V Low-Level Output Pulse Current IPOL STVR-STVL, VO = VEE1 + 1.0 V Input Leak Current IIL VI = 0 V or 3 V or 5 V Static Current Dissipation IDD VDD1, VDD2 pin, fCLK = 31.5 kHz IEE VEE1, VEE2 pin, fCLK = 31.5 kHz ICC VCC pin, fCLK = 31.5 kHz Data Sheet S11950EJ2V0DS00 2.0 mA ±1 µA 400 800 µA –400 –800 µA 50 µA 7 µ PD16655 SWICHING CHARACTERISTICS (TA = –30 to +85 °C, VDD1 = VDD2 = 22 V, VEE1 = VEE2 = –9 V, VSS = 0 V, VCC = 2.7 V to 5.5 V) Parameter MAX. Unit 600 ns 600 ns CL = 220 pF CLK → Xon 700 ns 700 ns 700 ns td2 CL = 220 pF, OE: L → H CL = 220 pF, OE: H → L 700 ns Output Rise Time tTLH CL = 220 pF 300 ns Output Fall Time tTHL1 CL = 220 pF 300 ns tTHL2 CL = 220 pF, VEE2 = VDD – 15 V 400 ns TA = 25°C 15 pF Cascade Output Delay Time Symbol tPHL1 Condition MIN. TYP. CL = 20 pF tPLH1 Driver Output Delay Time tPHL2 tPLH2 td1 Input Capacitance CI Clock Frequency fCLK In cascade connection 100 kHz TIMING REQUIREMENTS (TA = –30 to 85 °C, VDD1 = VDD2 = 22 V, VEE1 = VEE2 = –9 V, VSS = 0 V, VCC = 2.7 V to 5.5 V) Parameter Clock Pulse Width Condition PWCLK MIN. TYP. MAX. Unit 1000 ns Data Setup Time tsetup STVR(STVL) ↑ → CLK ↑ 100 ns Data Hold Time thold CLK ↑ → STVR(STVL) ↓ 100 ns Caution 8 Symbol Keep the time and fall time of the logic input to tr = tf = 20 ns (10 to 90 % of the rated values). Data Sheet S11950EJ2V0DS00 Data Sheet S11950EJ2V0DS00 O1-240 OE STVL O240 O239 • • • O2 O1 STVR CLK tSETUP tPLH2 tHOLD 1 2 90% tPHL2 10% tTLH PWCLK 3 tTHL 4 5 6 7 237 238 239 240 tPLH1 tPHL1 td1 td2 90% 10% tr tf µ PD16655 7. SWITCHING CHARACTERISTIC WAVEFORM 9 µ PD16655 8. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met for mounting conditions of the µ PD16655. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µ PD16655N-xxx : TCP(TAB package) Mounting Condition Thermocompression Caution Mounting Method Condition Soldering Heating tool 300 to 350°C, heating for 2 to 3 seconds: pressure 100 g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100°C; pressure 3 to 8 kg/cm ; time 3 to 5 secs. 2 Real bonding 165 to 180°C; pressure 25 to 45 kg/cm , time 30 to 40 secs. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) 2 To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time. 10 Data Sheet S11950EJ2V0DS00 µ PD16655 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S11950EJ2V0DS00 11 µ PD16655 Reference Documents NEC Semiconductor Device Reliability / Quality Control System (C10983E) Quality Grades to NEC’s Semiconductor Devices (C11531E) • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8