DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16664
144/160/184/208-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH RAM
DESCRIPTION
The µ PD16664 is a column (segment) driver with internal RAM and can drive a full-dot LCD. Equipped with
144/160/184/208-output pins and a display RAM of 208 x 160 x 2 bits, this driver can display any of four gray levels
selected from a 25-level palette. By using this IC in combination with the µ PD16667, 144 x 128 pixels to 416 x 320
pixels can be displayed.
FEATURES
• Internal display RAM : 208 x 160 x 2 bits
• Logic voltage
: 2.4 to 3.6 V
• Duty
: 1/128, 1/160 selectable
• Number of outputs
: 144,160,184 and 208 pins selectable
• Display
: Four gray levels (selectable from 25-level palette)
• Memory management : Packed pixel method
• Supports 8/16-bit data bus
ORDERING INFORMATION
Remark
Part number
Package
µ PD16664N-xxx
TCP (TAB)
µ PD16664N-001
2/4-side Standard TCP
The TCP’s external shape is customized. To order the required shape, please contact an NEC
salesperson.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S13780EJ1V0DS00(1st edition)
Date Published September 1999 NS CP(K)
Printed in Japan
The mark • shows major revised points.
©
1998, 1999
µ PD16664
1. PIN NAME
Classification
CPU interface
Pin NameNote
I/O
Function
D0-D15
I/O
A0-A16
I
Address bus: 17 bits
/CS
I
Chip select
VCC2 /OE
I
Read signal
/WE
I
Write signal
/UBE
I
Upper byte enable
RDY
O
Ready signal to CPU (“H”: ready)
PL0
I
Specifies LSI layout position (No. 0 to 3)
PL1
I
Specifies LSI layout position (No. 0 to 3)
DIR
I
Specifies liquid crystal panel layout position
DMODE
I
Duty selection (“H” = 1/128 duty, “L” =1/160 duty)
CMODE0,1
I
Number of column outputs selection
MS
I
Master/slave selection (“H”: master mode)
I
Data bus bit selection (“H” = 8 bits, “L” = 16 bits)
Control signals
VCC2 BMODE
/REFRH
I/O
Data bus: 16 bits
Self-diagnosis reset pin (wired-OR connection)
TEST
I
Test pin (“H” = test mode, with pull-down resistor)
/RESET
I
Reset signal
/DOFF
I
Display OFF input signal
OSC1
–
External resistor pin for oscillator
OSC2
–
External resistor pin for oscillator
STB
I/O
Column drive signal (MS pin “H” = output, MS pin “L” = input)
/FRM
I/O
Frame signal (MS pin “H” = output, MS pin “L” = input)
VCC1 PULSE
I/O
25-level pulse modulation clock
L1
I/O
Row driver drive level select signal (first line)
L2
I/O
Row driver drive level select signal (second line)
/DOUT
O
Display OFF output signal
Liquid crystal drive
Y1-Y208
O
Liquid crystal drive output
Power
GND
–
Ground (two pins for VCC1 system, three pins for VCC2 system)
VCC1
–
Power supply for liquid crystal drive and row driver interface
VCC2
–
Power supply for logic
V0
–
Liquid crystal drive analog power
V1
–
Liquid crystal drive analog power
V2
–
Liquid crystal drive analog power
Note VCC2 system pins : D 0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR,
OSC1, OSC2, /RESET, /DOFF, TEST, MS, CMODE0, CMODE1, DMODE
VCC1 system pins : STB, /FRM, L1, L2, /DOUT, PULSE
Remark
2
/xxx indicates active low signals.
Data Sheet S13780EJ1V0DS00
µ PD16664
2. BLOCK DIAGRAM
CMODE0,1
DIR
PL0, 1
TEST
A0-A16
Address
input
control
Address
management
circuit
Control
/CS, /OE
/WE, /UBE
RAM
208 × 160 × 2 bits
Arbiter
RDY
BMODE
D0-D15
Data bus
control
/REFRH
Data latch (1)
/RESET
MS
STOP
OSC1
CR
oscillator
OSC2
/DOFF
DMODE
Gray level
generation
circuit
Data latch (2)
Internal timing
generation
Gray level control
Liquid crystal
timing generation
VCC2 operation
PULSE
/FRM STB
Self-diagnosis
circuit
VCC2 operation
Level shifter
VCC1 operation
VCC1 operation
DEC
V0
V1
V2
Liquid crystal drive
circuit 208 outputs
PULSE
/FRM
STB /DOUT L1
L2
Data Sheet S13780EJ1V0DS00
Y 1 Y2 Y 3
Y208
3
µ PD16664
3. BLOCK FUNCTION
(1) Address management circuit
This circuit converts addresses from the system via A0 to A16 into addresses corresponding to the memory map
of the internal RAM.
By using this function and four µ PD16664 modules, addresses for up to 416 × 320 pixels can be managed,
making it easy to construct a liquid crystal display system.
Addresses 1FF00H to 1FF1EH are allocated to a gray level palette register, and any four gray levels can be
selected from a 25-level palette.
(2) Arbiter
This circuit arbitrates conflicts between access by the system to the RAM and reading the RAM by the LCD
driver.
(3) RAM
This is a static RAM of 208 x 160 x 2 bits (single port).
(4) Data bus control
This circuit controls the data transfer direction depending on whether the system reads or writes the RAM of the
µ PD16664.
The data bus width can be changed between 8 and 16 bits by the BMODE pin.
(5) Gray level generation circuit
This circuit offers 25 levels by means of frame interpolation and pulse width modulation.
(6) Internal timing generation
This circuit generates internal timing signals for each block from the /FRM and STB signals.
(7) CR oscillator
This oscillator generates a clock that serves as the reference of the frame frequency in the master mode.
Because this CR oscillator has an on-chip capacitor, the necessary oscillation frequency can be adjusted by using
an external resistor.
Oscillation is stopped in the slave mode.
(a) 1/160 duty
The frame frequency is 1/1296 of the oscillation frequency of this oscillator. For example, when the frame
frequency is 70 Hz, the oscillation frequency is 90.72 kHz.
(b) 1/128 duty
The frame frequency is 1/1040 of the oscillation frequency of this oscillator. For example, when the frame
frequency is 70 Hz, the oscillation frequency is 72.80 kHz.
(8) Liquid crystal timing generation
This circuit generates the /FRM (frame signal), STB(column drive signal strobe), and PULSE (25-level pulse
modulation clock) signals in the master mode.
4
Data Sheet S13780EJ1V0DS00
µ PD16664
(9) Gray level control
This circuit implements the 4-gray level display.
(10) Data latch (1)
This circuit reads data for 208 pixels from RAM and latches it.
(11) Data latch (2)
This circuit latches data for 208 pixels in synchronization with the STB signal.
(12) Level shifter
The level shifter converts the operating voltage of the internal circuit(VCC2) into the voltage for the liquid crystal
driver circuit and row driver interface (VCC1).
(13) DEC
This is a decoder that decodes gray level display data to liquid crystal drive voltages V0, V1, or V2.
(14) Liquid crystal drive circuit
This circuit selects liquid crystal drive voltage V0, V1, or V2 corresponding to gray level display data and the
display OFF signal (/DOFF), to generate a liquid crystal application voltage.
(15) Self-diagnosis circuit
If the operation timing of the master chip and that of the slave chip differ due to external noise, this circuit
automatically detects the difference and generates a refresh signal to all column drivers.
Data Sheet S13780EJ1V0DS00
5
µ PD16664
Address Map Image (CMODE0 = L, CMODE1 = L, DMODE = L)
A7 through A0 specify
column direction.
Y1
Y1
Y208
Y208
L1
Address incrementing direction
A16 through A8 specify
line direction.
No. 0
L160
No. 2
L1
Address incrementing direction
No. 1
L160
No. 3
Y1
Y208
6
Y1
Y208
Data Sheet S13780EJ1V0DS00
µ PD16664
4. DATA BUS
The byte data ordering on the data bus is little endian, in common with most NEC and Intel buses.
4.1 16-bit Data Bus (BMODE = L)
Byte access
D0 to D7
D8 to D15
00000H
00001H
Address incrementing
00002H
00003H
direction
00004H
00005H
:
:
:
:
D0 to D7
D8 to D15
Word access
00000H
Address incrementing
00002H
direction
00004H
:
:
If the system accesses the µ PD16664 in word(16-bit) or byte(8-bit) units, /UBE (upper byte enable) and A0 specify
whether bytes D0 to D7 or bytes D8 to D15 have valid data.
/CS
/OE
/WE
/UBE
A0
MODE
I/O
D0 to D7
D8 to D15
H
X
X
X
X
Not selected
Hi-Z
Hi-Z
L
L
H
L
L
Read
Dout
Dout
L
H
L
L
H
Hi-Z
Dout
H
L
Dout
Hi-Z
L
L
Din
Din
L
H
X
Din
H
L
Din
X
Write
L
H
H
X
X
Output
Hi-Z
Hi-Z
L
X
X
H
H
Disable
Hi-Z
Hi-Z
Remark
X : Don’t care
Hi-Z : High impedance
Data Sheet S13780EJ1V0DS00
7
µ PD16664
4.2 8-bit Data Bus (BMODE = H)
D0 to D7
00000H
Address incrementing
00001H
direction
00002H
:
:
/CS
/OE
/WE
MODE
I/O
D0 to D7
D8 to D15
H
X
X
Not selected
Hi-Z
Note
L
L
H
Read
Dout
Note
L
H
L
Write
Din
Note
L
H
H
Output disable
Hi-Z
Note
Note Leave D8 to D15 open because they are internally pulled down.
Remark
X: Don’t care
Hi-Z: High impedance
8
Data Sheet S13780EJ1V0DS00
µ PD16664
5. RELATION BETWEEN DATA BITS AND PIXELS
Because the µ PD16664 displays four gray levels, 1 pixel consists of 2 bits. The RAM consists of 4 pixels (8 pixels
per word) using the packed pixel method.
(1) BMODE = L
Byte (8-bit) access
D0
D1
Pixel 1
D2
D3
Pixel 2
D4
D5
Pixel 3
D6
D7
D8
Pixel 4
D9
Pixel 5
D10
D11
Pixel 6
00000H
Liquid crystal panel
D12
D13
Pixel 7
D14 D15
Pixel 8
00001H
Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8
00000H
00001H
00002H
00003H
Word (16-bit) access
D0
D1
Pixel 1
D2
D3
Pixel 2
D4
D5
Pixel 3
D6
D7
D8
Pixel 4
D9
Pixel 5
D10 D11
D12 D13
D14 D15
Pixel 6
Pixel 7
Pixel 8
00000H
Liquid crystal panel
Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8
00000H
00002H
(2) BMODE = H
D0
D1
Pixel 1
D2
D3
Pixel 2
D4
D5
Pixel 3
D6
D7
Pixel 4
D0
D1
Pixel 5
D2
D4
Pixel 6
00000H
Liquid crystal panel
D3
D5
Pixel 7
D6
D7
Pixel 8
00002H
Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8
00000H
00001H
Data Sheet S13780EJ1V0DS00
00002H
00003H
9
µ PD16664
6. GRAY LEVEL CONTROL
The gray level control of the µ PD16664 offers a 25-level palette by means of frame interpolation and pulse width
modulation. From this palette, four gray levels are selected and registered in a gray level palette register.
7. GRAY LEVEL PALETTE REGISTER
The gray level palette register selects four gray levels from 25 levels in advance. This register is allocated to
1FF00H to 1FF1EH, and its relation with gray level data is as shown below.
The gray level palette register can be set for each layout position of the column driver (No. 0 to 3) that is determined
by PL0 and PL1.
Address
Layout Position No.
Gray Level Data (Display Data)
Dn+1Note
DnNote
0
0
0
1
1FF04H
1
0
1FF06H
1
1
1FF08H
0
0
0
1
1FF0CH
1
0
1FF0EH
1
1
1FF10H
0
0
0
1
1FF14H
1
0
1FF16H
1
1
1FF18H
0
0
0
1
1FF1CH
1
0
1FF1EH
1
1
1FF00H
1FF02H
1FF0AH
1FF12H
1FF1AH
No.0
No.1
No.2
No.3
Note n = 0, 2, 4, 6, 8, 10, 12, or 14
10
Data Sheet S13780EJ1V0DS00
µ PD16664
8. RELATION BETWEEN GRAY LEVELS AND GRAY LEVEL PALETTE DATA
The relation between the gray levels and the gray level palette data set by the gray level palette register is as
follows:
PMODE
Gray Level Palette Data
Remark
D4
D3
D2
D1
D0
Gray level 0
0
0
0
0
0
Gray level 1
0
0
0
0
1
Gray level 2
0
0
0
1
0
Gray level 3
0
0
0
1
1
Gray level 4
0
0
1
0
0
Gray level 5
0
0
1
0
1
Gray level 6
0
0
1
1
0
Gray level 7
0
0
1
1
1
Gray level 8
0
1
0
0
0
Gray level 9
0
1
0
0
1
Gray level 10
0
1
0
1
0
Gray level 11
0
1
0
1
1
Gray level 12
0
1
1
0
0
Gray level 13
0
1
1
0
1
Gray level 14
0
1
1
1
0
Gray level 15
0
1
1
1
1
Gray level 16
1
0
0
0
0
Gray level 17
1
0
0
0
1
Gray level 18
1
0
0
1
0
Gray level 19
1
0
0
1
1
Gray level 20
1
0
1
0
0
Gray level 21
1
0
1
0
1
Gray level 22
1
0
1
1
0
Gray level 23
1
0
1
1
1
Gray level 24
1
1
0
0
0
Data Sheet S13780EJ1V0DS00
OFF
1/3
2/3
ON
11
µ PD16664
9. LSI LAYOUT AND ADDRESS MANAGEMENT
Addresses are managed so that up to four µ PD16664s can be used to organize a liquid crystal display of 416 x 320
pixels.
Four modules can be connected on the same bus with the /CS, /WE, and /OE pins shared.
The system can treats one screenful of the liquid crystal display as one memory area, and does not have to decode
more than one LSI.
Specify an LSI No. by using the PL0 and PL1 pin to determine the layout of the LSIs, and determine the direction
(vertical or horizontal) of the liquid crystal display by using the DIR pin.
PL1
PL0
LSI No.
0
0
No. 0
0
1
No. 1
1
0
No. 2
1
1
No. 3
10. NUMBER OF COLUMN OUTPUTS SELECTION
CMODE1
CMODE0
Number of Column Outputs
Valid Pins
0
0
208
Y1 to Y208
0
1
184
Y1 to Y184
1
0
160
Y1 to Y160
1
1
144
Y1 to Y144
Remark
Invalid column outputs are fastened to V1 level.
11. DUTY SELECTION
DMODE
Duty
0
1/160
1
1/128 Note
Note Valid row outputs of µ PD16667 are X1 to X128. Invalid row outputs are undefined.
12
Data Sheet S13780EJ1V0DS00
µ PD16664
Horizontally Long Address DIR = L, DMODE = L
• 144-output Mode
Specified by
A7 to A0
µ PD16664
µ PD16664
Y144
Y1
Specified by
A16 to A8
X1
00000
00020
00002
µ PD16667
00100
Y1
00022
00024
00122
00124
Y144
00026
09E22
09F00
09F02
X1
0A000
0A002
µ PD16667
09E24
09E46
09F20
09F22
09F24
09F26
09F44
09F46
0A020
0A022
0A024
0A026
0A044
0A046
0A122
0A124
0A100
0A146
No. 1
No. 3
13E00
X160
13F00
13F02
00046
No. 2
09E00
X160
00044
00146
No. 0
13F20
Y144
13E22
13E24
13F22
13F24
Y1
13E46
13F44
13F26
Y144
13F46
Y1
µ PD16664
µ PD16664
• 160-output Mode
Specified by
A7 to A0
µPD16664
X1
00000
00024
00002
00100
µ PD16667
µ PD16664
Y160
Y1
Specified by
A16 to A8
Y1
00026
00028
00126
00128
Y160
0002A
X1
09E26
09E28
09E4E
09F00
09F02
09F24
09F26
09F28
09F2A
09F4C
09F4E
0A000
0A002
0A024
0A026
0A028
0A02A
0A04C
0A04E
0A126
0A128
0A100
0A14E
No. 1
No. 3
13E00
X160
0004E
No. 2
09E00
X160
0004C
0014E
No. 0
µ PD16667
•
13F00
13F02
13F24
Y160
13E26
13E28
13F26
13F28
Y1
13E4E
13F2A
13F4C
Y160
µ PD16664
Data Sheet S13780EJ1V0DS00
13F4E
Y1
µ PD16664
13
µ PD16664
• 184-output Mode
Specified by
A7 to A0
µPD16664
µ PD16664
Y184
Y1
Specified by
A16 to A8
X1
00000
0002A
00002
µPD16667
00100
Y1
0002C
0002E
0012C
0012E
Y184
00030
00058
0015A
No. 0
No. 2
09E00
X160
X1
09E2C
09E2E
09E5A
09F00
09F02
09F2A
09F2C
09F2E
09F30
09F58
09F5A
0A000
0A002
0A02A
0A02C
0A02E
0A030
0A058
0A05A
0A12C
0A12E
µ PD16667
0A100
0A15A
No. 1
No. 3
13E00
X160
0005A
13F00
13F02
13F2A
Y184
13E2C
13E2E
13F2C
13F2E
Y1
13E5A
13F58
13F30
Y184
13F5A
Y1
µ PD16664
µPD16664
• 208-output Mode
Specified by
A7 to A0
µ PD16664
µ PD16664
Y208
Y1
Specified by
A16 to A8
X1
00000
00030
00002
µ PD16667
00100
Y1
00032
00034
00132
00134
00036
09E32
09E34
09E66
09F00
09F02
09F30
09F32
09F34
09F36
09F64
09F66
0A000
0A002
0A030
0A032
0A034
0A036
0A064
0A066
0A132
0A134
µ PD16667
0A100
0A166
No. 1
No. 3
13E00
X160
00066
No. 2
09E00
X1
00064
00166
No. 0
X160
13F00
13F02
13F30
Y208
13E32
13E34
13F32
13F34
Y1
13E66
13F36
13F64
Y208
µ PD16664
14
Y208
Data Sheet S13780EJ1V0DS00
13F66
Y1
µ PD16664
00122
00022 00020
Data Sheet S13780EJ1V0DS00
Y144
13F46 13F44
13E46
µPD16664
13F26
Y1
13F24
Y144
13F22 13F20
13E24 13E22
0A124 0A122
µ PD16664
No. 1
No. 0
09E00
00100
00000
Y1
13F02 13F00
13E00
0A100
0A002 0A000
09F02 09F00
00002
Y144
X1
X160
X1
X160
µ PD16667
0A146
0A026 0A024 0A022 0A020
0A046 0A044
09E24 09E22
00124
00024
09F26 09F24 09F22 09F20
No. 3
No. 2
00026
Y1
09F46 09F44
09E46
00146
00044
Y144
Specified by
A7 to A0
00046
Y1
µ PD16664
•
µ PD16664
µ PD16664
Vertically Long Address DIR = H, DMODE = L
• 144-output Mode
Specified by
A16 to A8
µ PD16667
15
16
Data Sheet S13780EJ1V0DS00
Y160
13F4E 13F4C
13E4E
µ PD16664
13F2A
Y1
13F28
Y160
13F26 13F24
13E28 13E26
0A128 0A126
µPD16664
No. 1
No. 0
09E00
00100
00000
Y1
13F02 13F00
13E00
0A100
0A002 0A000
09F02 09F00
00002
Y160
X1
X160
X1
X160
µ PD16667
0A14E
0A02A 0A028 0A026 0A024
0A04E 0A04C
09E28 09E26
00126
00026 00024
09F2A 09F28 09F26 09F24
No. 3
No. 2
00128
00028
Y1
09F4E 09F4C
09E4E
0014E
0002A
Y160
µ PD16664
Specified by
A7 to A0
0004E 0004C
Y1
µPD16664
µ PD16664
• 160-output Mode
Specified by
A16 to A8
µ PD16667
Data Sheet S13780EJ1V0DS00
Y184
µ PD16664
Y1
Y184
13F2E 13F2C 13F2A
13F5A 13F58
13F30
13E2E 13E2C
13E5A
0A12E 0A12C
µ PD16664
No. 1
No. 0
09E00
00100
00000
Y1
13F02 13F00
13E00
0A100
0A002 0A000
09F02 09F00
00002
Y184
X1
X160
X1
X160
µ PD16667
0A15A
0A030 0A02E 0A02C 0A02A
0A05A 0A058
09E2E 09E2C
09F30 09F2E 09F2C 09F2A
No. 3
No. 2
0012E 0012C
0002E 0002C 0002A
Y1
09F5A 09F58
09E5A
0015A
00030
Y184
µ PD16664
Specified by
A7 to A0
0005A 00058
Y1
µ PD16664
µ PD16664
• 184-output Mode
Specified by
A16 to A8
µ PD16667
17
18
00132
00032 00030
Data Sheet S13780EJ1V0DS00
Y208
µ PD16664
13F36
Y1
13F34
Y208
13F32 13F30
13E34 13E32
µ PD16664
No. 1
Y1
13F02 13F00
13E00
0A100
0A002 0A000
09F02 09F00
09E00
00100
00000
X160
X1
X160
X1
µ PD16667
13F66 13F64
13E66
0A134 0A132
No. 0
00002
Y208
µ PD16667
0A166
0A036 0A034 0A032 0A030
0A066 0A064
09E34 09E32
00134
00034
09F36 09F34 09F32 09F30
No. 3
No. 2
00036
Y1
09F66 09F64
09E66
00166
00064
Y208
µ PD16664
Specified by
A7 to A0
00066
Y1
µPD16664
µ PD16664
• 208-output Mode
Specified by
A16 to A8
µ PD16664
Horizontally Long Address DIR = L, DMODE = H
• 144-output Mode
Specified by
A7 to A0
µ PD16664
µ PD16664
Y144
Y1
Specified by
A16 to A8
X1
00000
00020
00002
µ PD16667
00100
Y1
00022
00024
00122
00124
Y144
00026
00044
00046
00146
No. 0
No. 2
07E00
07E22
07E24
07E46
X128
07F00
07F02
07F20
07F22
07F24
07F26
07F44
07F46
X1
08000
08002
08020
08022
08024
08026
08044
08046
08122
08124
µ PD16667
08100
08146
No. 1
No. 3
0FE00
X128
0FF00
0FF02
0FF20
Y144
0FE22
0FE24
0FF22
0FF24
Y1
0FE46
0FF44
0FF26
Y144
0FF46
Y1
µ PD16664
µ PD16664
• 160-output Mode
Specified by
A7 to A0
µPD16664
X1
00000
00024
00002
00100
µ PD16667
µ PD16664
Y160
Y1
Specified by
A16 to A8
Y1
00026
00028
00126
00128
Y160
0002A
0004C
0004E
0014E
No. 0
No. 2
07E00
07E26
07E28
07E4E
X128
07F00
07F02
07F24
07F26
07F28
07F2A
07F4C
07F4E
X1
08000
08002
08024
08026
08028
0802A
0804C
0804E
08126
08128
08100
µ PD16667
•
0814E
No. 1
No. 3
0FE00
X128
0FF00
0FF02
0FF24
Y160
0FE26
0FE28
0FF26
0FF28
Y1
0FE4E
0FF2A
0FF4C
Y160
µ PD16664
Data Sheet S13780EJ1V0DS00
0FF4E
Y1
µ PD16664
19
µ PD16664
• 184-output Mode
Specified by
A7 to A0
µPD16664
Y184
Y1
Specified by
A16 to A18
X1
00000
0002A
00002
00100
µPD16667
µ PD16664
Y1
0002C
0002E
0012C
0012E
Y184
00030
00058
0005A
0015A
No. 0
No. 2
07E00
07E2C
07E2E
07E5A
X128
07F00
07F02
07F2A
07F2C
07F2E
07F30
07F58
07F5A
X1
08000
08002
0802A
0802C
0802E
08030
08058
0805A
0812C
0812E
µ PD16667
08100
0815A
No. 1
No. 3
0FE2C 0FE2E
0FE00
X128
0FF00
0FF02
0FF2A
Y184
0FF2C
Y1
0FF2E
0FE5A
0FF58
0FF30
Y184
0FF5A
Y1
µ PD16664
µPD16664
• 208-output Mode
Specified by
A7 to A0
µ PD16664
µ PD16664
Y208
Y1
Specified by
A16 to A8
X1
00000
00030
00002
µ PD16667
00100
Y1
00032
00034
00132
00134
00036
07E32
07E34
07E66
07F00
07F02
07F30
07F32
07F34
07F36
07F64
07F66
08000
08002
08030
08032
08034
08036
08064
08066
08132
08134
µ PD16667
08100
08166
No. 1
No. 3
0FE00
X128
00066
No. 2
07E00
X1
00064
00166
No. 0
X128
0FF00
0FF02
0FF30
Y208
0FE32
0FE34
0FF32
0FF34
Y1
0FE66
0FF36
0FF64
Y208
µ PD16664
20
Y208
Data Sheet S13780EJ1V0DS00
0FF66
Y1
µ PD16664
Data Sheet S13780EJ1V0DS00
08020
Y144
Y1
Y144
0FF24 0FF22 0FF20
µPD16664
08022
08124 08122
08024
0FF46 0FF44
0FF26
08026
07F26 07F24 07F22 07F20
0FE24 0FE22
No. 3
00122
00022 00020
07E24 07E22
00124
00024
0FE46
08146
08044
No. 2
00026
Y1
µ PD16664
No. 1
No. 0
07E00
00100
00000
0FE00
08100
08000
Y1
0FF02 0FF00
08002
07F02 07F00
00002
Y144
X1
X128
X1
X128
µ PD16667
08046
07F46 07F44
07E46
00146
00044
Y144
Specified by
A7 to A0
00046
Y1
µ PD16664
•
µ PD16664
µ PD16664
Vertically Long Address DIR = H, DMODE = H
• 144-output Mode
Specified by
A16 to A8
µ PD16667
21
22
Data Sheet S13780EJ1V0DS00
Y160
0FF4E 0FF4C
0FE4E
0814E
µ PD16664
No. 3
No. 2
00126
00026 00024
08026
0FE28 0FE26
08128 08126
08028
08024
Y1
Y160
0FF2A 0FF28 0FF26 0FF24
0802A
07F2A 07F28 07F26 07F24
07E28 07E26
00128
00028
Y1
µPD16664
No. 1
No. 0
07E00
00100
00000
0FE00
08100
08000
Y1
0FF02 0FF00
08002
07F02 07F00
00002
Y160
X1
X128
X1
X128
µ PD16667
0804E 0804C
07F4E 07F4C
07E4E
0014E
0002A
Y160
µ PD16664
Specified by
A7 to A0
0004E 0004C
Y1
µPD16664
µ PD16664
• 160-output Mode
Specified by
A16 to A8
µ PD16667
Data Sheet S13780EJ1V0DS00
Y184
0FF5A 0FF58
0FE5A
0815A
µ PD16664
Y1
Y184
0FF30 0FF2E 0FF2C 0FF2A
0FE2E 0FE2C
0812E 0812C
0802E 0802C 0802A
08030
µ PD16664
No. 1
No. 0
07E00
00100
00000
0FE00
08100
08000
Y1
0FF02 0FF00
08002
07F02 07F00
00002
Y184
X1
X128
X1
X128
µ PD16667
0805A
08058
07E2E 07E2C
07F30 07F2E 07F2C 07F2A
No. 3
No. 2
0012E 0012C
0002E 0002C 0002A
Y1
07F5A 07F58
07E5A
0015A
00030
Y184
µ PD16664
Specified by
A7 to A0
0005A 00058
Y1
µ PD16664
µ PD16664
• 184-output Mode
Specified by
A16 to A8
µ PD16667
23
24
Data Sheet S13780EJ1V0DS00
08030
Y1
Y208
µ PD16664
No. 1
No. 0
07E00
00100
00000
0FE00
08100
08000
Y1
0FF02 0FF00
08002
07F02 07F00
00002
Y208
X128
X1
X128
X1
µ PD16667
Y208
0FF34 0FF32 0FF30
µ PD16664
08032
08134 08132
08034
0FF66 0FF64
0FF36
08036
07F36 07F34 07F32 07F30
0FE34 0FE32
No. 3
00132
00032 00030
07E34 07E32
00134
00034
0FE66
08166
08064
No. 2
00036
Y1
µ PD16667
08066
07F66 07F64
07E66
00166
00064
Y208
µ PD16664
Specified by
A7 to A0
00066
Y1
µPD16664
µ PD16664
• 208-output Mode
Specified by
A16 to A8
µ PD16664
12. CPU INTERFACE
12.1 Function of RDY(ready) Pin
The internal RAM is a single-port RAM. The CPU is kept waiting so that access from the CPU does not conflict with
reading by the driver.
(1) Timing
A0 to A16,/UBE
/CS
/OE,/WE
Hi-Z
Hi-Z
RDY
Wait
Ready
Wait
(2) Connection of RDY pin
The RDY pin uses a three-state buffer. The RDY pin should be connected to an external pull-up resistor. If more
than one LSI are used, the RDY pins of each LSI are wired together.
VCC2
CPU
Pull-up resistor
Ready input
Data Sheet S13780EJ1V0DS00
RDY
Column driver
RDY
Column driver
25
µ PD16664
12.2 Access Timing
(1) Display data read timing
A16 to A0
/UBE
/CS
/OE
Hi-Z
Hi-Z
RDY
Hi-Z
Hi-Z
D15 to D0
Dout
(2) Display data write timing
A16 to A0
/UBE
/CS
/WE
Hi-Z
Hi-Z
RDY
Din
D15 to D0
(3) Gray level palette data write timing
A16 to A0
/UBE
/CS
/WE
Hi-Z
RDY
Din
D15 to D0
26
Data Sheet S13780EJ1V0DS00
µ PD16664
13. INITIALIZATIONAL FUNCTION
The µ PD16664 has two types of initialization functions.
13.1 Initialization by /RESET
/RESET is the pin that is used to forcibly initialize the internal status of the IC from outside the IC. In the case of
/RESET = L, the internal status of IC is as follows:
• Oscillator stopped.
• Liquid crystal timing generation circuit initialized.
• Internal timing generation circuit initialized.
• Self-diagnostic circuit initialized.
At power-on, be sure to perform initialization using /RESET.
13.2 Initialization by /REFRH
/REFRH is the pin that is used when the internal self-diagnostic circuit initializes the internal status of IC in cases
when the timing of the column drivers deviate due to external noise, etc.
In the case of /REFRH = L, the internal status of IC is as follows:
• Oscillator stopped.
• Liquid crystal timing generation circuit initialized.
• Internal timing generation circuit initialized.
14. DISPLAY-OFF FUNCTION
When /DOFF = L, all column driver outputs Yn become V1 level, and because the /DOUT output becomes L at the
same time, the row driver will be /DOFF’ = L and all row driver outputs Xn will also be V1 level. Therefore, the display
is forcibly turned off without regard to the display data. At power-on, be sure to make /DOFF = L until each power
supply is stabilized.
Remark
/DOFF’ is the input pin of the row driver.
Data Sheet S13780EJ1V0DS00
27
µ PD16664
15. LIQUID CRYSTAL TIMING GENERATION CIRCUIT
If the master mode is set by making MS high, /FRM and STB are generated at timing with a duty factor
(1/128,1/160). Driver drive voltage select signals L1 and L2 are generated for a row driver.
/FRM is generated two times in 1 frame. When a duty rate is 1/160, STB is generated 81 times in 1/2 frame and
162 times in 1 frame. When a duty rate is 1/128, STB is generated 65 times in 1/2 frame and 130 times in 1 frame.
• /FRM and STB Signal Generation
OSC1
PULSE
STB
1
3
2
4
DUTY 1/160
STB
81
1
2
3
80
81
1
2
3
80
81
1
2
2
3
64
65
1
2
/FRM
Frame
DUTY 1/128
STB
65
1
2
3
64
65
1
/FRM
Frame
• L1 and L2 Signal Generation
28
STB
1
2
3
4
···
1
2
3
4
···
1
2
3
4
···
1
2
3
4
···
L1
1
1
1
1
···
1
1
1
1
···
0
0
0
0
···
0
0
0
0
···
L2
1
0
1
0
···
0
1
0
1
···
0
1
0
1
···
1
0
1
0
···
Data Sheet S13780EJ1V0DS00
µ PD16664
16. SELF-DIAGNOSIS FUNCTION
This function checks whether the timing of each column driver is different from that of the others due to external
noise. A slave chip compares internally generated L1 and L2 with L1 and L2 of the master chip. If a discrepancy is
found, a refresh signal is transmitted to all column drivers. On reception of the refresh signal, internal reset is
effected, and timing is initialized. At this time, the display is turned OFF while /REFRH = L for 4 frame cycles.
Discrepancy between L1 and L2 is monitored at the rising edge of /FRM once in 1/2 frame.
L1(master)
Discrepancy
L2(master)
L1(slave)
Discrepancy
L2 (slave)
/REFRH
Initialization
Initialization
Block Configuration (slave side)
/RESET
Internal reset
/REFRH
Self-diagnosis circuit
L1
Internal L1 signal
L2
Internal L2 signal
Data Sheet S13780EJ1V0DS00
29
µ PD16664
17. SYSTEM CONFIGURATION EXAMPLE
Here is an example using a liquid crystal panel of 416 x 320 pixels, horizontally long by using four µ PD16664s and
two row drivers.
• The LSI No. of each column driver is set by the PL0 and PL1 pins.
• The DIR pin of each column driver is set to low.
• The CMODE0, CMODE1 and DMODE pins of each column driver are set to low.
• One of the column drivers is set as a master and the others are set as slaves. The master column driver supplies
signals to the slave column drivers and row drivers.
• A resistor for oscillation is connected to the OSC1 and OSC2 pins of the master. These pins of the slaves are left
open.
• All the signals from the system (D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, /RESET, and /DOFF) are
connected in parallel with the column drivers. A pull-up resistor is connected to the RDY pin.
• The TEST pin is used to test the LSI and is open or connected to GND when the system is constructed.
VCC2
RDY
/DOFF
/RESET
D0 to D15
A0 to A16
Control
(/CS, /OE,
/WE, /UBE)
PULSE
STB
/FRM
/DOUT,/DOFF'
L1
L2
OSC1
OSC2
/REFRH
Y208
Y1
Y208
Row driver
160
Row driver
160
Scan direction
Scan direction
Y1
Y208
Y1
Slave
No. 1
30
Slave
No. 2
Master
No. 0
Y1
Y208
Slave
No. 3
Data Sheet S13780EJ1V0DS00
µ PD16664
18. CHIP SET POWER-UP SEQUENCE
It is recommended to apply power in the following sequence:
VCC2 → VCC1 → input → VDD, VEE → V1, V2
Be sure to apply LCD drive voltages V1, V2 in the end.
ON
VCC2
VCC1
OFF
ON
4.5 V
OFF
0 s or more
CPU Interface
(A0 to A16,/CS,/OE,
/WE,/UBE,D0 to D15)
/RESET
VCC2
0V
VCC2
0V
0.3 VCC2
100 ns or longer
/DOFF
0 s or more
VCC2
0.3 VCC2
0V
0 s or more
VDD Note
OFF
ON
OFF
VEE Note
ON
0 s or more
V1
ON
OFF
ON
V2
OFF
Note VDD and VEE do not have to be turned ON at the same time.
Caution Turn OFF power to the chip set in the sequence reverse to the above.
Data Sheet S13780EJ1V0DS00
31
µ PD16664
19. EXAMPLE OF CONNECTING OF INTERNAL SCHOTTKY BARRIER DIODE OF MODULE TO
REINFORCE POWER SUPPLY PROTECTION
VDDNote
VCC1
V2
V1
V0
VSS
VEENote
Diodes enclosed in a dotted line in the above figure must be connected
when V0 is other than 0 V (GND).
Note VDD and VEE are LCD power supply lines of row driver.
Remark Use schottky barrier diodes with Vf = 0.5 V or less.
32
Data Sheet S13780EJ1V0DS00
µ PD16664
20. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage (1)
Note1
Supply voltage (2)
Note2
Symbol
Ratings
Unit
VCC1
–0.5 to +6.5
V
VCC2
–0.5 to +4.5
V
Input/output voltage (1)
Note1
VI/O1
–0.5 to VCC1 + 0.5
V
Input/output voltage (2)
Note2
VI/O2
–0.5 to VCC2 + 0.5
V
Input/output voltage (3)
Note3
VI/O3
–0.5 to VCC1 + 0.5
V
Operating ambient temperature
TA
–20 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Notes 1. VCC1 signals (/FRM, STB, /DOUT, L1, L2, PULSE)
2. VCC2 signals (MS, DIR, PL0 and PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, OSC1,
OSC2, /DOFF, TEST, BMODE, /REFRH, CMODE0, CMODE1, DMODE)
3. Liquid crystal power (V0, V1, V2, Y1 to Y208)
Caution
If the absolute maximum rating of even one of the above parameters is exceeded even
momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,
specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the range of the absolute maximum ratings.
Recommended Operating Conditions (TA = –20 to +70°C, V0 = 0 V)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
5.0
5.5
V
Supply voltage (1)
VCC1
4.5
Supply voltage (2)
VCC2
2.4
3.6
V
Input voltage (1)
Note1
VI1
0
VCC1
V
Input voltage (2)
Note2
VI2
0
VCC2
V
V1 input voltage
V1
V0
V2
V
V2 input voltage
V2
V1
VCC1
V
External resistor for OSC
ROSC
75
270
kΩ
Notes 1. VCC1 signals (/FRM, STB, L1, L2, PULSE)
2. VCC2 signals (MS, DIR, PL0 and PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, OSC1,
OSC2, /DOFF, TEST, BMODE, /REFRH, CMODE0, CMODE1, DMODE)
Data Sheet S13780EJ1V0DS00
33
µ PD16664
DC Characteristics (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V,
TA = –20 to +70°C)
{VCC2 = 3.0 to 3.6 V
Parameter
Symbol
High-level input voltage (1), VCC1 Note1
VIH1
Low-level input voltage (1), VCC1 Note1
VIL1
High-level input voltage (2), VCC2
Note2
Low-level input voltage (2), VCC2
VIL2
High-level input voltage (2), VCC2
Note3
VIH3
Low-level input voltage (2), VCC2
Note3
VIL3
Low-level output voltage (1), VCC1
Note4
Note4
MIN.
TYP.
MAX.
0.7 VCC1
0.7 VCC2
0.8 VCC2
V
V
0.2 VCC2
IOH = –1 mA
V
V
0.3 VCC2
VOH1
Unit
V
0.3 VCC1
VIH2
Note2
High-level output voltage (1), VCC1
Conditions
VCC1 – 0.4
V
V
VOL1
IOL = 2 mA
High-level output voltage (2), VCC1
Note1
VOH2
IOH = –2 mA
Low-level output voltage (2), VCC1
Note1,3
VOL2
IOL = 4 mA
High-level output voltage (3), VCC2
Note5
VOH3
IOH = –1 mA
VOL3
IOL = 2 mA
0.4
V
II1
Other than TEST pin,
±10
µA
100
µA
Low-level output voltage (3), VCC2
Note5
Input leakage current (1)
0.4
VCC1 – 0.4
V
V
0.4
VCC2 – 0.4
V
V
V1 = VCC2 or GND
Input leakage current (2)
II2
Pull down (TEST pin),
10
40
V1 = VCC2
•
•
•
•
Display operating current consumption (1)
Note6
IMAS1
Master, VCC1
80
µA
Display operating current consumption (2)
Note6
IMAS2
Master, VCC2
200
µA
Display operating current consumption (3)
Note6
ISLV1
Slave, VCC1
50
µA
Display operating current consumption (4)
Note6
ISLV2
Slave, VCC2
130
µA
2
kΩ
Liquid crystal driver output ON resistance
Note7
RON
1
Notes 1. VCC1 signal (/FRM, STB, L1, L2, PULSE)
2. VCC2 signal (MS, DIR, PL0 and PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, /DOFF,
TEST, BMODE, CMODE0, CMODE1, DMODE)
3. /REFRH pin
4. /DOUT pin
5. D0 to D15, RDY, OSC2 pins
6. Frame frequency: 70 Hz, output: no load, not accessed by CPU
(D0 to D15, A0 to A16, /UBE = GND, /CS, /OE, /WE = VCC2)
7. Resistance between Y and V pins (any of V0, V1, and V2) when a load current (ION = 100 µ A) flows
through one pin of Y1 to Y208.
34
Data Sheet S13780EJ1V0DS00
µ PD16664
{ VCC2 = 2.4 to 3.0 V
Parameter
Symbol
High-level input voltage (1), VCC1
Low-level input voltage (1), VCC1
Low-level input voltage (2), VCC2
0.7 VCC2
0.3 VCC2
0.8 VCC2
IOH = –1 mA
VOL1
IOL = 2 mA
Note1
VOH2
IOH = –2 mA
Note1,3
VOL2
IOL = 4 mA
Note5
High-level output voltage (3), VCC2
V
V
V
0.2 VCC2
VOH1
Unit
V
VIL3
Note4
High-level output voltage (2), VCC1
Low-level output voltage (2), VCC1
0.3 VCC1
VIH3
Note4
MAX.
V
VIL2
Note3
Low-level output voltage (1), VCC1
TYP.
0.7 VCC1
VIH2
Note3
High-level output voltage (1), VCC1
MIN.
VIL1
Note2
Note2
High-level input voltage (2), VCC2
Conditions
VIH1
Note1
High-level input voltage (2), VCC2
Low-level input voltage (2), VCC2
Note1
VCC1 – 0.4
V
V
0.4
VCC1 – 0.4
V
V
0.4
VCC2 – 0.4
V
VOH3
IOH = –1 mA
Low-level output voltage (3), VCC2 Note5
V
VOL3
IOL = 2 mA
0.4
V
Input leakage current (1)
II1
Other than TEST pin,
±10
µA
100
µA
V1 = VCC2 or GND
Input leakage current (2)
II2
Pull down (TEST pin),
10
40
V1 = VCC2
•
•
•
•
Display operating current consumption (1)
Note6
IMAS1
Master, VCC1
100
µA
Display operating current consumption (2)
Note6
IMAS2
Master, VCC2
150
µA
Display operating current consumption (3)
Note6
ISLV1
Slave, VCC1
60
µA
Display operating current consumption (4)
Note6
ISLV2
Slave, VCC2
100
µA
2.4
kΩ
Liquid crystal driver output ON resistance Note7 RON
1.2
Notes 1. VCC1 signal (/FRM, STB, L1, L2, PULSE)
2. VCC2 signal (MS, DIR, PL0 and PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, /DOFF,
TEST, BMODE, CMODE0, CMODE1, DMODE)
3. /REFRH pin
4. /DOUT pin
5. D0 to D15, RDY, OSC2 pins
6. Frame frequency: 70 Hz, output: no load, not accessed by CPU
(D0 to D15, A0 to A16, /UBE = GND, /CS, /OE, /WE = VCC2)
7. Resistance between Y and V pins (any of V0, V1, and V2) when a load current (ION = 100 µ A) flows through
one pin of Y1 to Y208.
Data Sheet S13780EJ1V0DS00
35
µ PD16664
AC Characteristics 1 Display Data Transfer Timing
(1) Master Mode
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 2.4 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V,
TA = –20 to +70°C, frame frequency: 70 Hz (fOSC = 90.72 kHz at 1/160 duty, 72.8 kHz at 1/128 duty),
output load: 100 pF)
Parameter
Symbol
STB clock cycle time
tCYC
STB high-level width
tCWH
STB low-level width
tCWL
Conditions
MIN.
TYP.
MAX.
Unit
1/160 duty
87
8/fOSC
µs
1/128 duty
108
8/fOSC
µs
1/160 duty
43
4/fOSC
µs
1/128 duty
54
4/fOSC
µs
1/160 duty
43
4/fOSC
µs
1/128 duty
54
4/fOSC
µs
STB rise time
tR
100
ns
STB fall time
tF
100
ns
STB - /FRM delay time
tPSF
20
µs
/FRM - STB delay time
tPFS
20
µs
tCYC
tCWL
tCWH
tR
tF
0.9 VCC1
STB (output)
tPSF
tPFS
tPSF
0.1 VCC1
tPFS
0.9 VCC1
/FRM (output)
36
0.1 VCC1
Data Sheet S13780EJ1V0DS00
µ PD16664
(2) Slave mode
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 2.4 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V,
TA = –20 to +70 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
STB clock cycle time
tCYC
10
µs
STB high-level width
tCWH
4
µs
STB low-level width
tCWL
4
µs
STB rise time
tR
STB fall time
tF
/FRM setup time
tSFR
1
µs
/FRM hold time
tHFR
1
µs
150
150
ns
ns
tCYC
tCWL
tCWH
tF
tR
0.7 VCC1
STB (input)
tSFR
tHFR
tSFR
tHFR
0.3 VCC1
0.7 VCC1
/FRM (input)
0.3 VCC1
Data Sheet S13780EJ1V0DS00
37
µ PD16664
(3) Parameters Common to Master/Slave
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = –20 to +70°C)
{VCC2 = 3.0 to 3.6 V
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Output delay time (L1, L2)
tDOUT1
No output load
50
100
ns
Output delay time (Y1 to Y208)
tDOUT2
No output load
90
150
ns
TYP.
MAX.
Unit
{VCC2 = 2.4 to 3.0 V
Parameter
Symbol
Conditions
MIN.
Output delay time (L1, L2)
tDOUT1
No output load
120
ns
Output delay time (Y1 to Y208)
tDOUT2
No output load
180
ns
STB (output)
0.9 VCC1
tDOUT1
tDOUT1
L1, L2
0.9 VCC1
tDOUT2
tDOUT2
0.9 V2
0.1 V2
Y1 to Y208
0.9 V2
0.1 V2
38
Data Sheet S13780EJ1V0DS00
µ PD16664
AC Characteristics 2 Drawing Access Timing
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = –20 to +70°C,
tr = tf = 5 ns)
{VCC2 = 3.0 to 3.6 V
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
/OE,/WE recovery time
tRY
30
ns
Address setup time
tAS
10
ns
Address hold time
tAH
20
ns
RDY output delay time
tRYR
RDY float time
Note 1
Wait status time
Note 2
Ready status time (without conflict)
Ready status time (with conflict)
Data access time (read cycle)
Data float time (read cycle)
Note 2
Note 2
Note 3
Note 1
/CS - /OE time (read cycle)
CL = 15 pF
30
ns
tRYZ
30
ns
tRYW
35
ns
tRYF1
60
100
ns
tRYF2
650
1200
ns
tACS
100
ns
tHZ
40
ns
tCSOE
10
ns
/OE - /CS time (read cycle)
tOECS
20
ns
Write pulse width 1 (write cycle 1) Note 2
tWP1
50
ns
Note 2
tWP2
50
ns
Data setup time (write cycles 1, 2)
tDW
20
ns
Data hold time (write cycles 1, 2)
tDH
20
ns
/CS - /WE time (write cycles 1, 2)
tCSWE
10
ns
/WE - /CS time (write cycles 1, 2)
tWECS
20
ns
Reset pulse width
tWRES
100
ns
RDY - /OE time
tRDOE
Note 4
–
RDY - /WE time
tRDWE
Note 4
–
Write pulse width 2 (write cycle 2)
Notes 1. Load circuit
VCC2
1.8 kΩ
1.0 kΩ
5 pF
Data Sheet S13780EJ1V0DS00
39
µ PD16664
2. Load circuit
VCC2
1.8 kΩ
1.0 kΩ
60 pF
3. Load circuit
VCC2
1.8 kΩ
1.0 kΩ
100 pF
4. The display may be affected if the time from the rising of RDY to /OE or /WE is too long. It is recommended
that tRDOE and tRDWE be 1000 ns or less.
40
Data Sheet S13780EJ1V0DS00
µ PD16664
{VCC2 = 2.4 to 3.0 V
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
/OE,/WE recovery time
tRY
40
ns
Address setup time
tAS
20
ns
Address hold time
tAH
30
ns
RDY output delay time
tRYR
RDY float time
Note 1
Wait status time
Note 2
Ready status time (without conflict)
Ready status time (with conflict)
Data access time (read cycle)
Data float time (read cycle)
Note 2
Note 2
Note 3
Note 1
/CS - /OE time (read cycle)
CL = 15 pF
40
ns
tRYZ
40
ns
tRYW
50
ns
tRYF1
120
ns
tRYF2
1600
ns
tACS
120
ns
tHZ
50
ns
tCSOE
20
ns
/OE - /CS time (read cycle)
tOECS
30
ns
Write pulse width 1 (write cycle 1) Note 2
tWP1
60
ns
Note 2
tWP2
60
ns
Data setup time (write cycles 1, 2)
tDW
30
ns
Data hold time (write cycles 1, 2)
tDH
30
ns
/CS - /WE time (write cycles 1, 2)
tCSWE
20
ns
/WE - /CS time (write cycles 1, 2)
tWECS
30
ns
Reset pulse width
tWRES
120
ns
RDY - /OE time
tRDOE
Note 4
–
RDY - /WE time
tRDWE
Note 4
–
Write pulse width 2 (write cycle 2)
Notes 1. Load circuit
VCC2
1.8 kΩ
1.0 kΩ
5 pF
Data Sheet S13780EJ1V0DS00
41
µ PD16664
2. Load circuit
VCC2
1.8 kΩ
1.0 kΩ
60 pF
3. Load circuit
VCC2
1.8 kΩ
1.0 kΩ
100 pF
4. The display may be affected if the time from the rising of RDY to /OE or /WE is too long. It is recommended
that tRDOE and tRDWE be 1000 ns or less.
42
Data Sheet S13780EJ1V0DS00
µ PD16664
/OE,/WE Recovery Time
tRY
0.7 VCC2
/OE,/WE
0.3 VCC2
Read Cycle
0.7 VCC2
A16 to A0
/UBE
0.3 VCC2
tAS
tAH
0.7 VCC2
/CS
0.3 VCC2
0.3 VCC2
tCSOE
tOECS
tRDOE
0.7 VCC2
/OE
0.3 VCC2
tRYR
tRYW
tRYF
tRYZ
0.9 VCC2
RDY
0.1 VCC2
Hi-Z
0.1 VCC2
tACS
tHZ
OUT
D15 to D0
0.9 VCC2
0.1 VCC2
Data Sheet S13780EJ1V0DS00
43
µ PD16664
Write Cycle 1 (on writing display data)
0.7 VCC2
A16 to A0
/UBE
0.3 VCC2
tAH
tAS
0.7 VCC2
/CS
0.3 VCC2
0.3 VCC2
tCSWE
tRDWE
tWECS
0.7 VCC2
/WE
0.3 VCC2
tRYF
tRYR
tRYZ
tRYW
0.9 VCC2
RDY
0.1 VCC2
0.1 VCC2
Hi-Z
tWP1
0.7 VCC2
IN
D15 to D0
0.3 VCC2
tDW
tDH
Write Cycle 2 (on writing gray level palette)
0.7 VCC2
A16 to A0
/UBE
0.3 VCC2
tAH
tAS
/CS
0.3 VCC2
tWECS
tCSWE
0.7 VCC2
/WE
0.3 VCC2
tWP2
RDY
Hi-Z
0.7 VCC2
IN
D15 to D0
0.3 VCC2
tDW
44
Data Sheet S13780EJ1V0DS00
tDH
µ PD16664
Reset Pulse Width
/RESET
0.3 VCC2
tWRES
AC Characteristics 3 CR Oscillation
{VCC2 = 2.4 to 3.6 V, TA = –20 to +70 °C, 1/160 duty
Parameter
Oscillation frequency
Symbol
fOSC
Frame frequency
–
Conditions
MIN.
TYP.
MAX.
Unit
External resistor: 130 kΩ
80
95
110
kHz
External resistor: 130 kΩ
61.7
73.3
84.9
Hz
MIN.
TYP.
MAX.
Unit
External resistor: 160 kΩ
64
76
88
kHz
External resistor: 160 kΩ
61.5
73.1
84.6
Hz
{VCC2 = 2.4 to 3.6 V, TA = –20 to +70 °C, 1/128 duty
Parameter
•
•
Oscillation frequency
Frame frequency
Symbol
fOSC
–
Conditions
Data Sheet S13780EJ1V0DS00
45
µ PD16664
21. RELATION BETWEEN OSCILLATION FREQUENCY, FRAME FREQUENCY, AND STB
FREQUENCY
The relation between the oscillation frequency, frame frequency, and STB frequency is as follows:
1/160 duty
Frame frequency =
STB frequency =
1
× Oscillation frequency
162 × 2 × 4
1
× Oscillation frequency
2× 4
1/128 duty
Frame frequency =
STB frequency =
46
1
× Oscillation frequency
130 × 2 × 4
1
× Oscillation frequency
2× 4
Data Sheet S13780EJ1V0DS00
µ PD16664
22. PACKAGE DRAWINGS
Standard TCP Package Drawing (µPD16664N-001) (1/3)
Material
Polyimide UPILEX-S
t = 75 µm
Adhesive Epoxy
t = 12 µm
Copper
Electrolysis Cu t = 18 µm
Plating
Sn
t = 0.15 µm min
Solder Resist Epoxy
t = 25 µm
This products is single side Flex type.
This figure is shown by Copper side over Polymide.
All tolerances unless otherwise specified 0.05 mm.
Corner radius is 0.30 mm MAX.
13 Sprocket holes (61.75 mm) for 1 Pattern.
Data Sheet S13780EJ1V0DS00
47
µ PD16664
Standard TCP Package Drawing (µPD16664N-001) (2/3)
from P.C.
EIAJ test pad details
from P.C.
from P.C.
from P.C.
Alignment details
TCP tape winding direction
Output lead
Tape pull-up
direction
Wind-up direction
The Cu pattern side is
the underside of the tape
48
Data Sheet S13780EJ1V0DS00
µ PD16664
Standard TCP Package Drawing (µPD16664N-001) (3/3)
Pin configuration
No.1 DUMMY
V0
No.2
V1
No.3
V2
No.4
VCC1
No.5
GND
No.6
VCC2
No.7
GND
No.8
A0
No.9
A1
No.10
A2
No.11
A3
No.12
A4
No.13
A5
No.14
A6
No.15
A7
No.16
A8
No.17
A9
No.18
A10
No.19
A11
No.20
A12
No.21
A13
No.22
A14
No.23
A15
No.24
A16
No.25
D0
No.26
D1
No.27
D2
No.28
D3
No.29
D4
No.30
D5
No.31
D6
No.32
D7
No.33
D8
No.34
D9
No.35
D10
No.36
D11
No.37
D12
No.38
D13
No.39
D14
No.40
D15
No.41
VCC2
No.42
OSC1
No.43
OSC2
No.44
GND
No.45
DIR
No.46
PL0
No.47
PL1
No.48
No.49 /REFRH
No.50 /RESET
/UBE
No.51
/CS
No.52
/OE
No.53
/WE
No.54
RDY
No.55
/DOFF
No.56
TEST
No.57
No.58 BMODE
No.59 CMODE0
No.60 CMODE1
No.61 DMODE
MS
No.62
VCC2
No.63
GND
No.64
No.65 PULSE
/FRM
No.66
STB
No.67
No.68 /DOUT
L2
No.69
L1
No.70
VCC1
No.71
GND
No.72
V2
No.73
V1
No.74
V0
No.75
No.76 DUMMY
Data Sheet S13780EJ1V0DS00
DUMMY
DUMMY
Y208
Y207
Y206
Y205
Y204
Y203
Y202
Y201
Y200
Y199
No.1
No.2
No.3
No.4
No.5
No.6
No.7
No.8
No.9
No.10
No.11
No.12
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
DUMMY
DUMMY
No.201
No.202
No.203
No.204
No.205
No.206
No.207
No.208
No.209
No.210
No.211
No.212
49
µ PD16664
[MEMO]
50
Data Sheet S13780EJ1V0DS00
µ PD16664
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S13780EJ1V0DS00
51
µ PD16664
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8