DATA SHEET MOS INTEGRATED CIRCUIT ` µPD168001 MONOLITHIC 4-CHANNEL H BRIDGE + LOW-SIDE SWITCH DESCRIPTION The µPD168001 is a monolithic 4-channel H bridge driver and low-side switch IC that uses a power MOSFET at the output stage. Because of the MOSFET at the output stage, both the inputs and outputs are interfaced by PWM digital signals, and the power consumption can therefore be lowered. A 30-pin thin shrink SOP is employed as the package to help to create a small and thin set. FEATURES O Four H bridge circuits using power MOSFET and low-side switch O Low on-resistance 4-ch H bridge: 2 Ω MAX. (sum of upper and lower stages) Low-side switch: 2 Ω MAX. O High-speed PWM drive: Operating frequency up to 120 kHz O Thin 30-pin shrink SOP (7.62 mm (300) with 0.65 mm pitch) ORDERING INFORMATION Part Number µPD168001MC-6A4-A Package 30-pin plastic TSSOP (7.62 mm (300)) The information in this document is subject to change without notice. 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Document No. S15728EJ1V0DS00 (1st edition) Date Published March 2003 N CP(K) Printed in Japan © µPD168001 BLOCK DIAGRAM SEL 2 VDD 1 (9,13,18,22) VM IN1A IN1B 3 4 IN2A 5 IN2B 6 IN3A 30 IN3B 29 IN4A 28 IN4B 27 IN5 Controller 1 Controller 2 Controller 3 Controller 4 8 OUT1A 23 OUT1B 10 OUT2A 21 OUT2B 12 OUT3A 19 OUT3B 14 OUT4A 17 OUT4B 25 OUT5 H bridge 1 H bridge 2 H bridge 3 H bridge 4 26 Controller 5 GND (7,11,15,16,20,24) 2 Data Sheet S15728EJ1V0DS µPD168001 PIN CONFIGURATION Package: 30-pin TSSOP (7.62 mm with 0.65 mm pitch) VDD 1 30 IN3A SEL 2 29 IN3B IN1A 3 28 IN4A IN1B 4 27 IN4B IN2A 5 26 IN5 IN2B 6 25 OUT5 GND 7 24 GND OUT1A 8 23 OUT1B VM 9 22 VM OUT2A 10 21 OUT2B GND 11 20 GND OUT3A 12 19 OUT3B VM 13 18 VM OUT4A 14 17 OUT4B GND 15 16 GND Data Sheet S15728EJ1V0DS 3 µPD168001 PIN FUNCTION 4 Pin No. Pin Name Pin Function 1 VDD Logic power supply 2 SEL Control pin 3 IN1A Channel 1 input pin A 4 IN1B Channel 1 input pin B 5 IN2A Channel 2 input pin A 6 IN2B Channel 2 input pin B 7 GND GND pin 8 OUT1A Channel 1 output pin A 9 VM Motor power supply pin 10 OUT2A Channel 2 output pin A 11 GND 12 OUT3A Channel 3 output pin A 13 VM Motor power supply pin 14 OUT4A Channel 4 output pin A 15 GND GND pin 16 GND GND pin 17 OUT4B GND pin Channel 4 output pin B 18 VM Motor power supply pin 19 OUT3B Channel 3 output pin B 20 GND 21 OUT2B Channel 2 output pin B 22 VM Motor power supply pin 23 OUT1B Channel 1 output pin B 24 GND GND pin 25 OUT5 Channel 5 output pin GND pin 26 IN5 27 IN4B Channel 5 input pin Channel 4 input pin B 28 IN4A Channel 4 input pin A 29 IN3B Channel 3 input pin B 30 IN3A Channel 3 input pin A Data Sheet S15728EJ1V0DS µPD168001 FUNCTION SPECIFICATIONS (1) Revolution control A high-level/low-level binary signal is input to the H bridge driver block incorporating 4 outputs. The truth table of the input logic is shown below. VM VDD IN1A to 4A OUT1A to 4A IN1B to 4B OUT1B to 4B SEL Function Table (Common to All Channels) Input Output IN1A to IN4A IN1B to IN4B SEL 1A to 4A 1B to 4B L L H L L H L H H L L H H L H H H H H H − − L Hi-Z Hi-Z Data Sheet S15728EJ1V0DS 5 µPD168001 (2) Switching of H bridges VM When output A is switched in the figure shown on the right, a dead time (time for which both Pch and Nch are OFF) elapses to prevent through current. Pch Pch Consequently, the waveform of output A (rise time, fall time, and delay time) changes depending on whether output B is fixed to the high or low level. A The figure below shows the voltage waveform of output B in response to an B input waveform when output B is fixed to the low level and the high level. Nch Rise delay time (tTLH) Nch Fall delay time (tTHL) Input A waveform Dead time Output A when output B is fixed to low level Rise time (tTLH) Fall time (tTHL) Output A when output B is fixed to low level Dead time • When output B is fixed to low level Output A goes into a high-impedance state and is undefined during the dead time period, but a low level is output to output A because output B is pulled down by the load • When output B is fixed to high level Output A goes into a high-impedance state and is undefined during the dead time period, but a high level is output to output A because output B is pulled up by the load. 6 Data Sheet S15728EJ1V0DS µPD168001 (3) Low-side switch The low-side switch of ch 5 has an output stage configured of an N-ch MOSFET. Its input is a high-level/low-level binary signal. The truth table of the input logic is shown below. VM VDD M IN5 SEL Function Table (Channel 5) Input Output IN5 SEL OUT5 L H Hi-Z (output off) H H L (ouput on) − L Hi-Z (output off) (4) Power sequence This IC has logic power supply (VDD) and output power supply (VM) pins. The power sequence of these pins must be as follows. Turn on VM with VDD turned on to turn on power. To turn off power, turn off VM with VDD turned on, and then turn off VDD. (However, VDD and VM can be turned off at the same time.) Cautions 1. Because this IC switches a high current at high speeds, surge may be generated by VM, GND wiring, and inductance, degrading the IC. On the PWB, widen and shorten the pattern width of the GND lines as much as possible, and locate bypass capacitors between VM and GND as close to the IC as possible. Connect two capacitors in parallel: a magnetic capacitor with a low inductance (4700 pF or more) and an electrolytic capacitor of 10 µF or more, depending on the load current. 2. When a load such as a DC motor is connected to ch 5 and the switch is turned OFF, a counter electromotive force is generated. If the absolute maximum rating of the output pin voltage may be exceeded by the voltage applied to the load, be sure to connect a Schottky barrier diode to both the ends of the load to prevent the rating of the output pin voltage from being exceeded. Data Sheet S15728EJ1V0DS 7 µPD168001 ABSOLUTE MAXIMUM RATINGS (TA = 25°°C) Parameter Symbol Power supply voltage −0.5 to +6.0 V VM Motor block −0.5 to +6.0 V −0.5 to VDD+0.5 V 6.0 V Output pin voltage VOUT IDD DC ±0.3 A/ch IDP When two or more channels are turned ON at the same time PW ≤ 50 ms, Duty ≤ 5% ±1.0 A/ch Note 1 Power consumptionNote 2 Unit Control block VIN Instantaneous output current Rating VDD Input voltage DC output current Conditions PT Peak junction temperature TCH(MAX) Storage temperature Tstg 1.0 W 150 °C −55 to 150 °C Notes 1. DUTY indicates the period during which a current flows, exceeding IDD for the entire sequence 2. When mounted on a glass epoxy board (100 mm × 100 mm × 1 mm, with a copper foil area of 15%) RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Symbol Conditions MIN. TYP. MAX. Unit VDD Control block 3.0 3.3 3.6 V VMACT Motor block 4.5 5.0 5.5 V VDD V Input voltage VIN DC output current IDD DC ±0.2 A/ch Instantaneous output current IDP When two or more channels are turned ON at the same time PW ≤ 50 ms, Duty ≤ 5% ±0.85 A/ch Operating frequency fIN 120 kHz Operating temperature range TA 75 °C 8 0 0 Data Sheet S15728EJ1V0DS µPD168001 ELECTRICAL CHARACTERISTICS (UNLESS OTHERWISE SPECIFIED, VDD = 3.3 V, VM = 5 V, TA = 25°°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 1. DC characteristics VM pin current IM SEL = L 10 µA VDD pin current IDZ(OFF) SEL = L 10 µA Input pull-down resistance RIN IN and SEL pins 50 200 kΩ High-level input voltage VIH IN and SEL pins 0.7 × VDD VDD V Low-level input voltage VIL IN and SEL pins −0.3 0.3 × VDD V High-level input current IIH VIN = VDD 80 µA µA −2.0 Low-level input current IIL VIN = 0 V On-resistance (ch1 to 4, sum of upper and lower stages) RON ID = 0.2 A 2.0 Ω On-resistance (ch 5) RON ID = 0.2 A 2.0 Ω Switching current with no load on H Note bridge IS(AVE) Input frequency: 100 kHz 4.5 mA 2. AC characteristics 1 to 4ch With output of one side fixed to low Rise delay time tTLH 150 400 800 Rise time tTLH1 35 250 500 tTHL1 35 75 150 With output of one side fixed to high Fall delay time tTHL 150 500 800 Rise time tTHL2 35 75 150 35 300 600 tTLH3 100 200 tTHL3 50 100 Fall time Fall time Input frequency: 1 kHz tTHL2 Rise time 5ch Load: 20 Ω Fall time ns Note Average value of current consumed inside the H bridge when the switching operation is performed without a load. Data Sheet S15728EJ1V0DS 9 µPD168001 TIMING CHARTS • Channel 1 to Channel 4 When output B is fixed to low level 50% 50% Input waveform at A Fall delay time Rise delay time tTLH 90% 90% 50% 50% Voltage wavefrom at A 10% 10% Rise time tTLH1 Fall time tTHL1 When output B is fixed to high level 50% 50% Input waveform at A Fall delay time tTHL Rise delay time 90% Voltage wavefrom at A 90% 50% 50% 10% 10% Rise time tTLH2 Fall time tTHL2 • Channel 5 Input waveform 90% 90% Output waveform 10% 10% Rise time tTLH3 Rise time tTLH3 10 Data Sheet S15728EJ1V0DS µPD168001 POWER CONSUMPTION CHARACTERISTICS PT-TA Characteristics 1.4 100 mm × 100 mm × 1.0 mm when mounted on a glass epoxy board Power consumption PT (W) 1.2 25°C 1.0 W 1.0 125°C/W 0.8 0.6 0.4 0.2 75°C 0 –20 0 25 50 75 100 125 150 Ambient Temperature TA (°C) Data Sheet S15728EJ1V0DS 11 µPD168001 IDZ (OFF) -TA Characteristics IDZ (OFF) -VDD Characteristics 1 VDD = 3.6 V VDD Current IDZ (OFF) ( µ A) VDD Current IDZ (OFF) ( µ A) 1 0.8 0.6 0.4 0.2 0 –10 0 10 20 30 40 50 60 70 TA = 25°C 0.8 0.6 0.4 0.2 0 2.8 80 3 Ambient Temperature TA (°C) On Resistance RON1, RON2 (Ω) 1.5 RON1 1 RON2 10 20 30 40 50 60 70 80 1.5 RON1 1 0 4.4 4.6 4.8 5 5.2 5.4 RIN-VDD Characteristics 140 130 120 110 10 20 30 40 50 60 70 80 5.6 150 TA = 25°C 140 130 120 110 100 2.8 Ambient Temperature TA (°C) 12 RON2 0.5 RIN-TA Characteristics VDD = 3.6 V 0 TA = 25°C Supply Voltage TM (V) 150 100 –10 3.8 2 Ambient Temperature TA (°C) Input pull-down Resistance RIN (Ω) On Resistance RON1, RON2 (Ω) Input pull-down Resistance RIN (Ω) VDD = 3.6 V 0 3.6 RON1, RON2-VM Characteristics 2 0 –10 3.4 Supply Voltage VDD (V) RON1, RON2 Characteristics 0.5 3.2 Data Sheet S15728EJ1V0DS 3 3.2 3.4 3.6 Supply Voltage VDD (V) 3.8 µPD168001 VIH, VIL-VDD Characteristics VDD = 3.6 V 2.5 2 VIH 1.5 VIL 1 0.5 0 –10 0 10 20 30 40 50 60 70 80 Hi/Low Level Input Voltage VIH, VIL (V) Hi/Low Level Input Voltage VIH, VIL (V) VIH, VIL-TA Characteristics 3 3 TA = 25°C 2.5 2 VIH 1.5 VIL 1 0.5 0 2.8 3 3.2 800 VDD = 3.6 V 600 tTHL tTLH 200 0 –10 0 10 20 30 40 50 60 70 80 300 tTLH1 200 100 tTHL1 0 –10 0 10 20 30 40 50 60 tTLH2, tTHL2-TA Characteristics tTLH3, tTHL3-TA Characteristics 400 tTHL2 300 200 tTLH2 0 VDD = 3.6 V Ambient Temperature TA (°C) VDD = 3.6 V 0 –10 400 Ambient Temperature TA (°C) 500 100 10 20 30 40 50 3.8 tTLH1, tTHL1-TA Characteristics Rising/Falling Time tTLH1, tTHL1 (ns) tTLH, tTHL-TA Characteristics 400 3.6 Supply Voltage TDD (V) Rising/Falling Time tTLH2, tTHL2 (ns) Rising/Falling Time tTLH2, tTHL2 (ns) Rising/Falling Delay Time tTLH, tTHL (ns) Ambient Temperature TA (°C) 3.4 60 70 80 70 80 200 VDD = 3.6 V 150 100 tTLH3 50 tTHL3 0 –10 Ambient Temperature TA (°C) Data Sheet S15728EJ1V0DS 0 10 20 30 40 50 60 70 80 Ambient Temperature TA (°C) 13 µPD168001 PACKAGE DRAWING 30-PIN PLASTIC TSSOP (7.62mm(300)) 30 16 detail of lead end F G T P L 1 U 15 E A H A' I J S C D M N M B NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 14 Data Sheet S15728EJ1V0DS S K ITEM MILLIMETERS A A' 9.85±0.10 9.7±0.1 B 0.375 C 0.65 (T.P.) D 0.24±0.05 E 0.1±0.05 F 1.2 MAX. G 1.0±0.05 H 8.1±0.1 I 6.1±0.1 J 1.0±0.1 K 0.145±0.025 L 0.5 M 0.10 N 0.10 P +5° 3° −3° T 0.25 U 0.6±0.15 S30MC-65-6A4 µPD168001 RECOMMENDED SOLDERING CONDITIONS The µPD168001 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) µPD168001MC-6A4-A 30pin plastic TSSOP (7.62mm (300)) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher), Count: Three times or less, Exposure limit: None, IR60-00-3 Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended Caution Do not use different soldering methods together (except for partial heating). Data Sheet S15728EJ1V0DS 15 µPD168001 [MEMO] 16 Data Sheet S15728EJ1V0DS µPD168001 [MEMO] Data Sheet S15728EJ1V0DS 17 µPD168001 [MEMO] 18 Data Sheet S15728EJ1V0DS µPD168001 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15728EJ1V0DS 19 µPD168001 • The information in this document is current as of March, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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