DATA SHEET MOS INTEGRATED CIRCUIT µ PD168103 5-CHANNEL OPERATIONAL AMPLIFIER, IRIS DRIVER, AND 4-CHANNEL H-BRIDGE DRIVER DESCRIPTION The µ PD168103 is the motor driver IC with IRIS control circuit, operational amplifier and 4-ch H-bridge output. Smooth operation is possible for IRIS control with linear method. The package is 48-pin thin type QFN and then it helps reduce the mounting area and height. The µ PD168103 is suitable for the lens drive of a camcorder, DSC, etc. FEATURES • 5-ch H-bridge circuits employing power MOS FET • Low-voltage driving LVDD = 2.7 to 3.6 V, AVDD = 4.5 to 5.5 V, VM12 = VM34 = VSHUTTER = VIRIS = 2.7 to 5.5 V • Output on-state resistance: 2.0 Ω TYP., 3.0 Ω MAX. (4-ch H-bridge block, sum of top and bottom stage, VM = 5 V) • PWM output (ch1 to ch4) • Output current DC current: ±0.3 A/ch (when each channel is used independently) Peak current: ±0.7 A/ch (when each channel is used independently) • 3-ch general-purpose operational amplifier Input offset voltage: ±5 mV Input voltage range: 0 to AVDD − 1.5 V Output voltage range: 0.2 to AVDD − 0.2 V • 1-ch current sink amplifier Output current: 5 mA • 1-ch 1/2VDD output amplifier • IRIS driver block supporting linear driving • Pre-driver amplifier of the IRIS driver block • Undervoltage lockout circuit Output circuit and amplifier stop at LVDD = 1.7 V TYP. or less. • Overheat protection circuit Operates at 150°C or more and shuts down the output circuit. • Mounted on 48-pin plastic WQFN (7 x 7) APPLICATIONS Lens motor driving for DVC and DSC, etc. ORDERING INFORMATION Part Number µ PD168103K9-5B4-A Note Package Marking 48-pin plastic WQFN (7 x 7) D168103 Packing Type • Tray stuffing • Dry pack Note Pb-free (This product does not contain Pb in external electrode and other parts.) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S17332EJ1V0DS00 (1st edition) Date Published February 2005 NS CP(K) Printed in Japan 2004 µ PD168103 1. BLOCK DIAGRAM VM12 OUT1A OUT1B PGND12 OUT2A OUT2B 45 42 44 43 47 46 H-bridge 1 48 VM34 OUT3A OUT3B PGND34 OUT4A OUT4B 16 H-bridge 2 19 17 18 14 15 13 H-bridge 4 H-bridge 3 H-bridge Control EN12 4 7 EN34 IN1 5 8 IN3 IN2 6 9 IN4 10 RESETB 3 IRIN1 11 GND 2 27 IRIN2 VSUTTER LVDD 1 31 VIRIS 33 INIRP INIRM AVDD 12 IRIS Control LVDD UVLO Logic power AVDD TSD Analog power + − LVDD INREF 34 − + 35 AVDD AVDD AVDD AVDD + − + − + − + − AMP2 AMP1 39 40 IN1P IN1M 41 36 37 AMP3 38 OUT1 IN2P IN2M 24 25 OUT2 IN3P IN3M 28 OUTIRP OUTIRM 29 PGND5 21 OUT4D 30 AMP5 Amp. ON/OFF control 1/2LVDD OUTREF GND Amp. Control AMP0 32 AMP4 26 23 22 OUT3 IN4P IN4M 20 OUT4S Cautions 1. P in pin name means plus, and M in pin name means minus. 2. A pull-down resistor (50 to 200 kΩ) is connected to the logic input pins (EN12, EN34, IN1, IN2, IN3, and IN4). A pull-up resistor (50 to 200 kΩ) is connected to the IRIN1 and IRIN2 pins. 2 Data Sheet S17332EJ1V0DS µ PD168103 2. PIN FUNCTIONS (1/2) Pin No. Pin Name I/O Function 1 LVDD − Logic power supply voltage pin 2 GND − Logic and analog GND pin 3 RESETB Input Reset input pin 4 EN12 Input ch1 and ch2 output control input pin 5 IN1 Input ch1 input pin 6 IN2 Input ch2 input pin 7 EN34 Input ch3 and ch4 output control input pin 8 IN3 Input ch3 input pin 9 IN4 Input ch4 input pin 10 IRIN1 Input IRIS control logic input pin 1 11 IRIN2 Input IRIS control logic input pin 2 12 AVDD − 13 OUT4B 14 PGND34 15 OUT4A 16 VM34 17 OUT3B 18 PGND34 19 OUT3A Output ch3 output pin A 20 OUT4S Output Amplifier 4 (AMP4) source output pin (source) 21 OUT4D Output Amplifier 4 (AMP4) drain output pin (sink) 22 IN4M Input Amplifier 4 (AMP4) minus input pin 23 IN4P Input Amplifier 4 (AMP4) plus input pin 24 IN3P Input Amplifier 3 (AMP3) plus input pin 25 IN3M Input Amplifier 3 (AMP3) minus input pin 26 OUT3 Output 27 VSHUTTER − 28 OUTIRM Output 29 PGND5 − 30 OUTIRP Output 31 VIRIS − 32 INIRM Input IRIS linear control (AMP5) minus input pin 33 INIRP Input IRIS linear control (AMP5) plus input pin 34 INREF Input 1/2AVDD amplifier (AMP0) input pin (for capacitor connection) Output − Output − Output − Analog power supply voltage pin ch4 output pin B ch3 and ch4 GND pin ch4 output pin A ch3 and ch4 power supply voltage pin ch3 output pin B ch3 and ch4 GND pin Amplifier 3 (AMP3) output pin Shutter (ON/OFF) power supply voltage pin IRIS minus output pin IRIS and shutter GND pin IRIS plus output pin IRIS (linear) power supply voltage pin Data Sheet S17332EJ1V0DS 3 µ PD168103 (2/2) Pin No. 4 Pin Name I/O Output Function 35 OUTREF 36 IN2P Input Amplifier 2 (AMP2) plus input pin 37 IN2M Input Amplifier 2 (AMP2) minus input pin 38 OUT2 39 IN1P Input Amplifier 1 (AMP1) plus input pin 40 IN1M Input Amplifier 1 (AMP1) minus input pin 41 OUT1 Output Amplifier 1 (AMP1) output pin 42 OUT1A Output ch1 output pin A 43 PGND12 44 OUT1B 45 VM12 46 OUT2A 47 PGND12 48 OUT2B Output − Output − Output − Output 1/2AVDD amplifier (AMP0) output pin Amplifier 2 (AMP2) output pin ch1 and ch2 GND pin ch1 output pin B ch1 and ch2 power supply voltage pin ch2 output pin A ch1 and ch2 GND pin ch2 output pin B Data Sheet S17332EJ1V0DS µ PD168103 3. FUNCTION OPERATION TABLE 3.1 Reset Function The internal circuit is shut off and the circuit current is kept to 1 µA MAX. when the RESETB pin is made L (reset status). In this status, the output pin goes into a Hi-Z (High impedance) state. Set the RESETB pin H for normal usage. Remark H: High level, L: Low level 3.2 Stepping Motor Driving Block Table 3−1. I/O Truth Table of the Stepping Motor Driving Block EN12, EN34 IN1, IN2, IN3, IN4 OUT1A, OUT2A, OUT3A, OUT4A OUT1B, OUT2B, OUT3B, OUT4B H L H L H L H L Hi-Z Hi-Z H Hi-Z Hi-Z L Data Sheet S17332EJ1V0DS 5 µ PD168103 3.3 IRIS Motor Driving Block Table 3−2. I/O Truth Table of the IRIS Driving Block IRIN1 IRIN2 L Operation Mode L Normal operation Output State of H-bridge Q1 Q2 Q3 Q4 ON OFF OFF ON (Amp. control) OUTIRP OUTIRM Linear Linear (Linear) L H Shutter OFF ON ON OFF L H H L IRIS open ON OFF OFF ON H L H H Output all OFF OFF OFF OFF OFF Hi-Z Hi-Z Figure 3−1. Description of the Operation Figure of the IRIS Motor Driving Block VIRIS INIRP INIRM + − VSHUTTER Q4 Q2 OUT7A OUT7B Q3 Q1 Normal Shutter VSHUTTER VIRIS INIRP INIRM + − Q4 OUTIRP OUTIRM OUTIRP OUTIRM Open All OFF VIRIS OUTIRP 6 VIRIS OUTIRM OUTIRP Data Sheet S17332EJ1V0DS VSHUTTER OUTIRM µ PD168103 4. FUNCTIONAL DEPLOYMENT 4.1 Undervoltage Lockout (UVLO) Circuit This function is to forcibly stop the operation of the µ PD168103 to prevent malfunctioning if LVDD drops. When UVLO operates, the driver output and amplifier circuit are the OFF status. The UVLO circuit detects a voltage drop if LVDD drops to 1.7 V TYP. in the non-reset status (RESETB = H). In the reset status (RESETB = L), it detects a voltage drop if LVDD drops to 0.6 V TYP. This circuit may not operate if the LVDD voltage abruptly drops for just a few µs. 4.2 Overheat Protection (TSD) Circuit This function is to forcibly stop the operation of the driver output to protect it from destruction due to overheating if the chip temperature of the µ PD168103 rises. The overheat protection circuit operates when the chip temperature rises to 150°C or more. When overheat is detected, the driver output is stopped. When RESETB = L (the reset status) or when UVLO is detected, the overheat protection circuit does not operate. 4.3 Power Up Sequence The µ PD168103 has a circuit that prevents current from flowing into the VM, VSHUTTER and VIRIS pins (from the next, these are written as the motor power supply pins) when LVDD = 0 V or AVDD = 0 V. Therefore, the current that flows into the motor power supply pins are cut off when LVDD = 0 V. Because the LVDD pin voltage, the AVDD pin voltage and the motor power supply pins voltage are monitored, a current of 1 µA TYP. flows into each one of the motor power supply pins when LVDD is applied. Data Sheet S17332EJ1V0DS 7 µ PD168103 5. NOTE ON CORRECT USE 5.1 Pin Processing of Unused Circuit The input/output pins of an unused circuit must be processed as specified below. A pull-down or pull-up resistor is connected inside to the logic input pins. Connect the input pins to the GND or LVDD (INIR1 and INIR2) potential when they are not used. A pull-down resistor is not connected to the RESETB pin. Be sure to fix the RESETB pin to the LVDD or GND potential when it is used. 5.2 OUT4S pin Keep the voltage in the OUT4S pin to 2 V or less. If an application circuit like the one shown below is used, the input voltage range of the amplifier is also 2 V or less. IN4P IN4M + − OUT4D OUT4S 8 Data Sheet S17332EJ1V0DS µ PD168103 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area of 15%) Parameter Symbol Power supply voltage Input voltage Note1 Rating Unit LVDD Control block Condition −0.5 to +6.0 V AVDD Analog block −0.5 to +6.0 V VM12, VM34 Stepping motor block −0.5 to +6.0 V VSHUTTER, VIRIS IRIS block VIN Output pin voltage 1 VOUT1 −0.5 to +6.0 V −0.5 to LVDD + 0.5 V 6.2 V Motor block Output pin voltage 2 VOUT2 Amplifier block −0.5 to AVDD + 0.5 V DC output current ID1(DC) DC (stepping motor) ±0.3 A/ch ID2(DC) DC (IRIS) ±0.2 A/ch Instantaneous output current ID(pulse) PW < 10 ms, Duty Cycle ≤ 20% ±0.7 A/ch Power consumption PT 1.0 W Tch(MAX) 150 °C −55 to +150 °C Peak junction temperature Note2 Storage temperature Tstg Notes 1. Keep VIN to less than 6 V. 2. The overheat protection circuit operates at Tch > 150°C. When overheat is detected, all the circuits are stopped. The overheat protection circuit does not operate at reset or on detection of ULVO. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = 25°C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area of 15%) Parameter Power supply voltage Symbol Condition MIN. TYP. MAX. Unit LVDD Control block 2.7 3.6 V AVDD Analog block 4.5 5.5 V VM12, VM34 Stepping motor block 2.7 5.5 V VSHUTTER, VIRIS IRIS block 2.7 5.5 V 0 VDD V −0.2 +0.2 A/ch −0.1 +0.1 A/ch Input voltage VIN DC output current ID1(DC) DC (stepping motor, when 2 chs are driven at same time) ID2(DC) DC (IRIS), maximum current when the shutter operates Amplifier output current IOUT_AMP1 AMP1 to AMP3 −5 +5 mA/ch Amplifier output sink current IOUT_AMP2 AMP4 0 +5 mA Logic input frequency fIN 100 kHz Operating temperature range TA 70 °C −10 Caution Design each output current so that the junction temperature does not exceed 150ºC. Data Sheet S17332EJ1V0DS 9 µ PD168103 Electrical Characteristics (Unless otherwise specified, TA = 25°C, LVDD = 3.0 V, AVDD = 5.0 V, VM = VSHUTTER = VIRIS = 5.0 V) Overall and H-bridge block (stepping motor) Parameter Symbol Condition MIN. TYP. MAX. Unit LVDD pin current in standby mode ILVDD(STB) RESETB = 0 V 1.0 µA AVDD pin current in standby mode IAVDD(STB) RESETB = 0 V 1.0 µA VM pin current in standby mode IVM(STB) RESETB = 0 V 1.0 µA LVDD pin current in during operation IDD(ACT) RESETB = LVDD 2.0 mA High-level input current IIH VIN = LVDD 60 µA Low-level input current IIL VIN = 0 V Input pull-down resistance RIND 50 High-level input voltage VIH 0.7 x VDD Low-level input voltage VIL H-bridge on-state resistance Ron µA −1.0 IM = 0.2 A, sum of upper and lower 200 kΩ 0.3 x VDD V 3.0 Ω 1.0 µA V 2.0 stages Output leakage current Note 1 IM(off) Per VM pin, All control pins: low level VDDS1 RESETB = H 1.7 2.5 V Output turn-on time ton RL = 20 Ω 0.5 1.0 µs Output turn-off time toff 0.1 0.4 µs Output rise time tr 0.2 0.4 µs Output fall time tf 50 100 ns Low-voltage detection voltage Note 2 0.05 Notes 1. µ PD168103 has a circuit that prevents current from flowing into the VM pin when LVDD = 0 V. 2. Unlike normal operations, after a reset the detection voltage becomes 0.6 V TYP. Figure 6−1. Switching Characteristic Waveform of the Stepping Motor Driving Block 100% VIN 50% 50% 0% ton ton toff toff 100% 100% 90% 90% 50% IDR 0% tf 50% 10% −10% 10% −10% −50% −50% −90% tr 10 −90% −100% Data Sheet S17332EJ1V0DS tf tr µ PD168103 H-bridge block (IRIS motor) Parameter Symbol Condition MIN. TYP. MAX. Unit VIRIS pin current in standby mode IVIRIS(STB) RESETB = 0 V 1.0 µA VSHUTTER pin current in standby mode IVSHUTTER(STB) RESETB = 0 V 1.0 µA High-level input current IIH VIN = LVDD 1.0 µA Low-level input current IIL VIN = 0 V Input pull-up resistance RIND 50 High-level input voltage VIH 0.7 x VDD Low-level input voltage VIL H-bridge on-state resistance Ron1 µA −60 RL = 50 Ω, sum of upper and 200 kΩ V 0.3 x VDD V 2.5 3.5 Ω lower stages Output turn-on time tonH1 When linear driving, RL = 50 Ω 0.01 25 35 µs tonH2 When full ON, RL = 50 Ω 0.01 1.0 2.0 µs 0.01 1.0 2.0 µs Output turn-off time toffH Output rise time trH 60 ns Output fall time tfH 80 ns Control amplifier offset voltage VIO AMP5 ±5 ±7.5 mV Figure 6−2. Switching Characteristic Waveform of the IRIS Motor Driving Block at IRIN1 = L 100% IRIN2 50% 50% 0% ton ton toff toff Linear operation Linear operation 100% 0% IIRIS 100% 50% 50% −10% −10% −50% −50% −90% tr −90% −100% tf Shutter Data Sheet S17332EJ1V0DS 11 µ PD168103 Operational amplifier block Parameter Symbol Condition MIN. TYP. MAX. Unit 3.0 mA AVDD pin current in during operation IADD Output open Input offset voltage 1 VIO1 AMP1 to AMP3, AMP5 ±3 ±5 mV Input offset voltage 2 VIO2 AMP4 ±5 ±7 mV Common mode input voltage range 1 VICM1 AMP1 to AMP3, AMP5 0 AVDD − 1.5 V Common mode input voltage range 2 VICM2 AMP4 0 AVDD − 2.0 V High-level output voltage VOH AMP1 to AMP3, when IOUT = +2 mA Low-level output voltage VOL AMP1 to AMP3, when IOUT = −2 mA Large amplitude voltage gain AV AMP1 to AMP3, DC Slew-rate SR AMP1 to AMP3, AV = 1 dB ,RL ≥ 10 kΩ 1/2 AVDD output voltage accuracy VO AMP0, IOUT = ±100 µA 12 Data Sheet S17332EJ1V0DS AVDD − 0.2 V 0.2 80 dB V/µs 0.5 2.4 V 2.5 2.6 V µ PD168103 7. TYPICAL CHARACTERISTICS (Unless otherwise specified, TA = 25°C, LVDD = 3.0 V, AVDD = VM = VSHUTTER = VIRIS = 5.0 V) PT vs. TA CHARACTERISTIC Ron - H-bridge On-state Resistance - Ω Ron vs. TA CHARACTERISTIC (H-bridge 1 to 4) PT - Total Power Dissipation - W 1.2 1 125˚C/W 0.8 0.6 0.4 0.2 0 0 2.5 OUT4B → OUT4A OUT1A → OUT1B OUT4A → OUT4B OUT1B → OUT1A 2 1.5 1 10 20 30 40 50 60 70 80 90 100 -40 -20 TA - Ambient Temperature - ℃ 40 60 80 100 IIH, IIL vs. LVDD CHARACTERISTIC 2.5 70 OUTIR− → OUTIR+ IIH, IIL - Input Pin Current - µA Ron - H-bridge On-state Resistance - Ω 20 TA - Ambient Temperature - ℃ Ron vs. TA CHARACTERISTIC (H-bridge IRIS) 2 OUTIR+ → OUTIR− 1.5 60 IIH 50 40 30 20 IIL 10 1 0 -40 -20 0 20 40 60 80 100 0 TA - Ambient Temperature - ℃ 1 2 3 4 5 6 7 LVDD - Power Supply Voltage of Control Block - V VIH, VIL vs. LVDD CHARACTERISTIC UNDERVOLTAGE LOCKOUT CIRCUIT CHARACTERISTIC 2.5 4 3 VIH VIL 2 1 0 0 1 2 3 4 5 6 7 VDDS - Undervoltage Detection Voltage - V 5 VIH, VIL - Input Voltage - V 0 2 LVDD(L→H) 1.5 LVDD(H→L) 1 0.5 LVDD - Power Supply Voltage of Control Block - V Data Sheet S17332EJ1V0DS 0 0 1 2 3 4 5 6 7 VM - Power Supply Voltage of Motor Block - V 13 µ PD168103 Ron vs. VIRIS, VSHUTTER CHARACTERISTIC Ron - H-bridge On-state Resistance of IRIS Block - Ω Ron - H-bridge On-state Resistance - Ω Ron vs. VM CHARACTERISTIC 3.5 3 2.5 2 1.5 1 0.5 IM = 200 mA 0 0 1 2 3 4 5 6 7 VM - Power Supply Voltage of Motor Block - V 4 3.5 IRIS 3 Shutter 2.5 2 1.5 1 0.5 IM = 100 mA 0 0 1 1 TONH 0.6 0.4 TOFFH 0.2 0 2 3 4 5 6 7 VM - Power Supply Voltage of Motor Block - V Tr - IRIS H-bridge Output Circuit Rise Time - µs Tf - IRIS H-bridge Output Circuit Fall Time - µs TONH - H-bridge Output Circuit Turn-on Time - µs TOFFH - H-bridge Output Circuit Turn-off Time - µs RL = 20 Ω 1 0.8 RL = 20 Ω 0.6 0.5 Tf 0.4 0.3 0.2 Tr 0.1 0 1 2 3 4 5 6 7 VM - Power Supply Voltage of Motor Block - V 14 5 6 7 0.4 RL = 50 Ω 0.35 0.3 0.25 Tr 0.2 0.15 0.1 Tf 0.05 0 0 1 2 3 4 5 6 7 VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V TONH1, TOFFH vs. VIRIS, VSHUTTER CHARACTERISTIC (when Linear) TONH1 - IRIS H-bridge Output Circuit Turn-on Time - µs TOFFH - IRIS H-bridge Output Circuit Turn-off Time - µs Tr - H-bridge Output Circuit Rise Time - µs Tf - H-bridge Output Circuit Fall Time - µs Tr, Tf vs. VM CHARACTERISTIC 0.7 4 Tr, Tf vs. VIRIS, VSHUTTER CHARACTERISTIC (when full ON) 1.2 0 3 VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V TONH, TOFFH vs. VM CHARACTERISTIC 0.8 2 Data Sheet S17332EJ1V0DS 10 RL = 50 Ω 9 8 7 TONH1 6 5 4 3 2 1 TOFFH 0 0 1 2 3 4 5 6 7 VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V µ PD168103 TONH1, TOFFH vs. VIRIS, VSHUTTER CHARACTERISTIC (when full ON) Tr - IRIS H-bridge Output Circuit Rise Time - µs Tf - IRIS H-bridge Output Circuit Fall Time - µs 14 RL = 50 Ω 12 10 Tr 8 6 4 Tf 2 0 0 1 2 3 4 5 6 7 VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V TONH1 - IRIS H-bridge Output Circuit Turn-on Time - µs TOFFH - IRIS H-bridge Output Circuit Turn-off Time - µs Tr, Tf vs. VIRIS, VSHUTTER CHARACTERISTIC (when Linear) 1.2 RL = 50 Ω 1 TONH1 0.8 0.6 0.4 0.2 TOFFH 0 0 2 3 4 5 6 7 VIRIS, VSHUTTER - Power Supply Voltage of IRIS Block - V IM vs. VM CHARACTERISTIC ILVDD vs. LVDD CHARACTERISTIC 8 700 RESETB: H EN, IN: L 7 ILVDD - LVDD Pin Current - µA IM - VM Pin Current when OFF - µA 1 6 5 4 3 2 1 RESETB: H EN, IN: L 600 500 400 300 200 100 0 0 0 1 2 3 4 5 6 7 VM - Power Supply Voltage of Motor Block - V Data Sheet S17332EJ1V0DS 0 1 2 3 4 5 6 7 LVDD - Power Supply Voltage of Control Block - V 15 µ PD168103 8. STANDARD CONNECTION EXAMPLE AVDD = 4.5 to 5.5 V LVDD = 2.7 to 3.6 V VM = 2.7 to 5.5 V DC/DC Converter Motor 1 Motor 2 1 to 10 µ F Battey VM12 OUT1A OUT1B PGND12 OUT2A OUT2B H-bridge 1 IRIS-CTL H-GAIN CPU H-bridge 3 H-bridge 2 EN34 IN3 IN4 H-REF VM34 OUT3A OUT3B PGND34 OUT4A OUT4B H-bridge 4 H-bridge Control EN12 HALL-AD IRIN1 IRIN2 EN34 IN1 IN3 IN2 IN4 CPU CDS Reset RESETB LVDD UVLO Logic power AVDD VIRIS TSD Analog power GND Amp. Control AMP0 AMP5 Amp. ON/OFF control 1/2LVDD − + OUTIRP OUTIRM PGND5 OUTREF AVDD AVDD AVDD AVDD + − + − + − + − AMP2 AMP1 IRIS-CTL IN1P IN1M OUT1 IN2P IN2M AMP3 OUT2 IN3P IN3M Position Detection Circuit AVDD H 16 H-REF INIRP INIRM + − LVDD INREF IRIN2 VSUTTER LVDD GND AVDD IRIN1 IRIS Control + − Data Sheet S17332EJ1V0DS OUT4D AMP4 OUT3 IN4P IN4M OUT4S DR+ DR− µ PD168103 9. PACKAGE DRAWING 48-PIN PLASTIC WQFN (7x7) HD D D HD /2 /2 /2 36 37 4−C0.5 25 24 detail of P part A E A2 E S HE /2 HE c 48 1 13 12 x4 ZE f ZD y A1 S A B terminal section c2 P y1 S c1 S S x4 t B S A B b1 b (UNIT:mm) ITEM A D 6.75 E 6.75 f 0.20 HD 7.00 HE 7.00 t 0.20 A A1 A2 e 0.08MIN. b x M Lp S A B 0.08MIN. NOTES 1 "t" AND "f" EXCLUDES MOLD FLASH 2 ALTHOUGH THERE ARE 4 TERMINALS IN THE CORNER PART OF A PACKAGE, THESE TERMINALS ARE NOT DESIGNED FOR INTERCONNECTION, BUT FOR MANUFACTURING PROCESS OF THE PACKAGE, THEREFOR DO NOT INTEND TO SOLDER THESE 4 TERMINALS, SOLDERABLITY OF THE 4 TERMINALS ARE NOT GUARANTEED. DIMENSIONS 0.67 +0.08 −0.04 0.03 +0.02 −0.025 0.64 b 0.23±0.05 b1 0.20±0.03 c 0.17 c1 0.14∼0.16 c2 0.14∼0.20 e 0.50 Lp 0.40±0.10 x 0.05 y 0.08 y1 0.10 ZD 0.625 ZE 0.625 P48K9-50-5B4-1 Data Sheet S17332EJ1V0DS 17 µ PD168103 10. RECOMMENDED SOLDERING CONDITIONS The µ PD168103 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Type of Surface Mount Device µ PD168103K9-5B4-A Note1 : 48-pin plastic WQFN (7 x 7) Process Infrared reflow Conditions Symbol Package peak temperature: 260°C, Time: 60 seconds MAX. (at 220°C or higher) , Count: Three times or less, Exposure limit: 3 days Note2 IR60-103-3 (after that, prebake at 125°C for 10 hours) , Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. <Precaution> Products other than in heat-resistant trays (such as those packaged in a magazine, taping, or non-thermal-resistant tray) cannot be baked in their package. Notes 1. Pb-free (This product does not contain Pb in external electrode and other parts.) 2. After opening the dry pack, store it a 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 18 Data Sheet S17332EJ1V0DS µ PD168103 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S17332EJ1V0DS 19 µ PD168103 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) • The information in this document is current as of February, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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