DATA SHEET MOS INTEGRATED CIRCUIT µ PD168302 MONOLITHIC 2CH H-BRIDGE DRIVER DESCRIPTION The µPD168302 is monolithic dual H-bridge driver LSI which uses power MOS FETs in the output stages. By using the MOS process, this driver has substantially improved the voltage loss of the output stage and power consumption as compared with conventional driver using bipolar transistors. As the package, a 24-pin plastic TSSOP is adopted to enable the creation of compact, slim application sets. It is provided with forward/reverse and brake functions and is ideal as a driver for DC motor and stepping motor. FEATURES • 2ch H-Bridge circuit employing power MOS FETs • Charge-pump circuit for low-voltage operation • Low output FET on resistance: 1.0 Ω TYP. 2.0 Ω MAX. (Sum of upper and lower side) • Output current: DC current 0.6 A/ch Peak current 1.0 A/ch • Input logic frequency: 100 kHz • 5 V logic power supply: Minimum operating supply voltage 4.0 V • 0.9 to 3.6 V power supply for motor drive • Under voltage locked out circuit: shutdown internal circuit at VDD = 1.7 V TYP. • 24-pin plastic TSSOP (5.72 mm (225), 0.5 mm pitch) ORDERING INFORMATION Part Number Package µ PD168302MA-6A5 24-pin plastic TSSOP (5.72 mm (225)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16402EJ1V0DS00 (1st edition) Date Published May 2003 NS CP (K) Printed in Japan 2003 µPD168302 1. BLOCK DIAGRAM VDD C1H C1L C2H C2L VG UVLO VM Note3 Oscillator Circuit Charge-pump Circuit VM1 Note3 BGR Circuit /STB Note2 IN1 Note2 IN2 Note2 IN3 Note2 IN4 Note2 Control Circuit Control Circuit Level Shift Circuit Level Shift Circuit MOS H-bridge Circuit 1 OUT1A MOS H-bridge Circuit 2 OUT2A OUT1B OUT2B VM2 Note3 LGND PGND1 Note1, 4 PGND2 Note1, 4 Notes 1. The terminal which has more than one should connect not only one terminal but all terminals. 2. Pull down resistance (50 to 200 kΩ) is connected to the input terminal. 3. It is recommended that VM terminal is connected to the terminal which either VM1 or VM2 is higher. 4. It is recommended that the voltage of PGND1 and PGND2 is not lower value than GND. 2 Data Sheet S16402EJ1V0DS µPD168302 2. PIN CONNECTION C1L 1 24 C2L C1H 2 23 C2H VG 3 22 VM VDD 4 21 LGND 5 20 PGND2 OUT1A 6 19 OUT2A VM1 18 VM2 OUT1B 7 8 17 OUT2B PGND1 9 16 PGND2 10 11 15 N.C. IN1 14 IN3 IN2 12 13 IN4 PGND1 /STB 3. PIN FUNCTIONS PACKAGE: 24-pin plastic TSSOP (5.72 mm (225), 0.5 mm pitch) Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C1L C1H VG VDD PGND1 OUT1A VM1 OUT1B PGND1 /STB IN1 IN2 IN4 IN3 N.C. PGND2 OUT2B VM2 OUT2A PGND2 LGND VM C2L C2H Pin Function Capacitor connect pin for charge-pump circuit Capacitor connect pin for charge-pump circuit Gate voltage pin Power supply pin for logic circuit Power GND pin Output A pin for ch1 Power supply pin for power circuit Output B pin for ch1 Power GND pin Standby pin Input logic 1 pin for ch1 Input logic 2 pin for ch1 Input logic 4 pin for ch2 Input logic 3 pin for ch2 (No connect) Power GND pin Output B pin for ch2 Power supply pin for power circuit Output A pin for ch2 Power GND pin Logic GND pin Power supply pin for power circuit Capacitor connect pin for charge-pump circuit Capacitor connect pin for charge-pump circuit Cautions 1. The terminal which has more than one should connect not only one terminal but terminals. 2. Please recommend connecting unused pins to GND. Data Sheet S16402EJ1V0DS 3 µPD168302 4. APPLICATION EXAMPLE C1 VDD C1H C1L C2 C2H C2L C3 VG UVLO VM Oscillator Circuit Charge-pump Circuit BGR Circuit VM1 OUT1A Controller /STB IN1 IN2 Control Circuit MOS H-bridge Circuit 1 Level Shift Circuit M1 OUT1B OUT2A IN3 IN4 Control Circuit MOS H-bridge Circuit 2 Level Shift Circuit M2 OUT2B VM2 LGND PGND1 PGND2 Remark This circuit diagram is an example of connection, and is not a thing aiming at mass production. 4 Data Sheet S16402EJ1V0DS µPD168302 5. FUNCTION TABLE Input Output Current direction IN1 IN2 /STB OUT1A OUT1B L L H Hi-Z Hi-Z H L H H L Stop OUT1A→OUT1B (Forward) OUT1B→OUT1A L H H L H (Reverse) Brake H H H L L (Regeneration mode) All output stop mode x x L Hi-Z Hi-Z (Standby) Input Output Current direction IN3 IN4 /STB OUT2A OUT2B L L H Hi-Z Hi-Z H L H H L Stop OUT1A→OUT1B (Forward) OUT1B→OUT1A L H H L H (Reverse) Brake H H H L L (Regeneration mode) All output stop mode x x L Hi-Z Hi-Z (Standby) Remark H: High-level, L: Low-level, Hi-Z: High impedance Data Sheet S16402EJ1V0DS 5 µPD168302 6. H-BRIDGE OPERATION FIGURE Forward Reverse VM VM ON OFF OFF LOAD LOAD B A ON OFF B A OFF ON GND GND Stop Brake VM VM OFF OFF OFF LOAD OFF OFF OFF LOAD B A B A ON ON GND GND 6 ON Data Sheet S16402EJ1V0DS µPD168302 7. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25°°C. When mounted on a glass epoxy board (100 mm x 100 mm x 1 mm, 15% copper foil)) Parameter Symbol Power Supply Condition Rating Unit VDD Logic −0.5 to +6.0 V VM Motor −0.5 to +4.0 V VG Voltage VG −0.5 to +8.0 V Input Voltage VIN −0.5 to VDD + 0.5 V Output Voltage VOUT Motor 6.2 V DC Output Current ID(DC) DC ± 0.6 A/ch Peak Output Current ID(pulse) PW < 10 ms, Duty ≤ 20% ± 1.0 A/ch Power consumption PT 0.7 W Peak junction temperature Tch(MAX.) 150 °C Storage temperature Tstg −55 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = 25°C. When mounted on a glass epoxy board (100 mm x 100 mm x 1 mm, 15% copper foil)) Parameter Symbol Condition MIN. TYP. MAX. Unit 4.0 5.5 V Power Supply VDD Logic VM Motor 0.9 3.6 V VG Voltage Note VG VM + 3.5 7.5 V Input Voltage VIN 0 VDD V DC Output Current ID(DC) DC −0.3 +0.3 A/ch Peak Output Current ID(pulse) PW < 10 ms, Duty ≤ 20% −0.7 +0.7 A/ch Logic input frequency fIN 100 kHz Capacitor for charge-pump C1 to C3 0.012 µF Operating temperature TA 70 °C 0.008 0.01 0 Note When using charge-pump circuit, the voltage occurs internally at VG-pin (VM + 3.5 V (TYP.)). Data Sheet S16402EJ1V0DS 7 µPD168302 ELECTRICAL CHARACTERISTICS (Unless otherwise specified, TA = 25°C, VDD = 5 V, VM = 5.5 V) Parameter Symbol Condition MIN. VDD current at standby IDD(STB) VDD current at operating IDD(ACT) High-level Input current IIH VIN = VDD Low-level Input current IIL VIN = 0 V Input pull-down resistance RIND High-level Input voltage VIH 4.0 V ≤ VDD ≤ 5.5 V Low-level Input voltage VIL 4.0 V ≤ VDD ≤ 5.5 V On resistance H-Bridge Ron IM = 0.3 A, Sum of upper and lower Output Leak current IM(off) Per VM pin TYP. /STB = L MAX. Unit 1.0 µA 1.0 mA 100 µA 200 kΩ µA −1.0 50 0.7 x VDD V 0.3 x VDD V 2.0 Ω 1.0 µA 2.5 V 1.0 ms 0.1 5.0 µs 0.1 5.0 µs 1.0 All control-pin = L (VM = Recommenred range MAX.) low-voltage detected voltage VDDS 1.7 turn-ON time at charge-pump tONC C1 = C2 = C3 = 0.01 µF Output turn-ON time ton IM = 0.3 A, refer to Figure 1, 2 Output turn-OFF time toff Figure 1. Charge-pump circuit operating wave 50% STB tONC VM + 3.5 V (reference) 90% VG Figure 2. Switching Wave IN 50% 50% ton IM 8 toff 50% Data Sheet S16402EJ1V0DS 50% µPD168302 8. PACKAGE DRAWING 24-PIN PLASTIC TSSOP (5.72 mm (225)) 13 24 detail of lead end F G R P L S 12 1 E A H A' I J S D M N K C M S B NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 6.65±0.10 A' 6.5±0.1 B 0.575 C 0.5 (T.P.) D E 0.22±0.05 0.1±0.05 F 1.2 MAX. G 1.0±0.05 H I J K L M 4.4±0.1 1.0±0.1 0.17±0.025 0.5 0.10 6.4±0.1 N 0.08 P 3°+5° −3° R 0.25 S 0.6±0.15 P24MA-50-6A5 Data Sheet S16402EJ1V0DS 9 µPD168302 9. RECOMMENDED SOLDERING CONDITIONS The µPD168302 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) µPD168302MA-6A5: 24-pin plastic TSSOP (5.72 mm (225)) Soldering Method Soldering Conditions Recommended Condition symbol Infrared reflow Package peak temperature: 260°C, Time: 60 seconds MAX. (at 220°C or higher), Count: Three times or less, Exposure limit: None, Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended Caution Do not use different soldering methods together (except for partial heating). 10 Data Sheet S16402EJ1V0DS IR60-00-3 µPD168302 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S16402EJ1V0DS 11 µPD168302 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) • The information in this document is current as of May, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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