DATA SHEET MOS INTEGRATED CIRCUIT µPD17145(A1), 17147(A1), 17149(A1) SMALL, GENERAL-PURPOSE 4-BIT SINGLE-CHIP MICROCONTROLLERS The µ PD17145(A1), 17147(A1), and 17149(A1) are 4-bit single-chip microcontrollers integrating an 8-bit A/D converter (4 channels), a timer function (3 channels), and a serial interface. These microcontrollers employ a CPU of the general-purpose register type that can execute direct memory operations and direct memory-to-memory data transfer for efficient programming. All the instructions consist of 16 bits per word. In addition, a one-time PROM version, the µ PD17P149, is also available for program evaluation. The functions of these microcontrollers are described in detail in the following User’s Manual. Be sure to read the following manual when designing your system: µ PD17145 Subseries User’s Manual: IEU-1383 FEATURES • 17K architecture : General-purpose register type : Instruction length fixed to 16 bits • Program memory (ROM) : µPD17145(A1) : 2 KB (1024 × 16 bits) : µPD17147(A1) : 4 KB (2048 × 16 bits) : µPD17149(A1) : 8 KB (4096 × 16 bits) • Data memory (RAM) : 110 × 4 bits • External interrupt : 1 (INT pin, with sense input) • Instruction execution time : 2 µs (at 8 MHz: ceramic oscillation) • 8-bit A/D converter : 4 channels, absolute accuracy: ±1.5 LSB MAX. (VDD = 4.0 to 5.5 V) • Timer : 3 channels • Serial interface : 1 channel (clocked 3-wire) • POC circuit (mask option) : VDD = 2.7 to 5.5 V (at 400 kHz to 2 MHz) • Operating voltage : VDD = 4.5 to 5.5 V (at 400 kHz to 8 MHz) • Operating temperature : Ta = –40 to +110 ˚C APPLICATIONS Automotive electronics, etc. Unless contextually excluded, references in this data sheet to the µ PD17149 (A1) mean the µ PD17145 (A1) and µ PD17147 (A1). The information in this document is subject to change without notice. Document No. U13233EJ1V1DS00 (1st edition) (Previous No. IC-3580) Date Published January 1998 N CP(K) Printed in Japan © 1995 µPD17145(A1), 17147(A1), 17149(A1) ORDERING INFORMATION Part Number µ PD17145CT(A1)-××× Package Quality Grade 28-pin plastic shrink DIP (400 mil) Special µ PD17145GT(A1)-××× 28-pin plastic SOP (375 mil) Special µ PD17147CT(A1)-××× 28-pin plastic shrink DIP (400 mil) Special µ PD17147GT(A1)-××× 28-pin plastic SOP (375 mil) Special µ PD17149CT(A1)-××× 28-pin plastic shrink DIP (400 mil) Special µ PD17149GT(A1)-××× 28-pin plastic SOP (375 mil) Special Remark ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 µPD17145(A1), 17147(A1), 17149(A1) FUNCTION LIST Part Number µ PD17145 (A1) µ PD17147 (A1) µ PD17149 (A1) ROM capacity 2 KB (1024 × 16 bits) 4 KB (2048 × 16 bits) 8 KB (4096 × 16 bits) RAM capacity 110 × 4 bits Stack Address stack × 5, interrupt stack × 3 Item • I/O I/O ports 23 : 20 • Input : 2 • Sense input (INT pin A/D converter input Note ) : 1 4 channels (shared with port pins), absolute accuracy: ±1.5 LSB MAX. • 8-bit timer/counter: 2 channels (can be used as 1 channel of 16-bit timer) Timer 3 channels • 7-bit basic interval timer: 1 channel (can be used as watchdog timer) Serial interface 1 channel (3-wire) • Multiple interrupt by hardware (3 levels MAX.) • External interrupt (INT): 1 Interrupt Rising edge, falling edge, or both rising and falling edges selectable for detection. • Timer 0 (TM0) • Internal interrupt: 4 • Timer 1 (TM1) • Basic interval timer (BTM) • Serial interface (SIO) Instruction execution time 2 µ s (at 8 MHz, ceramic oscillation) Standby function HALT, STOP Mask option POC circuit (Can be used in application circuit that operates on V DD = 5 V ± 10 %, 400 kHz to 4 MHz) 2.7 to 5.5 V (at 400 kHz to 2 MHz) Operating voltage 4.5 to 5.5 V (at 400 kHz to 8 MHz) 28-pin plastic shrink DIP (400 mil) Package 28-pin plastic SOP (375 mil) One-time PROM version Note µ PD17P149 Quality grade is "standard" and not (A1). Operating temperature range: Ta = –40 to +85 ˚C The INT pin is used as an input pin (sense input) when the external interrupt function is not used. The status of this pin is read by using the INT flag of a control register, not by a port register. Caution The PROM version is functionally compatible with the mask ROM versions but its internal circuit and part of the electrical characteristics are different from those of the mask ROM versions. To replace the PROM version with a mask ROM version, thoroughly conduct application evaluation by using a sample of the mask ROM version. 3 µPD17145(A1), 17147(A1), 17149(A1) PIN CONFIGURATION (Top View) 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil) 1 28 GND P0F1/VREF 2 27 XIN P0C3/ADC3 3 26 XOUT P0C2/ADC2 4 25 RESET P0C1/ADC1 5 24 INT P0C0/ADC0 6 23 P0F0/RLS P0B3 7 22 P0D0/SCK P0B2 8 21 P0D1/SO P0B1 9 20 P0D2/SI P0B0 10 19 P0D3/TM1OUT P0A3 11 18 P0E0 P0A2 12 17 P0E1 P0A1 13 16 P0E2 P0A0 14 15 P0E3 ADC 0-ADC 3 : analog input GND : ground INT : external interrupt input P0A 0 to P0A 3 : port 0A P0B 0 to P0B 3 : port 0B P0C 0 to P0C 3 : port 0C P0D 0 to P0D 3 : port 0D P0E 0 to P0E 3 : port 0E µ PD17145CT(A1) - ××× µ PD17145GT(A1) - ××× µ PD17147CT(A1) - ××× µ PD17147GT(A1) - ××× µ PD17149CT(A1) - ××× µ PD17149GT(A1) - ××× VDD P0F 0 and P0F 1 : port 0F RESET 4 : reset input RLS : standby release signal input SCK : serial clock I/O SI : serial data input SO : serial data output TM1OUT : timer 1 output V DD : power V REF : A/D converter reference voltage X IN, X OUT : for system clock oscillation µPD17145(A1), 17147(A1), 17149(A1) BLOCK DIAGRAM VDD Clock Divider fx/2 N XIN System Clock Generator XOUT CPU CLOCK CLK STOP RF P0A3 P0A2 P0A1 P0A0 RAM P0A (CMOS) 110 × 4 bits INT Interrupt Controller IRQTM0 IRQTM1 IRQBTM IRQSIO SYSTEM REG. P0B3 P0B2 P0B1 P0B0 IRQBTM P0B (CMOS) Basic Interval Timer fx/2 N IRQTM1 ALU P0C3/ADC3 P0C2/ADC2 P0C1/ADC1 P0C0/ADC0 fx/2 N Timer 1 P0C (CMOS) IRQTM0 fx/2 N Timer 0 A/D Converter P0E (N-ch) P0F1/VREF P0F ROM P0F0/RLS P0D3/TM1OUT P0D2/SI P0D1/SO P0D0/SCK Note 1 P0E3 P0E2 P0E1 P0E0 Instruction Decoder RESET P0D (N-ch) Program Counter Serial Interface TM1 Stack GND Note 2 IRQSIO Notes 1. The ROM capacity of each product is as follows: 1024 × 16 bits: µ PD17145(A1) 2048 × 16 bits: µ PD17147(A1) 4096 × 16 bits: µ PD17149(A1) 2. The stack capacity of each product is as follows: 5 × 10 bits: µ PD17145(A1) 5 × 11 bits: µ PD17147(A1) 5 × 12 bits: µ PD17149(A1) Remark CMOS or N-ch in ( ) indicate the output format of the port. CMOS : CMOS push-pull output N-ch : N-ch open-drain output 5 µPD17145(A1), 17147(A1), 17149(A1) CONTENTS 1. PIN ..................................................................................................................................... 9 1.1. Pin Function ..................................................................................................................................... 9 1.2 Equivalent Circuit of Pin ............................................................................................................... 11 1.3 Handling of Unused Pins .............................................................................................................. 15 1.4 Note on Using RESET and P0F 0/RLS Pins ............................................................................... 16 2. PROGRAM MEMORY (ROM) ...................................................................................... 17 2.1 Configuration of Program Memory .............................................................................................. 17 3. PROGRAM COUNTER (PC) ....................................................................................... 18 3.1 Configuration of Program Counter .............................................................................................. 18 3.2 Operation of Program Counter .................................................................................................... 18 4. STACK ........................................................................................................................... 19 4.1 Configuration of Stack .................................................................................................................. 19 4.2 Stack Function ............................................................................................................................... 19 5. DATA MEMORY (RAM) ............................................................................................... 20 5.1 Configuration of Data Memory ..................................................................................................... 20 6. GENERAL REGISTER (GR)........................................................................................ 21 6.1 General Register Pointer (RP) ..................................................................................................... 21 7. SYSTEM REGISTER (SYSREG) ................................................................................ 22 7.1 Configuration of System Register ............................................................................................... 22 8. REGISTER FILE (RF) .................................................................................................. 24 8.1 Configuration of Register File ...................................................................................................... 24 8.2 Function of Register File .............................................................................................................. 25 9. DATA BUFFER (DBF) ................................................................................................. 26 9.1 Configuration of Data Buffer ........................................................................................................ 26 9.2 Function of Data Buffer ................................................................................................................ 27 10. ALU BLOCK .................................................................................................................. 28 10.1 Configuration of ALU Block .......................................................................................................... 28 11. PORTS ........................................................................................................................... 30 11.1 Port 0A (P0A 0, P0A 1, P0A 2, P0A 3) .............................................................................................. 30 11.2 Port 0B (P0B 0, P0B 1, P0B 2, P0B 3) .............................................................................................. 31 11.3 Port 0C (P0C 0/ADC 0, P0C 1/ADC 1, P0C 2/ADC 2, P0C 3/ADC 3) ................................................... 32 11.4 Port 0D (P0D 0/SCK, P0D 1/SO, P0D 2/SI, P0D 3/TM1OUT) ........................................................ 33 11.5 Port 0E (P0E 0, P0E 1, P0E 2, P0E 3) .............................................................................................. 34 11.6 Port 0F (P0F 0/RLS, P0F1/V REF) ................................................................................................... 34 6 µPD17145(A1), 17147(A1), 17149(A1) 12. 8-BIT TIMERS/COUNTERS (TM0, TM1) ................................................................... 35 12.1 Configuration of 8-Bit Timers/Counters ..................................................................................... 35 13. BASIC INTERVAL TIMER (BTM) ............................................................................... 39 13.1 Configuration of Basic Interval Timer ........................................................................................ 39 13.2 Registers Controlling Basic Interval Timer ............................................................................... 41 13.3 Watchdog Timer Function ........................................................................................................... 43 14. A/D CONVERTER ......................................................................................................... 45 14.1 Configuration of A/D Converter .................................................................................................. 45 14.2 Function of A/D Converter ........................................................................................................... 46 14.3 Operation of A/D Converter ........................................................................................................ 47 15. SERIAL INTERFACE (SIO) ......................................................................................... 50 15.1 Function of Serial Interface ......................................................................................................... 50 15.2 Operation Mode of 3-Wire Serial Interface ............................................................................... 52 16. INTERRUPT FUNCTION .............................................................................................. 54 16.1 Types of Interrupt Causes and Vector Addresses ................................................................... 54 16.2 Hardware of Interrupt Control Circuit ......................................................................................... 55 17. STANDBY FUNCTION ................................................................................................. 56 17.1 Outline of Standby Function ....................................................................................................... 56 17.2 HALT Mode ................................................................................................................................... 58 17.3 STOP Mode ................................................................................................................................... 60 18. RESET ............................................................................................................................ 63 18.1 Reset Function .............................................................................................................................. 63 18.2 Reset Operation ........................................................................................................................... 64 19. POC CIRCUIT (MASK OPTION) ................................................................................. 65 19.1 Function of POC Circuit ............................................................................................................... 65 19.2 Conditions to Use POC Circuit ................................................................................................... 66 20. INSTRUCTION SET ...................................................................................................... 67 20.1 Outline of Instruction Set ............................................................................................................. 67 20.2 Legend ........................................................................................................................................... 68 20.3 Instruction Set ............................................................................................................................... 69 20.4 Assembler (AS17K) Embedded Macro Instruction ................................................................... 71 21. ASSEMBLER RESERVED WORDS ........................................................................... 72 21.1 Mask Option Directive .................................................................................................................. 72 21.2 Reserved Symbols ....................................................................................................................... 74 22. ELECTRICAL SPECIFICATIONS ............................................................................... 82 23. CHARACTERISTIC CURVE (REFERENCE VALUE) ............................................... 88 7 µPD17145(A1), 17147(A1), 17149(A1) 24. PACKAGE DRAWINGS .................................................................................................... 90 25. RECOMMENDED SOLDERING CONDITIONS .............................................................. 94 APPENDIX A. FUNCTION COMPARISON BETWEEN µ PD17145 SUBSERIES AND THE µ PD17135A AND 17137A ...................................................................... 96 APPENDIX B. DEVELOPMENT TOOLS ................................................................................. 98 8 µPD17145(A1), 17147(A1), 17149(A1) 1. PIN 1.1. Pin Function Pin Number Symbol 1 V DD 2 P0F 1/V REF 3 to 6 P0C 3/ADC 3 to P0C 0/ADC 0 7 8 9 P0B3 P0B2 P0B1 10 P0B0 11 12 13 P0A3 P0A2 P0A1 14 P0A0 15 16 17 P0E3 P0E2 P0E1 18 P0E0 19 P0D3/TM1OUT 20 P0D 2/SI 21 P0D1/SO 22 P0D 0/SCK Function Power supply. Reference voltage input to port 0F and A/D converter. • Pull-up resistor can be connected by mask option. • P0F 1 • Bit 1 of 2-bit input port (P0F) • V REF • Reference voltage input pin of A/D converter Analog input to port 0C and A/D converter. • P0C 3-P0C 0 • 4-bit I/O port • Can be set in input or output mode bitwise. • ADC 3-ADC 0 • Analog inputs to A/D converter. Port 0B. • 4-bit I/O port • Can be set in input or output mode in 4-bit units. • Pull-up resistor can be connected in 4-bit units via software. Port 0A. • 4-bit I/O port. • Can be set in input or output mode in 4-bit units. • Pull-up resistor can be connected in 4-bit units via software. Port 0E. • 4-bit I/O port. • Can be set in input or output mode in 4-bit units. • Pull-up resistor can be connected in 4-bit units via software. Port 0D that is also used for timer 1 output, serial data input, serial data output, and serial clock I/O. • Pull-up resistor can be connected bitwise via software. • P0D 3-P0D 0 • 4-bit I/O port. • Can be set in input or output mode bitwise. • TM1OUT • Timer 1 output • SI • Serial data input • SO • Serial data output • SCK • Serial clock I/O Output Format After Reset — — Input Input (P0F 1) CMOS push-pull Input (P0C) CMOS push-pull Input CMOS push-pull Input N-ch open-drain Input N-ch open-drain Input (P0D) 9 µPD17145(A1), 17147(A1), 17149(A1) Pin Number 10 Symbol Function Output Format After Reset 23 P0F 0/RLS Port 0F or standby mode release signal input. • Pull-up resistor can be connected by mask option. • R0F 0 • Bit 0 of 2-bit input port (P0F) • RLS • Standby mode release signal input Input Input (P0F 0) 24 INT Input Input 25 RESET System reset input. • Pull-up resistor can be connected by mask option. Input Input 26 27 X OUT X IN For system clock oscillation. Connect ceramic resonator across X IN and X OUT. — — 28 GND GND — — External interrupt request signal input. Also used to release standby mode. • Pull-up resistor can be connected by mask option. µPD17145(A1), 17147(A1), 17149(A1) 1.2 Equivalent Circuit of Pin The input/output circuit of each pin is shown below, partially simplified. (1) P0A 0 to P0A 3 and P0B 0 to P0B 3 VDD VDD P-ch data Output latch pull-up flag P-ch N-ch output disable Selector Input buffer 11 µPD17145(A1), 17147(A1), 17149(A1) (2) P0C 0/ADC 0 to P0C 3/ADC3 VDD data Output latch P-ch N-ch output disable input disable Selector Input buffer A/D converter (3) P0D 3/TM1OUT and P0D 1/SO VDD pull-up flag data P-ch Output latch N-ch output disable Selector Input buffer 12 µPD17145(A1), 17147(A1), 17149(A1) (4) P0D 2/SI and P0D 0/SCK VDD pull-up flag data P-ch Output latch N-ch output disable Selector Input buffer (5) P0E 0 to P0E 3 VDD data pull-up flag P-ch Output latch N-ch output disable Selector Input buffer (6) P0F 0/RLS VDD Input buffer Mask option stand-by release 13 µPD17145(A1), 17147(A1), 17149(A1) (7) P0F 1/V REF VDD Input buffer A/D select Mask option A/D end STOP mode VREF P-ch (8) RESET and INT VDD Mask option Input buffer 14 µPD17145(A1), 17147(A1), 17149(A1) 1.3 Handling of Unused Pins Handle unused pins as shown in the table below. Table 1-1. Handling of Unused Pins Handling Pin Name Internally P0A, P0B, P0D, P0E Connect on-chip pull-up resistor via — Do not connect on-chip pull-up resistor P0F 1 Open software. P0C Input mode Externally by mask option. Connect to V DD via pull-up resistor, or to GND via pull-down resistorNote 1 . Directly connect to V DD or GND. Connect on-chip pull-up resistor by mask Open option. P0F 0Note 2 Port Do not connect on-chip pull-up resistor by mask option. P0A, P0B, P0C (CMOS — port) P0D Output mode (N-ch open-drain port) Directly connect to GND. Output low level. Open Do not connect pull-up on-chip resistor P0E via software, but output low level. (N-ch open-drain port) Connect on-chip pull-up resistor via software and output high level. Do not connect on-chip pull-up resistor by mask option. External interrupt (INT) Directly connect to V DD or GND. Connect on-chip pull-up resistor by mask Open option. RESET Note 3 (when only internal POC circuit is used) Notes 1. Do not connect on-chip pull-up resistor by mask option. Connect on chip pull-up resistor by Directly connect to V DD . mask option. Take into consideration the drive capability and current dissipation of a port when the port is externally pulled up or down. To pull up or down the port with a high resistance, exercise care so that noise is not superimposed on the port pin. The appropriate value of the pull-up or pulldown resistor differs depending on the application circuit. Generally, select a resistor of several 10 kΩ. 2. The P0F 0/RLS pin is also used to set a test mode. When this pin is not used, do not connect a pull-up resistor to it by mask option, but directly connect it to GND. 3. In an application circuit where a high reliability is required, be sure to input the RESET signal from an external source. The RESET pin is also used to set a test mode. When this pin is not used, directly connect it to V DD . Caution It is recommended to fix the input/output mode, pull-up resistor by software, and the output level of the pin by repeatedly setting them in each loop of the program. 15 µPD17145(A1), 17147(A1), 17149(A1) 1.4 Note on Using RESET and P0F 0 /RLS Pins The RESET and P0F 0/RLS pins also have a function to set a test mode in which the internal operation of the µ PD17149(A1) is tested (for IC test only), in addition to the function described in 1.1 Pin Function. If a voltage higher than V DD is applied to these pins, the test mode is set. If a noise higher than VDD is superimposed on these pins during normal operation, therefore, the test mode is set by mistake, affecting normal operation. If the wiring length of the RESET or P0F 0/RLS pin is too long, for example, noise may be superimposed on the pin. To prevent this, the wiring length must be kept as short as possible. Otherwise, use a diode or capacitor as shown below. ● Connect a low-V F diode between V DD and RESET, P0F 0/RLS ● Connect a capacitor between V DD and RESET, P0F 0/RLS VDD VDD Diode with low VF 16 RESET, P0F0/RLS VDD VDD RESET, P0F0/RLS µPD17145(A1), 17147(A1), 17149(A1) 2. PROGRAM MEMORY (ROM) Table 2-1 shows the program memory configuration of the µ PD17145(A1), 17147(A1), and 17149(A1). Table 2-1. Program Memory Configuration Part Number Program Memory Capacity Program Memory Address µ PD17145(A1) 2 KB (1024 × 16 bits) 0000H-03FFH µ PD17147(A1) 4 KB (2048 × 16 bits) 0000H-07FFH µ PD17149(A1) 8 KB (4096 × 16 bits) 0000H-0FFFH The program memory stores programs and constant data tables. The program memory is addressed by the program counter. Addresses 0000H-0005H are allocated to a reset start address and various interrupt vector addresses. 2.1 Configuration of Program Memory Figure 2-1 shows the program memory map. The program memory is divided in units called “pages” each of which consists of 2K steps with one step made up of 16 bits. Addresses 0000H-07FFH (page 0) of the program memory can be specified by the direct subroutine call instruction. The entire address range of the program memory, 0000H-0FFFH, can be specified by the branch, indirect subroutine call, and table reference instructions. Figure 2-1. Program Memory Map Address 0000H Reset start address 0001H Serial interface interrupt vector 0002H Basic interval timer interrupt vector 0003H Timer 1 interrupt vector 0004H Timer 0 interrupt vector 0005H External (INT) interrupt vector BR addr instruction branch address Page 0 03FFH 07FFH CALL addr instruction subroutine entry address BR @AR instruction branch address CALL @AR instruction subroutine entry address MOVT DBF, @AR instruction table reference address (With µPD17145(A1)) (With µPD17147(A1)) Page 1 0FFFH (With µPD17149(A1)) 16 bits 17 µPD17145(A1), 17147(A1), 17149(A1) 3. PROGRAM COUNTER (PC) The program counter is used to address the program memory. 3.1 Configuration of Program Counter The program counter is a 10-/11-/12-bit binary counter as shown in Figure 3-1. Figure 3-1. Program Counter MSB PC11 LSB PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC ( µ PD17145(A1)) PC ( µ PD17147(A1)) PC ( µ PD17149(A1)) 3.2 Operation of Program Counter Usually, the contents of the program counter are automatically incremented each time an instruction has been executed. When reset has been effected, when a branch, subroutine call, return, or table reference instruction has been executed, or when an interrupt has been acknowledged, the address of the program memory to be executed next is set to the program counter. Figure 3-2. Value of Program Counter after Instruction Execution Bit of Program Counter Instruction Value of Program Counter PC11 PC10 At reset 0 0 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 0 0 0 0 0 0 0 0 0 0 BR addr 1 CALL addr Value specified by addr 0 BR @AR CALL @AR Contents of address register (AR) (MOVT DBF, @AR) RET RETSK Contents of address stack indicated by stack pointer (return address) RETI When interrupt is acknowledged Remark 18 Vector address of each interrupt The µ PD17145(A1) does not have PC11 and PC10. The µ PD17147(A1) does not have PC11. µPD17145(A1), 17147(A1), 17149(A1) 4. STACK The stack is a register to which the return address of the program or the contents of the system registers, which are described later, are saved when a subroutine call instruction is executed or when an interrupt is acknowledged. 4.1 Configuration of Stack Figure 4-1 shows the configuration of the stack. The stack consists of a 3-bit binary counter, stack pointer (SP), five 10-bit ( µ PD17145(A1)), 11-bit ( µ PD17147(A1)), or 12-bit ( µ PD17149(A1)) address stack registers (ASRs), and three 5-bit interrupt stack registers (INTSKs). Figure 4-1. Configuration of Stack Address stack registers (ASRs) Stack pointer (SP) b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SPb2 SPb1 SPb0 0H Address stack register 0 SP is initialized to 5H at reset. 1H Address stack register 1 2H Address stack register 2 3H Address stack register 3 4H Address stack register 4 b2 b1 b0 Interrupt stack registers (INTSKs) 0H BCDSK0 CMPSK0 CYSK0 ZSK0 IXESK0 1H BCDSK1 CMPSK1 CYSK1 ZSK1 IXESK1 2H BCDSK2 CMPSK2 CYSK2 ZSK2 IXESK2 4.2 Stack Function The stack is used to save a return address when the subroutine call or table reference instruction is executed. When an interrupt is acknowledged, the return address of the program and the contents of the program status word (PSWORD) are automatically saved to the stack. After they are saved to the stack, all the bits of PSWORD are cleared to 0. 19 µPD17145(A1), 17147(A1), 17149(A1) 5. DATA MEMORY (RAM) The data memory is used to store data for operation and control. Data can always be written to or read from this memory by using an instruction. 5.1 Configuration of Data Memory The data memory is assigned addresses each consisting of 7 bits. The higher 3 bits of an address are called a “row address”, while the lower 4 bits are called a “column address”. Take address 1AH for example. The row address of this address is 1H and the column address is 0AH. One address consists of 4 bits (= 1 nibble) of memory. The data memory consists of an area to which the user can save data, and areas to which special functions are allocated in advance. These areas are: • System register (SYSREG) (Refer to 7. SYSTEM REGISTER (SYSREG).) • Data buffer (DBF) (Refer to 9. DATA BUFFER (DBF).) • Port register (Refer to 11. PORT.) Figure 5-1. Configuration of Data Memory Column address BANK0 0 1 2 3 4 5 6 7 8 9 A B C D E F DBF3 DBF2 DBF1 DBF0 0 1 Example : Address 1AH of BANK0 2 3 4 5 P0E (4 bits) 6 7 20 P0A (4 bits) P0B (4 bits) P0C (4 bits) P0D (4 bits) System register P0F (2 bits) µPD17145(A1), 17147(A1), 17149(A1) 6. GENERAL REGISTER (GR) As its name implies, the general register is used for general purposes such as data transfer and operation. The general register of the 17K series is not a fixed area, but an area specified on the data memory by using the general register pointer (RP). Therefore, a part of the data memory area can be specified as a general register as necessary, so that data can be transferred between data memory areas and the data in the data memory can be operated with a single instruction. 6.1 General Register Pointer (RP) RP is a pointer that specifies part of the data memory as the general register. RP specifies the bank and row addresses of a data memory area that is to be specified as the general register. Consisting of a total of 7 bits, RP is assigned to 7DH (RPH) and 7EH (RPL), and the higher 3 bits of the system register (refer to 7. SYSTEM REGISTER (SYSREG)). RPH specifies a bank, and RPL specifies a data memory row address. Figure 6-1. Configuration of General Register Pointer Column address BANK0 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 General register area when RPH = 0000B, RPL = 010×B General register (16 nibbles) 2 Row addresses 0H to 7H can be 3 Row specified by address general register 4 pointer (RP). 5 6 System register 7 7DH Address 7EH General register pointer (RP) Name Symbol Bit RP RPH RPL b3 b2 b1 b0 b3 b2 b1 b0 Data 0 0 0 0 Reset 0 0 0 0 B C D 0 0 0 21 µPD17145(A1), 17147(A1), 17149(A1) 7. SYSTEM REGISTER (SYSREG) The system register (SYSREG) is a register that directly controls the CPU, and is located on the data memory. 7.1 Configuration of System Register Figure 7-1 shows the location of the system register on the data memory. As shown in this figure, the system register is located at addresses 74H-7FH of the data memory. Because the system register is located on the data memory, it can be manipulated by all the data memory manipulation instructions. It is therefore possible to specify the system register as a general register. Figure 7-1. Location of System Register on Data Memory Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F C D E 0 Row address 1 2 Data memory (BANK0) 3 4 5 6 7 Port register 0 1 2 System register (SYSREG) 3 4 5 6 7 8 9 A B F Figure 7-2 shows the configuration of the system register. As shown in this figure, the system register consists of the following seven registers: 22 • Address register (AR) • Window register (WR) • Bank register (BANK) • Index register (IX) • Data memory row address pointer (MP) • General register pointer (RP) • Program status word (PSWORD) µPD17145(A1), 17147(A1), 17149(A1) Figure 7-2. Configuration of System Register Address 74H Symbol Data Note1 76H 77H AR3 AR2 AR1 78H 79H 7AH AR0 WR 7BH 7CH Index register (IX) Window Bank register register (WR) (BANK) Address register (AR) Name Bit 75H IXH IXM MPH MPL 7EH General register pointer (RP) Data memory row address pointer (MP) BANK 7DH IXL RPH 7FH Program status word (PSWORD) RPL PSW b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 0 0 0 0 (IX) M Note2 0 0 0 0 P 0 0 0 0 (AR) (BANK) E (MP) 0 0 0 0 (RP) B C C I C M Y Z X D P E Initial Undefivalue at 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset Notes 1. 2. 0 in this field means that the bit is “fixed to 0”. b 3 and b2 of AR2 of the µ PD17145(A1) are fixed to 0. b 3 of AR2 of the µ PD17147(A1) is fixed to 0. 23 µPD17145(A1), 17147(A1), 17149(A1) 8. REGISTER FILE (RF) The register file is a register that mainly sets the conditions of the peripheral hardware. 8.1 Configuration of Register File 8.1.1 Configuration of register file Figure 8-1 shows the configuration of the register file. As shown in this figure, the register file consists of 128 nibbles (128 × 4 bits). Like the data memory, the register file is assigned addresses in 4-bit units, with row addresses 0H-7H and column addresses 0H-0FH. Addresses 00H-3FH of the register file are called a control register. Figure 8-1. Configuration of Register File Register file Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 Control register 3 4 5 6 7 8.1.2 Register file and data memory Figure 8-2 shows the relationships between the register file and data memory. As shown in this figure, addresses 40H to 7FH of the register file overlaps the data memory. It seems from the program as if addresses 40H to 7FH of the data memory exist at addresses 40H-7FH of the register file. 24 µPD17145(A1), 17147(A1), 17149(A1) Figure 8-2. Relationships between Register File and Data Memory Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 Data memory 2 3 4 5 6 7 BANK0 Port register System register 0 1 Control register 2 3 Register file 8.2 Function of Register File 8.2.1 Function of register file The register file is a collection of registers that set the conditions of the peripheral hardware by using the PEEK or POKE instruction. The registers that control the peripheral hardware are allocated to addresses 00H-3FH. These registers are called control registers. Addresses 40H-7FH of the register file overlap the ordinary data memory. These addresses can therefore be read or written by not only the MOV instruction but also the PEEK and POKE instructions. 8.2.2 Functions of control registers The control registers are used to set the conditions of the peripheral hardware listed below. For the details of the peripheral hardware and control registers, refer to the description of each peripheral hardware. • Port • 8-bit timers/counters (TM0, TM1) • Basic interval timer (BTM) • A/D converter • Serial interface (SIO) • Interrupt function • Stack pointer (SP) 25 µPD17145(A1), 17147(A1), 17149(A1) 9. DATA BUFFER (DBF) The data buffer consists of 4 nibbles allocated to addresses 0CH-0FH of BANK0 of the data memory. This area is a data storage area that transfers data with the peripheral hardware of the CPU (address register, serial interface, timers 0 and 1, and A/D converter) by using the GET or PUT instruction. Moreover, the constants on the program memory can be read to the data buffer by using the MOVT DBF, @AR instruction. 9.1 Configuration of Data Buffer Figure 9-1 shows the location of the data buffer on the data memory. As shown in this figure, the data buffer is allocated addresses 0CH-0FH of the data memory, and consists of a total of 16 bits or 4 nibbles (4 × 4 bits). Figure 9-1. Location of Data Buffer Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F Data buffer (DBF) 0 Row address 1 2 Data memory 3 BANK0 4 5 6 7 System register (SYSREG) Figure 9-2 shows the configuration of the data buffer. As shown in this figure, the data buffer consists of 16 bits of the data memory, with the bit 0 of address 0FH as the LSB and bit 3 of address 0CH as the MSB. Figure 9-2. Configuration of Data Buffer Data memory Address BANK0 Bit b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Data buffer 0CH b2 b1 DBF3 Symbol 0DH b0 b3 DBF2 DBF0 L S B Data < > M S B DBF1 0FH < < Data 0EH Because the data buffer is located on the data memory, it can be manipulated by all the data memory manipulation instructions. 26 µPD17145(A1), 17147(A1), 17149(A1) 9.2 Function of Data Buffer The data buffer has two main functions. One is to transfer data with the peripheral hardware, and the other is to read the constant data on the program memory (table reference). Figure 9-3 shows the relationships between the data buffer and peripheral hardware. Figure 9-3. Data Buffer and Peripheral Hardware Data buffer (DBF) Internal bus Program memory (ROM) Peripheral address Peripheral hardware 01H Shift register (SIOSFR) 02H Timer 0 modulo register (TM0M) 03H Timer 1 modulo register (TM1M) 04H A/D converter data register (ADCR) 40H Address register (AR) 45H Timer 0 timer 1 count register (TM0TM1C) Constant data 27 µPD17145(A1), 17147(A1), 17149(A1) 10. ALU BLOCK The ALU executes arithmetic and logical operations, bit judgment, and rotation processing of 4-bit data. 10.1 Configuration of ALU Block Figure 10-1 shows the configuration of the ALU block. As shown, the ALU block consists of an ALU that processes 4-bit data, and peripheral circuits such as temporary registers A and B, status flip-flops that control the status of the ALU, and a decimal adjustment circuit that is used when a BCD operation is performed. The status flip-flops are a zero flag FF, carry flag FF, compare flag FF, and BCD flag FF, as shown in Figure 10-1. The status flip-flops correspond to the zero flag (Z), carry flag (CY), compare flag (CMP), and BCD flag (BCD) of the program status word (PSWORD: addresses 7EH, 7FH) on a one-to-one basis. 28 µPD17145(A1), 17147(A1), 17149(A1) Figure 10-1. Configuration of ALU Block Data bus Temporary register A Temporary register B Status flip-flop ALU • Arithmetic operation • Logical operation • Bit judgment • Compare judgment • Rotation processing Decimal adjustment circuit Address 7EH 7FH Program status word (PSWORD) Name Bit b0 b3 b2 b1 b0 Flag BCD CMP CY Z IXE Status flip-flop BCD flag FF CMP flag FF CY flag FF Z flag FF Functional Outline Indicates that result of arithmetic operation is 0. Stores carry or borrow resulting from arithmetic operation. Specifies whether result of arithmetic operation is stored. Specifies whether decimal adjustment is performed when arithmetic operation is executed. 29 µPD17145(A1), 17147(A1), 17149(A1) 11. PORTS 11.1 Port 0A (P0A 0, P0A 1 , P0A 2 , P0A 3 ) Port 0A is a 4-bit I/O port with an output latch. It is mapped at address 70H of BANK0 of the data memory. The output format is CMOS push-pull output. This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0AGIO (bit 0 of address 2CH) on the register file. When P0AGIO = 0, all the pins of port 0A are set in the input mode. When an instruction that reads the data of the port register is executed at this time, the pin status is read. When P0AGIO = 1, all the pins of port 0A are set in the output mode, and the contents written to the output latch are output to the pins. When an instruction that reads the port status is executed with the port set in the output mode, the contents of the output latch, instead of the pin status, are read. A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is connected is specified by P0AGPU (bit 0 at address 0CH) of the register file. All the four pins are pulled up when P0AGPU = 1. When P0AGPU = 0, the pull-up resistor is not connected. P0AGIO and P0AGPU are cleared to “0” at reset, and all the P0A pins are set in the input mode without the pull-up resistor connected. The value of the output latch is also cleared to “0”. Table 11-1. Writing and Reading Port Register (0.70H) 30 P0AGIO Input/Output BANK0 70H RF: 2CH, bit 0 Mode of Pin Write Read 0 Input Enabled P0A pin status 1 Output Write to P0A latch P0A latch contents µPD17145(A1), 17147(A1), 17149(A1) 11.2 Port 0B (P0B 0, P0B 1 , P0B 2 , P0B 3 ) Port 0B is a 4-bit I/O port with an output latch. It is mapped at address 71H of BANK0 of the data memory. The output format is CMOS push-pull output. This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0BGIO (bit 1 of address 2CH) on the register file. When P0BGIO = 0, all the pins of port 0B are set in the input mode. When an instruction that reads the data of the port register is executed at this time, the pin status is read. When P0BGIO = 1, all the pins of port 0B are set in the output mode, and the contents written to the output latch are output to the pins. When an instruction that reads the port status is executed with the port set in the output mode, the contents of the output latch, instead of the pin status, are read. A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is connected is specified by P0BGPU (bit 1 at address 0CH) of the register file. All the four-bit pins are pulled up when P0BGPU = 1. When P0BGPU = 0, the pull-up resistor is not connected. P0BGIO and P0BGPU are cleared to “0” at reset, and all the P0B pins are set in the input mode without the pull-up resistor connected. The value of the output latch is also cleared to “0”. Table 11-2. Writing and Reading Port Register (0.71H) P0BGIO Input/Output BANK0 71H RF: 2CH, bit 1 Mode of Pin Write Read 0 Input Enabled P0B pin status 1 Output Write to P0B latch P0B latch contents 31 µPD17145(A1), 17147(A1), 17149(A1) 11.3 Port 0C (P0C 0 /ADC0 , P0C 1 /ADC 1 , P0C 2 /ADC 2, P0C 3 /ADC 3 ) Port 0C is a 4-bit I/O port with an output latch. It is mapped at address 72H of BANK0 of the data memory. The output format is CMOS push-pull output. This port can be set in the input or output mode in 1-bit units. The input or output mode is specified by P0CBIO0-P0CBIO3 (address 1CH) on the register file. When P0CBIOn = 0 (n = 0 to 3), the corresponding port pin, P0Cn, is set in the input mode. When an instruction that reads the data of the port register is executed at this time, the pin status is read. When P0CBIOn = 1 (n = 0 to 3), the P0Cn pin is set in the output mode, and the contents written to the output latch are output to the pin. When an instruction that reads the port status is executed with a port pin set in the output mode, the contents of the output latch, instead of the pin status, are read. At reset, P0CBIO0-P0CBIO3 are cleared to “0”, setting all the P0C pins in the input mode. The contents of the output latch are also cleared to “0” at this time. Port 0C is also used to input analog voltages to the A/D converter. Whether each pin of the port is used as a port pin or analog input pin is specified by P0C0IDI-P0C3IDI (address 1BH) on the register file. When P0CnIDI = 0 (n = 0-3), the P0C n/ADC n pin functions as a port pin. When P0CnIDI = 1 (n = 0 to 3), the P0C n/ADC n pin functions as an analog input pin of the A/D converter. If any of the P0CnIDI (n = 0 to 3) bits is set to “1”, the P0F 1/V REF pin is used as the V REF pin. When a pin of port 0C is used as an analog input pin of the A/D converter, set the P0CnIDI corresponding to the pin to which an analog voltage is applied to 1, to disable the port input function. Moreover, clear P0CBIOn (n = 0-3) to 0 to set the input port mode. The pin used as an analog input pin is selected by ADCCH0 and ADCCH1 (bits 1 and 0 of address 22H) on the register file. At reset, P0CBIO0-P0CBIO3, P0C0IDI-P0C3IDI, ADCCH0, and ADCCH1 are cleared to 0, setting the input port mode. Table 11-3. Selecting Port or A/D Converter Mode (n = 0 to 3) P0CnIDI P0CBIOn RF:1BH RF:1CH BANK0 72H Function 0 Input port 1 Port output Write Read Enabled. P0C latch Pin status Enabled. P0C latch Contents of P0C latch Enabled. P0C latch Contents of P0C latch Enabled. P0C latch Contents of P0C latch 0 0 1 Analog input of A/D Note 1 Output port and analog 1 Notes 1. 2. input of A/D Note 2 Normal setting when the P0C pins are used as the analog input pins of the A/D converter. The P0C pins function as output port pins. At this time, the analog input voltages change with the output from the port. To use the pins as analog input pins, be sure to clear P0CBIOn to 0. 32 µPD17145(A1), 17147(A1), 17149(A1) 11.4 Port 0D (P0D 0 /SCK, P0D1 /SO, P0D 2/SI, P0D 3/TM1OUT) Port 0D is a 4-bit I/O port with an output latch. It is mapped at address 73H of BANK0 of the data memory. The output format is N-ch open-drain output. This port can be set in the input or output mode in 1-bit units. The input or output mode is specified by P0DBIO0-P0DBIO3 (address 2BH) on the register file. When P0DBIOn = 0 (n = 0 to 3), the corresponding port pin, P0Dn, is set in the input mode. When an instruction that reads the data of the port register is executed at this time, the pin status is read. When P0DBIOn = 1, the P0Dn pin is set in the output mode, and the contents written to the output latch are output to the pin. When an instruction that reads the port status is executed with a port pin set in the output mode, the contents of the output latch, instead of the pin status, are read. A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is connected or not is specified bitwise by using P0DBPU0-P0DBPU3 (address 0DH) on the register file. When P0DBPUn = 1, the P0Dn pin is pulled up. When P0DBPUn = 0, the pull-up resistor is not connected. At reset, P0DBIOn is cleared to “0”, setting all the P0D pins in the input mode. The contents of the output latch are also cleared to “0” at this time. Note that the contents of the output latch are not changed even if the status of P0DBIOn is changed from “1” to “0”. Port 0D is also used as serial interface input/output and timer 1 output pins. Whether the P0D 0 to P0D 2 pins are used as port pins or serial interface I/O pins (SCK, SO, and SI) is specified by SIOEN (bit 0 of 0BH) on the register file. Whether the P0D 3 pin is used as a port pin or timer 1 output (TM1OUT) pin is specified by TM1OSEL (bit 3 of 0BH) on the register file. If TM1OSEL = 1, “1” is output when timer 1 is reset, and the output is inverted each time the count value of timer 1 coincides with the contents of the modulo register. Table 11-4. Contents of Register File and Pin Function (n = 0 to 3) Value of Register File Pin Function TM1OSEL SIOEN P0DBIOn RF: 0BH RF: 0BH RF: 2BH Bit 3 Bit 0 Bit n P0D0/SCK P0D 1/SO P0D 2/SI 0 Input port 1 Output port P0D3/TM1OUT 0 0 0 1 SCK SO SI 1 Input port Output port 0 Input port 1 Output port 0 1 TM1OUT 0 1 SCK SO SI 1 33 µPD17145(A1), 17147(A1), 17149(A1) Table 11-5. Read Contents of Port Register (0.73H) Port Mode Read Contents of Port Register (0.73H) Input port Pin status Output port Contents of output latch Internal clock selected as serial clock Contents of output latch External clock selected as serial clock Pin status SCK SI Pin status SO Contents of output latch TM1OUT Contents of output latch 11.5 Port 0E (P0E 0 , P0E 1 , P0E 2 , P0E 3) Port 0E is a 4-bit I/O port with an output latch. It is mapped at address 6EH of BANK0 of the data memory. The output format is N-ch open-drain output. This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0EGIO (bit 2 of address 2CH) on the register file. When P0EGIO = 0, all the pins of port 0E are set in the input mode. When an instruction that reads the data of the port register is executed at this time, the pin status is read. When P0EGIO = 1, all the pins of port 0E are set in the output port, and the contents written to the output latch are output to the pins. When an instruction that reads the port status is executed with the port set in the output mode, the contents of the output latch, instead of the pin status, are read. A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is connected is specified by P0EGPU (bit 2 at address 0CH) of the register file. All the four-bit pins are pulled up when P0EGPU = 1. When P0EGPU = 0, the pull-up resistor is not connected. P0EGIO is cleared to “0” at reset, and all the P0E pins are set in the input mode. The value of the output latch is also cleared to “0”. Table 11-6. Writing and Reading Port Register (0.6EH) (n = 0 to 3) P0EGIO Input/Output BANK0 6EH RF: 2CH, bit 2 Mode of Pin Write Read 0 Input Enabled P0E pin status 1 Output Write to P0E latch P0E latch contents 11.6 Port 0F (P0F 0 /RLS, P0F 1 /VREF ) Port 0F is a 2-bit input port and mapped at address 6FH of BANK0 of the data memory. A pull-up resistor can be connected on-chip bitwise to this port by mask option. If a read instruction that reads the port register is executed when both pins of port 0F are used as input port pins, the higher 2 bits of the register are fixed to 0, and the pin statuses are read to the lower 2 bits. Executing a write instruction is meaningless as the contents of the port register remain unchanged. The P0F 0/RLS pin is also used to input a standby mode release signal. The P0F 1/V REF pin inputs a reference voltage to the A/D converter when even one of the bits of P0CnIDI (RF: address 1BH, n = 0 to 3) is set to “1”. If an instruction is executed to read the port register when the P0F1/V REF pin functions as the V REF pin, bit 1 of address 6FH is always cleared to 0. 34 µPD17145(A1), 17147(A1), 17149(A1) 12. 8-BIT TIMERS/COUNTERS (TM0, TM1) The µ PD17149(A1) is provided with two 8-bit timers/counters: timer 0 (TM0) and timer 1 (TM1). By using the count-up signal of timer 0 as the count pulse to timer 1, the two 8-bit timers can be used as a 16-bit timer. Each timer is controlled through hardware manipulation by using the PUT or GET instruction or manipulation of the registers on the register file by using the PEEK or POKE instruction. 12.1 Configuration of 8-Bit Timers/Counters Figure 12-1 shows the configuration of the 8-bit timers/counters. An 8-bit timer/counter consists of an 8-bit count register, an 8-bit modulo register, a comparator that compares the value of the count register with that of the modulo register, and a selector that selects the count pulse. Cautions 1. 2. The modulo register is a write register. The count register is a read register. 35 µPD17145(A1), 17147(A1), 17149(A1) Figure 12-1. Configuration of 8-Bit Timer/Counter Data buffer (DBF) Internal bus Interrupt control register (RF:0FH) Timer 0 mode register (RF:11H) INT TM0EN TM0RES TM0CK1 TM0CK0 Timer 0 modulo register (8) (TM0M) 2 Coincidence Timer 0 comparator (8) Timer 0 count-up signal (to timer 1) Latch D Selector System clock/16 System clock/512 System clock/64 Timer 0 count register (8) (TM0C) Clear Q CLK R INT IRQTM0 set signal Reset Internal reset IRQTM0 clear signal Data buffer (DBF) Internal bus Serial interface control register (RF:0BH) Timer 1 mode register (RF:12H) TM1OSEL TM1EN TM1RES TM1CK1 TM1CK0 Timer 1 modulo register (8) (TM1M) Timer 1 comparator (8) P0DBIO3 P0DB3 output latch Coincidence 2 Port control register of bit I/O (RF:2BH) P0D3/ TM1OUT TM1OUT FF Reset Selector Latch System clock/128 System clock/8192 System clock/16 Timer 0 count up D Q CLK R Reset Timer 1 count register (8) (TM1C) IRQTM1 set signal Clear Internal reset IRQTM1 clear signal 36 µPD17145(A1), 17147(A1), 17149(A1) Figure 12-2. Timer 0 Mode Register RF : 11H Bit 3 Bit 2 Bit 1 Bit 0 TM0EN TM0RES TM0CK1 TM0CK0 Read/write Initial value at reset R/W 0 0 0 0 Read = R, write = W Selects count pulse of timer 0 TM0CK1 TM0CK0 0 0 System clock/16 0 1 System clock/512 1 0 System clock/64 1 1 INT pin TM0RES Resets timer 0 0 Does not affect timer 0 1 Resets timer 0 count register and IRQTM0 Remark TM0RES is automatically cleared to 0 after it has been set to 1. When it is read, "0" is always read. TM0EN Timer 0 start command 0 Stops counting of timer 0 1 Resumes counting of timer 0 Remark TM0EN can be used as a status flag that detects the count status of timer 0 (1 : counting in progress, 0 : counting stopped) 37 µPD17145(A1), 17147(A1), 17149(A1) Figure 12-3. Timer 1 Mode Register RF : 12H Bit 3 Bit 2 Bit 1 Bit 0 TM1EN TM1RES TM1CK1 TM1CK0 Read/write Initial value at reset R/W 1 0 0 0 Selects count pulse of timer 1 TM1CK1 TM1CK0 0 0 System clock/128 0 1 System clock/8192 1 0 System clock/16 1 1 Count-up signal from timer 0 TM1RES Resets timer 1 0 Does not affect timer 1 1 Resets timer 1 count register and IRQTM1 Remark TM1RES is automatically cleared to 0 after it has been set to 1. When it is read, "0" is always read. TM1EN Timer 1 start command 0 Stops counting of timer 1 1 Resumes counting of timer 1 Remark TM1EN can be used as a status flag that detects the count status of timer 1 (1 : counting in progress, 0 : counting stopped) 38 µPD17145(A1), 17147(A1), 17149(A1) 13. BASIC INTERVAL TIMER (BTM) The µ PD17149(A1) is provided with a 7-bit basic interval timer. This timer has the following functions: (1) Generates reference time. (2) Selects and counts wait time when standby mode is released. (3) Watchdog timer function to detect program runaway. 13.1 Configuration of Basic Interval Timer Figure 13-1 shows the configuration of the basic interval timer. 39 µPD17145(A1), 17147(A1), 17149(A1) Figure 13-1. Configuration of Basic Interval Timer Internal bus BTM mode register (RF:13H) BTMISEL BTMRES Watchdog timer mode register (RF:13H) BTMCK1 BTMCK0 WDTRES 0 0 WDTEN 2 fBTM 25 Reset fBTM Selector Basic interval timer (7-bit divider) Selector fBTM 27 IRQBTM set signal (2) (3) Reset signal System clock/16384 System clock/4096 System clock/512 System clock/16 Reset 1-bit divider R Q (4) 1-shot pulse (1) S generator Outputs "1" while counting 0 to 7 during counting from 0 to 255. Remark 40 (1) to (4) in the figure correspond to the signals in the timing chart in Figure 13-4. µPD17145(A1), 17147(A1), 17149(A1) 13.2 Registers Controlling Basic Interval Timer The basic interval timer is controlled by the BTM mode register and watchdog timer mode register. Figures 13-2 and 13-3 show the configuration of each register. Figure 13-2. BTM Mode Register RF : 13H Bit 3 Bit 2 BTMISEL BTMRES Read/write Initial value at reset Bit 1 Bit 0 BTMCK1 BTMCK0 Read = R, Write = W R/W 0 0 0 0 BTMCK1 BTMCK0 Selects count pulse to BTM System clock/16 0 0 0 1 1 0 1 1 (1 instruction execution time) System clock/16384 (1024 instruction execution time) System clock/4096 (256 instruction execution time) System clock/512 (32 instruction execution time) BTMRES Resets BTM Does not affect basic interval timer 0 (BTM) Resets binary counter of basic interval 1 timer (BTM) Remark BTMRES is automatically cleared to 0 after it has been set to 1. When it is read, "0" is always read. BTMISEL Selects interval timer 0 Sets interval timer to 1/128 of count pulse 1 Sets interval timer to 1/32 of count pulse 41 µPD17145(A1), 17147(A1), 17149(A1) Figure 13-3. Watchdog Timer Mode Register RF : 03H Bit 3 Bit 2 Bit 1 Bit 0 WDTRES 0 0 WDTEN Initial value at reset Read = R, Write = W R/W Read/write 0 0 0 0 WDTEN Enable watchdog timer 0 Stops watchdog timer. 1 Starts watchdog timer. Remark 1. WDTEN cannot be cleared to 0 by program. 2. WDTEN is automatically cleared to 0 after it has been set to 1. When it is read, "0" is always read. WDTRES 0 Resets watchdog timer Does not affect watchdog timer. Resets flip-flop that retains overflow carry of 1 BTM used for watchdog timer. Remark WDTRES is automatically cleared to 0 after it has been set to 1. When it is read, "0" is always read. 42 µPD17145(A1), 17147(A1), 17149(A1) 13.3 Watchdog Timer Function The basic interval timer can also be used as a watchdog timer that detects a program runaway. 13.3.1 Function of watchdog timer The watchdog timer is a counter that generates a reset signal at fixed time intervals. By inhibiting generation of this reset signal by program, the system can be reset (started from address 0000H) if the system becomes runaway due to external noise (if the watchdog timer is not reset within specific time). This function allows the program to escape from the runaway status because a reset signal is generated at fixed time intervals even when the program jumps to an unexpected routine and enters an indefinite loop due to external noise. 13.3.2 Operation of watchdog timer When WDTEN is set to 1, the 1-bit divider is enabled to operate, and the basic interval timer starts operating as an 8-bit watchdog timer. Once the watchdog timer has been started, it cannot be stopped until the device is reset and WDTEN is cleared to 0. Reset effected by the watchdog timer can be inhibited in the following two ways: (1) Repeatedly set WDTRES in the program. (2) Repeatedly set BTMRES in the program. In the case of (1), WDTRES must be set while the count value of the watchdog timer is 8 to 191 (before it reaches 192). Therefore, program so that “SET1 WDTRES” is executed at least once in a cycle shorter than that in which the watchdog timer counts 184. In the case of (2), BTMRES must be set before the basic interval timer (BTM) counts 128. Therefore, program so that “SET1 BTMRES” is executed at least once in a cycle shorter than that in which BTM counts 128. In this case, however, interrupts cannot be processed with BTM. BTM is not reset even if WDTEN is set. Therefore, before setting WDTEN first, be sure to set BTMRES to reset BTM. … Example SET1 BTMRES SET2 WDTEN, WDTRES … Caution 43 µPD17145(A1), 17147(A1), 17149(A1) Figure 13-4. Timing Chart of Watchdog Timer (when WDTRES flag is used) 255 255 192 192 Count value of watchdog timer 255 192 128 128 128 192 128 64 8 8 8 0 0 0 0 WDTEN WDTRES acknowledge period WDTRES acknowledge period WDTRES 1-shot pulse generator output (1) (4) fBTM/27 (2) ( ↓ IRQBTM set) fBTM/28 (3) Watchdog reset signal (active high) Reset signal is not generated 44 WDTRES acknowledge period µPD17145(A1), 17147(A1), 17149(A1) 14. A/D CONVERTER The µ PD17149(A1) is provided with an A/D converter with 4 analog input channels (P0C 0/ADC 0-P0C 3/ADC 3) and a resolution of 8 bits. This A/D converter is of the successive approximation type and operates in the following two modes: 1 Successive mode in which 8-bit A/D conversion is sequentially performed starting from the most 2 Single mode in which an input analog voltage is compared with the set value of an 8-bit data register significant bit 14.1 Configuration of A/D Converter Figure 14-1 shows the configuration of the A/D converter. Figure 14-1. Block Diagram of A/D Converter Remark n = 0 to 3 Internal bus RF: 22H Read signal RF: 20H 0 0 ADCCH1 ADCCH0 P0CnIDI P0CBIOn Selector RF: 21H 0 0 0 ADCSTRT Output latch ADCSOFT 0 ADCCMP ADCEND Control circuit 8 Comparator 4 P0Cn/ADCn 8-bit data register Note (ADCR) Selector A/D end signal STOP instruction signal 8 Tap decoder P0F1/VREF 3R/2 R R R/2 D/A converter 4 P0CnIDI Note P0F1 input data The 8-bit data register (ADCR) is cleared to 00H when the STOP instruction is executed. 45 µPD17145(A1), 17147(A1), 17149(A1) 14.2 Function of A/D Converter (1) ADC 0 to ADC 3 pins These pins input analog voltages to the four channels of the A/D converter. The analog voltages are converted into digital signals. The A/D converter is provided with a sample and hold circuit, and an analog input voltage being converted into a digital signal is internally held. (2) V REF pin This pin inputs a reference voltage to the A/D converter. The signals input to ADC 0 to ADC 3 are converted into digital signals based on the voltage applied across V REF and GND. The A/D converter of the µ PD17149(A1) has a function to automatically stop the current flowing into the V REF pin when the A/D converter does not operate. A current flows into the VREF pin in the following cases: 1 In successive mode (ADCSOFT = 0) Since the ADCSTRT flag has been set to 1 until the ADCEND flag is set to 1. 2 In single mode (ADCSOFT = 1) Since the ADCSTRT flag has been set to 1 or a value has been written to the 8-bit data register until the result of comparison by the comparator is written to the ADCCMP flag. Remarks 1. If the HALT instruction is executed during A/D conversion, the A/D converter operates, in the successive mode, until the ADCEND flag is set, or in the single mode, until the result of conversion is stored to the ADCCMP flag. Therefore, a current flows to the VREF pin during this period. 2. A/D conversion in progress is stopped if the STOP instruction is executed. In this case, the A/D converter is initialized, and the current flowing to the VREF pin is cut (the A/D converter does not operate even if the STOP mode has been released). (3) 8-bit data register (ADCR) This is an 8-bit register that stores the result of A/D conversion of successive approximation type in the successive mode. The contents of this register are read by using the GET instruction. In the single mode, the contents of the 8-bit data register are converted into an analog voltage by an internal D/A converter and is compared by the comparator with an analog signal input from the ADCn pin. A value can be written to this register by using the PUT instruction. (4) Comparator The comparator compares the analog input voltage with the voltage output by the D/A converter. If the analog input voltage is high, it outputs “1”; if the voltage is low, the comparator outputs “0”. The result of comparison is stored to the 8-bit data register (ADCR) in the successive mode, and to the ADCCMP flag in the single mode. 46 µPD17145(A1), 17147(A1), 17149(A1) 14.3 Operation of A/D Converter The operation of the A/D converter can be executed in two modes, depending on the setting of the ADCSOFT flag: successive and single modes. ADCSOFT Operation Mode of A/D Converter 0 Successive mode (A/D conversion) 1 Single mode (compare operation) Figure 14-2. Relationships between Analog Input Voltage and Digital Conversion Result Ideal conversion result FFH FEH Digital conversion result FDH N 03H 02H 01H 00H 0 (× VDD) 1 256 2 256 N 256 254 256 255 256 256 256 Analog input voltage (V) 47 µPD17145(A1), 17147(A1), 17149(A1) (1) Timing in successive mode (A/D conversion) Figure 14-3. Timing in Successive Mode (A/D Conversion) → Number of executed instructions (instruction cycle) POKE 1 2 3 Sampling 4 5 6 Sampling 7 8 9 24 GET Sampling ADCSTRT executed ADCR read ADCSTRT ADCEND 8-bit data register Previous data Caution Initial value:80H Highest 1 bit determined Highest 2 bits determined All 8 bits determined Sampling is performed eight times while A/D conversion is executed once. If the analog input voltage changes heavily during A/D conversion, A/D conversion cannot be performed accurately. To obtain an accurate conversion result, it is necessary to minimize the changes in the analog input voltage during A/D conversion. Remark One sampling time = 14/f x (1.75 µ s, at 8 MHz) Sampling repeat cycle = 48/f x (6 µ s, at 8 MHz) Sampling capacitor capacitance = 100 pF (MAX.) 48 µPD17145(A1), 17147(A1), 17149(A1) (2) Timing in single mode (compare operation) Figure 14-4. Timing in Single Mode (Compare Operation) → Number of executed instructions (instruction cycle) POKE 1 2 PEEK PUT Sampling 1 2 PEEK Sampling ADCSTRT executed ADCCMP read ADCCMP read ADCSTRT ADCEND Previous data ADCCMP Comparison result Comparison result After 1 has been written to ADCSTRT in the single mode (execution of the POKE instruction), a value is stored to ADCCMP three instructions after, and the result of comparison can be read by the PEEK instruction. Even if data is set to ADCR (execution of the PUT instruction), comparison is started in the same manner as ADCSTRT, and the result of comparison can be read three instructions after. The ADCCMP flag is cleared to 0 when reset is executed or when an instruction that writes data to ADCR is executed. Caution Be sure to set ADCSOFT to 1 before setting a value to ADCR. When ADCSOFT = 0, no value can be set to ADCR (the PUT ADCR, DBF instruction is invalidated). Remark Sampling time = 14/f x (1.75 µ s, at 8 MHz) Sampling capacitor capacitance = 100 pF (MAX.) 49 µPD17145(A1), 17147(A1), 17149(A1) 15. SERIAL INTERFACE (SIO) The serial interface of the µ PD17149(A1) consists of an 8-bit shift register (SIOSFR), a serial mode register, and a serial clock counter, and is used to input/output serial data. 15.1 Function of Serial Interface The serial interface can transmit or receive 8-bit data in synchronization with the clock by using three wires: serial clock input (SCK), serial data output (SO), and serial data input (SI) pins. This serial interface can connect various peripheral I/O devices in a mode compatible with the method employed for the µ PD7500 series and 75X series. (1) Serial clock Four types of serial clocks, three internal and one external, can be selected. If an internal clock is selected as the serial clock, the selected clock is automatically output to the P0D 0/SCK pin. Table 15-1. Serial Clocks SIOCK1 SIOCK0 Selected Serial Clock 0 0 External clock from SCK pin 0 1 System clock/16 1 0 System clock/128 1 1 System clock/1024 (2) Transfer operation Each pin of port 0D (P0D 0/SCK, P0D 1/SO, P0D 2/SI) functions as a serial interface pin when SIOEN is set to 1. If SIOTS is set to 1 at this time, the serial interface starts its operation in synchronization with the falling edge of the external or internal clock. If SIOTS is set, IRQSIO is automatically cleared. Data is transferred starting from the most significant bit of the shift register in synchronization with the rising edge of the serial clock, and the information on the SI pin is stored to the shift register, starting from the least significant bit, in synchronization with the rising edge of the serial clock. When 8-bit data has been completely transferred, SIOTS is automatically cleared, and IRQSIO is set. Remark When serial transfer is executed, transfer is started only from the most significant bit of the contents of the shift register. In other words, transfer cannot be started from the least significant bit. The status of the SI pin is always loaded to the shift register in synchronization with the rising edge of the serial clock. 50 µPD17145(A1), 17147(A1), 17149(A1) Figure 15-1. Block Diagram of Serial Interface P0D2/SI LSB MSB Shift register (SIOSFR) SIOTS Serial start P0D1/SO Selector Output latch P0D1 output latch SIOHIZ SIOCK1 SIOCK0 IRQSIO clear signal One shot Serial clock counter P0D0 /SCK Carry Clock IRQSIO set signal Clear Selector S Q R P0D0 output latch fx/16 fx/128 fx/1024 Selector SIOEN P0DBIO0 P0DBIO1 Caution The output latch of the shift register is independent of the output latch of P0D1. Therefore, even if an output instruction is executed to P0D1, the status of the output latch of the shift register is not affected. The output latch of the shift register is cleared to “0” by RESET input. After that, it holds the status of the LSB of the previously transferred data. 51 µPD17145(A1), 17147(A1), 17149(A1) 15.2 Operation Mode of 3-Wire Serial Interface The serial interface can operate in the following two modes. When the serial interface function is selected, the P0D 2/SI pin always inputs data in synchronization with the serial clock. • 8-bit transmission/reception mode (simultaneous transmission/reception) • 8-bit reception mode (SO pin: high-impedance state) Table 15-2. Operation Modes of Serial Interface SIOEN SIOHIZ P0D0/SI Pin P0D 1/SO Pin Operation Mode of Serial Interface 1 0 SI SO 8-bit transmission/reception mode 1 1 SI P0D 1 (input) 8-bit reception mode 0 × P0D 0 (I/O) P0D 1 (I/O) General-purpose port mode × : Don't care (1) 8-bit transmission/reception mode (simultaneous transmission/reception) Input or output of serial data is controlled by the serial clock. The MSB of the shift register is output to the SO line at the falling edge of the serial clock (SCK pin signal). The contents of the shift register are shifted 1 bit at the rising edge of the serial clock. At the same time, the data on the SI line is loaded to the LSB of the shift register. The serial clock counter (3-bit counter) sets an interrupt request flag (IRQSIO <- 1) each time it has counted eight serial clocks. Figure 15-2. Timing in 8-Bit Transmission/Reception Mode (Simultaneous Transmission/Reception) SCK pin 1 2 3 4 5 6 7 8 SI pin DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO pin DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 IRQSIO Starts transfer in synchronization with falling of SCK pin Executes instruction that writes "1" to SIOTS (transfer start command) Remark DI: serial data input DO: serial data output 52 End of transfer µPD17145(A1), 17147(A1), 17149(A1) (2) 8-bit reception mode (SO pin: high-impedance state) The P0D 1/SO pin goes into a high-impedance state when SIOHIZ = 1. If supply of the serial clock is started at this time by writing “1” to SIOTS, the serial interface only receives data. Because the P0D1/SO pin goes into a high-impedance state, it can be used as an input port pin (P0D1). Figure 15-3. Timing in 8-Bit Reception Mode 1 SCK pin SI pin 2 DI7 3 DI6 4 DI5 5 DI4 6 DI3 7 DI2 8 DI1 DI0 Hi - Z SO pin IRQSIO Starts transfer in synchronization with falling of SCK pin End of transfer Executes instruction that writes "1" to SIOTS (transfer start command) Remark DI: serial data input (3) Operation stop mode When the value of SIOTS (RF: address 02H, bit 3) is 0, the serial interface is set in the operation stop mode. In this mode, serial transfer is not executed. Because the shift register does not perform the shift operation in this mode, it can be used as an ordinary 8-bit register. 53 µPD17145(A1), 17147(A1), 17149(A1) 16. INTERRUPT FUNCTION The µ PD17149(A1) has five interrupt causes, of which four are internal and one is external, enabling various applications. The interrupt control circuit of the µ PD17149(A1) has the following features and can perform interrupt processing at extremely high speeds: (a) Acknowledging an interrupt can be controlled by interrupt mask enable flag (INTE) and interrupt enable flag (IP×××). (b) Interrupt request flags (IRQ×××) can be tested and cleared (occurrence of an interrupt can be checked by software). (c) Multiple interrupts of up to 3 levels can be processed. (d) The standby mode (STOP or HALT) can be released by an interrupt request (releasing condition can be selected by the interrupt enable flag). Caution Only the BCD, CMP, CY, Z, and IXE flags are automatically saved to the stack by hardware when interrupt processing is performed. Up to three levels of multiple interrupts can be processed. If the peripheral hardware (timers, A/D converter, etc.) is accessed during interrupt processing, the contents of DBF and WR are not saved by the hardware. It is therefore recommended that DBF and WR be saved to the RAM by software at the beginning of interrupt processing, and that their contents be restored immediately before the interrupt processing. 16.1 Types of Interrupt Causes and Vector Addresses All the interrupts of the µ PD17149 (A1) are vectored interrupts, and therefore, program execution branches to a vector address corresponding to the interrupt cause when an interrupt has been acknowledged. Table 161 shows the types of interrupt causes and vector addresses. If two or more interrupts occur at the same time, or if two or more pending interrupts are enabled all at once, processing is performed according to the priority shown in Table 16-1. Table 16-1. Types of Interrupt Causes Interrupt Cause Priority Vector Address INT pin (RF: 0FH, bit 0) 1 0005H IRQ RF: 3FH, bit 0 IP RF: 2FH, bit 0 Timer 0 2 0004H IRQTM0 RF: 3EH, bit 0 IPTM0 RF: 2FH, bit 1 — IRQTM1 RF: 3DH, bit 0 IPTM1 RF: 2FH, bit 2 — Timer 1 3 0003H IRQ Flag IP Flag Basic interval timer 4 0002H IRQBTM RF: 3CH, bit 0 IPBTM RF: 2FH, bit 3 Serial interface 5 0001H IRQSIO RF: 3BH, bit 0 IPSIO RF: 2EH, bit 0 54 IEG Flag IEGMD0, 1 RF:1FH Internal /External External Internal Internal — Internal Internal — Remark Rising, falling, or both rising and falling edges selectable µPD17145(A1), 17147(A1), 17149(A1) 16.2 Hardware of Interrupt Control Circuit This section describes each flag of the interrupt control circuit. (1) Interrupt request flags and interrupt enable flags An interrupt request flag (IRQ×××) is set to 1 when an interrupt request is generated, and automatically cleared to 0 when interrupt processing is executed. An interrupt enable flag (IP×××) is provided for each interrupt request flag. The corresponding interrupt is enabled when this flag is “1”, and disabled when the flag is “0”. (2) EI/DI instruction Whether an interrupt that has been acknowledged is executed is specified by the EI or DI instruction. When the EI instruction is executed, an interrupt enable flag (INTE) that enables acknowledging an interrupt is set to 1. The INTE flag is not registered on the register file. Therefore, the status of this flag cannot be checked by an instruction. The DI instruction clears the INTE flag to “0”, disabling all the interrupts. The INTE flag is also cleared to 0 at reset, and therefore all the interrupts are disabled. Table 16-2. Interrupt Request Flags and Interrupt Enable Flags Interrupt Request Flag IRQ Interrupt Request Flag Setting Signal Sets when edge of INT pin input signal is detected. Edge to be detected is selected by IEGMD0 and IEGMD1 flags. Interrupt Enable Flag IP IRQTM0 Set by coincidence signal from timer 0. IPTM0 IRQTM1 Set by coincidence signal from timer 1. IPTM1 IRQBTM Set by overflow from basic interval timer (reference time interval signal). IPBTM IRQSIO Set when serial interface completes serial data transfer. IPSIO 55 µPD17145(A1), 17147(A1), 17149(A1) 17. STANDBY FUNCTION 17.1 Outline of Standby Function The current dissipation of the µ PD17149(A1) can be reduced by using the standby function. This function can be effected in two modes: STOP and HALT. The STOP mode stops the system clock. In this mode, the current dissipation by the CPU is minimized with only leakage current flowing. The CPU therefore does not operate, but the contents of the data memory are retained. In the HALT mode, oscillation of the clock continues. However, supply of the clock to the CPU is stopped. Therefore, the CPU stops operating. This mode cannot reduce the current dissipation as much as the STOP mode. However, because the system clock continues oscillating, the operation can be started immediately after the HALT mode has been released. In both the STOP and HALT modes, the statuses of the data memory, registers, and the output latches of the output ports immediately before the standby mode is set are retained (except STOP 0000B). Therefore, set the port status so that the current dissipation of the entire system is reduced before the standby mode is set. 56 µPD17145(A1), 17147(A1), 17149(A1) Table 17-1. Status in Standby Mode HALT Mode Setting instruction STOP instruction HALT instruction Clock oscillation circuit Stops oscillation Continues oscillation Operating status STOP Mode CPU • Stops operation RAM • Retains previous status Port • Retains previous status Note TM0 • Can operate only when INT input is selected as count clock • Stops when system clock is selected (count value is retained) • Operable TM1 • Stops operation (count value is reset to “0”) • Operable (count up is disabled) BTM • Stops operation (count value is retained) • Operable SIO • Can operate only when external clock is selected as serial clock Note • Operable A/D • Stops operation Note (ADCR <- 00H) • Operable INT • Can operate • Operable Note As soon as the STOP 0000B instruction is executed, the pins of these peripherals are set in the input port mode, even when the control signal functions of the pins are used. Cautions 1. Be sure to execute the NOP instruction immediately before the STOP and HALT instructions. 2. If both the interrupt request flag and interrupt enable flag corresponding to an interrupt are set, and if the interrupt is specified to release the standby mode, the standby mode is not set even if the STOP or HALT instruction is executed. 57 µPD17145(A1), 17147(A1), 17149(A1) 17.2 HALT Mode 17.2.1 Setting HALT mode The HALT mode is set when the HALT instruction is executed. The operand of the HALT instruction, b 3b 2b 1b 0, specifies the condition under which the HALT mode is released. Table 17-2. HALT Mode Releasing Condition Format: HALT b 3b 2b 1b 0B Bit HALT mode releasing condition Note 1 b3 Enables releasing HALT mode by IRQ××× when 1 Notes 2, 4 b2 Fixed to “0” b1 Enables forced release of HALT mode by IRQTM1 when 1 Notes 3, 4 b0 Enables releasing HALT mode by RLS input when 1Note 4 Notes 1. Only reset (RESET input or POC) is valid when HALT 0000B is specified. 2. IP××× must be set to 1. 3. The HALT mode is released regardless of the status of IPTM1. 4. Even if the HALT instruction is executed with IRQ××× = 1 or RLS input being low, the HALT instruction is ignored (treated as an NOP instruction), and the HALT mode is not set. 17.2.2 Start address after HALT mode is released The start address from which the program execution is started after the HALT mode has been released differs depending on the interrupt enable condition and the condition under which the HALT mode has been released. Table 17-3. Start Address after HALT Mode Is Released Releasing Condition Reset Note 1 Start Address after Release Address 0 RLS Address next to that of HALT instruction Address next to that of HALT instruction in DI status IRQ××× Note 2 Notes 1. 2. 58 Interrupt vector in EI status (if two or more IRQ××× flags are set, interrupt vector with higher priority) RESET input and POC are valid as reset. IP××× must be set to 1 except when the HALT mode is forcibly released by IRQTM1. µPD17145(A1), 17147(A1), 17149(A1) Figure 17-1. Releasing HALT Mode (a) By RESET input HALT instruction executed ↓ TM1 counts up ↓ RESET Operation mode HALT mode System reset status WAIT a Operation mode (starts from address 0) WAIT a : Wait time until TM1 counts 256 clocks divided by 128 256×128/f X (approx. 4 ms at f X =8 MHz) (b) By RLS input HALT instruction executed ↓ RLS Operation mode HALT mode Operation mode (c) By IRQ××× (in DI status) HALT instruction executed ↓ IRQ××× Operation mode HALT mode Operation mode (d) By IRQ××× (in EI status) HALT instruction executed ↓ Interrupt processing acknowledged ↓ IRQ××× Operation mode HALT mode Operation mode 59 µPD17145(A1), 17147(A1), 17149(A1) 17.3 STOP Mode 17.3.1 Setting STOP mode The STOP mode is set when the STOP instruction is executed. The operand of the STOP instruction, b 3b 2b 1b 0, specifies the condition under which the STOP mode is released. Table 17-4. STOP Mode Releasing Condition Format: STOP b 3b 2b 1b 0B Bit STOP mode releasing condition Note 1 b3 Enables releasing HALT mode by IRQ××× when 1 Notes 2, 4 b2 Fixed to “0” b1 Fixed to “0” b0 Enables releasing STOP mode by RLS input when 1 Notes 3, 4 Notes 1. Only reset (RESET input or POC) is valid when STOP 0000B is specified. When STOP 0000B is executed, the internal circuitry of the microcontroller is initialized to the status immediately after reset. 2. IP××× must be set to 1. The STOP mode cannot be released by IRQTM1. 3. b 0 alone cannot be set to 1 (STOP 0001B is prohibited). Before setting b 0 to 1, be sure to set b 3 to 1. 4. Even if the STOP instruction is executed with IRQ××× = 1 or the RLS input being low, the STOP instruction is ignored (treated as an NOP instruction), and the STOP mode is not set. 17.3.2 Start address after STOP mode is released The start address from which the program execution is started after the STOP mode has been released differs depending on the condition under which the STOP mode has been released, and interrupt enable condition. Table 17-5. Start Address after STOP Mode Is Released Releasing Condition Reset Note 1 Start Address after Release Address 0 RLS Address next to that of STOP instruction Address next to that of HALT instruction in DI status IRQ××× Note 2 Notes 1. 2. 60 Interrupt vector in EI status (if two or more IRQ××× flags are set, interrupt vector with higher priority) RESET input and POC are valid as reset. IP××× must be set to 1. The STOP mode cannot be released by IRQTM1. µPD17145(A1), 17147(A1), 17149(A1) Figure 17-2. Releasing STOP Mode (a) By RESET input STOP instruction executed ↓ TM1 counts up ↓ RESET Operation mode STOP mode System reset status WAIT b Operation mode (starts from address 0) WAIT b : Wait time until TM1 counts 256 clocks divided by 128 256 × 128/fX + α (apporox. 4 ms + α at fX = 8 MHz) α : Oscillation growth time (differs depending on the oscillator) (b) By RLS input STOP instruction executed ↓ TM1 counts up ↓ RLS Operation mode STOP mode WAIT c Operation mode WAIT c : Wait time until TM1 counts clocks divided by m n times n × m/fX + α (n and m are values immediately before STOP mode is set) : α Oscillation growth time (differs depending on the oscillator) (c) By IRQ××× (in DI status) STOP instruction executed ↓ TM1 counts up ↓ IRQ××× Operation mode STOP mode WAIT c Operation mode WAIT c : Wait time until TM1 counts clocks divided by m n times n × m/fX + α (n and m are values immediately before STOP mode is set) α : Oscillation growth time (differs depending on the oscillator) 61 µPD17145(A1), 17147(A1), 17149(A1) (d) By IRQ××× (in EI status) STOP instruction executed ↓ TM1 counts up, interrupt processing acknowledged ↓ IRQ××× Operation mode STOP mode WAIT c Operation mode WAIT c : Wait time until TM1 counts clocks divided by m n times n × m/f X + α (n and m are values immediately before STOP mode is set) α : Oscillation growth time (differs depending on the oscillator) 62 µPD17145(A1), 17147(A1), 17149(A1) 18. RESET The µ PD17149 (A1) can be reset not only by the RESET input, but also by the internal POC circuit that detects a supply voltage drop, watchdog timer function that resets the microcontroller if program runaway occurs, and overflow or underflow of the address stack. Note, however, that the internal POC circuit is a mask option. 18.1 Reset Function The reset function initializes the device operation. How the device is initialized differs depending on the type of reset. Table 18-1. Hardware Status at Reset Type of Reset Hardware Program counter General-purpose data memory • Reset by Internal POC Circuit • Reset by Internal POC Circuit in Standby Mode • Overflow and Underflow of Stack 0000H Input Input Input 0 0 Undefined General-purpose data memory (except DBF) Undefined Retains contents Undefined DBF Undefined Undefined Undefined 0 0 0 Undefined Retains contents Undefined Contents of output latch WR SP = 5H, IRQTM1 = 1, TM1EN = 1, IRQBTM = 1, INT = status at that time. Others are 0. Refer to 8. REGISTER FILE (RF). Control register SP = 5H, INT = status at that time. Others retain contents. Count register 00H 00H Timer 0: 00H, timer 1: undefined Modulo register FFH FFH FFH Undefined Undefined Undefined Retains contents Undefined 0 0 Undefined 00H 00H 00H Binary counter of basic interval timer Serial interface • Overflow of Watchdog Timer 0000H System register (except WR) Timer 0 and timer 1 • RESET Input in Standby Mode 0000H Input/output Port • RESET Input during Operation Shift register (SIOSFR) Output latch Data register of A/D converter (ADCR) Undefined. However, 40H if watchdog timer overflows. 63 µPD17145(A1), 17147(A1), 17149(A1) Figure 18-1. Configuration of Reset Block VDD POC circuit (mask option) Mask option Internal reset signal RESET 18.2 Reset Operation Figure 18-2 shows the operation when the system is reset by using the RESET pin. When the RESET pin is made high, oscillation of the system clock is started, oscillation stabilization wait time specified by timer 1 elapses, and program execution is started from address 0000H. These operations are also performed if the system is reset by the POC circuit. If the system is reset by using an overflow of the watchdog timer or an overflow or underflow of the stack, the oscillation stabilization wait time (WAIT a) does not elapse, and program execution is started from address 0000H after the internal circuitry has been initialized. Figure 18-2. Reset Operation RESET TM1EN TM1RES Operation mode Note Reset Note WAIT a Operation mode Oscillation stabilization wait time. An operation mode is set when system clock is counted 128 × 256 times by timer 1 (time required to executed 2048 instructions: approx. 4 ms at 8 MHz). 64 µPD17145(A1), 17147(A1), 17149(A1) 19. POC CIRCUIT (MASK OPTION) The POC circuit monitors the supply voltage. When the supply voltage is turned ON/OFF, it automatically resets the internal circuitry of the microcontroller. This circuit can be used in an application circuit with a clock frequency of 400 kHz to 4 MHz. The µ PD17149 (A1) can be provided with the POC circuit by mask option. Caution The POC circuit is not provided to the PROM model ( µ PD17P149). 19.1 Function of POC Circuit The POC circuit has the following functions: • Generates internal reset signal when V DD ≤ VPOC • Clears internal reset signal when VDD > V POC (where, V DD: supply voltage, V POC : POC detection voltage) Figure 19-1. Operation of POC Circuit VDD 5.5 V 4.5 V VPOC 2.7 V Note 3 Note 3 0V →t Internal reset signal Operation modeNote 4 Reset Note 1 ↑ Reset Note 2 Operation guaranteed range 65 µPD17145(A1), 17147(A1), 17149(A1) Notes 1. Actually, oscillation stabilization wait time specified by timer 1 elapses before the operation mode is set. This time is equal to that required for executing about 2048 instructions (approx. 8 ms at 4 MHz). 2. To reset the microcontroller again when the supply voltage drops, the status in which the voltage drops below V POC must be maintained at least for the duration of the reset detection pulse width t SAMP. Therefore, reset is actually effected with a delay time of up to tSAMP. 3. The operation is not guaranteed if the supply voltage drops below the rated minimum value (2.7 V). However, the POC circuit is designed to generate the internal reset signal so long as it is possible, regardless of oscillation. Therefore, the internal circuitry is reset when the voltage supplied to it has reached the level at which the circuitry can operate. 4. If the supply voltage abruptly increases (3 V/ms MIN.), the POC circuit may generate the internal reset signal, even in an operation mode, to prevent program runaway. Remark For the values of V POC and t SAMP, refer to 22. ELECTRICAL SPECIFICATIONS. 19.2 Conditions to Use POC Circuit The POC circuit can be used when the application circuit satisfies the following conditions: • The application circuit does not require a high reliability. • The operating voltage must range from 4.5 to 5.5 V. • The clock frequency must range from 400 kHz to 4 MHz. • The supply voltage must satisfy the ratings of the POC circuit. Cautions 1. If the application circuit requires an extremely high reliability, design the circuit so that 2. The current dissipation in the standby mode slightly increases if the POC circuit is the RESET signal is input from an external source. used. Remark 66 The guaranteed operating voltage range of the POC circuit is V DD = 2.7 to 5.5 V. µPD17145(A1), 17147(A1), 17149(A1) 20. INSTRUCTION SET 20.1 Outline of Instruction Set b 15 b 14-b 11 0 1 BIN HEX 0000 0 ADD r, m ADD m, #n4 0001 1 SUB r, m SUB m, #n4 0010 2 ADDC r, m ADDC m, #n4 0011 3 SUBC r, m SUBC m, #n4 0100 4 AND r, m AND m, #n4 0101 5 XOR r, m XOR m, #n4 0110 6 OR r, m OR m, #n4 INC AR INC IX MOVT DBF, @AR BR @AR CALL @AR RET RETSK EI DI 0111 7 RETI PUSH AR POP AR GET DBF, p PUT p, DBF PEEK WR, rf POKE rf, WR RORC r STOP s HALT h NOP 1000 8 LD r, m ST m, r 1001 9 SKE m, #n4 SKGE m, #n4 1010 A MOV @r, m MOV m, @r 1011 B SKNE m, #n4 SKLT m, #n4 1100 C BR addr (page 0) CALL addr 1101 D BR addr (page 1) MOV m, #n4 1110 E SKT m, #n 1111 F SKF m, #n 67 µPD17145(A1), 17147(A1), 17149(A1) 20.2 Legend AR ASR : address stack register indicated by stack pointer addr : program memory address (lower 11 bits) BANK : bank register CMP : compare flag CY : carry flag DBF : data buffer h : halt release condition INTEF : interrupt enable flag INTR : register automatically saved to the stack when interrupt processing is performed INTSK : interrupt stack register IX : index register MP : data memory row address pointer MPE : memory pointer enable flag : data memory address indicated by m R , mC m mR : data memory row address (high) mC : data memory column address (low) n : bit position (4 bits) n4 : immediate data (4 bits) PAGE : page (bit 11 of program counter) PC : program counter p : peripheral address pH pL r : peripheral address (higher 3 bits) : peripheral address (lower 4 bits) : general register column address rf : register file address rf R : register file row address (higher 3 bits) rf C : register file column address (lower 4 bits) SP : stack pointer s : stop release condition WR : window register (×) 68 : address register : contents addressed by × µPD17145(A1), 17147(A1), 17149(A1) 20.3 Instruction Set Instruc- Mnemonic tion Operand (r) ← (r) + (m) 00000 mR mC r m, #n4 (m) ← (m) + n4 10000 mR mC n4 r, m (r) ← (r) + (m) + CY 00010 mR mC r m, #n4 (m) ← (m) + n4 + CY 10010 mR mC n4 AR AR ← AR + 1 00111 000 1001 0000 IX IX ← IX + 1 00111 000 1000 0000 r, m (r) ← (r) – (m) 00001 mR mC r m, #n4 (m) ← (m) – n4 10001 mR mC n4 r, m (r) ← (r) – (m) – CY 00011 mR mC r m, #n4 (m) ← (m) – n4 – CY 10011 mR mC n4 r, m (r) ← (r) ∨ (m) 00110 mR mC r m, #n4 (m) ← (m) ∨ n4 10110 mR mC n4 r, m (r) ← (r) ∧ (m) 00100 mR mC r m, #n4 (m) ← (m) ∧ n4 10100 mR mC n4 r, m (r) ← (r) ∨ (m) 00101 mR mC r m, #n4 (m) ← (m) ∨ n4 10101 mR mC n4 SKT m, #n CMP ← 0, if (m) ∧ n = n, then skip 11110 mR mC n SKF m, #n CMP ← 0, if (m) ∧ n = 0, then skip 11111 mR mC n SKE m, #n4 (m) – n4, skip if zero 01001 mR mC n4 SKNE m, #n4 (m) – n4, skip if not zero 01011 mR mC n4 SKGE m, #n4 (m) – n4, skip if not borrow 11001 mR mC n4 SKLT m, #n4 (m) – n4, skip if borrow 11011 mR mC n4 RORC r 00111 000 0111 r LD r, m (r) ← (m) 01000 mR mC r ST m, r (m) ← (r) 11000 mR mC r 01010 mR mC r 11010 mR mC r 11101 mR mC n4 00111 000 0001 0000 Addition ADDC Subtraction Logical operation OR Judgment SUB Comparison Operand r, m INC Rotation Instruction code op code ADD SUBC AND XOR → CY → (r) b 3 → (r) b 2 → (r) b 1 → (r) b 0 @r, m MOV m, @r Transfer Operation m, #n4 if MPE = 1: (MP, (r)) ← (m) if MPE = 0: (BANK, mR , (r)) ← (m) if MPE = 1: (m) ← (MP, (r)) if MPE = 0: (m) ← (BANK, m R, (r)) (m) ← n4 SP ← SP –1, ASR ← PC, PC ← AR, MOVT DVF, @AR PUSH AR SP ← SP –1, ASR ← AR 00111 000 1101 0000 POP AR AR ← ASR, SP ← SP +1 00111 000 1100 0000 PEEK WR, rf WR ← (rf) 00111 rf R 0011 rf C POKE rf, WR (rf) ← WR 00111 rf R 0010 rf C GET DBF, p DBF ← (p) 00111 pH 1011 pL PUT p, DBF (p) ← DBF 00111 pH 1010 pL DBF ← (PC), PC ← ASR, SP ← SP +1 69 µPD17145(A1), 17147(A1), 17149(A1) Branch Instruc- Mnemonic tion Operand Operation addr Note @AR PC ← AR BR Instruction code op code Operand Note addr 00111 000 0100 0000 11100 addr 00111 000 0101 0000 SP ← SP – 1, ASR ← PC, Others Interrupt Subroutine addr CALL @AR PC ← addr SP ← SP – 1, ASR ← PC, PC ← AR RET PC ← ASR, SP ← SP + 1 00111 000 1110 0000 RETSK PC ← ASR, SP ← SP + 1 and skip 00111 001 1110 0000 RETI PC ← ASR, INTR ← INTSK, SP ← SP + 1 00111 100 1110 0000 EI INTEF ← 1 00111 000 1111 0000 DI INTEF ← 0 00111 001 1111 0000 STOP s STOP 00111 010 1111 s HALT h HALT 00111 011 1111 h No operation 00111 100 1111 0000 NOP Note The operation and op code of “BR addr” of the µ PD17145(A1), 17147(A1), and µ PD17149(A1) are as follows: (a) µ PD17145(A1), 17147(A1) Mnemonic BR Operand addr Operation PC ← addr, PAGE ← 0 op code 01100 (b) µ PD17149(A1) Mnemonic BR 70 Operand addr Operation op code PC ← addr, PAGE ← 0 01100 PC ← addr, PAGE ← 1 01101 µPD17145(A1), 17147(A1), 17149(A1) 20.4 Assembler (AS17K) Embedded Macro Instruction Legend flag n: FLG type symbol < >: Can be omitted Embedded macro Mnemonic Operand Operation n SKTn flag 1, …flag n if (flag 1) to (flag n) = all “1”, then skip 1≤n≤4 SKFn flag 1, …flag n if (flag 1) to (flag n) = all“0”, then skip 1≤n≤4 SETn flag 1, …flag n (flag 1) to (flag n) ← 1 1≤n≤4 CLRn flag 1, …flag n (flag 1) to (flag n) ← 0 1≤n≤4 NOTn flag 1, …flag n if (flag n) = “1”, then (flag n) ← 0 <NOT> flag 1, if description = NOT flag n, then (flag n) ← 0 …<<NOT> flag n> if description = flag n, then (flag n) ← 1 INITFLG BANKn if (flag n) = “0”, then (flag n) ← 1 (BANK) ← n 1≤n≤4 1≤n≤4 n=0 71 µPD17145(A1), 17147(A1), 17149(A1) 21. ASSEMBLER RESERVED WORDS 21.1 Mask Option Directive The µ PD17149 (A1) has the following mask options: • Internal pull-up resistor of RESET pin • Internal pull-up resistor of P0F 1 and P0F 0 pins • Internal pull-up resistor of INT pin • Internal POC circuit When developing a program, it is necessary to specify all the above mask options in the source program by using a mask option definition directive (pseudo instruction). 21.1.1 Specifying mask option The mask option is described in the assembler source program by using the following directives: • OPTION directive, ENDOP directive • Mask option definition directive (1) OPTION and ENDOP directives These directives specify the range in which the mask option is specified (mask option definition block). Specify the mask option by describing a mask option definition directive in the area sandwiched between the OPTION and ENDOP directives. Format Mnemonic field [label:] OPTION … Symbol field ENDOP 72 Operand field Comment field [;comment] µPD17145(A1), 17147(A1), 17149(A1) (2) Mask option definition directives Table 21-1. Mask Option Definition Directives Option Internal pull-up resistor Definition Directive and Format OPTRES <operand> of RESET pin Internal pull-up resistor OPTP0F <operand 1>, <operand 2> Note of P0F 1 and P0F 0 pins Internal pull-up resistor OPTINT <operand> of INT pin Internal POC circuit Note OPTPOC <operand> Operand Defined Contents OPEN None PULLUP Defined OPEN None PULLUP Defined OPEN None PULLUP Defined NOUSE Not used USE Used <operand 1> specifies the mask option of the P0F 1 pin, and <operand 2> specifies that of the P0F 0 pin. (3) Example of mask option description ; Example of describing mask option of the µ PD17149 (A1) MASK_OPTION: OPTION ; start of mask option definition block OPTRES PULLUP ; connects internal pull-up resistor to RESET pin OPTP0F PULLUP, OPEN ; connects internal pull-up resistor to P0F1, and leaves P0F 0 open (externally pulled up) OPTINT PULLUP ; connects internal pull-up resistor to INT pin OPTPOC NOUSE ; internal POC circuit is not used ENDOP ; End of mask option definition block 73 µPD17145(A1), 17147(A1), 17149(A1) 21.2 Reserved Symbols The following tables show the reserved symbols defined by the device file (AS17149) of the µ PD17149(A1): System register (SYSREG) Symbol Name Attribute Value Read/Write Description AR3 MEM 0.74H R AR2 MEM 0.75H R/W Bits b11-b8 of address register AR1 MEM 0.76H R/W Bits b7-b4 of address register AR0 MEM 0.77H R/W Bits b3-b0 of address register WR MEM 0.78H R/W Window register BANK MEM 0.79H R/W Bank register IXH MEM 0.7AH R/W Index register, high MPH MEM 0.7AH R/W Data memory row address pointer, high MPE FLG 0.7AH.3 R/W Memory pointer enable flag IXM MEM 0.7BH R/W Index register, middle MPL MEM 0.7BH R/W Data memory row address pointer, low IXL MEM 0.7CH R/W Index register, low RPH MEM 0.7DH R/W General register pointer, high RPL MEM 0.7EH R/W General register pointer, low PSW MEM 0.7FH R/W Program status word BCD FLG 0.7EH.0 R/W BCD flag CMP FLG 0.7FH.3 R/W Compare flag CY FLG 0.7FH.2 R/W Carry flag Z FLG 0.7FH.1 R/W Zero flag IXE FLG 0.7FH.0 R/W Index enable flag 74 Bits b15-b12 of address register µPD17145(A1), 17147(A1), 17149(A1) Figure 21-1. Configuration of System Register Address 74H 76H 77H Address register (AR) Name Symbol Bit 75H AR3 AR2 AR1 AR0 78H 79H Window register (WR) Bank register (BANK) WR BANK 7AH 7BH 7CH Index register (IX) IXM MPH MPL 7EH 7FH General register Program status word pointer (PSWORD) (RP) Data memory row address pointer (MP) IXH 7DH IXL RPH RPL PSW b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 (IX) M DataNote 1 0 0 0 0 Note 2 0 0 0 0 P 0 0 0 0 (AR) (BANK) E (MP) 0 0 0 0 (RP) B C C I C M Y Z X D P E Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Undefined 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value at reset Notes 1. 2. “0” in this field means that the bit is fixed to “0”. b 3 and b 2 of AR2 of the µ PD17145 (A1) are fixed to 0. b3 of AR2 of the µ PD17147 (A1) is fixed to 0. 75 µPD17145(A1), 17147(A1), 17149(A1) Data buffer (DBF) Symbol Name Attribute Value Read/Write Description DBF3 MEM 0.0CH R/W Bits 15 to 12 of DBF DBF2 MEM 0.0DH R/W Bits 11 to 8 of DBF DBF1 MEM 0.0EH R/W Bits 7 to 4 of DBF DBF0 MEM 0.0FH R/W Bits 3 to 0 of DBF Port register Symbol Name Attribute Value Read/Write Description P0A3 FLG 0.70H.3 R/W Bit 3 of port 0A P0A2 FLG 0.70H.2 R/W Bit 2 of port 0A P0A1 FLG 0.70H.1 R/W Bit 1 of port 0A P0A0 FLG 0.70H.0 R/W Bit 0 of port 0A P0B3 FLG 0.71H.3 R/W Bit 3 of port 0B P0B2 FLG 0.71H.2 R/W Bit 2 of port 0B P0B1 FLG 0.71H.1 R/W Bit 1 of port 0B P0B0 FLG 0.71H.0 R/W Bit 0 of port 0B P0C3 FLG 0.72H.3 R/W Bit 3 of port 0C P0C2 FLG 0.72H.2 R/W Bit 2 of port 0C P0C1 FLG 0.72H.1 R/W Bit 1 of port 0C P0C0 FLG 0.72H.0 R/W Bit 0 of port 0C P0D3 FLG 0.73H.3 R/W Bit 3 of port 0D P0D2 FLG 0.73H.2 R/W Bit 2 of port 0D P0D1 FLG 0.73H.1 R/W Bit 1 of port 0D P0D0 FLG 0.73H.0 R/W Bit 0 of port 0D P0E3 FLG 0.6EH.3 R/W Bit 3 of port 0E P0E2 FLG 0.6EH.2 R/W Bit 2 of port 0E P0E1 FLG 0.6EH.1 R/W Bit 1 of port 0E P0E0 FLG 0.6EH.0 R/W Bit 0 of port 0E P0F1 FLG 0.6FH.1 R Bit 1 of port 0F P0F0 FLG 0.6FH.0 R Bit 0 of port 0F 76 µPD17145(A1), 17147(A1), 17149(A1) Register file (control registers) Symbol Name Attribute Value Read/Write Description SP MEM 0.81H R/W Stack pointer SIOTS FLG 0.82H.3 R/W Serial interface start flag SIOHIZ FLG 0.82H.2 R/W P0D 1/SO pin function select flag SIOCK1 FLG 0.82H.1 R/W Bit 1 of serial clock select flag SIOCK0 FLG 0.82H.0 R/W Bit 0 of serial clock select flag WDTRES FLG 0.83H.3 R/W Watchdog timer reset flag WDTEN FLG 0.83H.0 R/W Watchdog timer enable flag TM1OSEL FLG 0.8BH.3 R/W P0D3/TM1OUT pin function select flag SIOEN FLG 0.8BH.0 R/W Serial interface enable flag P0EGPU FLG 0.8CH.2 R/W P0E group pull-up select flag (pull-up = 1) P0BGPU FLG 0.8CH.1 R/W P0B group pull-up select flag (pull-up = 1) P0AGPU FLG 0.8CH.0 R/W P0A group pull-up select flag (pull-up = 1) P0DBPU3 FLG 0.8DH.3 R/W P0D 3 pull-up select flag (pull-up = 1) P0DBPU2 FLG 0.8DH.2 R/W P0D 2 pull-up select flag (pull-up = 1) P0DBPU1 FLG 0.8DH.1 R/W P0D 1 pull-up select flag (pull-up = 1) P0DBPU0 FLG 0.8DH.0 R/W P0D 0 pull-up select flag (pull-up = 1) INT FLG 0.8FH.0 R INT pin status flag TM0EN FLG 0.91H.3 R/W Timer 0 enable flag TM0RES FLG 0.91H.2 R/W Timer 0 reset flag TM0CK1 FLG 0.91H.1 R/W Bit 1 of timer 0 count pulse select flag TM0CK0 FLG 0.91H.0 R/W Bit 0 of timer 0 count pulse select flag TM1EN FLG 0.92H.3 R/W Timer 1 enable flag TM1RES FLG 0.92H.2 R/W Timer 1 reset flag TM1CK1 FLG 0.92H.1 R/W Bit 1 of timer 1 count pulse select flag TM1CK0 FLG 0.92H.0 R/W Bit 0 of timer 1 count pulse select flag BTMISEL FLG 0.93H.3 R/W Basic interval timer interrupt request clock select flag BTMRES FLG 0.93H.2 R/W Basic interval timer reset flag BTMCK1 FLG 0.93H.1 R/W Bit 1 of basic interval timer count pulse select flag BTMCK0 FLG 0.93H.0 R/W Bit 0 of basic interval timer count pulse select flag P0C3IDI FLG 0.9BH.3 R/W P0C3 input port disable flag (selects ADC3/P0C3 pin function) P0C2IDI FLG 0.9BH.2 R/W P0C2 input port disable flag (selects ADC2/P0C2 pin function) P0C1IDI FLG 0.9BH.1 R/W P0C1 input port disable flag (selects ADC1/P0C1 pin function) P0C0IDI FLG 0.9BH.0 R/W P0C0 input port disable flag (selects ADC0/P0C0 pin function) P0CBIO3 FLG 0.9CH.3 R/W P0C3 input/output select flag (1 = output port) P0CBIO2 FLG 0.9CH.2 R/W P0C2 input/output select flag (1 = output port) P0CBIO1 FLG 0.9CH.1 R/W P0C1 input/output select flag (1 = output port) P0CBIO0 FLG 0.9CH.0 R/W P0C0 input/output select flag (1 = output port) IEGMD1 FLG 0.9FH.1 R/W Bit 1 of INT pin edge detection select flag IEGMD0 FLG 0.9FH.0 R/W Bit 0 of INT pin edge detection select flag 77 µPD17145(A1), 17147(A1), 17149(A1) Register file (control registers) Symbol Name Attribute Value Read/Write Description ADCSTRT FLG 0.0A0H.0 R/W A/D converter start flag (read: always “0”) ADCSOFT FLG 0.0A1H.3 R/W A/D converter mode select flag (1 = single mode) ADCCMP FLG 0.0A1H.1 R A/D converter comparator comparison result flag (valid only in single mode) ADCEND FLG 0.0A1H.0 R A/D converter conversion end flag ADCCH3 FLG 0.0A2H.3 R/W Dummy flag ADCCH2 FLG 0.0A2H.2 R/W Dummy flag ADCCH1 FLG 0.0A2H.1 R/W Bit 1 of A/D converter channel select flag ADCCH0 FLG 0.0A2H.0 R/W Bit 0 of A/D converter channel select flag P0DBIO3 FLG 0.0ABH.3 R/W P0D 3 input/output select flag (1 = output port) P0DBIO2 FLG 0.0ABH.2 R/W P0D 2 input/output select flag (1 = output port) P0DBIO1 FLG 0.0ABH.1 R/W P0D 1 input/output select flag (1 = output port) P0DBIO0 FLG 0.0ABH.0 R/W P0D 0 input/output select flag (1 = output port) P0EGIO FLG 0.0ACH.2 R/W P0E group input/output select flag (1 = all P0E as output port) P0BGIO FLG 0.0ACH.1 R/W P0B group input/output select flag (1 = all P0B as output port) P0AGIO FLG 0.0ACH.0 R/W P0A group input/output select flag (1 = all P0A as output port) IPSIO FLG 0.0AEH.0 R/W Serial interface interrupt enable flag IPBTM FLG 0.0AFH.3 R/W Basic interval timer interrupt enable flag IPTM1 FLG 0.0AFH.2 R/W Timer 1 interrupt enable flag IPTM0 FLG 0.0AFH.1 R/W Timer 0 interrupt enable flag IP FLG 0.0AFH.0 R/W INT pin interrupt enable flag IRQSIO FLG 0.0BBH.0 R/W Serial interface interrupt request flag IRQBTM FLG 0.0BCH.0 R/W Basic interval timer interrupt request flag IRQTM1 FLG 0.0BDH.0 R/W Timer 1 interrupt request flag IRQTM0 FLG 0.0BEH.0 R/W Timer 0 interrupt request flag IRQ FLG 0.0BFH.0 R/W INT pin interrupt request flag 78 µPD17145(A1), 17147(A1), 17149(A1) Peripheral hardware registers Symbol Name Attribute Value Read/Write Description SIOSFR DAT 01H R/W Peripheral address of shift register TM0M DAT 02H W Peripheral address of timer 0 modulo register TM1M DAT 03H W Peripheral address of timer 1 modulo register ADCR DAT 04H R/W TM0TM1C DAT 45H R AR DAT 40H R/W Peripheral address of A/D converter data register Peripheral address of timer 0 timer 1 count register Peripheral address of address register for GET/PUT/ PUSH/CALL/BR/MOVT/INC instruction Others Symbol Name Attribute Value Description DBF DAT 0FH Fixed operand value of PUT, GET, and MOVT instructions IX DAT 01H Fixed operand value of INC instruction 79 µPD17145(A1), 17147(A1), 17149(A1) Figure 21-2. Configuration of Control Register Column address Row address 0 Item 1 2 S P Symbol 0 At reset 0 0 (8) 0 1 Symbol 1 (9) At reset W D T 0 E N 0 0 0 At reset 0 0 2 (A) 0 R/W 0 0 0 0 R/W 0 T M 0 C K 0 T M 1 E N T M 1 R E S T M 1 C K 1 T B B B B M T T T T 1 M M M M C I R C C K S E K K 0 E S 1 0 L 0 0 0 0 1 0 0 0 R/W A D C C H 3 A D C C H 2 A D C C H 1 A D C C H 0 0 0 0 0 0 R/W 0 R 7 0 0 0 0 R/W A A A D D D C C C S 0 C E O M N F P D T 0 6 R/W T M 0 C K 1 0 5 0 T M 0 R E S R/W Symbol 0 T M 0 E N Read/ Write A D C 0 0 S T R T 4 S S S S W I I I I D O O O O T T H C C R 0 S I K K E Z 1 0 S R/W Read/ Write Read/ Write 1 3 R/W Symbol 3 (B) At reset Read/ Write Remark ( ) is the address when the assembler (AS17K) is used. All the flags of the control register are registered to the device file as assembler reserved words, and are convenient for program development. 80 µPD17145(A1), 17147(A1), 17149(A1) Figure 21-2. Configuration of Control Register 8 9 A B C E F S P P I 0 0 O E B 0 E 0 G G N P P U U P 0 A G P U P 0 D B P U 3 P 0 D B P U 2 P 0 D B P U 1 P 0 D B P U 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 R/W I N T R/W P 0 C 2 I D I P 0 C 1 I D I P 0 C 0 I D I P 0 C B I O 3 P 0 C B I O 2 P 0 C B I O 1 P 0 C B I O 0 0 0 0 0 0 0 0 0 0 0 R/W P 0 D B I O 2 P 0 D B I O 1 P P 0 0 D E B 0 G I I O O 0 P 0 B G I O P 0 A G I O 0 0 0 0 0 0 R/W 0 0 0 0 R/W 0 0 0 0 R/W I R Q 0 S 0 I O 0 0 0 0 0 0 R/W I E G M D 0 0 0 0 I P S 0 I O I P B T M I P T M 1 I I P P T M 0 0 0 0 0 0 R/W I R Q 0 B 0 T M 0 I E G 0 M D 1 R/W P 0 D B I O 3 0 Note R P 0 C 3 I D I R/W Note D T M 1 O 0 S E L 1 0 0 0 I R Q 0 T 0 M 1 0 1 0 R/W 0 0 R/W I R Q 0 T 0 M 0 0 R/W 0 0 0 I R Q 0 0 0 0 0 R/W INT flag differs depending on the status of the INT pin at that time. 81 µPD17145(A1), 17147(A1), 17149(A1) 22. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T a = 25 °C) Parameter Symbol Condition Ratings Unit Supply voltage V DD –0.3 to +7.0 V A/D converter reference voltage V REF –0.3 to V DD + 0.3 V –0.3 to V DD + 0.3 V –0.3 to V DD + 0.3 V Peak value –15 mA Effective value –7.5 mA Peak value –30 mA Effective value –15 mA Peak value 15 mA Effective value 7.5 mA Peak value 30 mA Effective value 15 mA Peak value 100 mA Effective value 50 mA Input voltage VI P0A, P0B, P0C, P0D, P0E, P0F, INT, RESET, X IN Output voltage VO Per P0A, P0B, or P0C I OHNote High-level output current Total of P0A, P0B, and P0C Per P0A, P0B, or P0C Per P0D or P0E I OLNote Low-level output current Total of P0A, P0B, P0C, P0D, and P0E Operating temperature T opt –40 to +110 °C Storage temperature T stg –65 to +150 °C Power dissipation Pd 28-pin plastic shrink DIP 140 mW 28-pin plastic SOP 85 mW Note Caution T a = 85 °C [Effective value] = [Peak value] × √Duty If the value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings are the values exceeding which may physically damage the product. Be sure to use the product with these values not exceeded. Recommended Supply Voltage Range (T a = –40 to +110 °C) Parameter Symbol Condition 82 TYP. MAX. Unit f x = 400 kHz to 2 MHz 2.7 5.5 V f x = 400 kHz to 4 MHz 3.6 5.5 V f x = 400 kHz to 8 MHz 4.5 5.5 V A/D converter Absolute accuracy: ±1.5LSB, 2.5 V ≤ V REF ≤ V DD 4.0 5.5 V POC circuit (mask option) f x = 400 kHz to 4 MHz 4.5 5.5 V CPU (other than A/D converter and POC circuit) Supply voltage MIN. V DD µPD17145(A1), 17147(A1), 17149(A1) DC Characteristics (V DD = 2.7 to 5.5 V, T a = –40 to +110 °C) Parameter Input voltage, high Input voltage, low Symbol Condition MIN. TYP. MAX. Unit V IH1 P0A, P0B, P0C, P0D, P0E, P0F 0.7VDD V DD V V IH2 RESET, SCK, SI, INT 0.8VDD V DD V V IH3 X IN V DD – 0.5 V DD V V IL1 P0A, P0B, P0C, P0D, P0E, P0F 0 0.3VDD V V IL2 RESET, SCK, SI, INT 0 0.2VDD V V IL3 X IN 0 0.4 V 4.5 ≤ V DD ≤ 5.5 V DD – 0.3 V V DD – 0.3 V I OH = –1.0 mA Output voltage, high V OH P0A, P0B, P0C 2.7 ≤ V DD < 4.5 I OH = –0.5 mA 4.5 ≤ V DD ≤ 5.5 0.3 V 0.3 V I OL = 1.0 mA V OL1 P0A, P0B, P0C, P0D, P0E Output voltage, low 2.7 ≤ V DD < 4.5 I OL = 0.5 mA V OL2 P0D, P0E 4.5 ≤ V DD ≤ 5.5 1.0 V I OL = 15 mA 2.7 ≤ V DD < 4.5 2.0 V Input leakage current, high I LIH P0A, P0B, P0C, P0D, P0E, P0F V IN = V DD 5 µA Input leakage current, low I LIL P0A, P0B, P0C, P0D, P0E, P0F V IN = 0 V –5 µA Output leakage current, high I LOH P0A, P0B, P0C, P0D, P0E V OUT = V DD 5 µA Output leakage current, low I LOL P0A, P0B, P0C, P0D, P0E V OUT = 0 V Internal pull-up resistorNote 1 –5 µA P0A, P0B, P0E, P0F, RESET, INT 50 100 250 kΩ P0D 3 10 30 kΩ RPULL I DD1 Operation mode fx = 8.0 MHz VDD = 5 V ± 10 % 2.0 4.5 mA fx = 4.0 MHz VDD = 5 V ± 10 % 1.4 3.3 mA fx = 2.0 MHz VDD = 3 V ± 10 % 0.5 1.5 mA VDD = 5 V ± 10 % 0.9 1.7 mA VDD = 3 V ± 10 % 0.3 1.0 mA fx = 8.0 MHz VDD = 5 V ± 10 % 1.0 2.0 mA fx = 4.0 MHz VDD = 5 V ± 10 % 0.9 1.9 mA fx = 2.0 MHz VDD = 3 V ± 10 % 0.3 1.0 mA VDD = 5 V ± 10 % 0.7 1.5 mA VDD = 3 V ± 10 % fx = 400 kHz Supply current Note 2 I DD2 HALT mode fx = 400 kHz I DD3 Notes 1. 2. STOP mode 0.3 0.9 mA V DD = 5 V ± 10 % 3.0 30 µA V DD = 3 V ± 10 % 2.0 30 µA The pull-up resistors of P0F, RESET, and INT are mask options. Excluding the current of the A/D converter and POC circuit, and the current flowing into the internal pull-up resistor. 83 µPD17145(A1), 17147(A1), 17149(A1) AC Characteristics (V DD = 2.7 to 5.5 V, T a = –40 to +110 ˚C) Parameter CPU clock cycle time (instruction execution time) Symbol t CY Condition MIN. TYP. MAX. Unit V DD = 4.5 to 5.5 V 1.9 41 µs V DD = 3.6 to 5.5 V 3.9 41 µs 7.9 41 µs 0 400 kHz INT input frequency f INT (TM0 count clock input) INT high-, low-level width t INTH, (external interrupt input) t INTL RESET low-level width t RSL V DD = 4.5 to 5.5 V V DD = 4.5 to 5.5 V RLS low-level width Remark t RLSL V DD = 4.5 to 5.5 V t CY = 16/f x (f x: system clock oscillation frequency) Interrupt input timing t INTL INT RESET input timing t RSL RESET RLS input timing t RLSL RLS 84 t INTH 10 µs 50 µs 10 µs 50 µs 10 µs 50 µs µPD17145(A1), 17147(A1), 17149(A1) Serial transfer operation (VDD = 2.7 to 5.5 V, Ta = –40 to +110 °C) Parameter Symbol Condition MIN. TYP. MAX. 2.0 µs 10 µs 2.0 µs 8 µs 32 µs CL = 100 pF 64 µs V DD = 4.5 to 5.5 V 1.0 µs 5.0 µs V DD = 4.5 to 5.5 V Input RL = 1 kΩ, SCK cycle time V DD = 4.5 to 5.5 V t KCY CL = 100 pF Output Internal pull-up, V DD = 4.5 to 5.5 V Input SCK high-, low-level t KH, width t KL Unit RL = 1 kΩ, V DD = 4.5 to 5.5 V t KCY/2 – 0.6 µs t KCY/2 – 1.2 µs V DD = 4.5 to 5.5 V t KCY /2 – 12 µs t KCY /2 – 24 µs CL = 100 pF Output Internal pull-up, CL = 100 pF SI setup time (to SCK ↑) t SIK 100 ns SI hold time (from SCK ↑) t KSI 100 ns V DD = 4.5 to 5.5 V 0.8 µs 1.4 µs 14 µs 26 µs RL = 1 kΩ, C L = 100 pF SO output delay time t KSO from SCK ↓ Internal pull-up, V DD = 4.5 to 5.5 V CL = 100 pF Remark R L: load resistance of output line C L: load capacitance of output line VDD RL Output line CL Serial transfer timing t KCY t KL t KH SCK t SIK t KSI Input data SI t KSO SO Output data 85 µPD17145(A1), 17147(A1), 17149(A1) A/D Converter (V DD = 4.0 to 5.5 V, T a = –40 to +110 °C) Parameter Symbol Condition Resolution Absolute accuracy MIN. TYP. MAX. Unit 8 8 8 bit ±1.5 LSB 25 t CY µs 2.5 V ≤ V REF ≤ V DD Note 1 Note 2 t CONV Analog input voltage V ADIN 0 V REF V Reference input voltage V REF 2.5 V DD V A/D converter circuit current I ADC 1.0 2.0 mA V REF pin current I REF 0.1 0.3 mA Conversion time Notes 1. 2. When A/D converter operates Absolute accuracy excluding quantization error (±0.5LSB) Time since a conversion start instruction has been executed until conversion ends (ADCEND = 1) (50 µ s at 8 MHz). Remark t CY = 16/fx (f x: system clock oscillation frequency) POC Circuit (mask option Note 1) (V DD = 2.7 to 5.5 V, Ta = –40 to +110 °C) Parameter Symbol POC detection voltageNote 2 V POC Supply voltage fall speed t POCS Reset detection pulse width t SAMP POC circuit current I POC Condition MIN. TYP. MAX. Unit 3.6 4.0 4.45 V 0.08 V/ms 1 ms 3.0 10 µA Notes 1. The POC circuit can be used in an application circuit that operates at VDD = 4.5 to 5.5 V, 2. This is the voltage at which the POC circuit clears its internal reset operation. The internal reset f x = 400 kHz to 4 MHz. is cleared when VPOC < V DD . 86 µPD17145(A1), 17147(A1), 17149(A1) Oscillator Characteristics (V DD = 2.7 to 5.5 V, Ta = –40 to +110 °C) Resonator Note Ceramic resonator Note Symbol Condition Oscillation frequency MIN. TYP. MAX. Unit 0.39 2.04 MHz V DD = 3.6 to 5.5 V 0.39 4.08 MHz V DD = 4.5 to 5.5 V 0.39 8.16 MHz Do not use a resonator whose oscillation growth time exceeds 2 ms. Recommended Ceramic Resonator (T a = –40 to +110 °C) Manufacturer Operating Supply Voltage [V] C1 [pF] C2 [pF] Rd [kΩ] MIN. MAX. CSB400JA 220 220 5.6 2.7 5.5 CSA2.00MGA040 100 100 0 2.7 5.5 0 2.7 5.5 0 3.6 5.5 0 3.6 5.5 0 4.5 5.5 0 4.5 5.5 CST2.00MGA040 Murata Mfg. Co. Recommended Constants Part Number Unnecessary (C-contained type) CSA4.00MGA CST4.00MGWA 30 Unnecessary (C-contained type) CSA8.00MTZA CST8.00MTWA 30 30 30 Unnecessary (C-contained type) Remark For automotive electronics External Circuit Example XIN XOUT Rd C1 C2 87 µPD17145(A1), 17147(A1), 17149(A1) 23. CHARACTERISTIC CURVE (REFERENCE VALUE) (Ta = 25 ˚C) 4.0 XIN XOUT C2 C1 Supply current IDD [mA] 3.0 CSA 8.00MTZA (C1 = C2 = 30 pF) CSA 4.00MGA (C1 = C2 = 30 pF) CSA 2.00MGA040 (C1 = C2 = 100 pF) Operation mode (8 MHz) 2.0 Operation mode (4 MHz) Operation mode (2 MHz) HALT mode (8 MHz) 1.0 HALT mode (2 MHz) HALT mode (4 MHz) 2.7 0 2.0 3.6 3.0 5.5 4.0 5.0 Supply voltage VDD [V] I OL vs. V OL Characteristic Example 1 (P0A, P0B, P0C) (Ta = 25 ˚C) 20 15 VDD = 5.0 V VDD = 4.5 V Low-level output current I OL [mA] VDD = 3.5 V 10 5 0 1 2 3 Low-level output voltage V OL [V] Caution 88 The absolute maximum rating is 15 mA (peak value) per pin. µPD17145(A1), 17147(A1), 17149(A1) I OL vs. V OL Characteristics Example 2 (P0D, P0E) (Ta = 25 ˚C) 30 VDD = 5.0 V Low-level output current IOL [mA] VDD = 4.5 V VDD = 3.5 V 20 10 0 1 2 Low-level output voltage VOL [V] Caution The absolute maximum rating is 30 mA (peak value) per pin. IOH vs. (V DD - V OH ) Characteristic Example (Ta = 25 ˚C) – 20 VDD = 5.0 V VDD = 4.5 V High-level output current IOH [mA] – 15 VDD = 3.5 V – 10 –5 0 1 2 3 VDD – VOH [V] Caution The absolute maximum rating is –15 mA (peak value) per pin. 89 µPD17145(A1), 17147(A1), 17149(A1) 24. PACKAGE DRAWINGS 28 PIN PLASTIC SHRINK DIP (400 mil) 28 15 1 14 A I K F H G J L D N M C B M R NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 28.46 MAX. 1.121 MAX. B 2.67 MAX. 0.106 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.85 MIN. 0.033 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K L 10.16 (T.P.) 8.6 0.400 (T.P.) 0.339 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° S28C-70-400B-1 Caution The ES model differs from the mass-produced model in terms of outline dimensions and materials. Refer to the drawing of the ES model. 90 µPD17145(A1), 17147(A1), 17149(A1) 28 PIN PLASTIC SOP (375 mil) 28 15 3° +7° –3° detail of lead end 1 14 A H J E K F G I D L B C N M M P28GT-50-375B-1 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. Caution ITEM MILLIMETERS INCHES A 18.2 MAX. 0.717 MAX. B 0.845 MAX. 0.034 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.40+0.10 –0.05 0.016+0.004 –0.003 E 0.125 ± 0.075 0.005 ± 0.003 F 2.9 MAX. 0.115 MAX. G 2.50 ± 0.2 0.098+0.009 –0.008 H 10.3 ± 0.3 0.406+0.012 –0.013 I 7.2 ± 0.2 0.283+0.009 –0.008 J 1.6 ± 0.2 0.063 ± 0.008 K 0.15+0.10 –0.05 0.006+0.004 –0.002 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.12 0.005 N 0.10 0.004 The ES model differs from the mass-produced model in terms of outline dimension and materials. Refer to the drawing of the ES model. 91 µPD17145(A1), 17147(A1), 17149(A1) 28 PIN CERAMIC SHRINK DIP (400 mil) (For ES) 28 15 1 14 A K J I G H L F D C N B R M M NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 28.0 MAX. 1.103 MAX. B 5.1 MAX. 0.201 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.46±0.05 0.018±0.002 F 0.8 MIN. 0.031 MIN. G 3.0±1.0 0.118±0.04 H 1.0 MIN. 0.039 MIN. I 2.7 0.106 J 4.3 MAX. 0.170 MAX. K 10.16 (T.P.) 0.400 (T.P.) L 9.84 0.387 M 0.25±0.05 0.010 +0.002 –0.003 N R 0.25 0~15° 0.010 0~15° P28D-70-400B-1 92 µPD17145(A1), 17147(A1), 17149(A1) 28 PIN CERAMIC SOP (For ES) K C G T 2 D J 1 I A NOTE The lengths of leads ( 1 ) and the height of potting ( 2 ) are not to be specified because the lead cutting process and the potting process are not controlled. ITEM MILLIMETERS INCHES A 18.0±0.2 0.709 +0.008 –0.009 C 1.27 (T.P.) 0.05 (T.P.) D 0.4±0.05 +0.002 0.016 –0.003 G 1.52±0.15 I 8.4±0.15 0.06±0.006 0.331+0.006 –0.007 J 16.4 0.646 K 0.15±0.025 0.006±0.001 T 1.0 0.039 X28B-50B1 93 µPD17145(A1), 17147(A1), 17149(A1) 25. RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the other soldering conditions and methods, consult NEC. Table 25-1. Soldering Conditions of Surface Mount Type µ PD17145GT(A1)-×××: 28-pin plastic SOP (375 mil) µ PD17147GT(A1)-×××: 28-pin plastic SOP (375 mil) µ PD17149GT(A1)-×××: 28-pin plastic SOP (375 mil) Soldering Method Soldering Condition Symbol of Recommended Condition Package peak temperature: 235 °C, Time: 30 seconds max. (210 °C min.), Number of times: 2 max., Duration Note : 7 (after that, prebaking is necessary for 20 hours at 125 °C.) <Remarks> Infrared reflow IR35-207-2 (1) Start second reflow after the device temperature that has risen because of the first reflow has fallen to room temperature. (2) Do not clean flux with water after the first reflow. Package peak temperature: 215 °C, Time: 40 seconds max. (200 ˚C min.), Number of times: 2 max., Duration Note: 7 (after that, prebaking is necessary for 20 hours at 125 °C.) <Remarks> VPS (1) Start second reflow after the device temperature that has risen because of the first reflow has fallen to room temperature. VP15-207-2 (2) Do not clean flux with water after the first reflow. Pin partial heating Note Caution 94 Pin temperature: 300 °C max., Time: 3 seconds max. (per side of device) — Number of storage days after the dry pack was opened. Storage conditions: 25 °C, 65 %RH max. Do not use two or more soldering methods in combination (except pin partial heating). µPD17145(A1), 17147(A1), 17149(A1) Table 25-2. Soldering Conditions of Insertion Type µ PD17145CT(A1)-×××: 28-pin plastic shrink DIP (400 mil) µ PD17147CT(A1)-×××: 28-pin plastic shrink DIP (400 mil) µ PD17149CT(A1)-×××: 28-pin plastic shrink DIP (400 mil) Soldering Method Soldering Condition Wave soldering (pin only) Solder bath temperature: 260 ˚C max., Time: 10 seconds max. Pin partial heating Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side of pin) Caution When performing wave soldering, exercise care that only the pins are wetted with solder and that no part of the package must be wetted. 95 µPD17145(A1), 17147(A1), 17149(A1) APPENDIX A. FUNCTION COMPARISON BETWEEN µPD17145 SUBSERIES AND THE µPD17135A AND 17137A ROM µ PD17145 µ PD17147 µ PD17149 µ PD17135A µ PD17137A 2 KB 4 KB 8 KB 2 KB 4 KB 110 × 4 bits RAM 112 × 4 bits Address stack × 5 levels Stack Interrupt stack × 3 levels Instruction execution time (clock, operating voltage) 2 µ s (8 MHz, 4.5 to 5.5 V) 4 µ s (4 MHz, 3.6 to 5.5 V) 8 µ s (2 MHz, 2.7 to 5.5 V) CMOS I/O 2 µ s (8 MHz, 4.5 to 5.5 V) 4 µ s (4 MHz, 2.7 to 5.5 V) Input Sense input I/O 12 (P0A, P0B, P0C) 2 (P0F0, P0F 1) 1 (P1B 0) 1 (INT) 1 (INT) Can be pulled up by mask option N-ch open-drain I/O Internal pull-up resistor 8 (P0D, P0E voltage: V DD ) P0D pull-up: software P0E pull-up: software 8 (P0D, P1A voltage: 9 V) P0D pull-up: mask option P1A pull-up: mask option 100 kΩ TYP. (except P0D) 100 kΩ TYP. 10 kΩ TYP. (P0D) A/D converter 8 bits × 4 channels 8 bits × 4 channels (operating voltage) (V DD = 4.0 to 5.5 V) (V DD = 4.5 to 5.5 V) V REF (V REF = 2.5 V to V DD ) None (V REF = V ADC = V DD) 8-bit (TM0, TM1) 2 (timer output: TM1OUT) TM0 clock: system clock/512 system clock/64 system clock/16 INT TM1 clock: system clock/8192 system clock/128 system clock/16 TM0 count up 2 (timer output: TM0OUT) TM0 clock: system clock/256 system clock/64 system clock/16 INT TM1 clock: system clock/1024 system clock/512 system clock/256 TM0 count up Basic interval (BTM) 1 (also used as Count clock: system system system system 1 (also used as watchdog timer) Count clock: system clock/8192 system clock/4096 TM0 count up INT Timer Reference voltage pin Interrupt External watchdog timer) clock/16384 clock/4096 clock/512 clock/16 1 1 (with AC zero cross detection) Internal 4 (TM0, TM1, BTM, SIO) SIO 1 (clocked 3-wire) Output latch Standby function Independent of P0D 1 latch Shared with P0D 1 latch HALT, STOP HALT, STOP (can be released by RLS input pin) 96 µPD17145(A1), 17147(A1), 17149(A1) µ PD17145 Oscillation stabilization wait time POC function µ PD17147 µ PD17149 µ PD17135A µ PD17137A 128 × 256 counts 512 × 256 counts Mask option Internal Package 28-pin plastic SDIP (400 mil) 28-pin plastic SOP (375 mil) One-time PROM Caution µ PD17P149 µ PD17P137A The µ PD17145 subseries is not pin-compatible with the µ PD17135A and 17137A. The µ PD17145 subseries does not include a product equivalent to the µ PD17134A and 17136A (RC oscillation type). For the electrical specifications of each product, refer to the Data Sheet of the product. 97 µPD17145(A1), 17147(A1), 17149(A1) APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for developing programs for the µ PD17145(A1), 17147(A1), and 17149(A1): Hardware Name Outline IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators that can be used with any products in the 17K series. IE-17K and IE-17K-ET are connected to PC-9800 series or IBM PC/AT as the host machine with RS-232-C. EMU-17K is inserted into an expansion slot of the PC-9800 series. In-circuit emulator IE-17K, IE-17K-ET Note 1, EMU-17K Note 2 These in-circuit emulators operate as the emulator for a device when used in combination with the dedicated system evaluation board (SE board) of the device. When man-machine interface, SIMPLEHOST, is used a sophisticated debugging environment can be realized. EMU-17K also has a function that allows real-time monitoring of the contents of the data memory. SE board (SE-17145) SE-17145 is an SE board for the µ PD17145 subseries. It can be used alone to evaluate the system, or in combination with an in-circuit emulator for debugging. Emulation probe (EP-17K28CT) EP-17K28CT is an emulation probe for the 17K series 28-pin shrink DIP (400 mil). Emulation probe (EP-17K28GT) EP-17K28GT is an emulation probe for the 17K series 28-pin SOP (375 mil). It connects the SE board and target system when used with EV-9500GT-28Note 3. Conversion adapter EV-9500GT-28 is an adapter for the 28-pin SOP (375 mil). It is used to connect EP- (EV-9500GT-28 Note 3) 17K28GT and target system. Note 4 PROM programmer (AF-9703, AF-9704, AF-9705 or AF-9706) AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers supporting the µ PD17P149. By connecting programmer adapter AF-9808M to these programmers, the µ PD17P149 can be programmed. Programmer adapter Note 4 (AF-9808M) AF-9808M is an adapter used to program the µ PD17P149, in combination with AF9703, AF-9704, AF-9705, or AF-9706. Notes 1. Low-cost model: external power supply type 2. This is a product of IC Corporation. For details, consult IC Corporation (Tokyo (03) 3447-3793). 3. Two EV-97500GT-28s are supplied with the EP-17K28GT. Five EV-9500GT-28s are separately available as a set. 4. These are products of Ando Electric Corporation. For details, consult Ando Electric Corporation (Tokyo (03) 3733-1151). 98 µPD17145(A1), 17147(A1), 17149(A1) Software Outline Name AS17K is an assembler that can be used with any products in the 17K series. To develop the program of the µ PD17145(A1), 17147(A1), and 17149(A1), the AS17K and a device file (AS17145, AS17147, or AS17149) are used in combination. 17K series assembler (AS17K) AS17145, AS17147, and AS17149 are device files for the µ PD17145(A1), 17147(A1), 17149(A1), and µ PD17P149. They can be used in combination with the assembler for the 17K series (AS17K). Device file AS17145, AS17147, AS17149 SIMPLEHOST is software that serves as man-machine interface on Windows when a program is developed by using an in-circuit emulator and a personal computer. Support software (SIMPLEHOST) Note Remark Host Machine OS PC-9800 series MS-DOS IBM PC/AT PC DOS PC-9800 series IBM PC/AT PC-9800 series Supply Media Order Code 5"2HD µ S5A10AS17K 3.5"2HD µ S5A13AS17K 5"2HC µ S7B10AS17K 3.5"2HC µ S7B13AS17K 5"2HD µS5A10AS17145Note 3.5"2HD µS5A13AS17145Note 5"2HC µS7B10AS17145Note 3.5"2HC µS7B13AS17145Note MS-DOS PC DOS 5"2HD µ S5A10IE17K 3.5"2HD µ S5A13IE17K 5"2HC µ S7B10IE17K 3.5"2HC µ S7B13IE17K MS-DOS Windows IBM PC/AT PC DOS µ S××××AS17145 includes AS17145, AS17147, and AS17149. The version of the OS supported is as follows: OS Version MS-DOS Ver. 3.30 to Ver. 5.00A Note PC DOS Ver. 3.1 to Ver. 5.0Note Windows Ver. 3.0 to Ver. 3.1 Note Although MS-DOS Ver.5.00/5.00A and PC DOS Ver. 5.0 have a task swap function, this function cannot be used with this software. 99 µPD17145(A1), 17147(A1), 17149(A1) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 100 µPD17145(A1), 17147(A1), 17149(A1) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J97. 8 101 µPD17145(A1), 17147(A1), 17149(A1) SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5