NEC UPD30500RJ-180

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30500, 30500A, 30500B
VR5000TM, VR5000ATM, VR5000BTM
64-BIT MICROPROCESSOR
DESCRIPTION
The µPD30500 (VR5000), µPD30500A (VR5000A), and µPD30500BNote (VR5000B) are a high-performance, 64bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed by
MIPSTM Technologies Inc.
The instructions of the VR5000, VR5000A, and VR5000B are compatible with those of the VR3000TM Series and
VR4000TM Series and higher, and completely compatible with those of the VR10000TM.
Therefore, present
applications can be used as they are.
Note
Under development
Detailed functions are described in the following manual. Be sure to read the manual when
designing your system.
• VR5000, VR5000A, VR5000B User’s Manual (U11761E)
FEATURES
• Employs 64-bit MIPS-based RISC architecture
• High-speed processing
• 2-way super scalar 5-stage pipeline
• 5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (µPD30500)
6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (µPD30500A)
8 SPECint95, 8 SPECfp95, 423 MIPS (µPD30500B)
• High-speed translation buffer mechanism (TLB) (48 entries)
• Address space
Physical: 36 bits, Virtual: 40 bits
• Floating-point unit (FPU)
• Sum-of-products operation instruction supported
• Primary cache memory (instruction/data: 32 Kbytes each)
• Secondary cache controller
• Maximum operating frequency Internal: 200 MHz (µPD30500), 250 MHz (µPD30500A), 300 MHz (µPD30500B)
External: 100 MHz
• Selectable external/internal multiple rate from twice to eight times
• Instruction set compatible with VR3000 and VR4000 Series and higher (conforms to MIPS I, II, III, and IV)
• Supply voltage: 3.3 V ±5% (µPD30500)
Core: 2.5 V ±5%, I/O: 3.3 V ±5% (µPD30500A)
Core: 1.8 V ±0.1 V, I/O: 3.3 V ±5% (µPD30500B)
Unless otherwise specified, the VR5000 (µPD30500) is treated as the representative model throughout this
document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12031EJ4V0DS00 (4th edition)
Date Published May 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
1997,1999
©
© MIPS Technologies Inc. 1997
µPD30500, 30500A, 30500B
APPLICATIONS
• High-performance embedded systems
• Multimedia systems
• Entry-class computers
• Image processing systems
ORDERING INFORMATION
Part number
Package
Maximum operating frequency (MHz)
µPD30500RJ-150
223-pin ceramic PGA (48 × 48)
150
µPD30500RJ-180
223-pin ceramic PGA (48 × 48)
180
µPD30500RJ-200
223-pin ceramic PGA (48 × 48)
200
µPD30500S2-150
272-pin plastic BGA (C/D advanced type) (29 × 29)
150
µPD30500S2-180
272-pin plastic BGA (C/D advanced type) (29 × 29)
180
µPD30500S2-200
272-pin plastic BGA (C/D advanced type) (29 × 29)
200
µPD30500AS2-250
272-pin plastic BGA (C/D advanced type) (29 × 29)
250
µPD30500BS2-300Note
272-pin plastic BGA (C/D advanced type) (29 × 29)
300
Note
Under development
MAIN DIFFERENCES BETWEEN VR5000, VR5000A, AND VR5000B
Parameter
Maximum internal operating frequency
VR5000
150/180/200 MHz
VR5000A
250 MHz
2.5Note 2,
300 MHz
Internal multiplication ratio for clock
interface input
2, 3, 4, 5, 6, 7, 8
2,
Supply voltage
3.3 V ±5%
Core: 2.5 V ±5%
I/O: 3.3 V ±5%
• 223-pin ceramic PGA
• 272-pin plastic BGA (C/D advanced type)
Package
• 272-pin plastic BGA
(C/D advanced type)
Notes 1. Under development
2. Selectable only when SysClock = 100 MHz
2
VR5000BNote 1
Data Sheet U12031EJ4V0DS00
3, 4, 5, 6, 7, 8
Core: 1.8 V ±0.1 V
I/O: 3.3 V ±5%
µPD30500, 30500A, 30500B
PIN CONFIGURATION
• 223-pin ceramic PGA (48 × 48)
µPD30500RJ-150
µPD30500RJ-180
µPD30500RJ-200
Bottom View
Top View
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V U T R P N M L K J H G F E D C B A
A B C D E F G H J K L M N P R T U V
Index mark
Data Sheet U12031EJ4V0DS00
3
µPD30500, 30500A, 30500B
No.
4
Name
No.
Name
No.
Name
No.
Name
No.
Name
No.
Name
A2
VDD
C5
SysADC6
E18
VDD
K17
GNDP
R6
SysAD51
U9
SysAD63
A3
GND
C6
SysAD16
F1
VDD
K18
GND
R7
SysAD55
U10
SysAD13
A4
VDD
C7
SysAD50
F2
Reserved
L1
GND
R8
SysAD27
U11
SysAD11
A5
GND
C8
SysAD22
F3
ScValid
L2
SysCmd8
R9
SysAD31
U12
SysAD9
A6
GND
C9
SysAD24
F4
Int1
L3
SysCmd7
R10
SysAD43
U13
SysAD37
A7
VDD
C10
SysAD28
F15
ScDCE0
L4
SysCmd5
R11
SysAD39
U14
SysAD3
A8
GND
C11
SysAD62
F16
ScCWE0
L15
ScLine12
R12
SysAD35
U15
ScWord0
A9
VDD
C12
SysAD44
F17
ScTDE
L16
ScLine14
R13
SysAD1
U16
VDD
A10
GND
C13
SysAD10
F18
GND
L17
ScLine15
R14
ScWord1
U17
GND
A11
VDD
C14
SysAD38
G1
GND
L18
VDD
R15
ScLine0
U18
GND
A12
GND
C15
SysAD4
G2
Reserved
M1
VDD
R16
ScLine3
V1
GND
A13
VDD
C16
SysAD34
G3
Reserved
M2
SysCmd6
R17
ScLine6
V2
GND
A14
GND
C17
SysAD2
G4
Reserved
M3
SysCmd4
R18
GND
V3
VDD
A15
GND
C18
GND
G15
ScCLR
M4
SysCmd1
T1
GND
V4
GND
A16
VDD
D1
GND
G16
ScTCE
M15
ScLine8
T2
SysAD15
V5
GND
A17
GND
D2
Int3
G17
Modeln
M16
ScLine10
T3
SysAD47
V6
VDD
A18
GND
D3
Int5
G18
VDD
M17
ScLine13
T4
SysAD17
V7
GND
B1
GND
D4
Release
H1
VDD
M18
GND
T5
SysAD19
V8
VDD
B2
GND
D5
VDD
H2
Reserved
N1
GND
T6
SysAD23
V9
GND
B3
VDD
D6
SysADC2
H3
Reserved
N2
SysCmd3
T7
SysAD57
V10
VDD
B4
SysADC4
D7
SysAD48
H4
Reserved
N3
SysCmd2
T8
SysAD29
V11
GND
B5
SysADC0
D8
SysAD52
H15
VDDOk
N4
SysADC7
T9
VDD
V12
VDD
B6
SysAD18
D9
SysAD56
H16
ModeClock N15
ScLine5
T10
SysAD45
V13
GND
B7
SysAD20
D10
SysAD60
H17
SysClock
N16
ScLine7
T11
SysAD41
V14
VDD
B8
SysAD54
D11
SysAD14
H18
GND
N17
ScLine11
T12
SysAD7
V15
GND
B9
SysAD26
D12
SysAD42
J1
GND
N18
VDD
T13
SysAD5
V16
GND
B10
SysAD58
D13
SysAD8
J2
WrRdy
P1
VDD
T14
SysAD33
V17
VDD
B11
SysAD30
D14
SysAD36
J3
Validln
P2
SysCmd0
T15
Reset
V18
GND
B12
SysAD46
D15
ColdReset
J4
ExtRqst
P3
SysCmdP
T16
ScLine1
B13
SysAD12
D16
SysAD0
J15
Reserved
P4
SysADC1
T17
VDD
B14
SysAD40
D17
ScTOE
J16
Reserved
P15
ScLine2
T18
VDD
B15
SysAD6
D18
VDD
J17
Reserved
P16
ScLine4
U1
VDD
B16
GND
E1
GND
J18
VDD
P17
ScLine9
U2
VDD
B17
VDD
E2
Int0
K1
VDD
P18
GND
U3
GND
B18
VDD
E3
Int2
K2
ScMatch
R1
VDD
U4
SysAD21
C1
VDD
E4
Int4
K3
RdRdy
R2
SysADC5
U5
SysAD53
C2
VDD
E15
SysAD32
K4
ScDOE
R3
SysADC3
U6
SysAD25
C3
ValidOut
E16
ScDCE1
K15
Reserved
R4
BigEndian
U7
SysAD59
C4
NMI
E17
ScCWE1
K16
VDDP
R5
SysAD49
U8
SysAD61
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
• 272-pin plastic BGA (C/D advanced type) (29 × 29)
µPD30500S2-150
µPD30500S2-180
µPD30500S2-200
µPD30500AS2-250
µPD30500BS2-300Note
Bottom View
Top View
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AA Y W V U T R P N M L K J H G F E D C B A
Note
A B C D E F G H J K L M N P R T U V W Y AA
Under development
Data Sheet U12031EJ4V0DS00
5
µPD30500, 30500A, 30500B
(1) µPD30500
No.
6
Name
No.
Name
No.
Name
No.
Name
No.
SysAD8
Name
No.
Name
A1
GND
C5
ScDCE1
F1
L20
SysAD63
U18
VDD
Y1
VDD
A2
VDD
C6
ScDCE0
F2
SysAD38
L21
GND
U19
SysAD17
Y2
VDD
A3
GND
C7
ScCWE0
F3
SysAD6
M1
SysAD26
U20
SysAD49
Y3
VDD
A4
SysAD32
C8
ScTCE
F4
GND
M2
SysAD56
U21
GND
Y4
Release
A5
GND
C9
Modeln
F18
GND
M3
SysAD24
V1
VDD
Y5
Int3
A6
ScCWE1
C10
Reserved
F19
SysAD1
M4
VDD
V2
VDD
Y6
Int2
SysAD33
A7
GND
C11
GNDP
F20
M18
VDD
V3
VDD
Y7
ScValid
A8
VDDOk
C12
Reserved
F21
SysAD3
M19
SysAD29
V4
GND
Y8
Reserved
A9
GND
C13
ScLine13
G1
GND
M20
SysAD61
V5
NMI
Y9
Reserved
A10
SysClock
C14
ScLine11
G2
SysAD10
M21
SysAD31
V6
GND
Y10
Reserved
A11
GND
C15
ScLine8
G3
SysAD40
N1
GND
V7
VDD
Y11
ExtRqst
A12
ScLine15
C16
ScLine5
G4
VDD
N2
SysAD54
V8
VDD
Y12
RdRdy
VDD
A13
GND
C17
ScLine4
G18
N3
SysAD22
V9
GND
Y13
SysCmd8
A14
ScLine12
C18
ScLine0
G19
SysAD35
N4
GND
V10
VDD
Y14
SysCmd5
A15
GND
C19
Reset
G20
SysAD5
N18
GND
V11
VDD
Y15
SysCmd3
A16
ScLine7
C20
VDD
G21
GND
N19
SysAD27
V12
VDD
Y16
SysCmd0
A17
GND
C21
GND
H1
SysAD42
N20
SysAD59
V13
GND
Y17
SysCmdP
A18
ScLine2
D1
VDD
H2
SysAD44
N21
GND
V14
VDD
Y18
SysADC1
SysAD12
A19
GND
D2
VDD
H3
P1
SysAD50
V15
VDD
Y19
SysAD15
A20
VDD
D3
VDD
H4
VDD
P2
SysAD52
V16
GND
Y20
VDD
A21
GND
D4
GND
H18
VDD
P3
SysAD20
V17
VDD
Y21
VDD
B1
VDD
D5
VDD
H19
SysAD7
P4
VDD
V18
GND
AA1
GND
B2
VDD
D6
GND
H20
SysAD39
P18
VDD
V19
VDD
AA2
VDD
B3
VDD
D7
VDD
H21
SysAD37
P19
SysAD25
V20
VDD
AA3
GND
GND
B4
SysAD2
D8
VDD
J1
P20
SysAD57
V21
VDD
AA4
ValidOut
B5
SysAD0
D9
GND
J2
SysAD46
P21
SysAD55
W1
GND
AA5
GND
B6
ScTOE
D10
VDD
J3
SysAD14
R1
GND
W2
VDD
AA6
Int0
B7
ScCLR
D11
VDDP
J4
GND
R2
SysAD18
W3
VDD
AA7
GND
B8
ScTDE
D12
VDD
J18
GND
R3
SysAD48
W4
VDD
AA8
Reserved
B9
ModeClock D13
GND
J19
SysAD9
R4
VDD
W5
Int5
AA9
GND
SysAD41
B10
Reserved
D14
VDD
J20
R18
VDD
W6
Int4
AA10
WrRdy
B11
Reserved
D15
VDD
J21
GND
R19
SysAD53
W7
Int1
AA11
GND
B12
NC
D16
GND
K1
SysAD60
R20
SysAD23
W8
Reserved
AA12
ScMatch
B13
ScLine14
D17
VDD
K2
SysAD30
R21
GND
W9
Reserved
AA13
GND
B14
ScLine10
D18
GND
K3
SysAD62
T1
SysAD16
W10
Reserved
AA14
SysCmd6
B15
ScLine9
D19
VDD
K4
VDD
T2
SysADC0
W11
Validln
AA15
GND
VDD
B16
ScLine6
D20
VDD
K18
T3
SysADC2
W12
ScDOE
AA16
SysCmd2
B17
ScLine3
D21
VDD
K19
SysAD11
T4
GND
W13
SysCmd7
AA17
GND
B18
ScLine1
E1
GND
K20
SysAD43
T18
GND
W14
SysCmd4
AA18
SysADC3
B19
VDD
E2
SysAD36
K21
SysAD13
T19
SysAD19
W15
SysCmd1
AA19
GND
B20
VDD
E3
SysAD4
L1
GND
T20
SysAD51
W16
SysADC7
AA20
VDD
B21
VDD
E4
VDD
L2
SysAD58
T21
SysAD21
W17
SysADC5
AA21
GND
SysAD28
C1
GND
E18
VDD
L3
U1
GND
W18
SysAD47
C2
VDD
E19
ScWord1
L4
VDD
U2
SysADC4
W19
BigEndian
C3
ColdReset
E20
ScWord0
L18
VDD
U3
SysADC6
W20
VDD
C4
SysAD34
E21
GND
L19
SysAD45
U4
VDD
W21
GND
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
(2) µPD30500A, 30500B
No.
Name
No.
Name
No.
Name
No.
Name
No.
Name
No.
Name
A1
GND
C5
ScDCE1
F1
SysAD8
L20
SysAD63
U18
VDD
Y1
VDDIO
A2
VDDIO
C6
ScDCE0
F2
SysAD38
L21
GND
U19
SysAD17
Y2
VDDIO
A3
GND
C7
ScCWE0
F3
SysAD6
M1
SysAD26
U20
SysAD49
Y3
VDDIO
A4
SysAD32
C8
ScTCE
F4
GND
M2
SysAD56
U21
GND
Y4
Release
A5
GND
C9
Modeln
F18
GND
M3
SysAD24
V1
VDD
Y5
Int3
A6
ScCWE1
C10
NC
F19
SysAD1
M4
VDDIO
V2
VDD
Y6
Int2
A7
GND
C11
GNDP
F20
SysAD33
M18
VDDIO
V3
VDD
Y7
ScValid
A8
VDDOk
C12
GND
F21
SysAD3
M19
SysAD29
V4
GND
Y8
GND
A9
GND
C13
ScLine13
G1
GND
M20
SysAD61
V5
NMI
Y9
GND
A10
SysClock
C14
ScLine11
G2
SysAD10
M21
SysAD31
V6
GND
Y10
GND
A11
GND
C15
ScLine8
G3
SysAD40
N1
GND
V7
VDD
Y11
ExtRqst
A12
ScLine15
C16
ScLine5
G4
VDDIO
N2
SysAD54
V8
VDDIO
Y12
RdRdy
A13
GND
C17
ScLine4
G18
VDDIO
N3
SysAD22
V9
GND
Y13
SysCmd8
A14
ScLine12
C18
ScLine0
G19
SysAD35
N4
GND
V10
VDD
Y14
SysCmd5
A15
GND
C19
Reset
G20
SysAD5
N18
GND
V11
VDDIO
Y15
SysCmd3
A16
ScLine7
C20
VDDIO
G21
GND
N19
SysAD27
V12
VDD
Y16
SysCmd0
A17
GND
C21
GND
H1
SysAD42
N20
SysAD59
V13
GND
Y17
SysCmdP
A18
ScLine2
D1
VDD
H2
SysAD44
N21
GND
V14
VDDIO
Y18
SysADC1
A19
GND
D2
VDD
H3
SysAD12
P1
SysAD50
V15
VDD
Y19
SysAD15
A20
VDDIO
D3
VDD
H4
VDD
P2
SysAD52
V16
GND
Y20
VDDIO
A21
GND
D4
GND
H18
VDD
P3
SysAD20
V17
VDDIO
Y21
VDDIO
B1
VDDIO
D5
VDD
H19
SysAD7
P4
VDD
V18
GND
AA1
GND
B2
VDDIO
D6
GND
H20
SysAD39
P18
VDD
V19
VDD
AA2
VDDIO
B3
VDDIO
D7
VDDIO
H21
SysAD37
P19
SysAD25
V20
VDD
AA3
GND
B4
SysAD2
D8
VDD
J1
GND
P20
SysAD57
V21
VDD
AA4
ValidOut
B5
SysAD0
D9
GND
J2
SysAD46
P21
SysAD55
W1
GND
AA5
GND
B6
ScTOE
D10
VDDIO
J3
SysAD14
R1
GND
W2
VDDIO
AA6
Int0
B7
ScCLR
D11
VDDP
J4
GND
R2
SysAD18
W3
VDDIO
AA7
GND
B8
ScTDE
D12
VDD
J18
GND
R3
SysAD48
W4
VDDIO
AA8
GND
B9
ModeClock D13
GND
J19
SysAD9
R4
VDDIO
W5
Int5
AA9
GND
B10
GND
D14
VDDIO
J20
SysAD41
R18
VDDIO
W6
Int4
AA10
WrRdy
B11
GND
D15
VDD
J21
GND
R19
SysAD53
W7
Int1
AA11
GND
B12
GND
D16
GND
K1
SysAD60
R20
SysAD23
W8
GND
AA12
ScMatch
B13
ScLine14
D17
VDDIO
K2
SysAD30
R21
GND
W9
GND
AA13
GND
B14
ScLine10
D18
GND
K3
SysAD62
T1
SysAD16
W10
VDD
AA14
SysCmd6
B15
ScLine9
D19
VDD
K4
VDDIO
T2
SysADC0
W11
Validln
AA15
GND
B16
ScLine6
D20
VDD
K18
VDDIO
T3
SysADC2
W12
ScDOE
AA16
SysCmd2
B17
ScLine3
D21
VDD
K19
SysAD11
T4
GND
W13
SysCmd7
AA17
GND
B18
ScLine1
E1
GND
K20
SysAD43
T18
GND
W14
SysCmd4
AA18
SysADC3
B19
VDDIO
E2
SysAD36
K21
SysAD13
T19
SysAD19
W15
SysCmd1
AA19
GND
B20
VDDIO
E3
SysAD4
L1
GND
T20
SysAD51
W16
SysADC7
AA20
VDDIO
B21
VDDIO
E4
VDD
L2
SysAD58
T21
SysAD21
W17
SysADC5
AA21
GND
C1
GND
E18
VDD
L3
SysAD28
U1
GND
W18
SysAD47
C2
VDDIO
E19
ScWord1
L4
VDD
U2
SysADC4
W19
BigEndian
C3
ColdReset
E20
ScWord0
L18
VDD
U3
SysADC6
W20
VDDIO
C4
SysAD34
E21
GND
L19
SysAD45
U4
VDD
W21
GND
Data Sheet U12031EJ4V0DS00
7
µPD30500, 30500A, 30500B
PIN NAMES
BigEndian:
8
Endian Mode Select
ColdReset:
Cold Reset
ExtRqst:
External Request
GND:
Ground
GNDP:
Quiet GND for PLL
Int (0:5):
Interrupt Request
ModeClock:
Boot Mode Clock
Modeln:
Boot Mode Data In
NC:
No Connection
NMI:
Non-maskable Interrupt Request
RdRdy:
Read Ready
Release:
Release Interface
Reset:
Reset
ScCLR:
Secondary Cache Block Clear
ScCWE (0:1):
Secondary Cache Write Enable
ScDCE (0:1):
Data RAM Chip Enable
ScDOE:
Data RAM Output Enable
ScLine (0:15):
Secondary Cache Line Index
ScMatch:
Secondary Cache Tag Match
ScTCE:
Secondary Cache Tag RAM Chip Enable
ScTDE:
Secondary Cache Tag RAM Data Enable
ScTOE:
Secondary Cache Tag RAM Output Enable
ScValid:
Secondary Cache Valid
ScWord (0:1):
Secondary Cache Word Index
SysAD (0:63):
System Address/Data Bus
SysADC (0:7):
System Address/Data Check Bus
SysClock:
System Clock
SysCmd (0:8):
System Command/Data Identifier
SysCmdP:
System Command/Data Identifier Bus Parity
Validln:
Valid Input
ValidOut:
Valid Output
VDD:
Power Supply (µPD30500)
VDD:
Power Supply for Processor Core (µPD30500A, 30500B)
VDDIO:
Power Supply for Processor I/O (µPD30500A, 30500B only)
VDDOk:
VDD is OK
VDDP:
Quiet VDD for PLL
WrRdy:
Write Ready
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
INTERNAL BLOCK DIAGRAM
Data, address
Control
System interface
SysClock
Clock
generator
Instruction cache
Data cache
CP0
TLB
Execution unit
Instruction address
Floating-point unit
Pipeline control
Data Sheet U12031EJ4V0DS00
9
µPD30500, 30500A, 30500B
CONTENTS
1.
PIN FUNCTIONS ................................................................................................................................ 11
2.
ELECTRICAL SPECIFICATIONS ...................................................................................................... 13
2.1
µPD30500 .................................................................................................................................................... 13
2.2
µPD30500A .................................................................................................................................................. 16
2.3
µPD30500B (Preliminary) .......................................................................................................................... 19
2.4
Test Condition ............................................................................................................................................ 22
2.5
Timing Chart ............................................................................................................................................... 22
3.
PACKAGE DRAWING ........................................................................................................................ 27
4.
RECOMMENDED SOLDERING CONDITIONS ................................................................................. 29
APPENDIX DIFFERENCES BETWEEN THE VR5000 AND VR4310TM .................................................... 30
10
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
1. PIN FUNCTIONS
Pin Name
I/O
SysAD (0:63)
I/O
System address/data bus.
64-bit bus for communication between processor, secondary cache and external agent.
SysADC (0:7)
I/O
System address/data check bus.
8-bit bus including check bits for the SysAD bus.
SysCmd (0:8)
I/O
System command/data ID bus.
9-bit bus for communication of commands and data identifiers between processor
and external agent.
SysCmdP
I/O
System command/data ID bus parity.
1-bit even number parity bit for the SysCmd bus.
ValidIn
Input
ValidOut
Output
ExtRqst
Input
Function
Valid in.
Signal indicating that external agent has transmitted valid address or data onto
SysAD bus and valid command or data identifier onto SysCmd bus.
Valid out.
Signal indicating that processor has transmitted valid address or data onto SysAD
bus and valid command or data identifier onto SysCmd bus.
External request.
Signal used by external agent to request for its use by system interface.
Release
Output
Interface release.
Signal indicating that the processor has released the system interface to the slave state.
WrRdy
Output
Write ready.
Signal indicating that the external agent can accept a processor write request.
RdRdy
Input
ScCLR
Output
Secondary cache block clear.
Clears all the valid bits of the tag RAM.
ScCWE (0:1)
Output
Secondary cache write enable.
Read ready.
Signal indicating that external agent can accept a processor read request.
Write enable signal for the secondary cache RAM.
ScDCE (0:1)
ScDOE
ScLine (0:15)
ScMatch
Output
Input
Output
Input
Data RAM chip select.
Chip select signal for secondary cache RAM.
Data RAM output enable.
Data output enable signal from the external agent.
Secondary cache line index.
Cache line index output of the secondary cache.
Secondary cache tag match.
Tag match signal from secondary cache tag RAM.
ScTCE
Output
Secondary cache tag RAM chip select.
Chip select signal of the secondary cache tag RAM.
ScTDE
Output
Secondary cache tag RAM data enable.
Data enable signal from the secondary cache tag RAM.
ScTOE
Output
Secondary cache tag RAM output enable.
Output enable signal from the secondary cache tag RAM.
ScWord (0:1)
I/O
Secondary cache word index.
Signal indicating that the double word of the secondary cache index is correct.
ScValid
I/O
Secondary cache valid.
Signal indicating that the data of the secondary cache is valid.
Data Sheet U12031EJ4V0DS00
11
µPD30500, 30500A, 30500B
Pin Name
I/O
Function
Int (0:5)
Input
Interrupt.
General-purpose processor interrupt requests whose input statuses can be confirmed by
bits 15 through 10 of cause register.
NMI
Input
Non-maskable interrupt.
Interrupt request that cannot be masked.
ColdReset
Input
Cold reset.
Signal initializing the internal status of the processor. Inactivate this signal in synchronization with SysClock.
Reset
Input
Reset.
Signal generating a reset exception, without initializing the internal status of the processor.
Inactivate this signal in synchronization with SysClock.
SysClock
Input
System clock.
Clock input signal to processor.
BigEndian
Input
Endian mode setting.
This signal sets the endian mode of the system interface.
When setting the endian mode with this signal, specify little endian with the data from the
ModeIn pin that is input at reset.
To set the endian mode with the data from the ModeIn pin, fix this signal to 0.
ModeClock
Output
BigEndian
Bit 8 of boot mode
Mode
1
1
0
0
1
0
1
0
—
Big endian
Big endian
Little endian
Boot mode clock.
Successive boot mode data clock output resulting from dividing SysClock by 256.
Modeln
Input
Boot mode data input.
Input of initialization bit stream.
VDDOk
Input
VDD and VDDIONote1 are valid.
Signal indicating that the voltage supplied to the VR5000 is reached to the rated levelNote2
for 100 ms or more, and that that status is stabilized. When VDDOk is asserted active, the
VR5000 starts an initialization sequence.
VDDP
–
PLL VDD.
Power supply for internal PLL.
GNDP
–
PLL GND.
Ground for internal PLL.
VDD
–
• VR5000
Positive power supply pin (3.3 V)
• VR5000A
Power supply pin for core (2.5 V)
• VR5000B
Power supply pin for core (1.8 V)
VDDIONote1
–
Power supply pin for I/O (3.3 V)
GND
–
Ground pin.
Notes 1. VDDIO is only for VR5000A and VR5000B.
2. VR5000: VDD = 3.135 V
VR5000A: VDD = 2.375 V, VDDIO = 3.135 V
VR5000B: VDD = 1.7 V, VDDIO = 3.135 V
12
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
2. ELECTRICAL SPECIFICATIONS
µPD30500
2.1
Absolute Maximum Ratings
Parameter
Supply voltage
Input
Symbol
Condition
Rating
Unit
–0.5 to +4.0
V
–0.5 to VDD + 0.3
V
–1.5 to VDD + 0.3
V
PGA package
0 to +70
°C
BGA package
0 to +85
°C
PGA package
–65 to +150
°C
BGA package
–40 to +125
°C
VDD
voltageNote
VI
Pulse of less than 10 ns
Operating case temperature
Storage temperature
Note
TC
Tstg
The upper limit of the input voltage (VDD + 0.3) is +4.0 V.
Cautions 1.
2.
Do not short circuit two or more outputs at the same time.
The quality of the product may be degraded if the absolute maximum rating of even one of
the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore,
specify the values which if exceeded may physically damage the product. Use the product
never exceeding these ratings.
The specifications and conditions shown in the following DC Characteristics and AC
Characteristics are the range within which the product can normally operate and the quality
can be guaranteed.
DC Characteristics (TC = 0 to +70°C (PGA Package), TC = 0 to +85°C (BGA Package), VDD = 3.3 V ±5%)
Parameter
Symbol
Condition
High-level output voltage
VOH
VDD = MIN., IOH = –4 mA
Low-level output voltage
VOL
VDD = MIN., IOL = 4 mA
MAX.
2.4
Unit
V
0.4
V
2.0
VDD + 0.3
V
–0.5
+0.8
V
–1.5
+0.8
V
VIHC
0.8 × VDD
VDD + 0.3
V
VILC
–0.5
0.2 × VDD
V
–1.5
0.2 × VDD
V
High-level input
voltageNote 1
VIH
Low-level input
voltageNote 1
VIL
High-level input
voltageNote 2
Low-level input voltageNote 2
Pulse of less than 10 ns
Pulse of less than 10 ns
Supply current
MIN.
IDD
Normal
150 MHz
2.16
A
operation
180 MHz
2.54
A
200 MHz
2.8
A
0.25
A
Standby
Input leakage current
ILI
–5
+5
µA
Input/output leakage current
ILIO
–5
+5
µA
Notes 1. Not applied to the SysClock pin.
2. Applied to the SysClock pin only.
Remark The operating supply current is almost proportional to the operating clock frequency.
Data Sheet U12031EJ4V0DS00
13
µPD30500, 30500A, 30500B
Capacitance
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Input capacitance
CIn
5
pF
Output capacitance
Cout
7
pF
AC Characteristics (TC = 0 to +70°C (PGA Package), TC = 0 to +85°C (BGA Package), VDD = 3.3 V ±5%)
Clock parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
System clock high-level width
tCH
3.0
ns
System clock low-level width
tCL
3.0
ns
System clock
frequencyNotes 1, 2
System clock cycle
System clock jitter
tCP
tji
150 MHz
20
75
MHz
180 MHz
20
90
MHz
200 MHz
20
100
MHz
150 MHz
13.3
50
ns
180 MHz
11.1
50
ns
200 MHz
10
50
ns
System clock frequency > 66 MHz
±125
ps
System clock frequency ≤ 66 MHz
±250
ps
System clock rise time
tCR
2.0
ns
System clock fall time
tCF
2.0
ns
Mode clock cycle
tMOC
256 × tCP
Notes 1. The operation of the VR5000 is guaranteed only when the PLL is operating
2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.
14
Data Sheet U12031EJ4V0DS00
ns
µPD30500, 30500A, 30500B
System Interface Parameter
Parameter
Data output hold time
Symbol
tDM
Condition
MIN.
MAX.
Unit
Modebit (14 : 13) = 10
1.0
ns
Modebit (14 : 13) = 11
1.1
ns
Modebit (14 : 13) = 00
1.3
ns
Modebit (14 : 13) = 01
1.3
ns
Data output delay time
tDO
5.0
ns
Data input setup time
tDS
1.6
ns
Data input hold time
tDH
0.5
ns
Boot Mode Interface Parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
More data setup time
tMDS
tCP × 0.35
ns
Mode data hold time
tMDH
tCP × 0.35
ns
Load Coefficient
Parameter
Load coefficient
Symbol
Condition
CLD
Data Sheet U12031EJ4V0DS00
MIN.
MAX.
Unit
1.5
ns/25 pF
15
µPD30500, 30500A, 30500B
2.2 µPD30500A
Absolute Maximum Ratings
Parameter
Supply voltage
Input
voltageNote
Symbol
Condition
Rating
Unit
VDDIO
–0.5 to +4.0
V
VDD
–0.3 to +3.3
V
–0.5 to VDDIO + 0.3
V
–1.5 to VDDIO + 0.3
V
VI
Pulse of less than 10 ns
Operating case temperature
TC
0 to +85
°C
Storage temperature
Tstg
–40 to +125
°C
Note
The upper limit of the input voltage (VDDIO + 0.3) is +4.0 V.
Cautions 1.
2.
Do not short circuit two or more outputs at the same time.
The quality of the product may be degraded if the absolute maximum rating of even one of
the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore,
specify the values which if exceeded may physically damage the product. Use the product
never exceeding these ratings.
The specifications and conditions shown in the following DC Characteristics and AC
Characteristics are the range within which the product can normally operate and the quality
can be guaranteed.
DC Characteristics (TC = 0 to +85°C, VDDIO = 3.3 V ±5%, VDD = 2.5 V ±5%)
Parameter
Symbol
Condition
High-level output voltage
VOH
VDDIO = MIN., IOH = –4 mA
Low-level output voltage
VOL
VDDIO = MIN., IOL = 4 mA
High-level input
voltageNote 1
VIH
Low-level input
voltageNote 1
VIL
High-level input
voltageNote 2
VIHC
Low-level input voltageNote 2
VILC
Pulse of less than 10 ns
2.4
Unit
V
0.4
V
2.0
VDDIO + 0.3
V
–0.5
+0.8
V
–1.5
+0.8
V
V
–0.5
0.2 × VDDIO
V
–1.5
0.2 × VDDIO
V
1.8
A
System clock frequency = 50 MHZ
0.7
A
System clock frequency = 67 MHZ
0.85
A
System clock frequency = 83 MHZ
0.95
A
System clock frequency = 100 MHZ
1.15
A
IDD
IDDIO
MAX.
0.8 × VDDIO VDDIO + 0.3
Pulse of less than 10 ns
Supply current
MIN.
Input leakage current
ILI
–5
+5
µA
Input/output leakage current
ILIO
–5
+5
µA
Notes 1. Not applied to the SysClock pin.
2. Applied to the SysClock pin only.
16
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
Power Application Sequence
Two kinds of power sources are provided with the VR5000A. The sequence of the power application order is not
fixed. However, make sure that either of the power supplies does not remain turned on for 1 second or more while
the other remains off.
Parameter
Power application delay
Symbol
Condition
tDP
MIN.
MAX.
Unit
0
1
sec
MIN.
MAX.
Unit
Capacitance
Parameter
Symbol
Condition
Input capacitance
CIn
5
pF
Output capacitance
Cout
7
pF
MAX.
Unit
AC Characteristics (TC = 0 to +85°C, VDDIO = 3.3 V ±5%, VDD = 2.5 V ±5%)
Clock parameter
Parameter
Symbol
Condition
MIN.
System clock high-level width
tCH
3.0
ns
System clock low-level width
tCL
3.0
ns
System clock
frequencyNotes 1, 2
System clock cycle
tCP
System clock jitter
tji
20
100
MHz
10
50
ns
System clock frequency > 66 MHz
±125
ps
System clock frequency ≤ 66 MHz
±250
ps
System clock rise time
tCR
2.0
ns
System clock fall time
tCF
2.0
ns
Mode clock cycle
tMOC
256 × tCP
ns
Notes 1. The operation of the VR5000A is guaranteed only when the PLL is operating
2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.
Data Sheet U12031EJ4V0DS00
17
µPD30500, 30500A, 30500B
System Interface Parameter
Parameter
Data output hold time
Data output delay time
Symbol
tDM
tDO
Condition
MIN.
MAX.
Unit
Modebit (14 : 13) = 10
1.3
ns
Modebit (14 : 13) = 11
1.4
ns
Modebit (14 : 13) = 00
1.5
ns
Modebit (14 : 13) = 01
1.5
ns
PClock/SysClock division ratio =
5.0
ns
7.0
ns
2, 3, 4, 5, 6, 7, 8,
PClock/SysClock division ratio = 2.5
Data input setup time
tDS
1.6
ns
Data input hold time
tDH
0.5
ns
Boot Mode Interface Parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Mode data setup time
tMDS
tCP × 0.35
ns
Mode data hold time
tMDH
tCP × 0.35
ns
Load Coefficient
Parameter
Load coefficient
18
Symbol
Condition
CLD
Data Sheet U12031EJ4V0DS00
MIN.
MAX.
Unit
1.5
ns/25 pF
µPD30500, 30500A, 30500B
2.3 µPD30500B (Preliminary)
Absolute Maximum Ratings
Parameter
Supply voltage
Input
voltageNote
Symbol
Condition
Rating
Unit
VDDIO
–0.5 to +4.0
V
VDD
–0.3 to +2.5
V
–0.5 to VDDIO + 0.3
V
–1.5 to VDDIO + 0.3
V
VI
Pulse of less than 10 ns
Operating case temperature
TC
0 to +85
°C
Storage temperature
Tstg
–40 to +125
°C
Note
The upper limit of the input voltage (VDDIO + 0.3) is +4.0 V.
Cautions 1.
2.
Do not short circuit two or more outputs at the same time.
The quality of the product may be degraded if the absolute maximum rating of even one of
the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore,
specify the values which if exceeded may physically damage the product. Use the product
never exceeding these ratings.
The specifications and conditions shown in the following DC Characteristics and AC
Characteristics are the range within which the product can normally operate and the quality
can be guaranteed.
DC Characteristics (TC = 0 to +85°C, VDDIO = 3.3 V ±5%, VDD = 1.8 V ±0.1 V)
Parameter
Symbol
Condition
High-level output voltage
VOH
VDDIO = MIN., IOH = –4 mA
Low-level output voltage
VOL
VDDIO = MIN., IOL = 4 mA
High-level input
voltageNote 1
VIH
Low-level input
voltageNote 1
VIL
High-level input
voltageNote 2
VIHC
Low-level input voltageNote 2
VILC
Pulse of less than 10 ns
Pulse of less than 10 ns
MIN.
MAX.
2.4
Unit
V
0.4
V
2.0
VDDIO + 0.3
V
–0.5
+0.8
V
–1.5
+0.8
V
0.8 × VDDIO VDDIO + 0.3
V
–0.5
0.2 × VDDIO
V
–1.5
0.2 × VDDIO
V
Input leakage current
ILI
–5
+5
µA
Input/output leakage current
ILIO
–5
+5
µA
Notes 1. Not applied to the SysClock pin.
2. Applied to the SysClock pin only.
Power Application Sequence
Two kinds of power sources are provided with the VR5000B. The sequence of the power application order is not
fixed. However, make sure that either of the power supplies does not remain turned on for 1 second or more while
the other remains off.
Parameter
Power application delay
Symbol
Condition
tDP
Data Sheet U12031EJ4V0DS00
MIN.
MAX.
Unit
0
1
se
19
µPD30500, 30500A, 30500B
Capacitance
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Input capacitance
CIn
5
pF
Output capacitance
Cout
7
pF
MAX.
Unit
AC Characteristics (TC = 0 to +85°C, VDDIO = 3.3 V ±5%, VDD = 1.8 V ±0.1 V)
Clock parameter
Parameter
Symbol
Condition
MIN.
System clock high-level width
tCH
3.0
ns
System clock low-level width
tCL
3.0
ns
System clock
frequencyNotes 1, 2
System clock cycle
tCP
System clock jitter
tji
20
100
MHz
10
50
ns
System clock frequency > 66 MHz
±125
ps
System clock frequency ≤ 66 MHz
±250
ps
System clock rise time
tCR
2.0
ns
System clock fall time
tCF
2.0
ns
Mode clock cycle
tMOC
256 × tCP
Notes 1. The operation of the VR5000B is guaranteed only when the PLL is operating
2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.
20
Data Sheet U12031EJ4V0DS00
ns
µPD30500, 30500A, 30500B
System Interface Parameter
Parameter
Data output hold time
Symbol
tDM
Condition
MIN.
MAX.
Unit
Modebit (14 : 13) = 10
1.3
ns
Modebit (14 : 13) = 11
1.4
ns
Modebit (14 : 13) = 00
1.5
ns
Modebit (14 : 13) = 01
1.5
ns
Data output delay time
tDO
5.0
ns
Data input setup time
tDS
1.6
ns
Data input hold time
tDH
0.5
ns
Boot Mode Interface Parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Mode data setup time
tMDS
tCP × 0.35
ns
Mode data hold time
tMDH
tCP × 0.35
ns
Load Coefficient
Parameter
Load coefficient
Symbol
Condition
CLD
Data Sheet U12031EJ4V0DS00
MIN.
MAX.
Unit
1.5
ns/25 pF
21
µPD30500, 30500A, 30500B
2.4 Test Condition
Test point
SysClock
50%
tDO
tDM
All output pins
50%
Load Conditions
All output pins
DUT
CL = 50 pF
2.5 Timing Chart
Clock timing
tCP
tCH
80%
SysClock
50%
20%
tCL
22
tCR
Data Sheet U12031EJ4V0DS00
tCF
µPD30500, 30500A, 30500B
Mode clock timing
tMOC
ModeClock
50%
Clock jitter
tji
tji
SysClock
50%
System interface edge timing
SysClock
tDO
tDH
tDM
SysAD (0 : 63), SysADC (0 : 7),
SysCmd (0 : 8), SysCmdP,
ScLine (0 : 15), ScWord (0 : 1), ScTCE, ScValid
tDS
Output
Output
Input
tDO
tDM
ValidOut, Release, ScCLR,
ScCWE (0 : 1), ScDCE (0 : 1),
ScTDE, ScTOE
Output
Output
tDS
tDH
ValidIn, ExtRqst, RdRdy,
WrRdy, ScDOE, ScMatch,
Int (0 : 5), NMI
Input
Data Sheet U12031EJ4V0DS00
23
µPD30500, 30500A, 30500B
Boot mode interface edge timing
ModeClock
tMDS
tMDH
Input
ModeIn
Clocking relations
Cycle
1
2
3
4
SysClock
(Input)
PClock
(Output)
tDO
tDM
SysAD Driven
(Output)
Data
Data
SysAD Received
(Input)
Data
Data
Data
tDS
tDH
Power application sequence (VR5000A, VR5000B only)
tDP
VDD
VDDIO
24
tDP
0.5VDD
0.5VDDIO
Data Sheet U12031EJ4V0DS00
Data
Data
Data
µPD30500, 30500A, 30500B
Reset Timing
Power-on reset timing
VDD
Note 1
VDDI/ONote 2
3.135 V
SysClock
≥ 100 ms
VDDOk
≥ 64 K SysClock
256 SysClock
ModeClock
Undefined
tMDS
tMDH
ModeIn
bit0
bit1
bit255
tDS
ColdReset
≥ 64 SysClock
tDS
Reset
Notes 1. 3.135 V (VR5000), 2.375 V (VR5000A), 1.7 V (VR5000B)
2. VR5000A, VR5000B only
Cold reset timing
VDD
H
VDDIONote
H
SysClock
≥ 64 K SysClock
≥ 64 SysClock
VDDOk
256 SysClock
ModeClock
Undefined
tMDS
tMDH
bit0
ModeIn
bit1
bit255
tDS
≥ 64 SysClock
ColdReset
tDS
Reset
Note
VR5000A, VR5000B only
Data Sheet U12031EJ4V0DS00
25
µPD30500, 30500A, 30500B
Warm reset timing
VDD
H
VDDIONote
H
SysClock
≥ 64 SysClock
VDDOk
H
ColdReset
H
tDS
tDS
Reset
Note
26
VR5000A, VR5000B only
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
3. PACKAGE DRAWING
223 PIN CERAMIC PGA
< Bottom View >
A
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D
T S RQP NM L K J HG F E DC B A
Index Mark
J
I
F
K
L
φM
E
M
H
G
NOTE
Each lead centerline is located within φ 0.254(φ 0.010 inch) of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
47.24±0.25
INCHES
1.860±0.010
D
E
F
47.24±0.25
2.03
2.54(T.P.)
1.860±0.010
0.080
0.100(T.P.)
G
3.30±0.2
0.130±0.008
H
0.50 MIN.
0.019 MIN.
I
2.82
0.111
0.157 MAX.
J
3.98 MAX.
K
φ 1.27±0.2
0.050±0.008
L
φ 0.46±0.05
φ 0.018±0.002
M
0.254
0.010
X223RJ-100A-1
Data Sheet U12031EJ4V0DS00
27
µPD30500, 30500A, 30500B
272-PIN PLASTIC BGA (C/D advanced type) (29x29)
A
B
A
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D
AA Y W V U T R P N M L K J H G F E D C B A
Z
Index area
Y
J
H
G
S
detail of A part
A
K
L
φM
φP
S
M
S A B
M
S
F
E
N
ITEM
A
MILLIMETERS
29.00±0.20
D
29.00±0.20
E
1.80
F
G
1.27 (T.P.)
0.60±0.10
0.90
H
J
1.50±0.20
K
L
0.15
φ 0.75±0.15
M
N
0.30
0.25 MIN.
P
Y
0.10
C1.5
Z
C0.5
S272S2-127-C6-3
28
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
4. RECOMMENDED SOLDERING CONDITIONS
Soldering this product under the following soldering conditions is recommended.
For the details of the recommended soldering conditions, refer to Information Document Semiconductor Device
Mounting Technology Manual (C10535E).
For the soldering methods and recommended other than those recommended, consult NEC.
(1) Soldering Conditions of Surface Mount Type
µPD30500S2-150:
272-pin plastic BGA (C/D advanced type) (29 × 29)
µPD30500S2-180:
272-pin plastic BGA (C/D advanced type) (29 × 29)
µPD30500S2-200:
272-pin plastic BGA (C/D advanced type) (29 × 29)
µPD30500AS2-250:
272-pin plastic BGA (C/D advanced type) (29 × 29)
µPD30500BS2-300Note 1:
272-pin plastic BGA (C/D advanced type) (29 × 29)
Soldering Method
Soldering Conditions
Recommended
Conditions Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 sec max. (210°C min.),
Number of times: 3 times max., Number of days: 3Note 2 (after that, prebaking is
necessary at 125°C for 10 hours)
IR35-103-3
VPS
Package peak temperature: 215°C, Time: 25 to 40 sec max. (200°C min.),
Number of times: 3 times max., Number of days: 3Note 2 (after that, prebaking is
necessary at 125°C for 10 hours)
VP15-103-3
Partial heating
Pin temperature: 300°C max., Time: 3 sec max. (per device side)
—
Notes 1. Under development
2. Number of days in storage after the dry pack has been opened. The storage conditions are at 25°C, 65% RH
MAX.
Caution Do not use two or more soldering methods in combination (except partial heating).
(2) Soldering Conditions of Insertion Type
µPD30500RJ-150: 223-pin ceramic PGA (48 × 48)
µPD30500RJ-180: 223-pin ceramic PGA (48 × 48)
µPD30500RJ-200: 223-pin ceramic PGA (48 × 48)
Soldering Method
Soldering Conditions
Wave soldering
(Pin only)
Solder bath temperature: 260°C max., Time: 10 sec max.
Partial heating
Pin temperature: 300°C max., Time: 3 sec max. (per pin)
Caution Wave soldering is only for the lead part in order that jet solder cannot contact with the chip directly.
Data Sheet U12031EJ4V0DS00
29
µPD30500, 30500A, 30500B
APPENDIX DIFFERENCES BETWEEN THE VR5000 AND VR4310TM
Item
Operating frequency
VR5000
VR4310
Internal
200 MHz MAX.
167 MHz MAX.
External
100 MHz MAX.
83.3 MHz MAX.
2-way super scalar 5-stage
pipeline
5-stage pipeline
Primary instruction cache
32 Kbytes
16 Kbytes
Primary data cache
32 Kbytes
8 Kbytes
Secondary cache interface
Provided
None
Data protection
Byte parity
None
Write data transfer rate
9 types (DDDD/DDxDDx/
DDxxDDxx/DxDxDxDx/
DDxxxDDxxx/DDxxxxDDxxxx/
DxxDxxDxxDxx/
DDxxxxxxDDxxxxxx/DxxxDxxx)
2 types (D/Dxx)
Initialization pin at reset
ModeIn (dedicated serial pin)
DivMode (0:2)
Status after last data write
Access ends
Last data retained when transfer
rate is set
Corresponding instruction
MIPS I, II, III, IV instruction sets
MIPS I, II, III instruction sets
JTAG interface
None
Provided
SyncOut-SyncIn bus
None
Provided
2, 3, 4, 5, 6, 7, 8
1.5, 2, 2.5, 3, 4, 5, 6
Division ratio of internal to
bus
2, 3, 4, 5, 6, 7, 8
1.5, 2, 2.5, 3, 4, 5, 6
Clock output
None
TClock
Standby mode (pipline does
Not provided
Pipeline
Cache
System bus
Integer operation unit
Clock interface
Multiplication ratio of input
to internal
Power management mode
not operate)
PRId register
30
Imp = 0x23
Data Sheet U12031EJ4V0DS00
Imp = 0x0B
µPD30500, 30500A, 30500B
[MEMO]
Data Sheet U12031EJ4V0DS00
31
µPD30500, 30500A, 30500B
[MEMO]
32
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
[MEMO]
Data Sheet U12031EJ4V0DS00
33
µPD30500, 30500A, 30500B
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Note that this document is not designated as ‘preliminary’, while some of the related documents are preliminary
versions.
V R3000, V R 4000, V R4310, V R5000, V R 5000A, V R5000B, V R10000, and V R Series are trademarks of NEC
Corporation.
MIPS is a trademark of MIPS Technologies Inc.
34
Data Sheet U12031EJ4V0DS00
µPD30500, 30500A, 30500B
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U12031EJ4V0DS00
35
µPD30500, 30500A, 30500B
Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some
countries because this product utilizes technologies limited by the export control regulations of the U.S.A.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8