DATA SHEET MOS INTEGRATED CIRCUIT µPD442012A-X 2M-BIT CMOS STATIC RAM 128K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD442012A-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM. The µPD442012A-X has two chip enable pins (/CE1, CE2) to extend the capacity. The µPD442012A-X is packed in 48-pin PLASTIC TSOP (I) (Normal bent). Features • 131,072 words by 16 bits organization ★ • Fast access time : 50, 55, 70, 85, 100, 120 ns (MAX.) • Byte data control : /LB (I/O1 - I/O8), /UB (I/O9 - I/O16) • Low voltage operation (BB version : VCC = 2.7 to 3.6 V, BC version : VCC = 2.2 to 3.6 V, DD version : VCC = 1.8 to 2.2 V) • Low VCC data retention : 1.0 V (MIN.) • Operating ambient temperature : TA = –25 to +85 °C • Output Enable input for easy application • Two Chip Enable inputs : /CE1, CE2 Part number Access time Operating supply Operating ambient ns (MAX.) ★ µPD442012A-BBxxX 50 Note 1 , 55, 70, 85 Supply current voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) 2.7 to 3.6 −25 to +85 4 2 30 Note 2 35 Note 3 40 Note 4 µPD442012A-BCxxX 70, 85, 100 2.2 to 3.6 30 ★ µPD442012A-DDxxX 85, 100, 120 1.8 to 2.2 15 ★ Notes 1. VCC ≥ 3.0 V ★ 2. Cycle time ≥ 70 ns ★ 3. Cycle time = 55 ns ★ 4. Cycle time = 50 ns 3 The information in this document is subject to change without notice. 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Document No. M14671EJ7V0DS00 (7th edition) Date Published July 2001 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 2000 µPD442012A-X Ordering Information Part number ★ ★ Package µPD442012AGY-BB55X-MJH 48-pin PLASTIC TSOP (I) µPD442012AGY-BB70X-MJH (12×18) (Normal bent) Access time Operating Operating ns (MAX.) supply voltage temperature V °C 2.7 to 3.6 −25 to +85 55, 50 Note BB version 70 µPD442012AGY-BB85X-MJH 85 µPD442012AGY-BC70X-MJH 70 µPD442012AGY-BC85X-MJH 85 µPD442012AGY-BC10X-MJH 100 µPD442012AGY-DD85X-MJH 85 µPD442012AGY-DD10X-MJH 100 µPD442012AGY-DD12X-MJH 120 Note VCC ≥ 3.0 V 2 Remark Data Sheet M14671EJ7V0DS 2.2 to 3.6 BC version 1.8 to 2.2 DD version µPD442012A-X Pin Configuration (Marking Side) /xxx indicates active low signal. ×18) (Normal bent) 48-pin PLASTIC TSOP (I) (12× [ µPD442012AGY-BBxxX-MJH ] [ µPD442012AGY-BCxxX-MJH ] [ µPD442012AGY-DDxxX-MJH ] A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE CE2 IC /UB /LB NC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A0 - A16 A16 NC GND I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VCC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 /OE GND /CE1 A0 : Address inputs I/O1 - I/O16 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable /LB, /UB : Byte data select VCC : Power supply GND : Ground NC : No Connection IC Note : Internal Connection Note Leave this pin unconnected or connect to GND. Remark Refer to Package Drawing for the 1-pin index mark. Data Sheet M14671EJ7V0DS 3 µPD442012A-X Block Diagram VCC GND A0 A16 Address buffer Row decoder I/O1 - I/O8 I/O9 - I/O16 Input data controller Memory cell array 2,097,152 bits Sense amplifier / Switching circuit Column decoder Address buffer /CE1 CE2 /LB /UB /WE /OE 4 Data Sheet M14671EJ7V0DS Output data controller µPD442012A-X Truth Table /CE1 CE2 /OE /WE /LB /UB Mode I/O Supply current I/O1 - I/O8 I/O9 - I/O16 H × × × × × Not selected High impedance High impedance × L × × × × Not selected High impedance High impedance × × × × H H Not selected High impedance High impedance L H H H L × Output disable High impedance High impedance × L Output disable High impedance High impedance L L Word read DOUT DOUT L H Lower byte read DOUT High impedance H L Upper byte read High impedance DOUT L L Word write DIN DIN L H Lower byte write DIN High impedance H L Upper byte write High impedance DIN L × H L ISB ICCA Remark × : VIH or VIL Data Sheet M14671EJ7V0DS 5 µPD442012A-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Product VCC µPD442012A-BBxxX, µPD442012A-BCxxX Supply voltage Rating µPD442012A-DDxxX Input / Output voltage VT µPD442012A-BBxxX, µPD442012A-BCxxX µPD442012A-DDxxX Unit –0.5 Note to +4.0 –0.5 Note to +2.7 V –0.5 Note to VCC+0.4 (4.0 V MAX.) –0.5 Note to VCC+0.4 (2.7 V MAX.) V Operating ambient temperature TA –25 to +85 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Supply voltage VCC High level input voltage VIH Low level input voltage VIL Operating ambient TA Condition µPD442012A-BBxxX µPD442012A-BCxxX µPD442012A-DDxxX Unit MIN. MAX. MIN. MAX. MIN. MAX. 2.7 3.6 2.2 3.6 1.8 2.2 V 2.7 V ≤ VCC ≤ 3.6 V 2.4 VCC+0.4 2.4 VCC+0.4 – – V 2.2 V ≤ VCC < 2.7 V – – 2.0 VCC+0.3 – – 1.8 V ≤ VCC < 2.2 V – – – – 1.6 –0.3 Note –25 +0.5 +85 –0.3 Note –25 +0.4 –0.2 +85 VCC+0.2 Note –25 +0.2 V +85 °C temperature Note –1.0 V (MIN.) (Pulse width : 20 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. 6 Data Sheet M14671EJ7V0DS µPD442012A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition µPD442012A-BBxxX MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 µA mA CE2 = VIL or /WE = VIL or /OE = VIH ★ Operating supply current ★ ICCA1 ICCA2 /CE1 = VIL, CE2 = VIH, Cycle time = 50 ns – 40 II/O = 0 mA, Cycle time = 55 ns – 35 Minimum cycle time Cycle time ≥ 70 ns – 30 – 4 – 4 – 0.6 mA µA /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ ★ ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB /CE1 = VIH or CE2 = VIL or /LB = /UB = VIH ISB1 /CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V 0.3 4 ISB2 CE2 ≤ 0.2 V 0.3 4 ISB3 /LB = /UB ≥ VCC – 0.2 V, 0.3 4 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1.0 mA 2.4 V 0.4 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product specification. Data Sheet M14671EJ7V0DS 7 µPD442012A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol µPD442012A-BCxxX µPD442012A-DDxxX MIN. MAX. MIN. Test condition TYP. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 –1.0 +1.0 µA mA CE2 = VIL or /WE = VIL or /OE = VIH Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, – 30 – – ★ II/O = 0 mA, VCC ≤ 2.7 V – 25 – – ★ Minimum cycle time VCC ≤ 2.2 V – – – 15 – 4 – – ★ ICCA2 /CE1 = VIL, CE2 = VIH, ★ II/O = 0 mA, VCC ≤ 2.7 V – 2 – – ★ Cycle time = ∞ VCC ≤ 2.2 V – – – 1 – 4 – – ★ ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, ★ VIL ≤ 0.2 V, VCC ≤ 2.7 V – 3 – – ★ VIH ≥ VCC – 0.2 V VCC ≤ 2.2 V – – – 3 – 0.6 – – VCC ≤ 2.7 V – 0.6 – – VCC ≤ 2.2 V – – – 0.6 0.3 4 – – VCC ≤ 2.7 V 0.25 3.5 – – VCC ≤ 2.2 V – – 0.2 3 0.3 4 – – VCC ≤ 2.7 V 0.25 3.5 – – VCC ≤ 2.2 V – – 0.2 3 0.3 4 – – Standby supply current ISB /CE1 = VIH or CE2 = VIL or /LB = /UB = VIH ISB1 /CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V ISB2 ISB3 High level output voltage Low level output voltage VOH VOL CE2 ≤ 0.2 V /LB = /UB ≥ VCC – 0.2 V, /CE1 ≤ 0.2 V, VCC ≤ 2.7 V 0.25 3.5 – – CE2 ≥ VCC – 0.2 V VCC ≤ 2.2 V – – 0.2 3 IOH = –0.5 mA 2.4 – VCC ≤ 2.7 V 1.8 – VCC ≤ 2.2 V – 1.5 IOL = 1.0 mA – VCC ≤ 2.7 V 0.4 – VCC ≤ 2.2 V – 0.4 VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product specification. 8 Data Sheet M14671EJ7V0DS µA V 0.4 Remarks 1. VIN : Input voltage mA V µPD442012A-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD442012A-BB55X, µPD442012A-BB70X, µPD442012A-BB85X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load 1TTL + 50 pF [ µPD442012A-BC70X, µPD442012A-BC85X, µPD442012A-BC10X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load 1TTL + 30 pF [ µPD442012A-DD85X, µPD442012A-DD10X, µPD442012A-DD12X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load 1TTL + 30 pF Data Sheet M14671EJ7V0DS 9 µPD442012A-X ★ Read Cycle (1/3) (BB version) Parameter µPD442012A-BB55X Symbol µPD442012A µPD442012A -BB70X -BB85X VCC ≥ 3.0 V MIN. MAX. MIN. 50 MAX. 55 MIN. MAX. MIN. 70 Unit Condition MAX. Read cycle time tRC 85 ns Address access time tAA 50 55 70 85 ns /CE1 access time tCO1 50 55 70 85 ns CE2 access time tCO2 50 55 70 85 ns /OE to output valid tOE 30 30 35 40 ns /LB, /UB to output valid tBA 50 55 70 85 ns Output hold from address change tOH 10 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 5 ns /LB, /UB to output in low impedance tBLZ 10 10 10 10 ns /CE1 to output in high impedance tHZ1 20 20 25 30 ns CE2 to output in high impedance tHZ2 20 20 25 30 ns /OE to output in high impedance tOHZ 20 20 25 30 ns /LB, /UB to output in high impedance tBHZ 20 20 25 30 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Read Cycle (2/3) (BC version) Parameter Symbol µPD442012A µPD442012A µPD442012A -BC70X -BC85X -BC10X MIN. Read cycle time tRC MAX. 70 MIN. MAX. 85 MIN. Unit MAX. 100 ns Address access time tAA 70 85 100 ns /CE1 access time tCO1 70 85 100 ns CE2 access time tCO2 70 85 100 ns /OE to output valid tOE 35 40 50 ns 100 ns 70 85 /LB, /UB to output valid tBA Output hold from address change tOH 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /LB, /UB to output in low impedance tBLZ 10 10 10 ns /CE1 to output in high impedance tHZ1 25 30 35 ns CE2 to output in high impedance tHZ2 25 30 35 ns /OE to output in high impedance tOHZ 25 30 35 ns /LB, /UB to output in high impedance tBHZ 25 30 35 ns Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. 10 Data Sheet M14671EJ7V0DS Condition Note 1 Note 2 µPD442012A-X Read Cycle (3/3) (DD version) Parameter Symbol µPD442012A µPD442012A µPD442012A -DD85X -DD10X -DD12X MIN. MAX. MIN. 85 MAX. 100 MIN. Unit Condition MAX. Read cycle time tRC 120 ns Address access time tAA 85 100 120 ns /CE1 access time tCO1 85 100 120 ns CE2 access time tCO2 85 100 120 ns /OE to output valid tOE 40 50 60 ns /LB, /UB to output valid tBA 85 100 120 ns Output hold from address change tOH 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /LB, /UB to output in low impedance tBLZ 10 10 10 ns /CE1 to output in high impedance tHZ1 30 35 40 ns CE2 to output in high impedance tHZ2 30 35 40 ns /OE to output in high impedance tOHZ 30 35 40 ns /LB, /UB to output in high impedance tBHZ 30 35 40 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. Read Cycle Timing Chart tRC Address (Input) tAA tOH /CE1 (Input) tHZ1 tCO1 tLZ1 CE2 (Input) tCO2 tHZ2 tLZ2 /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tBA tBHZ tBLZ I/O (Output) Remark High impedance Data out In read cycle, /WE should be fixed to high level. Data Sheet M14671EJ7V0DS 11 µPD442012A-X ★ Write Cycle (1/3) (BB version) Parameter µPD442012A-BB55X Symbol µPD442012A µPD442012A -BB70X -BB85X VCC ≥ 3.0 V MIN. Write cycle time MAX. MIN. MAX. MIN. MAX. MIN. Unit MAX. tWC 50 55 70 85 ns /CE1 to end of write tCW1 45 50 55 70 ns CE2 to end of write tCW2 45 50 55 70 ns /LB, /UB to end of write tBW 45 50 55 70 ns Address valid to end of write tAW 45 50 55 70 ns Address setup time tAS 0 0 0 0 ns Write pulse width tWP 40 45 50 55 ns Write recovery time tWR 0 0 0 0 ns Data valid to end of write tDW 25 25 30 35 ns Data hold time tDH 0 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 20 20 5 5 25 30 5 Condition 5 ns Note ns Note The output load is 1TTL + 5 pF. Write Cycle (2/3) (BC version) Parameter Symbol µPD442012A µPD442012A µPD442012A -BC70X -BC85X -BC10X MIN. MAX. MIN. MAX. MIN. Unit MAX. Write cycle time tWC 70 85 100 ns /CE1 to end of write tCW1 55 70 80 ns CE2 to end of write tCW2 55 70 80 ns /LB, /UB to end of write tBW 55 70 80 ns Address valid to end of write tAW 55 70 80 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 50 55 60 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 30 35 40 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 25 5 30 5 Note The output load is 1TTL + 5 pF. 12 Data Sheet M14671EJ7V0DS 35 5 Condition ns ns Note µPD442012A-X Write Cycle (3/3) (DD version) Parameter Symbol µPD442012A µPD442012A µPD442012A -DD85X -DD10X -DD12X MIN. Write cycle time MAX. MIN. MAX. MIN. Unit MAX. tWC 85 100 120 ns /CE1 to end of write tCW1 70 80 100 ns CE2 to end of write tCW2 70 80 100 ns /LB, /UB to end of write tBW 70 80 100 ns Address valid to end of write tAW 70 80 100 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 55 60 85 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 35 40 60 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 30 5 35 5 40 5 Condition ns Note ns Note The output load is 1TTL + 5 pF. Data Sheet M14671EJ7V0DS 13 µPD442012A-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS tWP tWR /WE (Input) tBW /LB, /UB (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CE1, a low level /WE, a low level /LB (or low level /UB) and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. 14 Data Sheet M14671EJ7V0DS µPD442012A-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tBW /LB, /UB (Input) tDW High impedance Data in I/O (Input) tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, a low level /WE, a low level /LB (or low level /UB) and a high level CE2. Data Sheet M14671EJ7V0DS 15 µPD442012A-X Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, a low level /WE, a low level /LB (or low level /UB) and a high level CE2. 16 Data Sheet M14671EJ7V0DS µPD442012A-X Write Cycle Timing Chart 4 (/LB, /UB Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tAS tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, a low level /WE, a low level /LB (or low level /UB) and a high level CE2. Data Sheet M14671EJ7V0DS 17 µPD442012A-X Low VCC Data Retention Characteristics (TA = –25 to +85 °C) Parameter Symbol Test Condition µPD442012A µPD442012A µPD442012A -BBxxX -BCxxX -DDxxX Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Data retention VCCDR1 /CE1 ≥ VCC − 0.2 V, 1.0 3.6 1.0 3.6 1.0 2.2 V CE2 ≥ VCC − 0.2 V supply voltage VCCDR2 CE2 ≤ 0.2 V 1.0 3.6 1.0 3.6 1.0 2.2 VCCDR3 /LB = /UB ≥ VCC − 0.2 V, 1.0 3.6 1.0 3.6 1.0 2.2 /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V ★ Data retention ICCDR1 VCC = 1.2 V, /CE1 ≥ VCC − 0.2 V, 0.15 2 0.15 2 0.15 2 µA CE2 ≥ VCC − 0.2 V supply current ICCDR2 VCC = 1.2 V, CE2 ≤ 0.2 V 0.15 2 0.15 2 0.15 2 ICCDR3 VCC = 1.2 V, /LB = /UB ≥ VCC − 0.2 V, 0.15 2 0.15 2 0.15 2 /CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V Chip deselection tCDR 0 0 0 ns Note ns to data retention mode Operation tR tRC Note recovery time Note tRC : Read cycle time 18 Data Sheet M14671EJ7V0DS tRC Note tRC µPD442012A-X Data Retention Timing Chart (1) /CE1 Controlled tCDR Data retention mode tR VCC VCC (MIN.) Note /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. (2) CE2 Controlled tCDR Data retention mode tR VCC VCC (MIN.) Note VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. Data Sheet M14671EJ7V0DS 19 µPD442012A-X (3) /LB, /UB Controlled tCDR Data retention mode tR VCC VCC (MIN.) Note /LB, /UB VIH (MIN.) VCCDR (MIN.) /LB, /UB ≥ VCC – 0.2 V VIL (MAX.) GND Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1 and CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. 20 Data Sheet M14671EJ7V0DS µPD442012A-X Package Drawing 48-PIN PLASTIC TSOP(I) (12x18) 1 detail of lead end 48 F G R Q 24 L 25 S E P I A J C S D K N B M M S NOTES ITEM MILLIMETERS 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. A 12.0±0.1 B 0.45 MAX. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 1.0±0.05 I 16.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 18.0±0.2 Q 3° +5° −3° R S 0.25 0.60±0.15 S48GY-50-MJH1-1 Data Sheet M14671EJ7V0DS 21 µPD442012A-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD442012A-X. Types of Surface Mount Device µPD442012AGY-BBxxX-MJH : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) µPD442012AGY-BCxxX-MJH : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) µPD442012AGY-DDxxX-MJH : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent) 22 Data Sheet M14671EJ7V0DS µPD442012A-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14671EJ7V0DS 23 µPD442012A-X • The information in this document is current as of July, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4