PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD444016L-Y 4M-BIT CMOS FAST SRAM 256K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD444016L-Y is a high speed, low power, 4,194,304 bits (262,144 words by 16 bits) CMOS static RAM. Operating supply voltage is 3.3 V ± 0.3 V. The µPD444016L-Y is packaged in 44-PIN PLASTIC TSOP (II). Features • 262,144 words by 16 bits organization • Fast access time : 8, 10, 12 ns (MAX.) • Byte data control : /LB (I/O1 - I/O8), /UB (I/O9 - I/O16) • Output Enable input for easy application • Single +3.3 V power supply Ordering Information Part number Package Access time Supply current mA (MAX.) ns (MAX.) At operating At standby 5 µPD444016LG5-A8Y-7JF 44-PIN PLASTIC TSOP (II) 8 210 µPD444016LG5-A10Y-7JF (10.16 mm (400)) 10 190 µPD444016LG5-A12Y-7JF (Normal bent) 12 180 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. 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Document No. M15392EJ1V0DS00 (1st edition) Date Published February 2001 NS CP(K) Printed in Japan © 2001 µPD444016L-Y Pin Configuration (Marking Side) /××× indicates active low signal. 44-PIN PLASTIC TSOP (II) (10.16 mm (400)) (Normal bent) [ µPD444016LG5-A×× ××Y-7JF ] ×× A0 1 44 A17 A1 2 43 A16 A2 3 42 A15 A3 4 41 /OE A4 5 40 /UB /CS 6 39 /LB I/O1 7 38 I/O16 I/O2 8 37 I/O15 I/O3 9 36 I/O14 I/O4 10 35 I/O13 VCC 11 34 GND GND 12 33 VCC I/O5 13 32 I/O12 I/O6 14 31 I/O11 I/O7 15 30 I/O10 I/O8 16 29 I/O9 /WE 17 28 NC A5 18 27 A14 A6 19 26 A13 A7 20 25 A12 A8 21 24 A11 A9 22 23 A10 A0 - A17 : Address Inputs I/O1 - I/O16 : Data Inputs / Outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable /LB, /UB : Byte data select VCC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawing for the 1-pin index mark. 2 Preliminary Data Sheet M15392EJ1V0DS µPD444016L-Y A0 | A17 I/O1 - I/O8 Row decoder Address buffer Block Diagram Memory cell array 4,194,304 bits Input data controller Sense amplifier / Switching circuit I/O9 - I/O16 Output data controller Column decoder /WE /CS /LB Address buffer /UB /OE VCC GND Truth Table /CS /OE /WE /LB /UB Mode I/O Supply current I/O1 - I/O8 I/O9 - I/O16 H × × × × Not selected High impedance High impedance ISB L L H L L Read DOUT DOUT ICC L H DOUT High impedance H L High impedance DOUT L L DIN DIN L H DIN High impedance H L High impedance DIN High impedance High impedance High impedance High impedance L × L L H H × × L × × H H Write Output disable Remark × : Don’t care Preliminary Data Sheet M15392EJ1V0DS 3 µPD444016L-Y Electrical Specifications Absolute Maximum Ratings Parameter Symbol Condition Rating Note Unit Supply voltage VCC –0.5 to +4.0 V Input / Output voltage VT –0.5 Note to +4.0 V Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –55 to +125 °C Note –2.0 V (MIN.) (pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 3.3 3.6 V VCC+0.3 V +0.8 V +85 °C Supply voltage VCC 3.0 High level input voltage VIH 2.0 Low level input voltage VIL Operating ambient temperature TA –0.3 –40 Note –2.0 V (MIN.) (pulse width : 2 ns) 4 Note Preliminary Data Sheet M15392EJ1V0DS µPD444016L-Y DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current ILI VIN = 0 V to VCC –2 +2 µA Output leakage current ILO VI/O = 0 V to VCC, /CS = VIH or /OE = VIH –2 +2 µA mA or /WE = VIL or /LB = VIH or /UB = VIH Operating supply current Standby supply current ICC /CS = VIL, Cycle time : 8 ns 210 II/O = 0 mA, Cycle time : 10 ns 190 Minimum cycle time Cycle time : 12 ns 180 ISB /CS = VIH, VIN = VIH or VIL 40 ISB1 /CS ≥ VCC – 0.2 V, 5 mA VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V High level output voltage VOH IOH = –4.0 mA Low level output voltage VOL IOL = +8.0 mA 2.4 V 0.4 V MAX. Unit Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product classification. Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. Input capacitance CIN VIN = 0 V 6 pF Input / Output capacitance CI/O VI/O = 0 V 8 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. Preliminary Data Sheet M15392EJ1V0DS 5 µPD444016L-Y AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time ≤ 3 ns) 3.0 V 1.5 V Test Points 1.5 V 1.5 V Test Points 1.5 V GND Output Waveform Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure 2. Figure 1 Figure 2 (tAA, tACS, tOE, tABD, tOH) (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW ) VTT = +1.5 V +3.3 V 50 Ω 317 Ω ZO = 50 Ω I/O (Output) I/O (Output) 30 pF CL 351 Ω Remark CL includes capacitances of the probe and jig, and stray capacitances. 6 Preliminary Data Sheet M15392EJ1V0DS 5 pF CL µPD444016L-Y Read Cycle Parameter µPD444016L-A8Y µPD444016L-A10Y µPD444016L-A12Y Unit Symbol MIN. MAX. 8 MIN. MAX. 10 MIN. Notes MAX. Read cycle time tRC 12 ns Address access time tAA 8 10 12 ns /CS access time tACS 8 10 12 ns /OE access time tOE 4 5 6 ns /LB, /UB access time tABD 4 5 6 ns Output hold from address change tOH 3 3 3 ns /CS to output in low impedance tCLZ 3 3 3 ns /OE to output in low impedance tOLZ 0 0 0 ns /LB, /UB to output in low impedance tBLZ 0 0 0 ns /CS to output in high impedance tCHZ 4 5 6 ns /OE to output hold in high impedance tOHZ 4 5 6 ns /LB, /UB to output hold in high impedance tBHZ 4 5 6 ns 1 2, 3 Notes 1. See the output load shown in Figure 1. 2. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2. 3. These parameters are not 100% tested. Read Cycle Timing Chart 1 (Address Access) tRC Address (Input) tAA tOH I/O (Output) Previous data out Data out Remarks 1. In read cycle, /WE should be fixed to high level. 2. /CS = /OE = /LB (or /UB) = VIL Preliminary Data Sheet M15392EJ1V0DS 7 µPD444016L-Y Read Cycle Timing Chart 2 (/CS Access) tRC Address (Input) tAA tACS /CS (Input) tCLZ tCHZ /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tABD tBHZ tBLZ I/O (Output) High impedance Data out Caution Address valid prior to or coincident with /CS low level input. Remark In read cycle, /WE should be fixed to high level. 8 Preliminary Data Sheet M15392EJ1V0DS High impedance µPD444016L-Y Write Cycle Parameter Symbol µPD444016L-A8Y µPD444016L-A10Y µPD444016L-A12Y Unit MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time tWC 8 10 12 ns /CS to end of write tCW 6 7 8 ns Address valid to end of write tAW 6 7 8 ns Write pulse width tWP 6 7 8 ns /LB, /UB to end of write tBW 6 7 8 ns Data valid to end of write tDW 4 5 6 ns Data hold time tDH 0 0 0 ns Address setup time tAS 0 0 0 ns Write recovery time tWR 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 4 3 5 6 3 3 Notes ns 1, 2 ns Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2. 2. These parameters are not 100% tested. Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS tWR tWP /WE (Input) tBW /LB, /UB (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CS, /LB and/or /UB, and a low level /WE. 2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Preliminary Data Sheet M15392EJ1V0DS 9 µPD444016L-Y Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS tCW /CS (Input) tAW tWP tWR /WE (Input) tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. Do not input data to the I/O pins while they are in the output state. Remark 10 Write operation is done during the overlap time of a low level /CS, /LB and/or /UB, and a low level /WE. Preliminary Data Sheet M15392EJ1V0DS µPD444016L-Y Write Cycle Timing Chart 3 (/LB, /UB Controlled) tWC Address (Input) tAW tCW tWR /CS (Input) tWP /WE (Input) tAS tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CS, /LB and/or /UB, and a low level /WE. Preliminary Data Sheet M15392EJ1V0DS 11 µPD444016L-Y Package Drawing 44-PIN PLASTIC TSOP (II) (10.16 mm (400)) 44 23 detail of lead end F P E 1 22 A H G I S C D N M M J L S B K NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 18.63 MAX. B 0.93 MAX. C 0.8 (T.P.) D 0.32 +0.08 −0.07 E 0.1±0.05 F 1.2 MAX. G 0.97 11.76±0.2 10.16±0.1 H I J K L M 0.8±0.2 0.145+0.025 −0.015 0.5±0.1 0.13 N 0.10 P 3°+7° −3° S44G5-80-7JF5-1 12 Preliminary Data Sheet M15392EJ1V0DS µPD444016L-Y Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD444016L-Y. Type of Surface Mount Device µPD444016LG5-7JF : 44-PIN PLASTIC TSOP (II) (10.16 mm (400)) (Normal bent) Preliminary Data Sheet M15392EJ1V0DS 13 µPD444016L-Y [ MEMO ] 14 Preliminary Data Sheet M15392EJ1V0DS µPD444016L-Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Data Sheet M15392EJ1V0DS 15 µPD444016L-Y • The information in this document is current as of February, 2001. The information is subject to change without notice. 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