DATA SHEET MOS INTEGRATED CIRCUIT µPD703003A, 703004A, 703025A V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS The µPD703003A, 703004A, and 703025A are members of the V850 Family TM of 32-bit single-chip microcontrollers designed for real-time control operations. These microcontrollers provide on-chip features including a 32-bit CPU core, ROM, RAM, an interrupt controller, a real-time pulse unit, a serial interface, an A/D converter, a D/A converter, and PWM. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. V853 User’s Manual Hardware: U10913E V850 Family User’s Manual Architecture: U10243E FEATURES • Number of instructions: 74 • Minimum instruction execution time: 30 ns (@ 33 MHz operation) • General-purpose registers: 32 bits × 32 registers • Instruction set optimized for control applications • On-chip memory ROM: 256 KB ( µPD703025A) 128 KB ( µPD703003A) 96 KB (µPD703004A) RAM: 8 KB ( µPD703025A) 4 KB (µPD703003A, 703004A) • Advanced on-chip interrupt controller • Real-time pulse unit suitable for control operations • Powerful serial interface (on-chip dedicated baud rate generator) • On-chip clock generator • 10-bit resolution A/D converter: 8 channels • 8-bit resolution D/A converter: 2 channels • 8-/9-/10-/12-bit resolution PWM: 2 channels • Power saving functions APPLICATIONS • AV: Camcorders, VCRs, etc. • Office equipment: PPCs, LBPs, printers, etc. • Industrial equipment: Motor controllers, NC machine tools, etc. • Communications equipment: Mobile telephones, etc. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13188EJ4V0DS00 (4th edition) Date Published July 2000 N CP(K) Printed in Japan The mark shows major revised points. © 1998 µPD703003A, 703004A, 703025A ORDERING INFORMATION Part Number Package Maximum Internal Internal Operating ROM RAM Frequency (MHz) (Bytes) (Bytes) µPD703003AGC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 25 128 K 4K µPD703003AGC-33-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 33 128 K 4K µPD703004AGC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 25 96 K 4K µPD703004AGC-33-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 33 96 K 4K µPD703025AGC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 25 256 K 8K µPD703025AGC-33-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 33 256 K 8K Remark xxx indicates ROM code suffix. PIN CONFIGURATION • 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703004AGC-33-xxx-8EU µPD703003AGC-33-xxx-8EU µPD703025AGC-25-xxx-8EU µPD703004AGC-25-xxx-8EU µPD703025AGC-33-xxx-8EU 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P43/AD3 P42/AD2 VSS VDD P41/AD1 P40/AD0 P90/LBEN P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRQ WAIT IC MODE RESET CVDD/CKSEL X2 X1 CVSS CLKOUT VSS VDD P110/TO140 P31/TO131 P32/TCLR13 P33/TI13 P34/INTP130 P35/INTP131/SO3 P36/INTP132/SI3 P37/INTP133/SCK3 P63/A19 P62/A18 P61/A17 P60/A16 VSS VDD P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P30/TO130 P27/SCK1 P26/RXD1/SI1 P25/TXD1/SO1 P24/SCK0 P23/RXD0/SI0 P22/TXD0/SO0 P21/PWM1 P20/PWM0 NMI VDD VSS P17/INTP123/SCK2 P16/INTP122/SI2 P15/INTP121/SO2 P14/INTP120 P13/TI12 P12/TCLR12 P11/TO121 P10/TO120 AVDD AVSS AVREF1 P77/ANI7 P76/ANI6 µPD703003AGC-25-xxx-8EU Caution Connect the IC (Internally Connected) pin directly to VSS. 2 Data Sheet U13188EJ4V0DS00 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 ANO0 ANO1 AVREF2 AVREF3 P07/INTP113/ADTRG P06/INTP112 P05/INTP111 P04/INTP110 P03/TI11 P02/TCLR11 P01/TO111 P00/TO110 P117/INTP143 P116/INTP142 P115/INTP141 P114/INTP140 P113/TI14 P112/TCLR14 P111/TO141 µPD703003A, 703004A, 703025A PIN NAMES A16 to A19: Address Bus P30 to P37: Port 3 AD0 to AD15: Address/Data Bus P40 to P47: Port 4 ADTRG: AD Trigger Input P50 to P57: Port 5 ANI0 to ANI7: Analog Input P60 to P63: Port 6 ANO0, ANO1: Analog Output P70 to P77: Port 7 ASTB: Address Strobe P90 to P96: Port 9 AVDD: Analog Power Supply P110 to P117: Port 11 AVREF1 to AVREF3: Analog Reference Voltage PWM0, PWM1: Pulse Width Modulation AVSS: Analog Ground RESET: Reset CVDD: Power Supply for Clock Generator R/W: Read/Write Status CVSS: Ground for Clock Generator RXD0, RXD1: Receive Data CKSEL: Clock Select SCK0 to SCK3: Serial Clock CLKOUT: Clock Output SI0 to SI3: Serial Input DSTB: Data Strobe SO0 to SO3: Serial Output HLDAK: Hold Acknowledge TO110, TO111,: Timer Output HLDRQ: Hold Request TO120, TO121, IC: Internally Connected TO130, TO131, INTP110 to INTP113,: Interrupt Request from Peripherals TO140, TO141 INTP120 to INTP123, TCLR11 to TCLR14: Timer Clear INTP130 to INTP133, TI11 to TI14: Timer Input INTP140 to INTP143 TXD0, TXD1: Transmit Data LBEN: Lower Byte Enable UBEN: Upper Byte Enable MODE: Mode WAIT: Wait NMI: Non-maskable Interrupt Request X1, X2: Crystal P00 to P07: Port 0 VDD: Power Supply P10 to P17: Port 1 VSS: Ground P20 to P27: Port 2 Data Sheet U13188EJ4V0DS00 3 µPD703003A, 703004A, 703025A INTERNAL BLOCK DIAGRAM Mask ROM CPU NMI PC INTC INTP110 to INTP113 INTP120 to INTP123 INTP130 to INTP133 INTP140 to INTP143 Instruction queue Note 1 32-bit barrel shifter Multiplier 16 × 16 → 32 System registers TO110, TO111 TO120, TO121 TO130, TO131 TO140, TO141 RPU BCU HLDRQ HLDAK RAM General-purpose registers 32 bits × 32 TCLR11 to TCLR14 TI11 to TI14 ASTB DSTB R/W UBEN LBEN WAIT A16 to A19 AD0 to AD15 ALU Note 2 SIO SO0/TXD0 SI0/RXD0 SCK0 UART0/CSI0 A/D converter D/A converter BRG1 SO2 SI2 SCK2 CSI2 BRG2 SO3 SI3 SCK3 CSI3 PWM0, PWM1 PWM Notes 1. µPD703003A: Port P110 to P117 P90 to P96 P70 to P77 P60 to P63 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P17 P00 to P07 UART1/CSI1 ANO0, ANO1 AVREF2, AVREF3 SO1/TXD1 SI1/RXD1 SCK1 ANI0 to ANI7 AVREF1 AVSS AVDD ADTRG BRG0 128 KB µPD703004A: 96 KB µPD703025A: 256 KB 2. µPD703003A, 703004A: 4 KB µPD703025A: 4 8 KB Data Sheet U13188EJ4V0DS00 CG CKSEL CLKOUT X1 X2 MODE RESET VDD VSS CVDD CVSS µPD703003A, 703004A, 703025A CONTENTS 1. DIFFERENCES AMONG PRODUCTS ............................................................................................ 6 2. PIN FUNCTIONS .............................................................................................................................. 7 2.1 Port Pins ................................................................................................................................ 7 2.2 Non-Port Pins ........................................................................................................................ 9 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................... 11 3. ELECTRICAL SPECIFICATIONS .................................................................................................... 14 4. PACKAGE DRAWING ..................................................................................................................... 36 5. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 37 Data Sheet U13188EJ4V0DS00 5 µPD703003A, 703004A, 703025A 1. DIFFERENCES AMONG PRODUCTS µPD703003 µPD703003A µPD703004A µPD703025A µPD70F3003 µPD70F3003A µPD70F3025A Item Internal ROM Mask ROM Flash memory 128 KB Internal RAM Operation Normal mode operation mode 4 KB 256 KB 128 KB 256 KB 8 KB 4 KB 8 KB Single-chip Implemented mode ROM-less mode Implemented Not implemented Implemented Not implemented Not implemented Implemented VPP pin Not implemented Implemented Value of CKC register after reset 00H 00H Electrical specifications Power consumption levels vary (see specific product’s data sheet). Other Depending on the products, noise tolerance and noise emission will vary due to the differences in circuit scale and mask layout. Flash memory programming mode 6 96 KB MODE = 0: 03H MODE = 1: 00H Data Sheet U13188EJ4V0DS00 MODE = 0: 03H MODE = 1: 00H µPD703003A, 703004A, 703025A 2. PIN FUNCTIONS 2.1 Port Pins (1/2) Pin Name P00 I/O I/O P01 Function Port 0 TO110 8-bit I/O port TO111 Input/output can be specified in 1-bit units. P02 Alternate Function TCLR11 P03 TI11 P04 INTP110 P05 INTP111 P06 INTP112 P07 INTP113/ADTRG P10 I/O P11 Port 1 TO120 8-bit I/O port TO121 Input/output can be specified in 1-bit units. P12 TCLR12 P13 TI12 P14 INTP120 P15 INTP121/SO2 P16 INTP122/SI2 P17 INTP123/SCK2 P20 I/O P21 Port 2 PWM0 8-bit I/O port PWM1 Input/output can be specified in 1-bit units. P22 TXD0/SO0 P23 RXD0/SI0 P24 SCK0 P25 TXD1/SO1 P26 RXD1/SI1 P27 SCK1 P30 I/O P31 Port 3 TO130 8-bit I/O port TO131 Input/output can be specified in 1-bit units. P32 TCLR13 P33 TI13 P34 INTP130 P35 INTP131/SO3 P36 INTP132/SI3 P37 INTP133/SCK3 P40 to P47 I/O Port 4 AD0 to AD7 8-bit I/O port Input/output can be specified in 1-bit units. P50 to P57 I/O Port 5 AD8 to AD15 8-bit I/O port Input/output can be specified in 1-bit units. Data Sheet U13188EJ4V0DS00 7 µPD703003A, 703004A, 703025A (2/2) Pin Name P60 to P63 I/O I/O Function Port 6 Alternate Function A16 to A19 4-bit I/O port Input/output can be specified in 1-bit units. P70 to P77 Input Port 7 ANI0 to ANI7 8-bit input port P90 I/O P91 LBEN UBEN Input/output can be specified in 1-bit units. P92 R/W P93 DSTB P94 ASTB P95 HLDAK P96 HLDRQ P110 P111 P112 8 Port 9 7-bit I/O port I/O Port 11 TO140 8-bit I/O port TO141 Input/output can be specified in 1-bit units. TCLR14 P113 TI14 P114 INTP140 P115 INTP141 P116 INTP142 P117 INTP143 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A 2.2 Non-Port Pins (1/2) Pin Name TO110 I/O Output Function Pulse signal output from timers 11 to 14 Alternate Function P00 TO111 P01 TO120 P10 TO121 P11 TO130 P30 TO131 P31 TO140 P110 TO141 P111 TCLR11 Input External clear signal input for timers 11 to 14 P02 TCLR12 P12 TCLR13 P32 TCLR14 P112 TI11 Input External count clock input for timers 11 to 14 P03 TI12 P13 TI13 P33 TI14 P113 INTP110 Input INTP111 External maskable interrupt request input, also used as external capture P04 trigger input for timer 11 P05 INTP112 P06 INTP113 P07/ADTRG INTP120 Input INTP121 External maskable interrupt request input, also used as external capture P14 trigger input for timer 12 P15/SO2 INTP122 P16/SI2 INTP123 P17/SCK2 INTP130 Input INTP131 External maskable interrupt request input, also used as external capture P34 trigger input for timer 13 P35/SO3 INTP132 P36/SI3 INTP133 P37/SCK3 INTP140 Input INTP141 External maskable interrupt request input, also used as external capture P114 trigger input for timer 14 P115 INTP142 P116 INTP143 P117 SO0 Output Serial transmit data output (3-wire) for CSI0 to CSI3 P22/TXD0 SO1 P25/TXD1 SO2 P15/INTP121 SO3 P35/INTP131 SI0 Input Serial receive data input (3-wire) for CSI0 to CSI3 P23/RXD0 SI1 P26/RXD1 SI2 P16/INTP122 SI3 P36/INTP132 Data Sheet U13188EJ4V0DS00 9 µPD703003A, 703004A, 703025A (2/2) Pin Name SCK0 I/O I/O Function Serial clock I/O (3-wire) for CSI0 to CSI3 Alternate Function P24 SCK1 P27 SCK2 P17/INTP123 SCK3 P37/INTP133 TXD0 Output Serial transmit data output for UART0 and UART1 TXD1 RXD0 P25/SO1 Input Serial receive data input for UART0 and UART1 RXD1 PWM0 P23/SI0 P26/SI1 Output PWM pulse signal output PWM1 AD0 to AD7 P22/SO0 P20 P21 I/O 16-bit multiplexed address/data bus for external memory expansion A16 to A19 Output Higher address bus used for external memory expansion P60 to P63 LBEN Output External data bus’s lower byte enable signal output P90 External data bus’s higher byte enable signal output P91 External read/write status output P92 DSTB External data strobe signal output P93 ASTB External address strobe signal output P94 AD8 to AD15 P50 to P57 UBEN R/W P40 to P47 Output HLDAK Output Bus hold acknowledge output P95 HLDRQ Input Bus hold request input P96 ANI0 to ANI7 Input Analog input to A/D converter P70 to P77 ANO0, ANO1 Output Analog output from D/A converter — NMI Input Non-maskable interrupt request input — CLKOUT Output System clock output — CKSEL Input Input for specifying clock generator’s operation mode WAIT Input Control signal input for inserting wait in bus cycle — MODE Input Operation mode specification — RESET Input System reset input — X1 Input Resonator connection for system clock. Input is via X1 when using an — external clock. — X2 — CVDD ADTRG Input A/D converter external trigger input P07/INTP113 AVREF1 Input Reference voltage input for A/D converter — AVREF2 Input Reference voltage input for D/A converter — AVREF3 — AVDD — Positive power supply for A/D converter — AVSS — Ground potential for A/D converter — CVDD — Positive power supply for on-chip clock generator CVSS — Ground potential for on-chip clock generator — VDD — Positive power supply — VSS — Ground potential — IC — Internally connected pin (Connect directly to VSS) — 10 Data Sheet U13188EJ4V0DS00 CKSEL µPD703003A, 703004A, 703025A 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. Figure 2-1 illustrates the various circuit types using partially abridged diagrams. When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended. Table 2-1. Types of Pin Input/Output Circuits (1/2) Pin Name P00/TO110, P01/TO111 Input/Output Circuit Type Recommended Connection of Unused Pins 5 Input: Independently connect to VDD or VSS via a resistor. P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113/ADTRG 8 Output: Leave open. P10/TO120, P11/TO121 5 P12/TCLR12, P13/TI12 P14/INTP120 P15/INTP121/SO2 P16/INTP122/SI2 P17/INTP123/SCK2 8 P20/PWM0, P21/PWM1 5 P22/TXD0/SO0 P23/RXD0/SI0, P24/SCK0 8 P25/TXD1/SO1 5 P26/RXD1/SI1, P27/SCK1 8 P30/TO130, P31/TO131 5 P32/TCLR13, P33/TI13 8 P34/INTP130 P35/INTP131/SO3 P36/INTP132/SI3 10-A P37/INTP133/SCK3 P40/AD0 to P47/AD7 5 P50/AD8 to P57/AD15 P60/A16 to P63/A19 P70/ANI0 to P77/ANI7 9 Connect directly to VSS. P90/LBEN 5 Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRQ P110/TO140, P111/TO141 P112/TCLR14, P113/TI14 P114/INTP140 to P117/INTP143 8 ANO0, ANO1 12 Leave open. NMI 2 Connect directly to VSS. Data Sheet U13188EJ4V0DS00 11 µPD703003A, 703004A, 703025A Table 2-1. Types of Pin Input/Output Circuits (2/2) Pin Name Input/Output Circuit Type Recommended Connection of Unused Pins CLKOUT 3 Leave open. WAIT 1 Connect directly to VDD. MODE 2 — RESET CVDD/CKSEL AVREF1 to AVREF3, AVSS — Connect directly to VSS. AVDD — Connect directly to VDD. IC — Connect directly to VSS. 12 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A Figure 2-1. Pin Input/Output Circuits Type 1 Type 8 VDD VDD Data P-ch IN/OUT P-ch Output disable IN N-ch N-ch Type 2 Type 9 P-ch IN + IN Comparator – N-ch VREF (threshold voltage) Input enable Schmitt-triggered input with hysteresis characteristics Type 10-A Type 3 VDD VDD Pull-up enable P-ch VDD P-ch Data OUT P-ch IN/OUT N-ch Open drain Output disable Type 5 N-ch Type 12 VDD Data P-ch IN/OUT Output disable N-ch Analog output voltage P-ch N-ch OUT Input enable Data Sheet U13188EJ4V0DS00 13 µPD703003A, 703004A, 703025A 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Ratings Unit –0.5 to +7.0 V CVDD pin –0.5 to VDD + 0.3 V CVSS CVSS pin –0.5 to +0.5 V AVDD AVDD pin –0.5 to VDD + 0.3 V AVSS AVSS pin –0.5 to +0.5 V Input voltage VI1 Note, VDD = 5.0 V ±10% –0.5 to VDD + 0.3 V Clock input voltage VK X1 pin, VDD = 5.0 V ±10% –0.5 to VDD + 1.0 V Output current, low IOL Per pin 4.0 mA Total for all pins 100 mA Per pin –4.0 mA Power supply voltage Symbol Conditions VDD VDD pin CVDD Output current, high IOH Output voltage VO VDD = 5.0 V ±10% Analog input voltage VIAN P70/ANI0 to P77/ANI7 Analog reference input voltage AVREF AVREF1 to AVREF3 Total for all pins –100 mA –0.5 to VDD + 0.3 V AVDD > VDD –0.5 to VDD + 0.3 V VDD ≥ AVDD –0.5 to AVDD + 0.3 V AVDD > VDD –0.5 to VDD + 0.3 V VDD ≥ AVDD –0.5 to AVDD + 0.3 V Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note X1, P70/ANI0 to P77/ANI7, and AVREF1 to AVREF3 are excluded. Cautions 1. Be sure to avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. However, open-drain pins and open collector pins can be directly connected. A direct connection to an external circuit can be made to avoid conflicting output from high-impedance pins if the external circuit is designed for the correct timing. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance. Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Input capacitance CI I/O capacitance CIO Output capacitance CO 14 Condition fC = 1 MHz Unmeasured pins returned to 0 V. Data Sheet U13188EJ4V0DS00 MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF µPD703003A, 703004A, 703025A Operating Conditions Operation Mode Internal Operating Clock Frequency (φ) Operating Ambient Temperature (TA) Power Supply Voltage (VDD) 2 to 33 MHzNote 1 –40 to +85°C 5.0 V ±10% MHzNote 2 –40 to +85°C 5.0 V ±10% Direct mode, PLL mode 5 to 33 Notes 1. When not using A/D converter 2. When using A/D converter Recommended Oscillator (1) Ceramic resonator connection (TA = –40 to +85°C) (a) µPD703003A, 703004A X1 X2 Rd C1 Manufacturer Kyocera Corporation TDK Murata Mfg. Co., Ltd. Part Number C2 Oscillation Frequency fXX (MHz) Recommended Circuit Constant Oscillation Voltage Range Oscillation Stabilization Time MIN. (V) MAX. (V) (MAX.) TOST (ms) C1 (pF) C2 (pF) Rd (Ω) KBR-5.0MSA/MSB 5.0 33 33 680 4.5 5.5 0.14 KBR-5.0MKC 5.0 On-chip On-chip 680 4.5 5.5 0.14 KBR-5.0MKD 5.0 On-chip On-chip 680 4.5 5.5 0.14 KBR-5.0MKS 5.0 On-chip On-chip 680 4.5 5.5 0.14 PBRC5.00A 5.0 33 33 680 4.5 5.5 0.14 PBRC5.00B 5.0 On-chip On-chip 680 4.5 5.5 0.14 KBR-6.6MSA/MSB 6.6 33 33 — 4.5 5.5 0.10 KBR-6.6MKC 6.6 On-chip On-chip — 4.5 5.5 0.10 KBR-6.6MKD 6.6 On-chip On-chip — 4.5 5.5 0.10 KBR-6.6MKS 6.6 On-chip On-chip — 4.5 5.5 0.10 PBRC6.60A 6.6 33 33 — 4.5 5.5 0.10 PBRC6.60B 6.6 On-chip On-chip — 4.5 5.5 0.10 CCR5.0MC3 5.0 On-chip On-chip — 4.5 5.5 0.18 FCR5.0MC5 5.0 On-chip On-chip — 4.5 5.5 0.16 CCR6.6MC3 6.6 On-chip On-chip — 4.5 5.5 0.17 CSA5.00MG040 5.0 100 100 — 4.5 5.5 0.31 CST5.00MGW040 5.0 On-chip On-chip — 4.5 5.5 0.31 CSA6.60MTZ040 6.6 100 100 — 4.5 5.5 0.30 CST6.60MTW040 6.6 On-chip On-chip — 4.5 5.5 0.30 Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible. 2. Do not cross the wiring with the other signal lines in the area enclosed by the broken lines. 3. Sufficiently evaluate the matching between the µPD703003A or 703004A and the resonator. Data Sheet U13188EJ4V0DS00 15 µPD703003A, 703004A, 703025A (b) µPD703025A X1 X2 Rd C1 Manufacturer TDK Murata Mfg. Co., Ltd. Part Number C2 Oscillation Frequency fXX (MHz) Recommended Circuit Constant Oscillation Voltage Range Oscillation Stabilization Time MIN. (V) MAX. (V) (MAX.) TOST (ms) C1 (pF) C2 (pF) Rd (Ω) CCR4.0MC3 4.0 On-chip On-chip — 4.5 5.5 0.28 CCR5.0MC3 5.0 On-chip On-chip — 4.5 5.5 0.20 CSA4.00MG040 4.0 100 100 — 4.5 5.5 0.20 CST4.00MGW040 4.0 On-chip On-chip — 4.5 5.5 0.20 CSTS0400MG06 4.0 On-chip On-chip — 4.5 5.5 0.16 CSA6.60MTZ040 6.6 100 100 — 4.5 5.5 0.20 CST6.60MTW040 6.6 On-chip On-chip — 4.5 5.5 0.20 CSTS0660MG06 6.6 On-chip On-chip — 4.5 5.5 0.09 Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible. 2. Do not cross the wiring with the other signal lines in the area enclosed by the broken lines. 3. Sufficiently evaluate the matching between µPD703025A and the resonator. (2) External clock input X1 X2 Open High-speed CMOS inverter External clock Cautions 1. Put the high-speed CMOS inverter as close to the X1 pin as possible. 2. Sufficiently evaluate the matching between the µPD703003A, 703004A, or 703025A and the high-speed CMOS inverter. 16 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V) Parameter Input voltage, high Symbol VIH Conditions MIN. Except for X1 and pins listed in Note Note Input voltage, low VIL (1/2) TYP. MAX. Unit 2.2 VDD + 0.3 V 0.8VDD VDD + 0.3 V Except for X1 and pins listed in Note –0.5 +0.8 V Note –0.5 0.2VDD V VDD + 0.5 V +0.6 V Clock input voltage, high VXH X1 0.8VDD Clock input voltage, low VXL X1 –0.5 Schmitt-triggered input Threshold voltage VT + Note, rising edge 3.0 V VT – Note, falling edge 2.0 V Schmitt-triggered input hysteresis width VT+ Output voltage, high VOH Output voltage, low – V T– Note 0.5 V IOH = –2.5 mA 0.7VDD V IOH = –100 µA VDD – 0.4 V VOL IOL = 2.5 mA 0.45 V Input leakage current, high ILIH Input leakage current, low ILIL VI = VDD 10 µA VI = 0 V –10 µA Output leakage current, high ILOH VO = VDD 10 µA Output leakage current, low ILOL VO = 0 V –10 µA Software pull-up resistor R P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3 90 kΩ 15 40 Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/ SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V. 2. φ = Internal system clock frequency Data Sheet U13188EJ4V0DS00 17 µPD703003A, 703004A, 703025A DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V) Parameter Symbol Power µPD703003A, When operating supply 703004A IDD1 current IDD2 In HALT mode Conditions Direct PLL IDD3 In IDD4 modeNote Direct modeNote PLL In IDLE mode modeNote modeNote Direct modeNote PLL modeNote (2/2) MIN. TYP. MAX. Unit 1.9 × φ + 5 2.1 × φ + 17 mA 2.0 × φ + 7 2.2 × φ + 20 mA 1.2 × φ + 5 1.3 × φ + 13 mA 1.3 × φ + 7 1.4 × φ + 15 mA 8 × φ + 300 10 × φ + 500 µA 0.1 × φ + 2 0.2 × φ + 3 mA 2 50 µA STOP mode µPD703025A When operating IDD1 In HALT mode IDD2 In IDLE mode IDD3 In STOP mode IDD4 Direct modeNote 2.5 × φ + 2 2.8 × φ + 16.5 mA PLL modeNote 2.6 × φ + 4 2.9 × φ +19.5 mA 1.3 × φ + 5 1.4 × φ + 13 mA 1.3 × φ + 10 1.4 × φ + 18 mA 8 × φ + 300 10 × φ + 500 µA 0.1 × φ + 2 0.2 × φ + 3 mA Direct PLL modeNote modeNote Direct modeNote PLL modeNote 2 50 µA Note When using A/D converter: φ = 5 to 33 MHz When not using A/D converter: φ = 2 to 33 MHz Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V. The power supply current does not include AVREF1 to AVREF3 or the current that flows across a software pull-up resistor. 2. φ = Internal system clock frequency 18 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Conditions Data retention voltage VDDDR STOP mode Data retention current IDDDR VDD = VDDDR MIN. TYP. 1.5 MAX. Unit 5.5 V –40°C ≤ TA ≤ +50°C 0.2VDDDR 50 µA 50°C < TA ≤ 85°C 0.2VDDDR 200 µA µs Power supply voltage rise time tRVD 200 Power supply voltage fall time tFVD 200 µs Power supply voltage hold time (vs. STOP mode setting) tHVD 0 ms ns STOP mode release signal input time tDREL Note 0 Data retention high-level input voltage VIHDR Note 0.9VDDDR VDDDR V Data retention low-level input voltage VILDR 0 0.1VDDDR V Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/ SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1 Remark TYP. values are reference values for when TA = 25°C and VDD = 5.0 V. STOP mode setting (fifth clock after PSC register is set) VDD VDD VDD VDDDR tHVD RESET (input) NMI (input) (Released at falling edge) tFVD tRVD tDREL VIHDR VIHDR NMI (input) (Released at rising edge) VILDR Data Sheet U13188EJ4V0DS00 19 µPD703003A, 703004A, 703025A AC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V) AC test input waveform (a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/ TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1 VDD 0V 0.8VDD 0.2VDD Point of mesurement 0.8VDD Point of mesurement 2.2 V 0.2VDD (b) Pins other than those listed in (a) above 2.4 V 0.4 V 2.2 V 0.8 V 0.8 V AC test output measurement points 2.2 V 0.8 V Point of mesurement 2.2 V 0.8 V Load condition DUT (Device under testing) CL = 50 pF Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert a buffer or other element to reduce the device’s load capacitance to below 50 pF. 20 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A (1) Clock timing Parameter Symbol X1 input cycle <1> tCYX Conditions MAX. MIN. MAX. 20 Note 1 15 Note 1 ns PLL mode (PLL locked) 200 Note 1 151 Note 1 ns 7 80 tWXH Direct mode PLL mode X1 input low-level width <3> t WXL Direct mode PLL mode X1 input fall time <5> CPU operating frequency – tXR t XF Unit MIN. <2> <4> 33 MHz Version Direct mode X1 input high-level width X1 input rise time 25 MHz Version 6 60 ns ns 7 6 ns 80 60 ns Direct mode 7 7 ns PLL mode 15 10 ns Direct mode 7 7 ns PLL mode 15 10 ns φ Note 2 25 Note 2 33 MHz CLKOUT output cycle <6> tCYK 40 Note 3 30 Note 3 ns CLKOUT input high-level width <7> tWKH 0.5T – 5 0.5T – 5 ns CLKOUT input low-level width <8> tWKL 0.5T – 5 0.5T – 5 ns CLKOUT input rise time <9> tKR 5 5 ns CLKOUT input fall time <10> tKF 5 5 ns 17 ns Delay time from X1↓ to CLKOUT <11> tDXK Direct mode 3 17 3 Notes 1. When using A/D converter: 100 ns When not using A/D converter: 250 ns 2. When using A/D converter: 5 MHz When not using A/D converter: 2 MHz 3. When using A/D converter: 200 ns When not using A/D converter: 500 ns Remark T = tCYK <1> <2> <3> X1 (input) <4> <11> <5> <6> <11> <7> <8> CLKOUT (output) <9> Data Sheet U13188EJ4V0DS00 <10> 21 µPD703003A, 703004A, 703025A (2) Input waveform (a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/ SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/ SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE Parameter Symbol Conditions 25 MHz Version MIN. 33 MHz Version MAX. MIN. Unit MAX. Input rise time <12> tIR2 20 20 ns Input fall time <13> tIF2 20 20 ns VDD 0.8VDD 0.8VDD Input signal 0.2VDD 0V 0.2VDD <13> <12> (b) Pins other than those listed in (a) above Parameter Symbol Conditions 25 MHz Version MIN. 33 MHz Version MAX. MIN. Unit MAX. Input rise time <14> tIR1 10 10 ns Input fall time <15> tIF1 10 10 ns 2.4 V 2.2 V 2.2 V Input signal 0.8 V 0.8 V 0.4 V <15> <14> (3) Output waveform (other than CLKOUT) Parameter Symbol Conditions 25 MHz Version MIN. MAX. 33 MHz Version MIN. Unit MAX. Output rise time <16> tOR 10 10 ns Output fall time <17> tOF 10 10 ns 2.2 V 2.2 V Output signal 0.8 V 0.8 V <16> 22 Data Sheet U13188EJ4V0DS00 <17> µPD703003A, 703004A, 703025A (4) Reset timing Parameter Symbol Conditions 25 MHz Version MIN. RESET high-level width <18> tWRSH RESET low-level width <19> tWRSL When power supply is ON and STOP mode has been released Other than when power supply is ON and STOP mode has been released MAX. 33 MHz Version MIN. Unit MAX. 500 500 ns 500 + TOST 500 + TOST ns 500 500 ns Remark TOST: Oscillation stabilization time <18> <19> RESET (input) Data Sheet U13188EJ4V0DS00 23 µPD703003A, 703004A, 703025A (5) Read timing (1/2) Parameter Symbol Conditions 25 MHz Version 33 MHz Version Unit MIN. MAX. MIN. MAX. Delay time from CLKOUT↑ to address <20> tDKA 3 20 3 20 ns Delay time from CLKOUT↑ to R/W, UBEN, LBEN <78> tDKA2 –2 +13 –2 +13 ns Delay time from CLKOUT↑ to address float <21> tFKA 3 15 3 15 ns Delay time from CLKOUT↓ to ASTB <22> tDKST 3 15 3 15 ns Delay time from CLKOUT↑ to DSTB <23> tDKD 3 15 3 15 ns Data input setup time (to CLKOUT↑) <24> tSIDK 5 5 ns Data input hold time (from CLKOUT↑) <25> tHKID 5 5 ns WAIT setup time (to CLKOUT↓) <26> tSWTK 5 5 ns WAIT hold time (from CLKOUT↓) <27> tHKWT 5 5 ns Address hold time (from CLKOUT↑) <28> tHKA 0 0 ns Address setup time (to ASTB↓) <29> tSAST –40°C ≤ TA ≤ +70°C 0.5T – 10 0.5T – 10 ns 70°C < TA ≤ 85°C 0.5T – 12 0.5T – 12 ns 0.5T – 10 0.5T – 10 ns Address hold time (from ASTB↓) <30> tHSTA Delay time from DSTB↓ to address float <31> tFDA Data input setup time (to address) <32> tSAID Data input setup time (to DSTB↓) <33> tSDID 0 0 ns –40°C ≤ TA ≤ +70°C (2 + n)T – 22 (2 + n)T – 22 ns 70°C < TA ≤ 85°C (2 + n)T – 25 (2 + n)T – 25 ns –40°C ≤ TA ≤ +70°C (1 + n)T – 20 (1 + n)T – 20 ns (1 + n)T – 24 ns 70°C < TA ≤ 85°C (1 + n)T – 24 Delay time from ASTB↓ to DSTB↓ <34> tDSTD 0.5T – 10 0.5T – 10 ns Data input hold time (from DSTB↑) <35> tHDID 0 0 ns Delay time from DSTB↑ to address output <36> tDDA (1 + i)T (1 + i)T ns Delay time from DSTB↑ to ASTB↑ <37> tDDSTH 0.5T – 10 0.5T – 10 ns Delay time from DSTB↑ to ASTB↓ <38> tDDSTL (1.5 + i)T – 10 (1.5 + i)T – 10 ns –40°C ≤ TA ≤ +70°C (1 + n)T – 10 (1 + n)T – 10 ns 70°C < TA ≤ 85°C (1 + n)T – 13 (1 + n)T – 13 ns T – 10 T – 10 ns DSTB low-level width <39> tWDL ASTB high-level width <40> tWSTH WAIT setup time (to address) <41> tSAWT1 <42> tSAWT2 n ≥ 1, –40°C ≤ TA ≤ +70°C 1.5T – 20 1.5T – 20 ns n ≥ 1, 70°C < TA ≤ 85°C 1.5T – 24 1.5T – 24 ns n ≥ 1, –40°C ≤ TA ≤ +70°C (1.5 + n)T – 20 (1.5 + n)T – 20 ns n ≥ 1, 70°C < TA ≤ 85°C (1.5 + n)T – 24 (1.5 + n)T – 24 ns WAIT hold time (from address) <43> tHAWT1 n≥1 (0.5 + n)T <44> tHAWT2 n≥1 (1.5 + n)T WAIT setup time (to ASTB↓) <45> tSSTWT1 n ≥ 1, –40°C ≤ TA ≤ +70°C T – 18 T – 18 ns n ≥ 1, 70°C < TA ≤ 85°C T – 20 T – 20 ns (1 + n)T – 15 (1 + n)T – 15 ns WAIT hold time (from ASTB↓) (0.5 + n)T ns (1.5 + n)T ns <46> tSSTWT2 n≥1 <47> tHSTWT1 n≥1 nT nT ns <48> tHSTWT2 n≥1 (1 + n)T (1 + n)T ns Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function. 3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle. 4. Maintain at least one of the two data input hold times, either tHKID (<25>) or tHDID (<35>). 24 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A (5) Read timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output) <20> <28> A16 to A19 (output) <78> R/W (output) UBEN (output) LBEN (output) <32> <21> AD0 to AD15 (I/O) <24> A0 to A15 (output) D0 to D15 (input) <22> <29> <25> <35> <30> <22> ASTB (output) <40> <37> <23><31> <34> <23> <33> <36> DSTB (output) <38> <39> <45> <26> <27> <26> <27> <47> <46> <48> WAIT (input) <41> <43> <42> <44> Remark Broken lines indicate high impedance. Data Sheet U13188EJ4V0DS00 25 µPD703003A, 703004A, 703025A (6) Write timing (1/2) Parameter Symbol Conditions 25 MHz Version 33 MHz Version Unit MIN. MAX. MIN. MAX. Delay time from CLKOUT↑ to address <20> tDKA 3 20 3 20 ns Delay time from CLKOUT↑ to R/W, UBEN, LBEN <78> tDKA2 –2 +13 –2 +13 ns Delay time from CLKOUT↓ to ASTB <22> tDKST 3 15 3 15 ns Delay time from CLKOUT↑ to DSTB <23> tDKD 3 15 3 15 ns WAIT setup time (to CLKOUT↓) <26> tSWTK 5 5 ns WAIT hold time (from CLKOUT↓) <27> tHKWT 5 5 ns Address hold time (from CLKOUT↑) <28> tHKA 0 0 ns –40°C ≤ TA ≤ +70°C 0.5T – 10 0.5T – 10 ns 70°C < TA ≤ 85°C 0.5T – 12 0.5T – 12 ns Address hold time (from ASTB↓) <30> tHSTA 0.5T – 10 0.5T – 10 ns Delay time from ASTB↓ to DSTB↓ <34> tDSTD 0.5T – 10 0.5T – 10 ns Delay time from DSTB↓ to ASTB↓ <37> tDDSTH 0.5T – 10 0.5T – 10 ns –40°C ≤ TA ≤ +70°C (1 + n)T – 10 (1 + n)T – 10 ns 70°C < TA ≤ 85°C (1 + n)T – 13 (1 + n)T – 13 ns T – 10 T – 10 ns Address setup time (to ASTB↓) DSTB low-level width <29> tSAST <39> tWDL ASTB high-level width <40> tWSTH WAIT setup time (to address) <41> tSAWT1 <42> tSAWT2 WAIT hold time (from address) WAIT setup time (to ASTB↓) n ≥ 1, –40°C ≤ TA ≤ +70°C 1.5T – 20 1.5T – 20 ns n ≥ 1, 70°C < TA ≤ 85°C 1.5T – 24 1.5T – 24 ns n ≥ 1, –40°C ≤ TA ≤ +70°C (1.5 + n)T – 20 (1.5 + n)T – 20 ns n ≥ 1, 70°C < TA ≤ 85°C (1.5 + n)T – 24 (1.5 + n)T – 24 ns <43> tHAWT1 n≥1 (0.5 + n)T (0.5 + n)T ns <44> tHAWT2 n≥1 (1.5 + n)T (1.5 + n)T ns <45> tSSTWT1 n ≥ 1, –40°C ≤ TA ≤ +70°C T – 18 n ≥ 1, 70°C < TA ≤ 85°C WAIT hold time (from ASTB↓) Delay time from CLKOUT↑ to data output T – 18 ns T – 20 T – 20 ns (1 + n)T – 15 (1 + n)T – 15 ns <46> tSSTWT2 n≥1 <47> tHSTWT1 n≥1 nT nT ns <48> tHSTWT2 n≥1 (1 + n)T (1 + n)T ns <49> tDKOD –40°C ≤ TA ≤ +70°C 20 20 ns 70°C < TA ≤ 85°C 23 23 ns 10 10 ns Delay time from DSTB↓ to data output <50> tDDOD Data output hold time (from CLKOUT↑) <51> tHKOD 0 0 ns Data output setup time (to DSTB↑) <52> tSODD (1 + n)T – 15 (1 + n)T – 15 ns Data output hold time (from DSTB↑) <53> tHDOD T – 10 T – 10 ns Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function. 26 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A (6) Write timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output) <20> <28> A16 to A19 (output) <78> R/W (output) UBEN (output) LBEN (output) <49> AD0 to AD15 (I/O) <51> A0 to A15 (output) D0 to D15 (output) <22> <29> <30> <22> ASTB (output) <23> <23> <40> <34> <50> <37> <53> <52> DSTB (output) <39> <45> <26> <27> <26> <27> <47> <46> <48> WAIT (input) <41> <43> <42> <44> Remark Broken lines indicate high impedance. Data Sheet U13188EJ4V0DS00 27 µPD703003A, 703004A, 703025A (7) Bus hold timing (1/2) Parameter Symbol Conditions 25 MHz Version MIN. MAX. 33 MHz Version MIN. Units MAX. HLDRQ setup time (to CLKOUT↓) <54> tSHQK 5 5 ns HLDRQ hold time (from CLKOUT↓) <55> tHKHQ 5 5 ns HLDAK delay time from CLKOUT↑ <56> tDKHA HLDRQ high-level width <57> tWHQH HLDAK low-level width <58> tWHAL 20 20 ns T + 10 T + 10 ns –40°C ≤ TA ≤ +70°C T – 10 T – 10 ns 70°C < TA ≤ 85°C T – 12 Delay time from CLKOUT↑ to bus float <59> tDKF T – 12 20 Delay time from HLDAK↑ to bus output <60> tDHAC –3 Delay time from HLDRQ↓ to HLDAK↓ <61> tDHQHA1 –3 (2n + 7.5)T + 20 Delay time from HLDRQ↑ to HLDAK↑ <62> tDHQHA2 0.5T ns 20 1.5T + 20 0.5T ns ns (2n + 7.5)T + 20 ns 1.5T + 20 ns Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function. 28 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A (7) Bus hold timing (2/2) TH TH TH TH TI CLKOUT (output) <54> <54><55> <57> HLDRQ (input) <56> <56> <61> <62> HLDAK (output) <58> <60> <59> A16 to A19 (output), Note AD0 to AD15 (I/O) D0 to D15 (input or output) ASTB (output) DSTB (output) R/W (output) Note UBEN (output), LBEN (output) Remark Broken lines indicate high impedance. Data Sheet U13188EJ4V0DS00 29 µPD703003A, 703004A, 703025A (8) Interrupt timing Parameter Symbol Conditions 25 MHz Version MIN. MAX. 33 MHz Version MIN. Unit MAX. NMI high-level width <63> tWNIH 500 500 ns NMI low-level width <64> tWNIL 500 500 ns INTPn high-level width <65> tWITH n = 110 to 113, 120 to 123, 130 to 133, 140 to 143 3T + 10 3T + 10 ns INTPn low-level width <66> tWITL n = 110 to 113, 120 to 123, 130 to 133, 140 to 143 3T + 10 3T + 10 ns Remark T = tCYK <63> <64> <65> <66> NMI (input) INTPn (input) Remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143 30 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A (9) CSI timing (1/2) (a) Master mode (i) Timing of CSI0 to CSI2 Parameter Symbol Conditions 25 MHz Version MIN. MAX. 33 MHz Version MIN. Unit MAX. SCKn cycle <67> tCYSK1 Output 160 120 ns SCKn high-level width <68> tWSKH1 Output 0.5tCYSK1 – 20 0.5tCYSK1 – 20 ns SCKn low-level width <69> tWSKL1 Output 0.5tCYSK1 – 20 0.5tCYSK1 – 20 ns SIn setup time (to SCKn↑) <70> tSSISK1 30 30 ns SIn hold time (from SCKn↑) <71> tHSKSI1 0 0 ns SOn output delay time (from SCKn↓) <72> tDSKSO1 18 SOn output hold time (from SCKn↑) <73> tHSKSO1 0.5tCYSK1 – 5 18 0.5tCYSK1 – 5 ns ns Remark n = 0 to 2 (ii) Timing of CSI3 Parameter Symbol Conditions 25 MHz Version MIN. SCK3 cycle <67> tCYSK3 Output SCK3 high-level width <68> tWSKH3 Output SCK3 low-level width <69> tWSKL3 Output SI3 setup time (to SCK3↑) SI3 hold time (from SCK3↑) MAX. MIN. Unit MAX. 500 500 ns 0.5tCYSK3 – 70 0.5tCYSK3 – 70 ns 0.5tCYSK3 – 70 0.5tCYSK3 – 70 ns <70> tSSISK3 100 100 ns <71> tHSKSI3 50 50 ns SO3 output delay time (from SCK3↓) <72> tDSKSO3 SO3 output hold time (from SCK3↑) <73> tHSKSO3 RL = 1.5 kΩ CL = 50 pF 33 MHz Version RL = 1.5 kΩ CL = 50 pF 150 0.5tCYSK3 – 5 150 0.5tCYSK3 – 5 ns ns Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines. (b) Slave mode (i) Timing of CSI0 to CSI2 Parameter Symbol Conditions 25 MHz Version MIN. MAX. 33 MHz Version MIN. Unit MAX. SCKn cycle <67> tCYSK2 Input 160 120 ns SCKn high-level width <68> tWSKH2 Input 50 30 ns SCKn low-level width <69> tWSKL2 Input 50 30 ns SIn setup time (to SCKn↑) <70> tSSISK2 10 10 ns SIn hold time (from SCKn↑) <71> tHSKSI2 10 SOn output delay time (from SCKn↓) <72> tDSKSO2 10 30 SOn output hold time (from SCKn↑) <73> tHSKSO2 tWSKH2 ns 30 tWSKH2 ns ns Remark n = 0 to 2 Data Sheet U13188EJ4V0DS00 31 µPD703003A, 703004A, 703025A (9) CSI timing (2/2) (ii) Timing of CSI3 Parameter Symbol Conditions 25 MHz Version MIN. MAX. 33 MHz Version MIN. Unit MAX. SCK3 cycle <67> tCYSK4 Input 500 500 ns SCK3 high-level width <68> tWSKH4 Input 180 180 ns SCK3 low-level width <69> tWSKL4 Input 180 180 ns SI3 setup time (to SCK3↑) <70> tSSISK4 100 100 ns SI3 hold time (from SCK3↑) <71> tHSKSI4 SO3 output delay time (from SCK3↓) <72> tDSKSO4 SO3 output hold time (from SCK3↑) <73> tHSKSO4 50 RL = 1.5 kΩ CL = 50 pF 50 150 tWSKH4 ns 150 tWSKH4 Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines. <67> <69> <68> SCKn (I/O) <70> SIn (Input) <71> Input data <72> <73> SOn (output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0 to 3 32 Data Sheet U13188EJ4V0DS00 ns ns µPD703003A, 703004A, 703025A (10) RPU timing Parameter Symbol Conditions 25 MHz Version MIN. MAX. 33 MHz Version MIN. Unit MAX. TI1n high-level width <74> tWTIH 3T + 10 3T + 10 ns TI1n low-level width <75> tWTIL 3T + 10 3T + 10 ns TCLR1n high-level width <76> tWTCH 3T + 10 3T + 10 ns TCLR1n low-level width <77> tWTCL 3T + 10 3T + 10 ns Remark T = tCYK <74> <75> <76> <77> TI1n (input) TCLR1n (input) Remark n = 1 to 4 Data Sheet U13188EJ4V0DS00 33 µPD703003A, 703004A, 703025A A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V) Parameter Resolution Overall Symbol — errorNote 1 Quantization error — 4.5 V ≤ AVREF1 ≤ AVDD — 3.5 V ≤ AVREF1 ≤ AVDD tCONV Sampling time tSAMP errorNote 1 Full-scale errorNote 1 Non-linearity errorNote 1 Analog input voltageNote 2 25 MHz Version 33 MHz Version Unit MIN. TYP. MAX. MIN. TYP. MAX. 10 10 10 10 10 10 bit ±0.4 %FSR ±0.7 ±0.7 %FSR ±1/2 ±1/2 LSB ±0.4 — Conversion time Zero-scale Conditions 4.5 V ≤ AVREF1 ≤ AVDD 48 3.5 V ≤ AVREF1 ≤ AVDD 48 60 tCYK 4.5 V ≤ AVREF1 ≤ AVDD 8 10 tCYK 3.5 V ≤ AVREF1 ≤ AVDD 8 10 tCYK 60 tCYK — 4.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±3.5 ±1.5 ±3.5 LSB — 3.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±4.5 ±1.5 ±4.5 LSB — 4.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±2.5 ±1.5 ±2.5 LSB — 3.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±4.5 ±1.5 ±4.5 LSB — 4.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±2.5 ±1.5 ±2.5 LSB — 3.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±4.5 ±1.5 ±4.5 LSB AVDD + 0.3 V VIAN –0.3 Reference voltage AVREF1 3.5 AVDD V AVREF1 current AIREF1 1.2 3.0 1.2 3.0 mA AIDD 2.3 6.0 2.3 6.0 mA AVDD power supply current AVDD + 0.3 –0.3 AVDD 3.5 Notes 1. Excludes quantization error. 2. When VIAN = 0, the conversion result becomes 000H. When 0 < VIAN < AVREF1, conversion has 10-bit resolution. When AVREF1 ≤ VIAN ≤ AVDD, the conversion result becomes 3FFH. 34 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V) Parameter Symbol Conditions 25 MHz Version 33 MHz Version Unit MIN. TYP. MAX. MIN. TYP. MAX. 8 8 8 8 8 8 bit Resolution — Overall error — Load condition: 2 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 0.8 0.8 % — Load condition: 2 MΩ, 30 pF AVREF2 = 0.75VDD AVREF3 = 0.25VDD 1.0 1.0 % — Load condition: 4 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 0.6 0.6 % — Load condition: 4 MΩ, 30 pF AVREF2 = 0.75VDD AVREF3 = 0.25VDD 0.8 0.8 % Settling time — Load condition: 2 MΩ, 30 pF Output resistance RO 10 10 8 8 µs kΩ AVREF2 input voltage AVREF2 0.75VDD VDD 0.75VDD VDD V AVREF3 input voltage AVREF3 0 0.25VDD 0 0.25VDD V Resistance between AVREF2 and AVREF3 RAIREF DACS0, DACS1 = 55H 2 Data Sheet U13188EJ4V0DS00 4 2 4 kΩ 35 µPD703003A, 703004A, 703025A 4. PACKAGE DRAWING 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D Q R 26 25 100 1 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 16.00±0.20 B 14.00±0.20 C 14.00±0.20 D 16.00±0.20 F 1.00 G 1.00 H 0.22 +0.05 −0.04 I J 0.08 0.50 (T.P.) K 1.00±0.20 L 0.50±0.20 M 0.17 +0.03 −0.07 N 0.08 P 1.40±0.05 Q 0.10±0.05 R 3° +7° −3° S 1.60 MAX. S100GC-50-8EU, 8EA-2 36 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A 5. RECOMMENDED SOLDERING CONDITIONS The µPD703003A, 703004A, and 703025A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representatives. Table 5-1. Soldering Conditions µPD703003AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703003AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703004AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703004AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703025AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703025AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) IR35-107-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) VP15-107-2 Partial heating Pin temperature: 300°C max., Time 3 seconds max. (per pin row) — Note After opening a dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U13188EJ4V0DS00 37 µPD703003A, 703004A, 703025A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. RELATED DOCUMENTS µPD703003 Data Sheet (U12261E) µPD70F3003 Data Sheet (U12036E) µPD70F3003A, 70F3025A Data Sheet (U13189E) The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V850 Family and V853 are trademarks of NEC Corporation. 38 Data Sheet U13188EJ4V0DS00 µPD703003A, 703004A, 703025A Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. 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Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U13188EJ4V0DS00 39 µPD703003A, 703004A, 703025A The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of March, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. 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