DATA SHEET MOS INTEGRATED CIRCUIT µPD70433 V55PITM 16-BIT MICROPROCESSOR DESCRIPTION The µPD70433 (V55PI) is a microprocessor in which a 16-bit CPU, RAM, serial interface, parallel interface, A/D converter, timers, DMA controller, interrupt controller, etc., are integrated in a single chip. The V55PI is software-compatible with the µPD70320 and 70330 (V25TM and V35TM) single-chip microcontrollers. The V55PI provides a migration path from the V25. It offers higher-level functions and higher performance, and is particularly suitable for control of data processing systems associated with mechanical control, including printer and facsimile. Detailed functions are described in the following user’s manuals, which should be read when carrying out design work. • V55PI User’s Manual Hardware • V55PI User’s Manual Instruction : U10514E : U10231E FEATURES • Internal 16-bit architecture, selectable external data bus width (16/8 bits) • Software compatible with V20TM and V30TM (native mode) and V25 and V35 (includes additional instructions) • Minimum instruction cycle: 160 ns/12.5 MHz (external 25 MHz) 125 ns/16 MHz (external 32 MHz) • Address space: 16M bytes: 1-Mbyte basic memory space 16-Mbyte extended memory space • Register file space (in on-chip RAM) : 512 bytes/16 register banks • I/O space : 64K bytes • Automatic wait control with memory space divided in variable sizes (max. 6 blocks) • I/O line (input ports: 11 bits, input/output ports: 42 bits) • DMA controller (DMAC): Max. 4-channel configuration possible • Four DMA transfer modes (single transfer, demand release, single step, burst) • Intelligent DMA modes 1 and 2 • Serial interface: 2 channels • Asynchronous mode (UART) or clocked mode (CSI) selectable • Parallel interface: 8 bits • Centronics data input/output and general-purpose data input/output • A/D converter (8 bits): 4 channels • Real-time output port: 4 bits × 2 channels or 8 bits × 1 channel • PMW (Pulse Width Modulation) output function : 8 bits The information in this document is subject to change without notice. Document No. U11775EJ4V0DS00 (4th edition) Previous No. IC-8257 Date Published November 1996 P Printed in Japan The mark shows major revised points. © 1995 µPD70433 • Interrupt controller • Programmable priority (4 levels) • Three interrupt servicing methods Vectored interrupt function, register bank switching function, macro service function • 16-bit timer: 4 channels • Watchdog timer function • Software interval timer (16 bits) • Address field wait insertion function and RAS/CAS switchover timing generation function • DRAM and pseudo-SRAM refresh functions • Standby functions (STOP mode, HALT mode) • On-chip clock generator APPLICATIONS • Control of data processing systems using serial or parallel communication (Data processing terminals, printer, G3 facsimile, etc.) ORDERING INFORMATION 2 Part Number Package µPD70433GD-12-5BB µPD70433GD-16-5BB µPD70433R-12 µPD70433R-16 µPD70433GJ-12-3EB µPD70433GJ-16-3EB 120-pin 120-pin 132-pin 132-pin 120-pin 120-pin Maximum Operating Frequency (MHz) plastic QFP (28 × 28 mm) plastic QFP (28 × 28 mm) ceramic PGA ceramic PGA plastic QFP (fine pitch) (20 × 20 mm) plastic QFP (fine pitch) (20 × 20 mm) 12.5 16 12.5 16 12.5 16 µPD70433 PIN CONFIGURATION (TOP VIEW) (1) 120-Pin Plastic QFP (28 × 28 mm), 120-pin plastic QFP (fine pitch) (20 × 20 mm) OPEN DEX RAS IORD IOWR RD WRL WRH ASTB IC (L) D8/D16 GND VDD A23 A22 A21 A20 A19 A18 A17 A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 µPD70433GD-xx-5BB µPD70433GJ-xx-3EB 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 1 90 2 89 3 88 4 87 5 86 6 85 7 84 8 83 9 82 10 81 11 80 12 79 13 78 14 77 15 76 16 75 17 74 18 73 19 72 20 71 21 70 22 69 23 68 24 67 25 66 26 65 27 64 28 63 29 62 30 61 313233343536373839404142434445464748495051525354555657585960 AD6 AD5 AD4 AD3 AD2 AD1 AD0 IC (H) GND VDD TCE1 TCE0 DMAAK1 DMAAK0 P81/DMARQ1 P80/DMARQ0 VDD P77/RTPT7 P76/RTPT6 P75/RTPT5 P74/RTPT4 P73/RTPT3 P72/RTPT2 P71/RTPT1 P70/RTPT0 GND AVDD AVREF P63/ANI3 P62/ANI2 P20/PWM P21/TO00 P22/TO01 P23/TO20 P24/TO21 P25/TO30 P30/TXD0/SB0/SO0 P31/RXD0/SB1/SI0 P32/TXC/SCK0 P33/CTS0 P34/TXD1/SO1 P35/RXD1/SI1 P36/SCK1/CTS1 VDD P40/PD0 P41/PD1 P42/PD2 P43/PD3 P44/PD4 P45/PD5 P46/PD6 P47/PD7 GND P50/DATASTB P51/ACK P52/BUSY VDD AVSS P60/ANI0 P61/ANI1 VDD BUSLOCK HLDAK HLDRQ READY POLL CLKOUT RESET WDTOUT VDD X1 X2 GND REFRQ P00 P01 P02 P03 P04 P05 P06 P07 GND P10/NMI P11/INTP0 P12/INTP1 P13/INTP2 P14/INTP3/TI P15/INTP4 P16/INTP5 Remark IC: Internally Connected Notes 1. The IC (H) pin should be connected to VDD with an external resistor (1 to 10 kΩ). 2. The IC (L) pin should be connected to GND with an external resistor (1 to 10 kΩ). 3. No connection should be made to the OPEN pin. 3 µPD70433 (2) 132-Pin Ceramic PGA µPD70433R-xx Bottom View Top View 14 13 12 11 10 9 8 7 Locator Pin 6 5 4 3 2 1 P N M L K J H G F E D C B A A B C D E F G H J K L M N P Signal Name Port Index Mark Remark The locator pin is not included in the pin count. No. 4 Signal Nane Port No. Signal Name Port No. A1 ANI1 P61 B5 PD7 P47 C9 CTS0 P33 A2 AVSS –– B6 PD5 P45 C10 TO30 P25 A3 ACK P51 B7 PD2 P42 C11 TO00 P21 A4 DATASTB P50 B8 PD0 P40 C12 NC A5 PD6 P46 B9 RXD1/SI1 P35 C13 INTP4 P15 A6 PD4 P44 B10 RXD0/SB1/SI0 P31 C14 INTP0 P11 A7 PD1 P41 B11 TO21 P24 D1 RTPT2 P72 A8 NC –– B12 TO01 P22 D2 GND –– A9 SCK1/CTS1 P36 B13 NC –– D3 ANI3 P63 A10 TXD1/SO1 P34 B14 INTP3/TI P14 D12 INTP5 P16 A11 TXC/SCK0 P32 C1 RTPT1 P71 D13 INTP2 P13 A12 TXD0/SB0/SO0 P30 C2 AVREF –– D14 NMI P10 A13 TO20 P23 C3 NC –– E1 RTPT5 P75 A14 PWM P20 C4 NC –– E2 RTPT3 P73 B1 AVDD –– C5 VDD –– E3 RTPT0 P70 B2 ANI2 P62 C6 GND –– E12 INTP1 P12 B3 ANI0 P60 C7 PD3 P43 E13 GND B4 BUSY P52 C8 VDD –– E14 –– –– –– P06 µPD70433 No. Signal Nane Port No. Signal Name Port No. Signal Name Port F1 RTPT7 P77 K3 AD2 ––– N3 AD9 ––– F2 RTPT6 P76 K12 POLL ––– N4 AD11 ––– F3 RTPT4 P74 K13 WDTOUT ––– N5 AD14 ––– X1 ––– N6 A18 ––– F12 ––– P07 K14 F13 ––– P05 L1 AD0 ––– N7 A21 ––– F14 ––– P04 L2 AD3 ––– N8 A23 ––– G1 NC ––– L3 AD6 ––– N9 D8/D16 ––– G2 DMARQ0 P80 L12 BUSLOCK ––– N10 ASTB ––– G3 VDD ––– L13 READY ––– N11 IOWR ––– G12 ––– P03 L14 RESET ––– N12 DEX ––– G13 ––– P02 M1 AD1 ––– N13 VDD ––– G14 ––– P01 M2 AD5 ––– N14 HLDRQ ––– H1 DMARQ1 P81 M3 NC ––– P1 AD7 ––– H2 DMAAK0 ––– M4 AD8 ––– P2 AD10 ––– H3 DMAAK1 ––– M5 AD12 ––– P3 AD13 ––– H12 REFRQ ––– M6 A16 ––– P4 AD15 ––– P00 M7 A20 ––– P5 A17 ––– NC ––– M8 VDD ––– P6 A19 ––– J1 TCE0 ––– M9 WRH ––– P7 NC ––– J2 TCE1 ––– M10 IORD ––– P8 A22 ––– J3 GND ––– M11 NC ––– P9 GND ––– J12 VDD ––– M12 NC ––– P10 IC (L) ––– J13 X2 ––– M13 HLDAK ––– P11 WRL ––– J14 GND ––– M14 CLKOUT ––– P12 RD ––– K1 VDD ––– N1 AD4 ––– P13 RAS ––– K2 IC (H) ––– N2 NC ––– P14 OPEN ––– H13 H14 Remark ––– IC: Internally Connected NC: Non-Connection Notes 1. The IC (H) pin should be connected to VDD with an external resistor (1 to 10 kΩ). 2. The IC (L) pin should be connected to GND with an external resistor (1 to 10 kΩ). 3. No connection should be made to the OPEN pin. 5 X1 X2 AVSS AVREF AVDD 8 ANI0–ANI3 BUSY ACK DATASTB PD0–PD7 CTS1/SCK1 TXD1/SO1 RXD1/SI1 CTS0 TXC/SCK0 RXD0/SB1/SI0 ALU TXD0/SB0/SO0 GND GENERAL REGISTERS & DATA MEMORY 512 BYTES 4 RESET SYSTEM CONTROL MICRO SEQUENCE CONTROL UART/CSI UART/CSI PIU INTERNAL BLOCK DIAGRAM 6 EXU VDD CLKOUT 8-BIT A/D MICRO ROM ASTB READY RD WRH WRL IORD BCU PREFETCH QUEUE 6 BYTES DMA request IOWR RAS DEX D8/D16 BUSLOCK POLL BUS CONTROL & PREFETCH CONTROL TIMER/ COUNTER UNIT PWM UNIT HLDRQ TCE1 • PWM • TO00 • TO20 • TO03 • WDTOUT • TO01 • TO21 µPD70433 DMARQ1 DMAAK1 DMAC • INTP0 • INTP1 • INTP2 • INTP3/TI • INTP4 • INTP5 NMI DMAAK0 4 6 AD0–AD15 DMARQ0 4 RTP0–RTP3 4 A16–A23 2 8 4 3 8 7 6 7 8 RTP4–RTP7 REFRQ RTOP PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8 WDT HLDAK TCE0 PORT PROGRAMMABLE INTERRUPT CONTROLLER µPD70433 CONTENTS 1. PIN FUNCTIONS ....................................................................................................................................... 10 1.1 LIST OF PIN FUNCTION .................................................................................................................................... 10 1.1.1 Port Pins ................................................................................................................................................ 10 1.1.2 Non-Port Pins ........................................................................................................................................ 11 2. BLOCK CONFIGURATION ....................................................................................................................... 14 2.1 BUS CONTROL UNIT (BCU) ............................................................................................................................. 14 2.2 2.3 EXECUTION UNIT (EXU) ................................................................................................................................... 14 INTERRUPT CONTROLLER (INTC) ................................................................................................................. 14 2.4 2.5 DMA CONTROLLER (DMAC) ........................................................................................................................... 14 UART/CLOCKED SERIAL INTERFACE (UART/CSI) ...................................................................................... 14 2.6 2.7 PARALLEL INTERFACE UNIT (PIU) ................................................................................................................ 14 A/D CONVERTER UNIT (8-BIT A/D) ................................................................................................................ 14 2.8 2.9 TIMER/COUNTER UNIT (TCU) ......................................................................................................................... 14 PWM (PULSE WIDTH MODULATION) UNIT (PWM) ....................................................................................... 14 2.10 2.11 WATCHDOG TIMER (WDT) .............................................................................................................................. 14 PORTS (PORT) ................................................................................................................................................... 14 2.12 2.13 REAL-TIME OUTPUT PORT (RTOP) ................................................................................................................ 14 CLOCK GENERATOR (CG) .............................................................................................................................. 15 2.14 SOFTWARE INTERVAL TIMER (SIT) .............................................................................................................. 15 3. CPU FUNCTIONS ....................................................................................................................................... 16 3.1 FEATURES .......................................................................................................................................................... 16 3.2 REGISTERS ......................................................................................................................................................... 17 3.2.1 Register Banks ...................................................................................................................................... 17 3.2.2 3.2.3 General Registers (AW, BW, CW, DW) .............................................................................................. 19 Pointers (SP, BP) and Index Registers (IX, IY)................................................................................. 20 3.2.4 3.2.5 Segment Registers (PS, SS, DS0, DS1) ............................................................................................. 20 Extended Segment Registers (DS2, DS3) ......................................................................................... 21 3.3 3.2.6 Special Function Registers (SFR) ...................................................................................................... 22 PROGRAM COUNTER (PC) .............................................................................................................................. 23 3.4 3.5 PROGRAM STATUS WORDS (PSW) ............................................................................................................... 23 MEMORY SPACE ............................................................................................................................................... 24 3.6 3.7 3.5.1 3.5.2 Basic Memory Space ........................................................................................................................... 24 Extended Memory Space ..................................................................................................................... 25 3.5.3 3.5.4 Special Function Register Area .......................................................................................................... 26 Vector Table Area ................................................................................................................................. 34 REGISTER FILE SPACE ..................................................................................................................................... 36 I/O SPACE .......................................................................................................................................................... 38 4. BUS CONTROL FUNCTIONS .................................................................................................................... 39 4.1 4.2 WAIT FUNCTION ............................................................................................................................................... 39 REFRESH FUNCTION ........................................................................................................................................ 41 4.2.1 4.2.2 Refresh Mode Register (RFM)............................................................................................................. 41 Wait Control in Refresh Cycle ............................................................................................................ 41 4.2.3 Refresh Address ................................................................................................................................... 41 7 µPD70433 5. INTERRUPT FUNCTIONS ......................................................................................................................... 42 5.1 5.2 FEATURES ......................................................................................................................................................... 42 INTERRUPT RESPONSE METHODS ............................................................................................................... 45 5.2.1 5.2.2 Vectored Interrupts .............................................................................................................................. 45 Register Bank Switching Function .................................................................................................... 46 5.2.3 Macro Service Function ....................................................................................................................... 47 6. DMA FUNCTION (DMA CONTROLLER) ..................................................................................................48 6.1 FEATURES .......................................................................................................................................................... 48 7. SERIAL INTERFACE FUNCTIONS ...........................................................................................................50 7.1 FEATURES .......................................................................................................................................................... 50 7.2 7.3 PROTOCOLS ....................................................................................................................................................... 50 UART ................................................................................................................................................................... 51 7.4 7.3.1 Features ................................................................................................................................................. 51 CLOCKED SERIAL INTERFACE (CSI) ............................................................................................................... 52 7.4.1 Features ................................................................................................................................................. 52 8. PARALLEL INTERFACE FUNCTIONS .....................................................................................................53 8.1 FEATURES .......................................................................................................................................................... 53 9. TIMER FUNCTION ..................................................................................................................................... 55 9.1 9.2 FEATURES .......................................................................................................................................................... 55 TIMER UNIT CONFIGURATION ....................................................................................................................... 55 9.3 REAL-TIME OUTPUT PORT FUNCTION .......................................................................................................... 57 9.3.1 Real-Time Output Port Configuration ................................................................................................ 57 9.3.2 Real-Time Output Port Operation ...................................................................................................... 59 10. PWM UNIT .................................................................................................................................................. 61 10.1 FEATURES .......................................................................................................................................................... 61 10.2 PWM UNIT CONFIGURATION ......................................................................................................................... 61 11. WATCHDOG TIMER FUNCTION .............................................................................................................. 63 11.1 FEATURES .......................................................................................................................................................... 63 11.2 WATCHDOG TIMER CONFIGURATION AND OPERATION .......................................................................... 63 12. A/D CONVERTER FUNCTION .................................................................................................................. 64 12.1 FEATURES .......................................................................................................................................................... 64 13. STANDBY FUNCTION ............................................................................................................................... 66 13.1 13.2 HALT MODE ....................................................................................................................................................... 66 STOP MODE ....................................................................................................................................................... 67 14. CLOCK GENERATOR ............................................................................................................................... 68 14.1 8 CLOCK GENERATOR CONFIGURATION AND OPERATION ......................................................................... 68 µPD70433 15. SOFTWARE INTERVAL TIMER FUNCTION ........................................................................................... 70 15.1 SOFTWARE INTERVAL TIMER CONFIGURATION ........................................................................................ 70 16. CODEC INSTRUCTION.............................................................................................................................. 71 16.1 FEATURES .......................................................................................................................................................... 71 16.2 16.3 MEMORY MAP ................................................................................................................................................... 74 PROCESSING FLOW ......................................................................................................................................... 76 17. INSTRUCTION SET .................................................................................................................................... 78 17.1 17.2 INSTRUCTIONS NEWLY ADDED TO V20/V30 AND V25/V35 ..................................................................... 78 INSTRUCTION SET OPERATIONS ................................................................................................................... 80 17.3 INSTRUCTION SET TABLE ............................................................................................................................. 105 18. ELECTRICAL SPECIFICATIONS ............................................................................................................128 19. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ................................................................... 158 20. PACKAGE DRAWINGS ........................................................................................................................... 159 21. RECOMMENDED SOLDERING CONDITIONS ...................................................................................... 162 9 µPD70433 1. PIN FUNCTIONS 1.1 LIST OF PIN FUNCTIONS 1.1.1 Port Pins Pin Name P00 to P07 Input/Output Input/output Function Alternate Function Port 0 Input/output specifiable bit-wise 8-bit input/output port P10* NMI P11 INTP0 P12 P13 INTP1 Input Port 1 7-bit input port INTP2 P14 INTP3/TI P15 INTP4 P16 INTP5 P20 PWM P21 TO00 Port 2 Input/output specifiable bit-wise 6-bit input/output port P22 P23 TO01 TO20 P24 TO21 P25 TO30 P30 TxD0/SB0/SO0 P31 RxD0/SB1/SI0 P32 Input/output P33 Port 3 Input/output specifiable bit-wise 7-bit input/output port TxC/SCK0 CTS0 P34 TxD1/SO1 P35 RxD1/SI1 P36 CTS1/SCK1 Port 4 Input/output specifiable bit-wise 8-bit input/output port P40 to P47 P50 Port 5 Input/output specifiable bit-wise 3-bit input/output port P51 P52 P60 to P63 Input P70 to P77 Input/output P80 P81 * 10 PD0 to PD7 DATASTB ACK BUSY Port 6 Input/output specifiable bit-wise 4-bit input/output port ANI0 to ANI3 Port 7 Input/output specifiable bit-wise 8-bit input/output port RTP0 to RTP7 Port 8 Input/output specifiable bit-wise 2-bit input/output port Unusable as general-purpose port (non-maskable interrupt) DMARQ0 DMARQ1 µPD70433 1.1.2 Non-Port Pins (1) Bus control pins Pin Name Input/ Output ASTB External bus cycle address strobe signal output in external bus RD External memory cycle data read strobe signal output in external bus Output WRL External memory cycle lower byte data write strobe signal output in external bus WRH External memory cycle upper byte data write strobe signal output in external bus READY Input DEX Alternate Function Function External bus cycle ready signal input in external bus External bus cycle upper byte data enable signal output Output RAS D8/D16 BUSLOCK DRAM low address latch timing signal output Input Output POLL External bus data bus width selection signal input ––– External bus bus lock signal output Input of POLL signal (sampled in POLL instruction execution) Input HLDRQ External bus hold request signal input HLDAK External bus hold acknowledge signal output Output REFRQ AD0 to AD15 A16 to A23 Refresh pulse signal output 3–state input/output 3–state output IORD External bus cycle address/data multiplex signal input/output in external bus External bus cycle address signal output in external bus External I/O cycle data read strobe signal output Output IOWR External I/O cycle data write strobe signal output DMARQ0 DMA request signal input (channel 0) P80 DMARQ1 DMA request signal input (channel 1) P81 DMAAK0 DMA acknowledge signal output (channel 0) Input DMAAK1 DMA acknowledge signal output (channel 1) Output ––– TCE0 DMA termination signal output (channel 0) TCE1 DMA termination signal output (channel 1) 11 µPD70433 (2) Other pins Pin Name Input/ Output GND Alternate Function Function GND potential Positive power supply VDD ––– AVSS A/D converter GND potential AVDD A/D converter analog power supply AVREF A/D converter reference voltage input ––– RESET Input System reset signal input ––– Connection pins of crystal resonator/ceramic resonator for system clock generation. In case of external clock supply, input to X1 and leave X2 open. X1 X2 CLKOUT Internal system clock ø output Output WDTOUT Watchdog timer overflow signal output NMI Non-maskable interrupt request input *1 P10 INTP0 P11 INTP1 P12 INTP2 P13 Input External interrupt request input *2 INTP3 P14/TI INTP4 P15 INTP5 P16 TI External event clock input P14/INTP3 PWM PWM output P20 Timer unit output P21 to P25 UART transmission data output P30/SB0/SO0 UART reception data input P31/SB1/SI0 UART transmission clock output P32/SCK0 TO00, TO01, TO20, TO21, TO30 Output TXD0 RXD0 Input T XC Output CTS0 P33 Input UART transmission enable signal input CTS1 P36/SCK1 SB0 P30/TXD0/SO0 Input/output SB1 SBI transmission/reception data input/output P31/RXD0/SI0 * 1. Because NMI interrupt is unmaskable, NMI interrupt is always initiated by detecting a valid edge (when reading from port 1, the pin level is read). 2. By masking or disabling (IE = 0) these interrupts, these pins can be used as general–purpose input/output ports, respectively. 12 µPD70433 Pin Name Input/ Output Alternate Function Function P30/TXD0/SB0 SO0 Output CSI transmission data output SO1 P34/TXD1 SI0 P31/RXD0/SB1 Input CSI reception data input SI1 P35/RXD1 SCK0 P32/TXC CSI serial clock input/output SCK1 P36/CTS1 PD0 to PD7 Parallel interface — Data input/output P40 to P47 DATASTB Parallel interface — Data strobe signal P50 ACK Parallel interface — Acknowledge signal P51 BUSY Parallel interface — Busy signal P52 Analog input signal to A/D converter P60 to P63 Real-time output port P70 to P77 Input/output ANI0 to ANI3 RTP0 to RTP7 Input Output 13 µPD70433 2. BLOCK CONFIGURATION 2.1 BUS CONTROL UNIT (BCU) The BCU performs control of the main bus. The BCU starts the necessary internal/external bus cycle on the basis of the physical address obtained from the execution unit (EXU). 2.2 EXECUTION UNIT (EXU) The EXU controls address calculation, arithmetic and logical operations, data transfer, etc., by means of a microprogram (firmware for controlling the microsequencer on the basis of decoded op code). The EXU contains 512 bytes of RAM (corresponding to the register file space). 2.3 INTERRUPT CONTROLLER (INTC) The INTC services hardware interrupt requests generated by on-chip peripheral hardware and interrupt requests generated externally with vectored interrupts, bank switching, or macro service. It can also control the programmable 4level interrupt priority order, and can also perform multiprocessing control for interrupt. 2.4 DMA CONTROLLER (DMAC) The DMAC is a general-purpose DMA controller, capable of handling the 16M-byte memory space in a linear fashion. Operating modes comprise memory-to-memory transfer mode, intelligent DMA (ring buffer method and counter control method) mode, next address specification mode, and 2-channel operation. 2.5 UART/CLOCKED SERIAL INTERFACE (UART/CSI) This block supports the asynchronous interface (UART) in which data synchronization is achieved by means of start/ stop bits, and the clocked serial interface (CSI), allowing either to be used. For the clocked serial interface there is a further choice of serial bus interface mode (SBI) or 3-wire serial I/O mode. 2.6 PARALLEL INTERFACE UNIT (PIU) This performs input/output using strobe signal synchronization in 8-bit units, and supports the Centronics interface and general-purpose parallel data communication functions. 2.7 A/D CONVERTER UNIT (8-BIT A/D) This is an A/D converter with 4 analog inputs, and provided with 4 A/D conversion result registers. 2.8 TIMER/COUNTER UNIT (TCU) The timer/counter unit incorporates a 16-bit timer/counter, and can be used as an interval timer, free-running counter, or event counter. 2.9 PWM (PULSE WIDTH MODULATION) UNIT (PWM) An 8-bit precision PWM (pulse width modulation) signal output function. 2.10 WATCHDOG TIMER (WDT) The WDT incorporates an 8-bit watchdog timer for detection of inadvertent program looping, system errors, etc. The WDTOUT pin is provided to give external notification of the generation of watchdog timer interrupts. 2.11 PORTS (PORT) 53 port pins are provided, allowing port pin and control pin functions to be selected. 2.12 REAL-TIME OUTPUT PORT (RTOP) This is a real-time output port which uses an interrupt from timer 0 as a trigger. It can output the contents of the 8-bit buffer register at programmable intervals in 4-bit or 8-bit units. 14 µPD70433 2.13 CLOCK GENERATOR (CG) The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1 and X2 pins and supplies it as the CPU operating clock. 2.14 SOFTWARE INTERVAL TIMER (SIT) The SIT incorporates a 16-bit software interval timer as a software timer function and watch function timer. Interval interrupts can be set by input clock (count clock) selection and software timer/counter compare register setting. 15 µPD70433 3. CPU FUNCTIONS The CPU of the V55PI is software upword compatible with the V20 and V30 (native mode), and the V25 and V35. 3.1 FEATURES • Software upward compatible with V20 & V30 (native mode) and V25 & V35 (includes additional instructions) • Minimum instruction cycle: 160 ns/12.5 MHz (external 25 MHz clock) 125 ns/16 MHz (external 32 MHz clock) • Address space: 16M bytes 1M-byte basic memory (program) space 16M-byte extended memory (data) space • Register file space (in on-chip RAM): 512 bytes/16 register banks • I/O space: 64K bytes • Register configuration (compared with V20/V30 and V25/V35) Item V20, V30 V25, V35 V55PI Extended segment register None None DS2, DS3 Register bank None 8 banks (in memory space) 16 banks (in register file space) MD None None Register bank flags None RB0 to RB2 RB0 to RB3 Input/output instruction trap flag None IBRK IBRK User flag None F0, F1 None None 240 bytes (memory mapping onto FFF00H to FFFEFH) 496 bytes (memory mapping onto FFE00H to FFFEFH) Mode flag PSW Special function register area • Internal 16-bit architecture, switchable external data bus width (16/8 bits) • Automatic wait control with memory divided in variable sizes (max. 6 blocks) • Programmable wait function • Wait function using READY pin • Refresh function • Automatic generation of refresh cycle (RAS only) • RAS pin functions RAS pin RD, WRH, WRL pins ASTB pin 16 → DRAM RAS timing → DRAM CAS timing → DRAM row/column address switching timing µPD70433 3.2 REGISTERS The V55PI CPU has general register sets compatible with the V20 and V30 (native mode), and the V25 and V35. The general register sets are mapped onto the register file space. These general register sets are also used as on-chip RAM, and there can be a maximum of 16 register sets in bank form. In addition, the V55PI has various special function registers for controlling on-chip peripheral hardware. These special function registers are mapped onto memory space addresses 0FFE00H to 0FFFEFH. 3.2.1 Register Banks The general register sets are mapped onto the register file space (in on-chip RAM). The general register sets are used in a bank arrangement; each bank consists of 32 bytes and up to 16 banks can be set. The CPU normally uses register bank 15 for program execution, and it is possible to switch to another bank automatically by means of maskable hardware interrupt or software interrupt (BRKCS instruction). It is possible to return from the switchedto register bank to the original register bank by means of the instruction for returning from an interrupt (RETRBI). The register bank configuration is shown in Figure 3-1. The general register sets are mapped onto the area with an offset of (+08H) to (+1FH) from the start address of each register bank. The word address from the start in a register bank is the extended segment register (DS2) area. The vector PC/DS3 area is used to set the value to be loaded into the PC when the register bank is switched, that is, the offset value of the start address of the interrupt service routine. This area is also used as the extended segment register (DS3) area. The PSW save area is used to save the PSW when the register bank is switched, and the PC save area is used to save the PC when the register bank is switched. After a reset, register bank 15 is selected automatically. Also, segment register initialization after a reset is performed for register bank 15 only. The register file space onto which these general register sets are mapped can also be accessed as data memory by addition of a special prefix instruction (IRAM:) to a memory manipulation instruction. Of the 16 set register banks, banks 0 and 1 have macro service channels (parameter and work area for macro service) allocated in duplicate. 17 µPD70433 Figure 3-1. Register Bank Configuration Register File Space (512 bytes) +00H 15 87 0 000H Register Bank DS2 0 +02H 020H Vector PC/DS3 1 040H +04H PSW Save 2 +06H 060H PC Save 3 +08H 080H DS0 4 +0AH 0A0H SS 5 +0CH 0C0H 6 PS +0EH 0E0H DS1 7 +10H 100H 8 IY +12H 120H 9 IX +14H 140H BP 10 160H +16H SP 11 +18H 180H 12 BW BH BL +1AH 1A0H DW 13 DH +1CH 1C0H 14 1E0H DL CW CH CL +1EH AW 15 AH AL 1FFH (Offset from the starting address of each register bank) 18 µPD70433 3.2.2 General Registers (AW, BW, CW, DW) There are four 16-bit general registers. In addition to being accessed as 16-bit registers, these registers can also be accessed as 8-bit registers by dividing each register into upper and lower 8-bit halves (AH, AL, BH, BL, CH, CL, DH, DL). These registers are used as 8-bit or 16-bit registers with a wide range of instructions including transfer, arithmetic and logical operation instructions. Each register is also used as the default register for specific instruction processing, as shown below. AW : Word multiplication/division, word input/output, data conversion AL : Byte multiplication/division, byte input/output, BCD rotation, data conversion AH : Byte multiplication/division BW : Data conversion CW : Loop control branch, repeat prefix CL : Shift instructions, rotate instructions, BCD operations DW : Word multiplication/division, indirect addressing input/output These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number × 32). Table 3-1. General Register Offsets Register Offset AW 1EH BW CW DW Register Offset AL 1EH AH 1FH BL 18H BH 19H CL 1CH CH 1DH DL 1AH DH 1BH 18H 1CH 1AH 19 µPD70433 3.2.3 Pointers (SP, BP) and Index Registers (IX, IY) These are 16-bit registers used as base pointers or index registers in memory accesses using based addressing (BP), indexed addressing (IX, IY), based indexed addressing (BP, IX, IY), etc. The SP is also used as the pointer in stack operations. As with general registers, these are used with transfer instructions, arithmetic operation instructions, etc., but in this case they cannot be used as 8-bit registers. Each register is also used as the fixed address pointer for specific instruction processing, as shown below. SP : Stack manipulation IX : Block transfers, BCD operation source side address specification IY : Block transfers, BCD operation destination side address specification These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number × 32). Table 3-2. Pointer and Index Register Offsets Register Offset SP 16H BP 14H IX 12H IY 10H 3.2.4 Segment Registers (PS, SS, DS0, DS1) The CPU manages the 1M-byte basic memory space by dividing it into 64K-byte units. The CPU specifies the start address of each segment with a segment register, and uses another register or effective address for the specification of phyiscal address, with the relative address from the start address as the offset. The physical address is created as shown below. Segment Register 4-Bit Fixed + x x x x 0 H .... Segment Start Address 0 x x x x H .... Offset Value x x x x x H ..... Physical Address (20 Bits) There are four segment registers: PS (Program Segment), SS (Stack Segment), DS0 (Data Segment 0), and DS1 (Data Segment 1). The respective segments are used in the following cases. PS : Program fetch SS : Stack manipulation instructions, addressing using BP as base register DS0 : General variable accesses, source block data accesses such as block transfer instructions, etc. DS1 : Destination block data accesses such as block transfer instructions, etc. 20 µPD70433 However, using a segment override prefix instruction makes it possible for access of general variables to change from DS0 to another segment register. Also, in addressing which uses BP as the base register, another segment register can be used instead of SS. Example MOV MOV AW, 1000H DS1 : AW MOV BL, DS1, BYTE PTR [IX]; DSI : Byte data read from IX When a reset is performed, PS of register bank 15 is initialized to FFFFH, and SS, DS0 and DS1 are initialized to 0000H. These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number × 32). Table 3-3. Segment Register Offsets Register Offset DS0 08H DS1 0EH SS 0AH PS 0CH 3.2.5 Extended Segment Registers (DS2, DS3) In addition to the segment registers for accessing the 1M-byte basic memory space, the V55PI is provided with extended segment registers which specify the start address of each 64K-byte segment of the 16M-byte extended memory space. There are two extended segment registers, DS2 (Data Segment 2) and DS3 (Data Segment 3), which are used as shown below. DS2: Extended memory space general variable accesses (by segment override prefix instructions), source block data accesses in extended memory space block transfer instructions, etc. DS3: Extended memory space general variable accesses (by segment override prefix instructions), destination block data accesses in extended memory space block transfer instructions, etc. The data access using an extended semgnet register is performed by using the segment override prefix. Especially, in the block transfer instruction, DS2 and DS3 can be specified simultaneously by segment override prefix. (In this case, the order for DS2 and DS3 is optional.) Example REP DS2: DS3: MOVBKW ; Word memory block transfer from DS2 : IX to DS3 : IY. The CPU specifies the start address of each segment with an extended segment register, and performs an access by using another register or effective address for the specification of physical address, with the relative address from the start address as the offset value. The physical address is created as shown in the next page. 21 µPD70433 Extended Segment Register 8-Bit Fixed + x x x x 0 0 H 0 0 x x x x H x x x x x x H ... Segment Start Address ... Offset Value ... Physical Address (24 Bits) When a reset is performed, DS2 and DS3 of register bank 15 are initialized to 0000H. These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number × 32). Table 3-4. Extended Segment Register Offsets 3.2.6 Register Offset DS2 00H DS3 02H (Also used as vectored PC) Special Function Registers (SFR) The V55PI has a group of registers with the function of controlling on-chip peripheral hardware. A number of registers are provided according to the type of cotrol for each peripheral hardware unit, and the actual operation can be set using the individual bits in the registers. These registers are mapped onto the memory space, and are read and written to using the same method as for ordinary memory (see 3.5.3 "Special Function Register Area"). Example MOV AW, 0FFE0H MOV MOV DS1, AW BL, DS1 : BYTE PTR [1EFH]; 0FFE0H : 1EFH (PRC register) Read There are also two instructions, BTCLR and BTCLRL, which are only valid for special function registers. Of these, BTCLRL is an instruction newly provided in the V25 or V35. The BTCLR instruction is valid for registers in the upper 240 bytes (0FFF00H to 0FFFEFH) of the special function register area, and the BTCLRL instruction is valid for registers in the lower 256 bytes (0FFE00H to 0FFEFFH). 22 µPD70433 3.3 PROGRAM COUNTER (PC) This is a 16-bit binary counter which holds the offset value of the program memory address on which the CPU is to perform execution. The PC is incremented each time an instruction code is fetched from the instruction queue, and is also loaded with the new location address value when a branch, call, return or break instruction is executed. When a reset is performed, 0000H is loaded into the PC. Because the PS register is initialized to FFFFH in a reset, after a reset the CPU begins execution at physical address 0FFFF0H. 3.4 PROGRAM STATUS WORDS (PSW) The PSW consists of 6 status flags and 5 control flags. • Status flags • V (Overflow) ...Overflow detection flag • S (Sign) • Z (Zero) ...Sign bit detection flag ...All zero detection flag • AC (Auxiliary Carry) • P (Parity) ...4-bit carry/borrow detection flag ...Parity detection flag • CY (Carry) • Control flags ...Carry/borrow detection flag • RB0 to RB3 (Register Banks 0 to 3) ...Register bankspecification flags • DIR (Direction) ...Block transfer/input/output instruction direction control flag • IE (Interrupt Enable) • BRK (Break) ...Interrupt enabled state control flag ...Single-step interrupt control flag • IBRK (I/O Break) ...Input/output instruction trap control flag The status flags are set (1) or reset (0) automatically according to the result (data value) of execution of various kinds of instructions. The CY flag can be directly set, reset or inverted by an instruction. The control flags are set or reset by instructions, and control the operation of the CPU. The IE and BRK flags are always reset when interrupt servicing is initiated. The contents of the PSW can be saved to and restored from the stack by the PUSH and POP instructions. However, when the contents are restored by the POP PSW instruction, bits 12 to 15 (RB0 to RB3) are not returned to the PSW. The low-order 8 bits of the PSW can also be saved to or restored from the AH register by an MOV instruction. The PSW bit configuration is shown below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RB3 RB2 RB1 RB0 Y DIR IE BRK S Z 0 AC 0 P IBRK CY 23 µPD70433 3.5 MEMORY SPACE The V55PI has a 16M-byte memory space. Of this, using lowest 1M bytes (000000H to 0FFFFFH) as the basic memory space, the 16M bytes including the basic memory space (000000H to FFFFFFH) can be accessed as the extended memory space. The basic memory space can be accessed using the segment registers (PS, SS, DS0, DS1) in the same way as in the V25 and V35. The extended memory space can be accessed using the extended segment registers (DS2, DS3), and has the basic memory space mapped onto the lowest 1M bytes. See 3.2.4 "Segment Registers (PS, SS, DS0, DS1)" and 3.2.5 "Extended Segment Registers (DS2, DS3)" for the physical addresses. The 496-byte space 0FFE00H to 0FFFEFH has mapped onto it a group of registers to which specific functions are allocated such as on-chip peripheral hardware registers, control registers, etc., and these are manipulated by memory accesses. In addition, independent of these, there is a 512-byte register file space (in on-chip RAM). In addition to being accessed by using register manipulation instructions as in the V25 and V35, the register file space can also be accessed as data memory by adding a special prefix instruction (IRAM:) to a memory manipulation in. Figure 3-2. Memory Space 000000H Vector Area 003FFH Basic Memory Space (1M Bytes) 0FFFFFH 100000H FFE00H FFFEFH Extended Memory Space (16M Bytes) Special Function Register Area (On-Chip Area) FFFFFFH 3.5.1 Basic Memory Space The memory space comprises a 1M-byte basic memory space and 16M-byte extended memory space. The basic memory space is mapped onto the lowest 1M bytes (000000H to 0FFFFFH) of the extended memory space. The 1M-byte basic memory space is shown in Figure 3-3. Conditions for accessing the basic memory space by software are the same as for the V20/V30 and V25/V35. A basic memory space physical address is specified by the segment start address indicated by the segment register (PS, SS, DS0, DS1) and the offset value from the segment start position indicated by another register or immediate data. The basic memory space has the vectored interrupt vector area and special function register area mapped onto it. For an area in which special function registers are mapped, data accesses cannot be made to external memory (program fetches are possible.) 24 µPD70433 Figure 3-3. Basic Memory Space 000000H 00000H Vector Area 003FFH 1M Bytes FFE00H Spaecial Function Register Area (Internal Area) FFFEFH 0FFFFFH 0FFF0H to 0FFFFFH is a program area used for the system boot, and PS and PC become 0FFFH and 0H, respectively, therefore the program execution starts from 0FFFF0H. 3.5.2 Extended Memory Space The 16M-byte extended memory space is shown in Figure 3-4. The only accesses that can be performed on the extended memory space are data accesses. The basic memory space is mapped onto the lowest 1M bytes (000000H to 0FFFFFH) of the extended memory space, and can be accessed using the segment registers PS, SS, DS0 and DS1. Data accesses can be performed in the extended memory space using the extended segment registers DS2 and DS3. With DS2 and DS3 it is possible to use a specification as a segment override prefix instruction added to a memory manipulation instruction. An extended memory space physical address is specified by the segment start address indicated by the extended segment register and the offset value from the segment start position indicated by another register or immediate data. If the generated address indicates the lowest 1M-byte area (000000H to 0FFFFFH), the basic memory space is accessed. 25 µPD70433 Figure 3-4. Extended Memory Space 000000H Vector Area 00000H 003FFH 1M Bytes FFE00H FFFEFH 0FFFFFH 100000H 16M Bytes Spaecial Function Register Area (Internal Area) FFFFFFH 3.5.3 Special Function Register Area The 496-byte space 0FFE00H to 0FFFEFH has mapped onto it a group of registers to which functions such as on-chip peripheral hardware operation specification, status monitoring, etc., are assigned. Program fetches cannot be performed from these areas. Special function register manipulation is performed by accesses by means of memory manipulation instructions. If the special function register area is accessed, RD, WRH, WRL, IORD, IOWR and other control signals do not become active. A list of special function registers is given in Table 3-5. The meaning of the items in the table is explained below. • Symbol ............................ The symbol used to indicate the special function register name. Corresponds to the operand description format (symbol name) in a memory manipulation instruction. • R/W ................................. Indicates whether this special function register is read/write enabled. R/W : Read/write enabled R : Read only W : Write only • Manipulation Method ..... Indicates which of the following can be used on the register: bit manipulation, 8-bit manipulation, 16-bit manipulation, 32-bit manipulation. • RESET ............................ Indicates the status of the register after RESET input. Note Addresses which are not listed are the reserved area, therefore, they should not be accessed by the user program. 26 Table 3-5. Special Function Registers (1/7) Address Special Function Register Name Symbol Manipulable Bit Units R/W 1 Bit 0FFE00H A/D conversion result register 0 ADCR0 R 0FFE02H A/D conversion result register 1 ADCR1 R 0FFE04H A/D conversion result register 2 ADCR2 R 0FFE06H A/D conversion result register 3 ADCR3 R 0FFE10H Parallel interface buffer PAD R/W *1 0FFE18H Parallel interface control register 0 PAC0 R/W 0FFE19H Parallel interface control register 1 PAC1 R/W 0FFE1AH Parallel interface status register PAS R/W *2 0FFE1CH Parallel interface acknowledge interval register 1 PAI1 W 0FFE1DH Parallel interface acknowledge interval register 2 PAI2 W 0FFE20H A/D converter mode register ADM R/W 0FFEC0H Interrupt mask flag register 0 (low) MK0L R/W MK0H R/W MK1L R/W MK1H R/W MK0 0FFEC1H Interrupt mask flag register 0 (high) 0FFEC2H Interrupt mask flag register 1 (low) MK1 Interrupt mask flag register 1 (high) 0FFEC4H In-service priority register ISPR R 0FFEC5H Interrupt mode control register IMC R/W 0FFEC9H Interrupt request control register 09 IC09 R/W 0FFECAH Interrupt request control register 10 IC10 R/W 0FFECBH Interrupt request control register 11 IC11 R/W 0FFECCH Interrupt request control register 12 IC12 R/W 0FFECDH Interrupt request control register 13 IC13 R/W 27 * 1. Varies according to input/output mode. 2. Some bits R, others R/W (possible). • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Undefined Undefined Undefined Undefined Undefined 90H 03H 40H Undefined Undefined 00H • • FFH FFH FFH FFH 00H 80H 43H 43H 43H 43H 43H µPD70433 0FFEC3H • • After Reset 8 Bits 16 Bits 32 Bits 28 Table 3-5. Special Function Registers (2/7) Address Special Function Register Name Symbol Manipulable Bit Units R/W 1 Bit Interrupt request control register 14 IC14 R/W 0FFED0H Interrupt request control register 16 IC16 R/W 0FFED1H Interrupt request control register 17 IC17 R/W 0FFED2H Interrupt request control register 18 IC18 R/W 0FFED3H Interrupt request control register 19 IC19 R/W 0FFED4H Interrupt request control register 20 IC20 R/W 0FFED5H Interrupt request control register 21 IC21 R/W 0FFED6H Interrupt request control register 22 IC22 R/W 0FFED7H Interrupt request control register 23 IC23 R/W 0FFED8H Interrupt request control register 24 IC24 R/W 0FFED9H Interrupt request control register 25 IC25 R/W 0FFEDAH Interrupt request control register 26 IC26 R/W 0FFEDBH Interrupt request control register 27 IC27 R/W 0FFEDCH Interrupt request control register 28 IC28 R/W 0FFEDDH Interrupt request control register 29 IC29 R/W 0FFEDEH Interrupt request control register 30 IC30 R/W 0FFEDFH Interrupt request control register 31 IC31 R/W 0FFEE0H Interrupt request control register 32 IC32 R/W 0FFEE4H Interrupt request control register 36 IC36 R/W 0FFEE5H Interrupt request control register 37 IC37 R/W 0FFF00H Port 0 P0 R/W 0FFF01H Port 1 P1 R 0FFF02H Port 2 P2 R/W 0FFF03H Port 3 P3 R/W • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H Undefined Undefined Undefined Undefined µPD70433 0FFECEH After Reset 8 Bits 16 Bits 32 Bits Table 3–5. Special Function Registers (3/7) Address Special Function Register Name Symbol Manipulable Bit Units R/W 1 Bit Port 4 P4 R/W 0FFF05H Port 5 P5 R/W 0FFF06H Port 6 P6 R 0FFF07H Port 7 P7 R/W 0FFF08H Port 8 P8 R/W 0FFF0CH Port read control register PRDC R/W 0FFF0EH Real–time output port RTP R/W 0FFF10H Port 0 mode register PM0 R/W 0FFF12H Port 2 mode register PM2 R/W 0FFF13H Port 3 mode register PM3 R/W 0FFF14H Port 4 mode register PM4 R/W 0FFF15H Port 5 mode register PM5 R/W 0FFF17H Port 7 mode register PM7 R/W 0FFF18H Port 8 mode register PM8 R/W 0FFF22H Port 2 mode conrol register PMC2 R/W 0FFF23H Port 3 mode control register PMC3 R/W 0FFF24H Port 4 mode control register PMC4 R/W 0FFF25H Port 5 mode control register PMC5 R/W 0FFF27H Port 7 mode control register PMC7 R/W 0FFF28H Port 8 mode control register PMC8 R/W 0FFF2CH Real–time output port control register RTPC R/W 0FFF2DH Real–time output port delay specification register RTPD R/W 0FFF2EH Port 7 buffer (low) P7L R/W 0FFF2FH Port 7 buffer (high) P7H R/W • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Undefined Undefined Undefined Undefined Undefined 00H Undefined FFH FFH FFH FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H 40H Undefined Undefined Undefined µPD70433 29 0FFF04H After Reset 8 Bits 16 Bits 32 Bits 30 Table 3-5. Special Function Registers (4/7) Address Special Function Register Name Symbol Manipulable Bit Units R/W 1 Bit 0FFF30H Timer control register 0 TMC0 R/W 0FFF31H Timer control register 1 TMC1 R/W 0FFF32H Timer output control register 0 TOC0 R/W 0FFF33H Timer output control register 1 TOC1 R/W 0FFF34H External interrupt mode register 0 INTM0 R/W INTM1 R/W INTM External interrupt mode register 1 0FFF40H Timer register 0 TM0 R/W 0FFF42H Timer register 1 TM1 R/W 0FFF44H Timer register 2 TM2 R/W 0FFF46H Timer register 3 TM3 R/W 0FFF48H Timer capture register 00 CT00 R/W 0FFF4AH Timer capture register 01 CT01 R/W 0FFF4CH Timer compare register 00 CM00 R/W 0FFF4EH Timer compare register 01 CM01 R/W 0FFF50H Timer capture register 10 CT10 R/W 0FFF52H Timer compare register 10 CM10 R/W 0FFF54H Timer compare register 11 CM11 R/W 0FFF58H Timer compare register 20 CM20 R/W 0FFF5AH Timer compare register 21 CM21 R/W 0FFF5CH Timer compare register 22 CM22 R/W 0FFF5EH Timer compare register 23 CM23 R/W 0FFF60H Watchdog timer mode register WDM R/W* 0FFF64H Timer compare register 30 CM30 R/W WDT can only be written to by the RSTWDT instruction (8-bit unit only). • • • • • • • • • • • • • • • • • • • • • • • • • • 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00H • Undefined µPD70433 * 0FFF35H • • • • • • After Reset 8 Bits 16 Bits 32 Bits Table 3-5. Special Function Registers (5/7) Address Special Function Register Name Symbol Manipulable Bit Units R/W 1 Bits 0FFF66H Timer compare register 31 CM31 R/W 0FFF6CH PWM register PWM R/W 0FFF6DH PWM control register PWMC R/W 0FFF70H Transmit baud rate generator register 0 TXBRG0 R/W 0FFF71H Receive baud rate generator register 0 RXBRG0 R/W 0FFF72H Prescaler register 0 PRS0 R/W 0FFF73H UART mode register 0 / clocked serial interface mode register 0 UARTM0/CSIM0 R/W 0FFF74H UART status register 0 / SBI control register 0 UARTS0/SBIC0 *1/*2 0FFF75H UART transmit buffer 0 / clocked serial I/O shift register 0 TXB0/SIO0 W 0FFF76H Receive buffer 0 RXB0 R 0FFF78H Transmit baud rate generator register 1 TXBRG1 R/W 0FFF79H Receive baud rate generator register 1 RXBRG1 R/W 0FFF7AH Prescaler register 1 PRS1 R/W 0FFF7BH UART mode register 1 / clocked serial interface mode register 1 UARTM1/CSIM1 R/W 0FFF7CH UART status register 1 UARTS1 *1/*2 0FFF7DH UART transmit buffer 1 / clocked serial I/O shift register 1 TXB1/SIO1 W 0FFF7EH Receive buffer 1 RXB1 R 0FFF7FH Protocol selection register ASP R/W 0FFF80H Terminal counter 0 (low) 0FFF82H Terminal counter 0 (high) 2. R or W in bit units. 31 Remark ( ): Depends on the mode. TC0L R/W TC0H R/W • • • • • • ( ) • ( ) • • • • ( ) • ( ) • • Undefined • • • • • • • • • • • • • • • • • • 00H 00H Undefined Undefined 00H 00H 00H Undefined Undefined Undefined Undefined 00H 00H 00H Undefined Undefined 00H • • • Undefined Undefined µPD70433 * 1. Some bits R, others R/W. TC0 After Reset 8 Bits 16 Bits 32 Bits 32 Table 3-5. Special Function Registers (6/7) Address Special Function Register Name Symbol Manipulable Bit Units R/W 1 Bit 0FFF84H Terminal counter modulo register 0 (low) TCM0L R/W TCM0H R/W UDC0L R/W UDC0H R/W DCM0L R/W DCM0H R/W MAR0L R/W MAR0H R/W DPTC0L R/W DPTC0H R/W TCM0 0FFF86H Terminal counter modulo register 0 (high) 0FFF88H DMA up/down counter 0 (low) • UDC0 0FFF8AH DMA up/down counter 0 (high) 0FFF8CH DMA compare register 0 (low) • DCM0 0FFF8EH DMA compare register 0 (high) 0FFF90H DMA memory address register 0 (low) • MAR0 0FFF92H DMA memory address register 0 (high) 0FFF94H DMA read/write pointer 0 (low) • DPTC0 0FFF96H DMA read/write pointer 0 (high) 0FFF9CH DMA mode register 0 DMAM0 R/W 0FFF9DH DMA control register 0 DMAC0 R/W 0FFF9EH DMA status register DMAS R/W 0FFFA0H Terminal counter 1 (low) R/W 0FFFA2H Terminal counter 1 (high) TC1H R/W 0FFFA4H Terminal counter modulo register 1 (low) TCM1L R/W TCM1H R/W UDC1L R/W UDC1H R/W DCM1L R/W DCM1H R/W MAR1L R/W MAR1H R/W TCM1 0FFFA6H Terminal counter modulo register 1 (high) 0FFFA8H DMA up/down counter 1 (low) UDC1 0FFFAAH DMA up/down counter 1 (high) 0FFFACH DMA compare register 1 (low) DCM1 0FFFAEH DMA compare register 1 (high) 0FFFB0H DMA memory address register 1 (low) MAR1 0FFFB2H * DMA memory address register 1 (high) Bit clear operation possible. • • • • • • • • • • • • • • • • • • • • • • • • Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined E0H 00H 00H • • • • • • • • • • • • • • • Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined µPD70433 TC1L TC1 • • •* After Reset 8 Bits 16 Bits 32 Bits Table 3-5. Special Function Registers (7/7) Address Special Function Register Name Symbol Manipulable Bit Units R/W 1 Bit 0FFFB4H DMA read/write pointer 1 (low) DPTC1L R/W DPTC1H R/W DPTC1 0FFFB6H DMA read/write pointer 1 (high) 0FFFBCH DMA mode register 1 DMAM1 R/W 0FFFBDH DMA control register 1 DMAC1 R/W 0FFFE0H Software timer/counter STC 0FFFE2H Software timer/counter compare register STMC R/W 0FFFE8H Programmable wait control register 0 PWC0 R/W 0FFFE9H Programmable wait control register 1 PWC1 R/W 0FFFEAH Memory block control register MBC R/W 0FFFECH Refresh mode register RFM R/W 0FFFEEH Standby control register STBC R/W *1 0FFFEFH Processor control register PRC R/W • • • • • • • • • • • • • • Undefined Undefined E0H 00H • • R • • • • • • After Reset 8 Bits 16 Bits 32 Bits Undefined FFFFH EAH AAH FCH 77H Undefined *2 EEH *1 The SFB bit of the standby control register can be set (1) by instruction, but cannot be cleared (0). (Only '1' can be written.) *2 After power-on reset: 00H, otherwise: no change µPD70433 33 µPD70433 3.5.4 Vector Table Area The 1K–byte area 00000H to 003FFH in the memory space holds 256 vectors (4 bytes used per vector) for the start addresses of interrupt routines initiated by interrupt requests, break instructions, etc. In the initial state, vectors 0 to 47 are reserved as V55PI family dedicated on-chip peripheral and software interrupt vectors. For vectors 8 to 47, the vector address of hardware interrupts except NMI can be changed by means of bits V0 and V1 of the interrupt mode control register (IMC). Vector 0 Vector 1 (00000H) (00004H) : Divide error : Single step Vector 2 Vector 3 (00008H) (0000CH) : NMI instruction : BRK 3 instruction Vector 4 Vector 5 (00010H) (00014H) : BRKV instruction : CHKIND instruction Vector 6 Vector 7 (00018H) (0001CH) : Input/output instruction : FPO instruction/exception trap When V1 = V0 = 0 : 34 Vector 8 Vector 9 (00020H) (00024H) : INTWDT : INTP0 Vector 10 Vector 11 (00028H) (0002CH) : INTP1 : INTP2 Vector 12 Vector 13 (00030H) (00034H) : INTP3 : INTP4 Vector 14 Vector 15 (00038H) (0003CH) : INTP5 : System reserved Vector 16 Vector 17 (00040H) (00044H) : INTCM00 : INTCM01 Vector 18 Vector 19 (00048H) (0004CH) : INTCM10 : INTCM11 Vector 20 Vector 21 (00050H) (00054H) : INTCM21 : INTCM31 Vector 22 Vector 23 (00058H) (0005CH) : INTD0 DMA#0_MAIN : INTD0S DMA#0_SUB Vector 24 Vector 25 (00060H) (00064H) : INTD1 DMA#1_MAIN : INTD1S DMA#1_SUB Vector 26 Vector 27 (00068H) (0006CH) : INTSER0 : INTSER1 Vector 28 Vector 29 (00070H) (00074H) : INTSR0/INTCSI0 : INTSR1/INTCSI1 Vector 30 Vector 31 (00078H) (0007CH) : INTST0 : INTST1 Vector 32 Vector 33 (00080H) (00084H) : INTSIT : System reserved Vector 34 Vector 35 (00088H) (0008CH) : System reserved : System reserved Vector 36 Vector 37 (00090H) (00094H) : INTPAI : INTAD Vector 38 Vector 39 (00098H) (0009CH) : System reserved : System reserved µPD70433 Vector 40 Vector 41 (000A0H) (000A4H) : System reserved : System reserved Vector 42 Vector 43 (000A8H) (000ACH) : System reserved : System reserved Vector 44 Vector 45 (000B0H) (000B4H) : System reserved : System reserved Vector 46 Vector 47 (000B8H) (000BCH) : System reserved : System reserved When V1 = 0, V0 = 1 : Vector 72 Vector 73 • • • Vector 110 Vector 111 (00120H) (00124H) : INTWDT : INTP0 • • • • • • (001B8H) (001BCH) : System reserved : System reserved When V1 = 1, V0 = 0 : Vector 136 Vector 137 • • • Vector 174 Vector 175 (00220H) (00224H) : INTWDT : INTP0 • • • • • • (002B8H) (002BCH) : System reserved : System reserved When V1 = 1, V0 = 1 : Vector 200 Vector 201 • • • Vector 238 Vector 239 (00320H) (00324H) : INTWDT : INTP0 • • • • • • (003B8H) (003BCH) : System reserved : System reserved 35 µPD70433 3.6 REGISTER FILE SPACE The register file space is shown in Figure 3-5. The size of the register file space is 512 bytes, and a maximum 16-bank register set can be set. The register file space is separate from the memory space, and in addition to accesses using a register manipulation instruction as with the V25 and V35, the register file space can be accessed as data memory by adding a special prefix instruction (IRAM:) to a memory manipulation instruction. (Access is performed asynchronously independently of the external bus cycle. When the IRAM: prefix instruction is added to a memory manipulation instruction, the CPU performs a data access with the low–order 9 bits of the memory address offset value as the register file address. In this case, segment register and physical address addition is not performed, and an external bus cycle is not initiated. Example Label1: MOV MOV IRAM : [0024H], AW ..... <1> ..... <2> [0056H], BW <1> This shows the case where data is transferred to the register file space using an "IRAM:" prefix instruction. The AW register value is stored in address 24H of the register file. <2> This shows the case where an instruction for data transfer to the memory space is used. If the IRAM prefix instruction is added to the primitive block transfer instruction and BCD operation instruction, which specify the source block and destination block, it becomes effective for the destination block. Also, the macro service conrol word area (008H to 03FH), the macro service work area (000H to 007H), and the area used by the macro service channel (008H to 0FFH) are allocated in overlapping fashion in the file space. If a specific macro service which requires work area (RTOPTRN) is not used, these work areas can be used as data space. 36 µPD70433 Figure 3-5. Register File Space 000H Macro Service Work Area 0 0 0H Register Bank 0 Macro Service Control Word Area 008H + 0 0 H 15 87 03FH DS2 +02H 0 2 0H 1 Vector PC/DS3 +04H 0 4 0H 2 0 6 0H 3 PSW Save Macro Service Channel Area +06H 0FFH PC Save +08H 0 8 0H 4 DS0 +0AH 0A 0H 5 SS +0CH 0C 0H 6 PS +0EH 0E 0H 7 DS1 +10H 1 0 0H 8 IY +12H 1 2 0H 9 IX +14H 1 4 0H 10 BP +16H 1 6 0H 11 SP +18H 1 8 0H 12 +1AH 1A 0H 13 +1CH 1C 0H 14 +1EH 1E 0H 15 1FFH 0 BW BH BL DW DH DL CW CH CL AW AH AL (Offset from the starting address of each register bank) 37 µPD70433 3.7 I/O SPACE The V55PI has a 64K-byte I/O space. The I/O space map is shown in Figure 3-6. The I/O space is accessed using address bus/data bus and control signals (IORD, IOWR, etc). 0 is output from the unused high-order 8 bits of the address bus. Wait cycles can be inserted in an I/O cycle by software and the READY pin. The area FF80H to FFFFH of the I/O space is a reserved area, in which two V55PI on-chip peripheral DMA input/output read/write pointers (IOP) are allocated. The address of IOP0 is FF94H, and the address of IOP1 is FFB4H. When the CPU executes an input/output instruction with an IOP address as an operand, the DMA controller performs a read/write of data in the DMA controller transfer buffer, with the IOP contents as the address value, and increments (or decrements) the IOP value automatically in accordance with the contents of the DMA control register. Therefore, data written by the DMA controller can be referenced by an input/output instruction, and conversely, data written by an input/output instruction can be transferred by the DMA controller. Figure 3-6. I/O Map (64K Bytes) 0000H FF80H FF94H FFB4H IOP 0 : IOP 1 : FFFFH Remark 38 IOPn corresponds to the DMA read/write pointer (DPTCn). Reserved Area µPD70433 4. BUS CONTROL FUNCTIONS With the V55PI pin, refer to 1.1.2 (1) "Pin function for bus control". As regards pins which have an alternate function as port pins, when that function is used, the corresponding function must be selected by means of the port mode control register (PMCn). 4.1 WAIT FUNCTION The V55PI divides the basic memory space (000000H to 0FFFFFH) into a maximum of 4 blocks with a variable memory size, divides the uppermost extended memory space area (100000H to FFFFFFH) into two areas with a variable memory size, and performs wait control for each block. The memory size of each block in the basic memory space is specified by the memory block control register (MBC). Figure 4-1 shows the memory block configuration when A9H has been set for the MBC register value. Figure 4-1. Partitioned Memory Control 1 0 1 0 1 1 0 1 MBC MB31 MB30 MB21 MB20 MB11 MB10 MB01 MB00 Main Memory Space 00 Block 0 128K Bytes 01 00 256K Bytes 10 Block 1 01 512K Bytes 11 640K Bytes 00 01 768K Bytes 10 Block 2 896K Bytes 10 Block 3 11 00 11 Block 4 1M Bytes 2M Bytes 01 4M Bytes 10 6M Bytes 11 8M Bytes Block 5 16M Bytes 39 µPD70433 Figure 4-2. Memory Wait Control 7 6 5 (BLOCK3) 4 3 (BLOCK2) 2 1 (BLOCK1) 0 (BLOCK0) PWC1 DW31 DW30 DW21 DW20 DW11 DW10 DW01 DW00 7 6 5 4 3 2 1 0 (BLOCK4) (BLOCK1) (I/O Space) (BLOCK5) (BLOCK4) PWC0 AW1 AW0 IOW1 IOW0 DW51 DW50 DW41 Data Wait (DW, IOW) DWn1/IOW1 DWn0/IOW0 Wait State 0 0 0 *1 0 1 1 *2 1 0 2 *2 1 1 3 *2 * 1. 2. READY signal is ignored. Additional control by means of READY signal is also possible. Address Wait (AW) AWn Wait State 0 Not inserted (block 1) 1 Inserted (block 1) 0 Not inserted (block 4) 1 Inserted (block 4) AW0 AW1 40 DW40 µPD70433 4.2 REFRESH FUNCTION The following functions are provided to refresh DRAM and pseudo-SRAM. • Function to insert periodically a refresh cycle in a series of bus cycles • Refresh address output function to refresh DRAM and pseudo-SRAM • Function to generate a refresh cycle in hold mode and HALT mode. • Function to insert a wait state in a refresh cycle 4.2.1 Refresh Mode Register (RFM) The RFM register is an 8-bit register to control refresh operation. A refresh cycle can be selected from the time base counter output tap. While a refresh request is held by another bus cycle if the next refresh request is generated, only the latter is valid. The RFM register value after a reset is 77H. 4.2.2 Wait Control in Refresh Cycle A wait state can be inserted in a refresh cycle. The specified number of wait states is inserted for memory block 4 by the programmable wait control register (PWC0) or READY pin. 4.2.3 Refresh Address Bus pins AD0 to AD15 and A16 to A19 are activated in a refresh cycle. For each refresh cycle, the count is performed in one-address increments from x00000 to x1FFFFF in the case of the external 8-bit bus width, and in two-address increments from x00001H to xFFFFF in the case of the external 16-bit bus width (the minimum address is returned to after the maximum address). After initialization by a reset, count-up is started from x00000H in the case of the external 8-bit bus width and x00001H in the case of the external 16-bit bus width. In the case of the external 16-bit bus width, the refresh address minimum address bit (A0) is fixed at “1” and the DEX pin output is also fixed at “1”. A20 to A23 are undefined in a refresh cycle. 41 µPD70433 5. INTERRUPT FUNCTIONS The V55PI incorporates a powerful interrupt controller (INTC) which controls multiple-interrupt servicing for a total of 25 maskable hardware interrupt requests: 19 internal and 6 external. The interrupt controller controls multiple-interrupt servicing based on programmable priority. The following functions are provided as interrupt servicing modes: vectored interrupt function, macro service function, register bank switching function. 5.1 FEATURES V55PI interrupt functions offer the following features: • Comprehensive servicing states for interrupt requests • Vectored interrupt function : Branch to interrupt service routine specified by vector table • Register bank switching function • Macro service function : High-speed interrupt response by automatic register bank switching : High-speed interrupt servicing by microprogram (firmware) • 4-level programmable priority order control • Interrupt multiprocessing control according to the priority • Rich variety of macro service functions (following 7 modes) closely tied to V55PI on-chip peripheral hardware EVTCNT : Event count processing BLKTRS : Data transfer between special function register and external memory buffer BLKTRS-C : Data transfer between special function register and external memory buffer (with transfer data DTACMP detection function) : Special function register status detection DTADIF RTOPTRN : Time measurement by timer capture function : Automatic control of real-time output port DTACMP-M : Data transfer between external I/O and memory • 7 external interrupt request inputs (NMI, INTP0 to INTP5) • Maskable interrupt requests are individually maskable. A list of interrupt sources is given in Table 5-1. 42 Table 5-1. Interrupt Sources (1/2) Interrupt Classification Default Priority 1 Interrupt Request Signal Interrupt Source Interrupt Request Control Register NMI Nonmaskable Generating Source NMI pin input Generating Unit Default Vector Table Number Vectored Address Macro Service Register Bank Switching ––– 2 00008H No No WDT 8 00×20H No No –– Macro Service Control Word Address –– 2 WDT Watchdog timer overflow 3 INTP0 IC9 INTP0 pin input 9 00×24H Yes Yes 012H 4 INTP1 IC10 INTP1 pin input 10 00×28H Yes Yes 014H 5 INTP2 IC11 INTP2 pin input 11 00×2CH Yes Yes 016H External 6 INTP3 IC12 INTP3 pin input 12 00×30H Yes Yes 018H 7 INTP4 IC13 INTP4 pininput 13 00×34H Yes Yes 01AH 8 INTP5 IC14 INTP5 pin input 14 00×38H Yes Yes 01CH 9 INTCM00 IC16 CM00 match detection 16 00×40H Yes Yes 020H 10 INTCM01 IC17 CM01 match detection 17 00×44H Yes Yes 022H 11 INTCM10 IC18 CM10 match detection 18 00×48H Yes Yes 024H Maskable Timer 12 INTCM11 IC19 CM11 match detection 19 00×4CH Yes Yes 026H 13 INTCM21 IC20 CM21 match detection 20 00×50H Yes Yes 028H 14 INTCM31 IC21 CM31 match detection 21 00×54H Yes Yes 02AH 15 INTD0 IC22 DMA channel 0_main 22 00×58H Yes Yes 02CH 16 INTD0S IC23 DMA channel 0_sub 23 00×5CH Yes Yes 02EH DMA 17 INTD1 IC24 DMA channel 1_main 24 00×60H Yes Yes 030H 18 INTD1S IC25 DMA channel 1_sub 25 00×64H Yes Yes 032H µPD70433 43 44 Table 5-1. Interrupt Sources (2/2) Interrupt Classification Default Priority Interrupt Request Signal Interrupt Sourse Generating Source Interrupt Request Control Register Generating Unit Default Vector Table Number Vectored Address Macro Service Register Bank Switching Macro Service Control Word Address 19 INTSER0 IC26 UART reception error (ch0) 26 00×68H No Yes 034H 20 INTSER1 IC27 UART reception error (ch1) 27 00×6CH No Yes 036H Yes Yes 28 00×70H Yes Yes Yes Yes Yes Yes INTSR0/ 21 UART reception (ch0)/ IC28 INTCSI0 Serial transmission/reception (ch0) INTSR1/ UART reception (ch1)/ 038H Serial I/F 22 Maskable IC29 INTCSI1 29 00×74H LDMA channel 5 03AH 23 INTST0 IC30 UART transmission (ch0) 30 00×78H Yes Yes 03CH 24 INTST1 IC31 UART transmission (ch1) 31 00×7CH Yes Yes 03EH 25 INTSIT IC32 STM match detection SIT 32 00×80H No Yes –– 26 INTPAI IC36 Parallel I/F Parallel I/F 36 00×90H Yes Yes –– 27 INTAD IC37 A/D converter A/D converter 37 00×94H Yes Yes 008H Divide error 0 00000H No No BRK flag (single-step) 1 00004H No No BRK3 instruction 3 0000CH No No BRKV instruction 4 00010H No No 5 00014H No No Input/output instruction (IBRK flag) 6 00018H No No BRK imm8 * 00×*H No No –– –– No Yes 7 0001CH No No Software CHKIND instruction –– –– –– –– BRKCS instruction –– Exception trap * Indicates that the value is variable in the range 0 to 255 (0 to FFH). Remarks "×" indicates that the value is determined by the V0 and V1 bits of the IMC register. µPD70433 FP0 instruction/ Exception trap µPD70433 5.2 INTERRUPT RESPONSE METHODS The V55PI has three interrupt response methods: a vectored interrupt function, register bank switching function, and macro service function. In the case of a maskable interrupt request, one of these functions can be selected by means of the interrupt request control register (IC××) for each interrupt source according to the purpose of the interrupt. The on-chip interrupt controller handles interrupt requests according to the set response method. 5.2.1 Vectored Interrupts A vectored interrupt can only be acknowledged in the interrupt enabled state (EI state). When a vectored interrupt is acknowledged, the CPU enters the interrupt disabled state (DI state), and the current PSW contents and PC and PS contents are saved to the stack. Then the corresponding vector is selected from the vector table, and the interrupt service routine is started at the address indicated by that vector. Vector numbers are fixed for each interrupt source. In the DI state, interrupts are held pending, and are acknowledged when the EI state is set again. The return from the interrupt is performed by an RETI instruction. In the case of a hardware interrupt other than a nonmaskable interrupt, an FINT instruction must be executed before the return instruction. When a return is made from an interrupt, the PC, PS and PSW are restored from the stack. Figure 5-1. Interrupt Acknowledge Operation (Performed in Sequence <1> → <4>) Vector Table Stack n×4 SP – 6 n×4+2 SP – 4 SP – 2 n: Vector Number <4> <2> SP ← SP – 6 PC <1> PS PSW <3> IE =0 BRK = 0 45 µPD70433 5.2.2 Register Bank Switching Function In the V55PI, general register sets are mapped onto on-chip RAM, and register sets can be held in up to 16 banks. Interrupt servicing is performed by automatically switching the register bank when a BRKCS or TSKSW instruction is executed or when an interrupt is responded to. Because saving of registers to the stack previously performed by software is not required, high-speed switching of the program execution environment is possible. The register bank switching sequence is performed as follows (See Figure 5-2). <1> The contents of PSW is saved to temporary register. <2> The register bank is switched. <3> IE and BRK are set to 0. <4> The contents of PSW which is saved to the PC and the temporary register are saved to the saving area, respectively. <5> The interrupt service routine start address offset value is loaded from the vector PC area in the register bank to PC. Figure 5-2. Register Bank Switching Sequence (In Case of Register Bank Switching by Interrupt) Old Register Bank New Register Bank for Interrupt Servicing AW AW CW CW DW DW BW BW SP SP BP BP IX IX IY IY DS1 DS1 PS PS SS SS DS0 DS0 <4> PC Save PC Save <4> PSW Save <5> Vector PC/DS3 Vector PC/DS3 DS2 DS2 PC PSW <1> Temporary Register <2> Register Bank Switching <3> IE = 0, BRK = 0 46 PSW Save µPD70433 5.2.3 Macro Service Function The macro service function performs processing of simple data transfers, etc., by means of a microprogram (CPU internal dedicated firmware) started by generation of an interrupt request. The simple, standardized interrupt servicing which was coded and executed by a user program is performed automatically. Macro service processing is caused by an interrupt request and is performed. Macro service is designed to minimize as far as possible the frequency of generation of interrupts consisting mainly of software processing, hold down the software overhead due to a series of processes used in an interrupt (register saving, initialization, register restoration, return from the interrupt routine), and improve the CPU efficiency. Processing performed by the macro service is transparent in terms of software, and it is possible to process as a single mass of data what was previously processed by software byte by byte, allowing more efficient programming. The V55PI macro service supports not only the simple data transfers used in the V25 and V35, but also various operating modes closely linked to the on-chip V55PI peripheral hardware, as shown below. (a) EVTCNT (EVENT COUNTER) The counter is updated each time the macro service are generated, and when the counter reaches 0 the macro service for the corresponding interrupt source is terminated and a vectored interrupt or a register bank switching is generated. (b) DTACMP (DATA COMPARE) The interrupt source specific SFR and preset byte data are compared, and if they match, the macro service for the corresponding interrupt source is terminated and a vectored interrupt or register bank switching is generated. (c) DTADIF (DATA DIFFERENCE) The difference in using the timer/counter unit capture register is calculated. This is initiated by a timer interrupt: the value of the capture register latched last time is subtracted from the value of the capture register latched this time, and the result is stored in the previously specified memory buffer. When processing has been performed the previously set number of times, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. (d) BLKTRS (BLOCK TRANSFER) A data transfer is performed between the previously specified memory buffer and SFR. When the previously set number of data transfers have been performed, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. (e) BLKTRS–C (BLOCK TRANSFER WITH CHARACTER SEARCH) A data transfer is performed between the previously specified memory buffer and SFR. When the previously set number of data transfers have been completed, or when the transfer data matches the previously set character data, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. (f) RTOPRTN (RTOP TRANSFER) Data to be output to the real-time output port is transferred to the port 7 buffer (P7H, P7L), and data which specifies interval for output to the real-time output port is transferred to the timer compare register (CM00, CM01). (g) DTACMP-M (DATA COMPARE WITH CHARACTER MASK) The logical product of the status data read from the external I/O and the previously set mask data is performed. The previously set byte data is compared with the result. If it matches, a data transfer is performed between the external I/ O and memory. If it does not match, or if the previously set number of data transfers have been performed, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. 47 µPD70433 6. DMA FUNCTION (DMA CONTROLLER) The V55PI incorporates a 2-channel DMA controller which controls execution of memory-to-I/O or memory-to-memory DMA transfers on the basis of DMA requests generated by an on-chip peripheral hardware (serial interface, parallel interface, or timer), the external DMARQ pin or a software trigger. Each channel of the DMA controller further comprises a main channel and a sub-channel: the operating mode determines whether the main channel and sub-channel are used as a single channel or as separate channels. When used as separate channels, function for a maximum of 4 channels can be constructed. 6.1 FEATURES • Two independent DMA channels (max. 4-channel configuration possible) • Four transfer modes • Single transfer mode ... One DMA transfer cycle is executed in response to one DMA request. • Demand release mode ... Consecutive DMA transfer cycles are executed while DMA request is active. • Single-step mode ... DMA transfer cycles and CPU bus cycles are executed alternately after DMA • Burst mode request generation. ... For each DMA request, the specified number of DMA transfer cycles are executed consecutively. • Five operating modes • Intelligent DMA mode–1 (ring buffer system) ... DMA transfers to ring buffer are controlled. • Intelligent DMA mode–2 (counter control system) ... Transfer data is transferred consecutively, divided into • Next address specification mode an arbitrary number of bytes. ... Consecutive transfers are possible between different • 2-channel operating mode transfer buffers. ... Main channel and subchannel are used as independent • Memory-to-memory transfer mode channels. ... Two bus cycles are started for one DMA transfer cycle, and memory-to-memory transfer is executed. • 3 clocks/1 bus cycle (no wait case) • Transfer objects • External I/O ←→ memory ... 1 DMA transfer cycle/1 bus cycle • SFR (internal I/O) ←→ memory ... 1 DMA transfer cycle/1 bus cycle • Memory ←→ memory (memory includes SFR) ... 1 DMA transfer cycle/2 bus cycles • Byte transfer/word transfer selectable • Transfer address increment/decrement/non-update selectable • DMA transfer end signal (TCE0, TCE1) output • 24-bit DMA memory address registers (MAR0, MAR1) • 21-bit terminal counters (TC0, TC1) • External DMA request signal input pins (DMARQ0, DMARQ1: alternate function as port P80 and P81 pins) • External DMA acknowledge signal output pins (DMAAK0, DMAAK1) 48 µPD70433 Table 6-1. Transfer Modes DMA Start Source Transfer STOP Method Mode Single transfer mode Software Peripheral Trigger Available Available Interrupt DMARQ Pin Available Reset of EDMA bit of DMAMn register Acknowledged Not acknowledged during transfer. Acknowledged at other times. Not Available Not Available Available Stops when the DMARQ pin is driven low during the transfer. Reset of EDMA bit of DMAMn register Single step mode Available* Available Available Reset of EDMA bit of DMAMn Acknowledged register Burst mode Available* Available Available None (stop disabled during the transfer) Not acknowledged Demand release mode * On–Chip The DMA start source is an on-chip timer interrupt, and transfer is possible only when the transfer I/O specification is external. Table 6-2. Correspondence Between Operating Modes and Transfer Modes Possible Transfer Modes* Operating Mode <1> <2> <3> <4> Yes Yes No No No No Yes Yes I/O (SFR) ←→ Memory Yes Yes No No Intelligent DMA mode–1 (ring buffer method) I/O (SFR) → Memory Intelligent DMA mode–2 (counter control method) Memory → I/O (SFR) Next address specification mode * Transfer Type 2–channel operating mode (Stop at end) I/O ←→ Memory Yes Yes Yes Yes (Repetition) I/O ←→ Memory Yes Yes Yes No Memory–memory transfer mode (Stop at end) Memory ←→ Memory Yes No Yes Yes (Repetition) Memory ←→ Memory Yes No Yes No Transfer modes <1> Single transfer mode <2> Demand release mode <3> Single step mode <4> Burst mode 49 µPD70433 7. SERIAL INTERFACE FUNCTIONS The V55PI is equipped with a 2-channel serial interface unit (ch0, ch1). The two communication protocols supported by the V55PI are as follows: (1) (2) Asynchronous Clocked UART CSI SBI: 2-wire serial bus interface IOE: I/O expansion 3-wire serial interface 7.1 FEATURES • Two communication protocols supported • Two serial channels • Wake-up function • On-chip dedicated baud rate generator • DMA request generated by completion of transmission/reception (transmit/receive data DMA transfer is capable) 7.2 PROTOCOLS The UART is an asynchronous serial interface which achieves data synchronization by means of start/stop bits, and is functionally enhanced UART functions compared with previous single-chip microcontroller. The CSI (clocked serial interface) is a clocked serial interface which achieves synchronization by transmission/reception of a clock. The CSI is a subset of the standard serial bus interface specification for NEC single-chip microcontrollers, and I2C functions are not supported. The wake-up release function is implemented by using macro service. Table 7-1. Supported Protocols Supported Protocols Serial Interface Unit Clocked (CSI) Asynchronous SBI IOE (UART) Channel 0 Yes Yes Yes Channel 1 No Yes Yes The UART function or CSI function can be programmably selected for each channel. Protocol selection is performed by means of the protocol selection register (ASP). 50 µPD70433 7.3 UART 7.3.1 Features • Transfer rate: 95 to 390 Kbps (with 12.5 MHz system clock φ) 123 to 500 Kbps (with 16 MHz system clock φ) • Full-duplex operation capability • On-chip dedicated (transmission and reception) baud rate generators • Wake-up function • Zero parity function • Parity error detection • Framing error detection • Overrun error detection • Three dedicated UART interrupt sources • UART receive error interrupts (INTSER0, INTSER1) • UART reception interrupts (INTSR0, INTSR1) • UART transmisstion interrupts (INTST0, INTST1) • Macro service function • UART reception interrupts (INTSR0, INTSR1) • UART transmission interrupts (INTST0, INTST1) Figure 7–1. UART Block Diagram INTSRn T×B R×B INTSTn UARTM R×Dn Shift Register Reception Control Parity Check UARTS ERP ERF ERO INTSERn T×C* * External Clock Control AS Shift Register T×Dn Transmission Control Parity Addition CTS Transmit Serial Clock Receive Serial Clock Channel 0 only 51 µPD70433 7.4 CLOCKED SERIAL INTERFACE (CSI) 7.4.1 Features • Transfer speed: Max. 3.125 Mbps (with 12.5 MHz system clock φ) Max. 4.0 Mbps (with 16 MHz system clock φ) • Half-duplex communication • Data length: 8-bit unit • External/internal clock selection function • Data MSB-first/LSB-first selection function • SBI mode (2-wire NEC type serial bus) ... ch0 only • Address/command/data identification function • Function for chip selection by address • Wake-up function • Acknowledge signal (ACK) control function • Busy signal (BUSY) control function The V55PI clocked serial interface has the following two operating modes. (1) 3–wire serial I/O mode (IOE mode) In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK), and serial data input and output (SI, SO). This mode is useful when connecting an I/O device, display controller, etc., which incorporates a conventional clocked serial interface. The functions of the V25 and V25+ have been enhanced, and data MSB-first/LSB-first selection is possible. (2) Serial bus interface mode (SBI mode) In the SBI mode, communication is performed with multiple devices by means of two lines: the serial clock (SCK) and the serial bus interface (SB0 or SB1). This mode conforms to the NEC serial bus format. In the SBI mode, the sender can output to the serial data bus an address to select the target device for serial communication, a command which gives a directive to the target device, and actual data. Thus there is no need for the line for handshaking required when multiple devices are connected with a conventional clocked serial interface, allowing input/output ports to be used efficiently. In addition, wake-up release is performed using macro service. 52 µPD70433 8. PARALLEL INTERFACE FUNCTIONS The V55PI incorporates a parallel interface unit for data input on a Centronics specification interface, and general data input/output. 8.1 FEATURES The following features are provided as parallel interface functions: • Centronics specification interface compatibility • Input/output mode switchable by software • BUSY signal manipulable by software • BUSY signal and ACK signal output timing settable • Initialization by external interrupt • Dedicated parallel interface interrupt source • Parallel interface interrupt (INTPAI) • DMA request signal generation in parallel transmission/reception • INTPAI functions as a DMA start trigger. • Signal pin input/output characteristic is TTL level (Centronics specification interface) 53 µPD70433 Figure 8-1. Parallel Interface Block Diagram (a) Input mode Input Data Latch PD0–PD7 OE DATASTB IBF S R Q Internal Bus MB0, 1 DATA RD DMA Request BUSY Control Circuit BUSY ACK Control Circuit ACK PAI Timer Counter RESET (b) ACK Timing Control INTP5 IBSY S R Output mode Output Data Latch DATA WR PD0–PD7 WR Internal Bus PAI Timer DATASTB Counter DMA Request INTPAI Request INT/ DMA Request Control BUSY ACK 54 µPD70433 9. TIMER FUNCTION The V55PI timer unit can be used as an interval timer, free-running timer and event counter. It is also possible to manipulate P7 as a real-time output port, synchronized with interrupt requests generated by the timer. The normal timer function and real-time output port function are described here. 9.1 FEATURES The timer function offers the following features. • 16-bit timer × 4 • Two count clock sources are selectable • System clock scaled output selectable (φ/8, φ/32: system clock φ) • External input pulses from TI pin • External count output signal (TOn output) • Three 16-bit capture registers on chip (external interrupt input signals INTP0 to INTP2 as triggers) • Six dedicated timer unit interrupt source (INTCM00, INTCM01, INTCM10, INTCM11, INTCM21, INTCM31) • Real-time output port function synchronized with timer interrupts 9.2 TIMER UNIT CONFIGURATION The timer unit configuration is shown in Figure 9-1, and the function of each timer in Table 9-1. Table 9-1. Timer Functions Timer 0 Timer 1 Timer 2 Timer 3 Count function Available Available Available Available Capture function Available Available Not Available Not Available Compare function Available Available Available Available Available Not Available Available Not Available Not Available Not Available Available Available Not Available Not Available Function Timer output function Cascading Toggle output Set/reset output Available 55 56 Figure 9-1. Timer Unit Block Diagram Timer 1 Timer 0 φ/8 16–Bit Free Running Timer (TM0) INTP0 Capture Register (CT00) INTP1 Capture Register (CT01) TI OVF φ/8 INTP2 Compare Register (CM00) INTCM00 Compare Register (CM01) INTCM01 T TO00 T TO01 16–Bit Timer Register/Event Counter 1 (TM1) OVF Clear Capture Register (CT10) Compare Register (CM10) INTCM10 Compare Register (CM11) INTCM11 To Real–Time Output Port Timer 3 Timer 2 φ/8 φ/32 φ/8 Clear 16–Bit Timer Register 2 (TM2) INTCM21 φ/32 16–Bit Timer Register 3 (TM3) INTCM31 Clear Clear, Count Enable Compare Register (CM20) S Compare Register (CM21) R Compare Register (CM22) S Compare Register (CM23) R Q TO20 Compare Register (CM30) S Compare Register (CM31) R Q TO30 Q TO21 T µPD70433 To DMA Controller µPD70433 9.3 REAL-TIME OUTPUT PORT FUNCTION Port 7 of the V55PI incorporates a real-time output port function, and can output the contents of the port 7 buffer (P7H, P7L) at programmable intervals from timer 0 bit-wise. 9.3.1 Real-Time Output Port Configuration The real-time output port configuration is shown in Figure 9-2. It comprises the following buffer registers, output and control registers. (1) Port 7 buffer (P7H, P7L) The buffer registers hold the data to be output next when port 7 is set to the real-time output port mode. The port 7 buffer contents are not affected by reset input. (2) Real-time output port (RTP) Real-time output port output data is held in this port after being taken from the port 7 buffer, and output from the pins. RTP can be read or written to by an 8-bit or single-bit manipulation instruction (unlike the port 7 output port). (3) Real-time output port delay specification regiser (RTPD) and delay counter This register is set and used when using the mode in which a delay time is inserted in the timing for output from the real-time output port (RTP) to the output pins. If the P7L bit is set to "0", "0" is output to the corresponding output pin bit after the elapse of the delay time equivalent to the count clock cycle time set in the real-time output port delay specification register after the time at which the transfer trigger is generated. The delay time in this case is counted by the delay counter. (4) Real-time output port control register (RTPC) RTPC specifies the operating mode of the real-time output port. It is possible to specify whether or not a delay is to be inserted when data is output, the timing for transferring data to the port 7 buffer, the transfer timing trigger, and so on. 57 58 Figure 9–2. Real–Time Output Port Operation RTPC Real–Time Output Port Control Register TRG, BYTE DLY 8 Internal Bus P7L Port 7 Buffer INTCM00 (Timer 0) Selector P7H Port 7 Buffer Output Latch RTP Bit 3 INTCM01 (Timer 1) Borrow Delay Counter φ /2 Preset Q S R RTPD Delay Delay Specification Register No Delay Output Latches RTP7 to RTP4 To Port 7 P77 P76 P75 P74 P73 P72 P70 µPD70433 Control Output Signals P71 µPD70433 9.3.2 Real-Time Output Port Operation Real-time output port specification is performed bit-wise by the port 7 mode control register (PCM7). Port 7 (P7), the port 7 buffer (P7H, P7L) and the real-time output port can be accessed as real-time output ports. Data output is performed as described below. When output data is written in the port 7 buffer (P7H, P7L), the port 7 buffer contents are transferred to the real-time output port (RTP) and output to the pins in synchronization with the timing of an interrupt request from timer 0 (INTCM00, INTCM01), or a write to the TRG bit in the control register (RTPC). An example of the direct control of the output pattern for a real-time output port and the output interval is shown in Figure 9-3. Update data is transferred from the two data storage areas set beforehand in the external memory space to the realtime output function buffer registers (P7H, P7L) and compare registers (CM00, CM01). Figure 9-3. Real-Time Output Port Stepping Motor Control Register File Space Output Data Pointer Buffer Register Address External Memory Space Compare Register Address +1 Output Data Area D1 Output Timing Data Pointer D2 RC Initial Value D3 Real–Time Output Counter (RC) D4 T1 Macro Service Counter –1 –1 T2 Output Timing Data Area Mode Register Channel Pointer T3 T4 Transfer or Addition Transfer Macro Service Control Word Internal Bus Real-Time Output Port Timer 0 Macro Service Processing Compare Register CM00 or CM01 RTP f CLK/8 INTCM00 or INTCM01 Output Latch Interrupt Request Match Buffer Register P7H, P7L Real-Time Output Trigger/ Macro Service Activation Free Running Timer TM0 Stepping Motor 59 µPD70433 In particular, it is possible to insert a delay time in the timing for output by setting the real-time output port delay specification register (RTPD) pins. If the P7L bit is changed from "1" to "0", it is possible to perform output after inserting a delay time of 2 × the system clock set in the RTPD from the timing at which the transfer trigger is generated. In this case, "0" is output from the corresponding output pin. This delay is counted by the delay counter. 60 µPD70433 10. PWM UNIT The V55PI is provided with an 8-bit precision PWM (pulse width modulation) signal output function. PWM output can be used as a digital-to-analog conversion output by connecting a low-pass filter, etc., externally. This is ideal for the actuator control signal for motors, etc. 10.1 FEATURES The PWM unit offers the following features: • PWM output pulse active level selectable • Frequency: 25 MHz (with 12.5 MHz system clock φ) → PWM cycle: 40.96 µs : 32 MHz (with 16 MHz system clock φ) → PWM cycle: 32.00 µs • Output pulse width (duty): 0, 1/256, ....., 255/256 → Resolution: 160 ns (with 12.5 MHz system clock φ) 125 ns (with 16 MHz system clock φ) 10.2 PWM UNIT CONFIGURATION The configuration of the PWM unit is shown in Figure 10-1. The PWM unit consists of the PWM register (PWM) and PWM control register (PWMC), and an 8-bit counter. The PWM register controls the pulse width (duty) in the PWM output mode. The 8–bit counter is set to 00H by reset input. The PWM register is not affected by reset input. 61 62 Figure 10-1. PWM Unit Block Diagram 8-Bit Counter Overflow S Q R Q Active Level Control PWM Output Comparator Match Detection Signal PWM Slave Latch Preset PWM Register 0 0 0 0 0 0 CE ALV PWM Control Register Internal Bus µPD70433 µPD70433 11. WATCHDOG TIMER FUNCTION The watchdog timer is a function for preventing inadvertent program looping and deadlocks. 11.1 FEATURES • Three overflow times settable (8.1, 32.7, 131.0 [ms]: system clock φ = 16 MHz) (10.4, 41.9, 167.7 [ms]: system clock φ = 12.5 MHz) • Output pin provided (WDTOUT pin) which can be directly connected to the RESET pin 11.2 WATCHDOG TIMER CONFIGURATION AND OPERATION Non-generation of a watchdog timer interrupt enables normal operation of the program or system to be confirmed. To use the watchdog function, an instruction (RSTWDT) to clear the watchdog timer (start the count) must be included in at fixed intervals in the program execution time, at the start of a subroutine, etc. If the instruction which clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a watchdog timer interrupt (INTWDT) is generated and the low-level signal is output to the WDTOUT pin to report a program error. The watchdog timer configuration is shown in Figure 11-1. Figure 11-1. Watchdog Timer Configuration Diagram φ *1 Frequency Divider φ /2 9 φ /2 11 φ /2 13 Watchdog Timer (8 bits) Overflow WDTOUT Active Timer (5 bits) OVF S Q WDTOUT R Clear INTWDT WDTCLR *2 RESET STOP Oscillation Stabilizing Time Control Circuit * 1. φ: System clock 2. WDTCLR: Watchdog timer clearance by instruction 63 µPD70433 12. A/D CONVERTER FUNCTION The V55PI incorporates a high-speed, high-precision 8-bit analog/digital (A/D) converter with four analog inputs (ANI0 to ANI3). The A/D converter uses the successive approximation method, and is provided with four A/D conversion result registers (ADCR0 to ADCR3) which hold the conversion results. 12.1 FEATURES The A/D converter offers the following features: • Incorporates four 8-bit A/D conversion result registers. • Four analog input pins (ANI0 to ANI3) • Two A/D converter conversion operating modes • Scan mode : Performs conversion by selecting multiple analog inputs in sequence. • Select mode : Performs continuous conversion with only one pin used as the analog input. • Two conversion start methods • Hardware start : Started by trigger input (INTP4) • Software start : Started by A/D converter mode register (ADM) bit setting • Generation of conversion end interrupt request (INTAD) 64 Figure 12-1. A/D Converter Block Diagram Series Resistance String R/2 ANI0 Sample & Hold Circuit Tap Decoder ANI1 ANI2 ANI3 Input Circuit AVREF R R/2 AVSS P15/INTP4 External Trigger Comparator AVDD A/D Converter Mode Register (ADM) Successive Approxi8 mation Register (SAR) 8 8 Internal Bus Control A/D Conversion Result Register 0 (ADCR0) A/D Conversion Result Register 1 (ADCR1) A/D Conversion Result Register 2 (ADCR2) INTAD A/D Conversion Result Register 3 (ADCR3) 65 µPD70433 Internal Bus µPD70433 13. STANDBY FUNCTIONS The V55PI has two methods for controlling the operating clock as standby functions designed to reduce power dissipation. Transition to either of these standby modes is possible by means of a dedicated instruction. Table 13-1. HALT/STOP Mode Operating Status Parameter HALT Mode Clock generator Operating Internal system clock Stopped STOP Mode 16–bit timer Watchdog timer Hold circuit Stopped Serial interface Operating Parallel interface A/D Converter Interrupt request controller DMA controller IORD, IOWR High level High level Change accordng to DMAC operating status Retained R/W output High level High level Refresh operation Operating Stopped Data retention All internal data retained (CPU status, RAM contents, etc.) All internal data retained (CPU status, RAM contents, etc.) Release method • • • • • NMI • RESET input AD0 to AD15 Bus lines A16 to A23 NMI INTWDT Maskable interrupt request RESET input 13.1 HALT MODE In this mode, the CPU operating clock is halted. Setting the CPU idle time to the HALT mode enables overall system power dissipation to be reduced. The HALT mode is entered by executing the HALT instruction. In the HALT mode the CPU clock and program execution are stopped, and all register and on-chip RAM contents immediately prior to the stoppage are retained. The status of each hardware unit is shown in Table 13-1. When the HALT instruction is executed during a DMA transfer, transition to the HALT mode is deferred until the transfer bus cycle for one DMA request is completed. 66 µPD70433 13.2 STOP MODE In this mode, clock oscillation is stopped. This is effective when the entire application system is stopped, and offers extremely low power dissipation. The STOP mode is entered by executing the STOP instruction. In this mode all clocks are stopped. Program execution is stopped, and all register and on-chip RAM contents immediately prior to the stoppage are retained. The status of each hardware unit is shown in Table 13-1. When the STOP instruction is executed during a DMA transfer, transition to the STOP mode is deferred until the transfer bus cycle for one DMA request is completed. If there is contention between a refresh cycle and STOP instruction execution, transition to the STOP mode is deferred until the refresh cycle is completed. 67 µPD70433 14. CLOCK GENERATOR The clock generator supplies various clocks to the CPU and peripheral hardware, and controls the CPU operating mode. 14.1 CLOCK GENERATOR CONFIGURATION AND OPERATION The clock generator is configured as shown in Figure 14-1. The clock generator clock is generated by a crystal resonator or ceramic resonator connected to the X1 and X2 pins. The clock generator output is subjected to waveform shaping (dividing frequency by 2) and selection of the scaling factor by means of the processor control register (PRC), and is then used as the system clock φ. The system clock φ scaling factor is specified by the PCK1 and PCK0 bits of the PRC register, and can be selected as 1/2, 1/4, 1/8 or 1/16 the oscillator frequency (fXX). Selecting a low-speed system clock φ reduces the current consumption of internal circuit, allowing extended operation of a battery-driven system even when the voltage drops. An external clock can be input. In this case, the clock signal should be input to the X1 pin, and leave the X2 pin open. Figure 14-1. Clock Generator Waveform Shaping Frequency Dividers f 1 16 f XX XX Clock Oscillator 1/2 1/2 X2 1/2 1/2 1 8 f XX 1 4 f XX Selector X1 φ (=f X ) Time Base Counter Software Interval Timer Refresh Cycle Generator PWM Baud Rate Generator 1 2 f XX PRC PCK0 Internal Bus 8 PCK1 TB0 TB1 0 ENCLK 1 1 fXX : Oscillator frequency φ : System clock PRC : Processor control register 68 Watchdog Timer System Clock CLKOUT µPD70433 In the V55PI, the frequency divider (time base counter: TBC) which divides the internal system clock φ is shared by each timer unit. The TBC cannot be read or written to by an instruction. The TBC tap output (divide-by-2n clock) is supplied to the units shown below as a count clock. (1) Refresh cycle generator (2) (3) Software interval timer PWM unit (4) Baud rate generator The TBC is cleared to 00H only by reset input, after which it is constantly incremented. TBC operation is stopped in the STOP mode. The configuration of the TBC is shown in Figure 14-2. Figure 14-2. Frequency Divider (Time Base Counter, TBC) Configuration φ TBC φ /2 to φ /2 9 φ /2 to φ /2 8 φ /2 3 to φ /2 9 φ /2 2 and φ /2 7 PWM Baud Rate Generator Refresh Cycle Generator Software Interval Timer 69 µPD70433 15. SOFTWARE INTERVAL TIMER FUNCTION The V55PI incorporates a 16-bit software interval timer as a timer for software timer functions and watch functions. 15.1 SOFTWARE INTERVAL TIMER CONFIGURATION The configuration of the software interval timer is shown in Figure 15-1. Figure 15-1. Software Interval Timer Configuration φ /4 φ /128 Clear Software Timer Counter (STC) Software Timer Counter Compare Register (STMC) INTSIT Match Detection 70 µPD70433 16. CODEC INSTRUCTIONS The V55PI has 9 codec instructions. Using these special instructions on the V55PI enables not only image information MH encoding but also MR encoding which previously required the use of a special device such as an ACEE (advanced compression/expansion engine) to be implemented by means of a small-scale, high-speed codec. 16.1 FEATURES The V55PI has the following 9 codec instructions (4 for compression, 5 for expansion): • Compression instructions (1) Change point table creation instruction: COLTRP (2) Data transmission instruction (transmission of EOL *1, FILL, RTC *2, etc.): ALBIT (3) MH encoding instruction: MHENC (4) MR encoding instruction: MRENC • Expansion instructions (5) EOL detection instruction: SCHEOL (6) 1-bit (tag) detection instruction: GETBIT (7) MH decoding change point table creation instruction: MHDEC (8) MR decoding change point table creation instruction: MRDEC (9) Pixel data creation instruction: CNVTRP MH/MR encoding and MH/MR decoding using these instructions are performed as shown in Figures 16-1 and 16-2. * 1. 2. Note EOL: End Of Line RTC: Return To Control When compression/expansion processing is performed using the V55PI codec instructions, the following should be specified as preconditions. • Compression/expansion is to be performed line by line. • Consideration must be given to task switching and interrupt generation during compression processing. • The number of bits processed per line must not be changed during processing of one page. • The segment value must be changed for data over 64 Kbytes that straddles segments during processing. 71 µPD70433 Figure 16-1. MH/MR Encoding Processing Flow Start K=0 L = Number of lines K=0 No Yes Data transmission instruction (EOL + tag bit "1" transmission) Data transmission instruction (EOL + tag bit "0" transmission) Change point table creation instruction Change point table creation instruction MH encoding instruction MR encoding instruction K = K factor – 1 K=K–1 Data transmission instruction (FILL transmission) L=L–1 No L=0 Yes Data transmission instruction (RTC transmission) End 72 µPD70433 Figure 16-2. MH and MR Decoding Processing Flow Start EOL detection instruction Error detection Yes To Error Processing No 1–bit detection instruction (tag bit detection) Tag = 1 No Yes MH decoding instruction MR decoding instruction * Yes EOL detection at start EOL detection at start No No Yes End Pixel data creation instruction * Yes Error detection Error detection No Yes To Error Processing End No Pixel data creation instruction RTC is detected by two EOLs. 73 µPD70433 16.2 MEMORY MAP The data memory areas required by the V55PI's codec instructions are shown below. (1) Register file space This is the register bank for parameter setting. (2) User RAM Encoding line change point table : Storage area for change point information required for performing encoding Reference line table In the case of n bit/lines, a maximum area of 2n + 4 bytes is required. : Reference line change point information storage area Image data buffer : Storage area for pixel data read from scanner in encoding, or encoding data received from modem in decoding Transmit/receive buffer Print buffer : Buffer for transferring encoded data to modem/scanner : Buffer for transferring decoded pixel data to recording system (3) User ROM Encoding conversion table : Conversion table for MH/MR encoding Decoding conversion table : Conversion table for MH/MR decoding (4) Access to Expanded Memory Space The 16-Mbyte expanded memory space can be accessed by using the expanded segment override prefix instruction (DS2: or DS3:). However, the segment registers DS2 and DS3 that are used during instruction execution are DS2 and DS3 in the parameter setting register banks of each instruction. Table 16-1. Instructions to which Expanded Segment Override Prefix Can Be Attached DS2: DS3: CODEC Instruction Yes Yes COLTRP Yes No MHENC Yes Yes MHDEC Yes No MRENC Yes Yes MRDEC Yes No SCHEOL Yes No GETBIT Yes Yes CNVTRP Example DS2 : DS3 : COLTRP DS2 : SCHEOL The relationship between encoding instructions and data in memory is shown in Figure 16-3, and the relationship between decoding instruction and data in memory is shown in Figure 16-4. 74 µPD70433 Figure 16-3. Encoding Instructions and Data in Memory DMA Register File Software Parameter Frame User RAM Data Output Instruction Image Data (1 Line) Change Point Table Creation Instruction MH/MR Encoding Instruction Work (Change Points) Coding Data (1 Line) User ROM Encoding Conversion Table (512 Bytes) * * In case of MH/MR encoding instructions Figure 16-4. Decoding Instruction and Data in Memory DMA Register File Parameter Frame Software EOL Detection Instruction User RAM Coding Data 1–Bit Detection Instruction MH/MR Decoding Instruction Image Data Creation Instruction User ROM Work (Change Points) Image Data (1 Line) Decoding Conversion Table (2304 Bytes)* * In case of MH/MR decoding instructions 75 µPD70433 16.3 PROCESSING FLOW The instructions shown in 16.1 "Features" are used in the order shown in Figures 16-5 and 16-6 in encoding/decoding procesing. Figure 16-5. Processing Flow for Encoding of One Line Start Data transmission instruction (ALBIT) Transmission of EOL and tag (Pixel Data) ..... Change point table creation instruction (COLTRP) Change point information for 1 line created, and stored in prescribed storage area (change point table) Input Output (Change Point Table) Black Black Black Black White White White White 0 2 1 1 3 1 1 6 1 Word Input MH/MR encoding instruction (MHENC/MRENC) MH/MR encoding for 1 line Encoded Data → Transmision Buffer Fill transmission End 76 ..... µPD70433 Figure 16-6. Processing Flow for Decoding of One Line Start EOL detection instruction (SCHEOL) EOL (000000000001) is detected 1 bit detection instruction (GETBIT) Tag (1 bit) is detected Encoded Data ← Printer Buffer MH/MR decoding instruction (MHDEC/MRDEC) MH/MR decoding change point information for 1 line is generated and stored in specified area (change point table) Input Output (Change Point Table) Black Black Black Black White White White White 0 2 1 1 3 1 1 6 ..... 1 Word Pixel data creation instruction (CNVTRP) Input Pixel data for 1 line is created Output (Pixel Data) End ..... 77 µPD70433 17. INSTRUCTION SET The V55PI instruction set is upward compatible with the V20/V30 (native mode) and V25/V35 instruction sets. 17.1 INSTRUCTIONS NEWLY ADDED TO V20/V30 AND V25/V35 Instructions which have been added to the V20/V30 and V25/V35 instruction sets, and instructions whose application range has been extended, are shown below. (1) Instructions added to V20/V30. Mnemonic Operand BRKCS reg 16 TSKSW reg 16 MOVSPA None MOVSPB reg 16 BTCLR sfr, imm3, short-label RETRBI None FINT None STOP None Instruction Group Register bank switching instruction Data transfer instruction Conditional branch instruction Interrupt instruction 78 CPU control instruction µPD70433 (2) Instructions added to V25/V35. Mnemonic Operand IRAM None DS2 None DS3 None Instruction Group Register file space access override prefix instrution Extended segment override prefix instruction DS2, reg16, mem32 DS3, reg16, mem32 xsreg, reg16 MOV Data transfer instruction xsreg, mem16 reg16, xsreg mem16, xsreg DS2 PUSH DS3/VPC Stack manipulation instruction DS2 POP DS3/VPC RSTWDT imm8, imm8’ Watchdog timer manipulation instruction BTCLRL sfrl, imm3, short-label Conditional branch instruction reg8 mem8 BSCH Bit manipulation instruction reg16 mem16 QHOUT imm16 QOUT imm16 QTIN imm16 ALBIT None COLTRP None MHENC None MRENC None SCHEOL None GETBIT None MHDEC None MRDEC None CNVTRP None Remark Queue manipulation instruction Dedicated FAX instruction VPC: Vector PC 79 µPD70433 17.2 INSTRUCTION SET OPERATIONS Table 17-1. Operand Type Legend Identifier reg, reg’ reg8, reg8' reg16, reg16' mem mem8 mem16 mem32 sfr sfrl dmem imm imm3 imm4 imm8 imm8' imm16 acc sreg xsreg src-table src-block dst-block src-string dst-string near-proc far-proc near-label short-label far-label regptr16 memptr16 memptr32 pop-value fp-op repeat IRAM : R () or, / 80 Description 8/16-bit general register (Destination register in an instruction using two 8/16-bit general registers) Source register in an instruction using two 8/16-bit general registers 8-bit general register (Destination register in an instruction using two 8-bit general registers) Source register in an instruction using two 8-bit general registers 16-bit general register (Destination register in an instruction using two 16-bit general registers) Source register in an instruction using two 16-bit general registers 8/16-bit memory address 8-bit memory address 16-bit memory address 32-bit memory address Special function register location: FFF00H to FFFEFH Special function register location: FFE00H to FFEFFH 16-bit direct memory address 8/16-bit immediate data 3-bit immediate data 4-bit immediate data 8-bit immediate data 8-bit immediate date (1’s compliment of imm8) 16-bit immediate data Accumulator AW or AL Segment register Extended segment register Name of 256-byte conversion table Name of source block addressed by register IX Name of destination block addressed by register IY Name of source string addressed by register IX Name of destination string addressed by register IY Procedure start address in current program segment Procedure start address in a different program segment Absolute address in current program segment Relative address of memory in range –128 to +127 bytes from end of instruction Absolute address in a different program segment 16-bit general register holding call address offset in current program segment 16-bit memory address holding call address offset in current program segment 32-bit memory address holding call address offset and segment data in a different program segment Number of bytes removed from stack (0 to 64K, normally an even number) Immediate value which identifies external floating point operation coprocessor operation code Repeat prefix instruction Register file space access override prefix instruction Register set (AW, BW, CW, DW, SP, BP, IX, IY) Omissible Or µPD70433 Table 17-2. Operation Code Legend Identifier W reg, reg’ mod, mem (disp-low) (disp-high) disp-low disp-high imm3 imm4 imm8 imm8' imm16-low imm16-high addr-low addr-high sreg xsreg s offset-low offset-high seg-low seg-high pop-value-low pop-value-high disp8 X XXX YYY ZZZ Description Word/byte specification bit (1: word, 0: byte). However, when s = 1, sign extension byte data is specified as 16-bit operand even if W = 1. 8/16-bit general register specification bits (000 to 111) Memory addressing specification bits (mod: 00 to 10, mem: 000 to 111) Optional 16-bit displacement low byte Optional 16-bit displacement high byte 16-bit displacement low byte for PC relative addition 16-bit displacement high byte for PC relative addition 3-bit immediate data 4-bit immediate data 8-bit immediate data 8-bit immediate data (1's complement of imm8) 16-bit immediate data low byte 16-bit immediate data high byte 16-bit direct address low byte 16-bit direct address high byte Segment register specification bits (00 to 11) Extended segment register specification bits (10 to 11) Sign extension specification bit (1: sign extension, 0: no sign extension) Low byte of 16-bit offset data to be loaded in PC High byte of 16-bit offset data to be loaded in PC Low byte of 16-bit segment data to be loaded in PS High byte of 16-bit segment data to be loaded in PS Low byte of 16-bit data which specifies number of bytes to be removed from stack High byte of 16-bit data which specifies number of bytes to be removed from stack 8-bit displacement for relative addition to PC Operation code of an external floating point operation coprocessor 81 µPD70433 Table 17-3. Operation Description Legend Identifier AW AH AL BW CW CL DW SP BP PC PSW IX IY PS DS3 DS2 DS1 DS0 SS AC CY P S Z IE V IBRK BRK RB0 RB1 RB2 RB3 VPC (...) disp temp ext–disp8 seg offset ← + − × ÷ % ∧ ∨ V ××H ××××H / 82 Description Accumulator (16 bits) Accumulator (high byte) Accumulator (low byte) Register BW (16 bits) Register CW (16 bits) Register CL (low byte) Register DW Stack pointer (16 bits) Base Pointer (16 bits) Program counter (16 bits) Program status word (16 bits) Index register (source) (16 bits) Index register (destination) (16 bits) Program segment register (16 bits) Extended data segment 3 register (16 bits) Extended data segment 2 register (16 bits) Data segment 1 register (16 bits) Data segment 0 register (16 bits) Stack segment register (16 bits) Auxiliary carry flag Carry flag Parity flag Sign flag Direction flag Interrupt enable flag Overflow flag I/O break flag Break flag Register bank 0 flag Register bank 1 flag Register bank 2 flag Register bank 3 flag Vector PC Contents of memory indicated by contents of in parenthesis Displacement (8/16-bit) Temporary register (8/16/32 bits) 16 bits with 8-bit displacement sign-extended Immediate segment data (16 bits) Immediate offset data (16 bits) Transfer direction Addition Subtraction Multiplication Division Modulo Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) 2-digit hexadecimal number 4-digit hexadecimal number Alternate function, or µPD70433 Table 17-4. Flag Operation Legend Identifier (Blank) 0 1 × U R Description No change Cleared to 0 Set to 1 Set or cleared depending on result Undefined Previously saved value is restored Table 17-5. Memory Addressing mem Note mod 00 01 10 000 BW + IX BW + IX + disp8 BW + IX + disp16 001 BW + IY BW + IY + disp8 BW + IY + disp16 010 BP + IX BP + IX + disp8 BP + IX + disp16 011 BP + IY BP + IY + disp8 BP + IY + disp16 100 IX IX + disp8 IX + disp16 101 IY 110 111 IY + disp8 IY + disp16 Direct address BP + disp8 BP + disp16 BW BW + disp8 BW + disp16 When BP is used in memory addressing other than in a primitive instruction, the default segment register is SS. When BP is not used, the default segment register is DS0. In primitive instruction memory addressing, the destination block default segment register is DS1. In memory addressing, the source block default segment register is DS0. Table 17-6. 8/16-Bit General Register Selection Table 17-7. Segment Register Selection reg W=0 W=1 sreg 000 AL AW 00 DS1 001 CL CW 01 PS 010 DL DW 10 SS 011 BL BW 11 DS0 100 AH SP 101 CH BP 110 DH IX 111 BH IY Table 17-8. Extended Segment Register Selection xsreg 10 DS3/VPC 11 DS2 83 µPD70433 Number of Clock Cycles In the case of a memory operand the number of clock cycles depends on the addressing mode. The following numbers should be used for “EA” in Table 17-9 “Number of Clock Cycles”. mod 00 mem 000 001 010 011 100 101 110 111 BW + IX BW + IY BP + IX BP + IY IX IY Direct address BW Clock Cycles 3 3 3 3 2 2 2 2 01 BW + IX + disp8 BW + IY + disp8 BP + IX + disp8 BP + IY + disp8 IX + disp8 IY + disp8 BP + disp8 BW + disp8 Clock Cycles 3 3 3 3 2 2 2 2 10 BW + IX + disp16 BW + IY + disp16 BP + IX + disp16 BP + IY + disp16 IX + disp16 IY + disp16 BP + disp16 BW + disp16 Clock Cycles 3 3 3 3 2 2 2 2 “T” indicates the number of wait states. Any number of wait states from "0" (no wait) up can be used. 84 µPD70433 Mnemonic Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (1/20) On-Chip RAM Access reg, reg' –– 2 2 2 2 mem, reg –– EA + 2 EA + 3 EA + 2 EA + 3 EA + 2 EA + 5 + T EA + 2 Operands Byte Processing Word Processing Other Access On-Chip RAM Access Other Access 8 reg, mem EA + 8 + 2T 16 EA + 5 + T mem, imm –– EA + 2 EA + 3 EA + 2 EA + 3 reg, imm –– 2 2 2 2 4 7+T 4 8 acc, dmem 10 + 2T Data transfer instructions 16 dmem, acc –– 4 5 4 5 sreg, reg16 –– –– –– 2 2 –– –– 2 2 –– –– EA + 2 xsreg, reg16 VPC, reg16 8 16 8 MOV sreg, mem16 EA + 8 + 2T 16 xsreg,mem16/ VPC, mem16 reg16, sreg reg16, xsreg/ reg16, VPC mem16, sreg mem16, xsreg/ mem16, VPC DS0, reg16, mem32 DS2, reg16, mem32 DS1, reg16, mem32 DS3, reg16, mem32 * 7+T EA + 5 + T 8 EA + 8 + 2T –– –– EA + 2 16 –– EA + 5 + T –– –– 2 2 –– –– 2 2 –– –– EA + 2 EA + 3 –– –– EA + 2 EA + 3 –– –– EA + 5 8 16 –– 8 16 8 EA + 17 + 4T 16 EA + 11 + 2T 8 EA + 17 + 4T –– –– EA + 5 16 EA + 11 + 2T 8 EA + 17 + 4T –– –– EA + 5 16 EA + 11 + 2T 8 EA + 17 + 4T –– –– 16 EA + 5 EA + 11 + 2T 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 85 µPD70433 Mnemonic Operands AH, PSW MOV Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (2/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 2 2 –– –– 8 3 3 –– –– 16 2 2 Byte Processing Word Processing Data transfer instructions PSW, AH LDEA reg16, mem16 –– –– –– EA + 2 EA + 2 TRANS/ TRANSB src-table –– 6 9+T –– –– reg, reg' –– 4 4 4 4 EA + 4 EA + 7 + T EA + 4 AW, reg16/ reg16, AW EA + 7 + T –– –– –– 4 4 –– –– –– 8 8 –– –– –– 9 9 REPC –– 0 to 1 0 to 1 0 to 1 0 to 1 REPNC –– 0 to 1 0 to 1 0 to 1 0 to 1 REP/ REPE/ REPZ –– 0 to 1 0 to 1 0 to 1 0 to 1 REPNE/ REPNZ –– 0 to 1 0 to 1 0 to 1 0 to 1 21 + 2T 22 + 2T 18 + T 19 + T 9 + (14 + 2T)n 9 + (18 + 4T)n 5 5 18 + T 19 + T 9 + (11 + T)n 9 + (12 + 2T)n 5 5 23 + 2T 28 + 4T 9 + (16 + 2T)n 9 + (21 + 4T)n 5 5 20 + T 22 + 2T 9 + (13 + T)n 9 + (15 + 2T)n 5 5 MOVSPA MOVSPB Repeat prefixes EA + 10 + 2T mem, reg/ reg, mem XCH MOVBK reg16 dst-block, src-block Primitive block transfer instructions 8 (rep) 9 + (11 + T)n MOVBKB/ MOVBKW 16 CMPBK src-block, dst-block (rep CW = 0) 5 5 20 + T 22 + 2T 8 (rep) 9 + (13 + T)n CMPBKB/ CMPBKW 16 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width Remark 86 n: Number of repetitions 9 + (15 + 2T)n (rep CW = 0) 5 * 9 + (12 + 2T)n 5 µPD70433 Mnemonic CMPM Operands Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (3/20) Byte Processing Word Processing On-Chip RAM Access Other Access On-Chip RAM Access 15 17 + T 15 dst-block 20 + T 8 5 10 + (9 + T)n 10 + 7n 17 + T 16 Primitive block transfer instructions 10 + (12 + 2T)n (rep) 10 + 7n CMPMB/ CMPMW LDM (rep CW = 0) 10 + (9 + T)n 5 5 5 10 13 + T 10 src-block 9 + (9 + 2T)n (rep) 9 + 3n LDMB/ LDMW 5 9 + (6 + T)n 9 + 3n 13 + T 16 (rep CW = 0) 9 + (6 + T)n 5 5 5 12 13 12 dst-block 9 + (9 + 2T)n (rep) 9 + 5n STMB/ STMW 5 9 + (6 + T)n 9 + 5n 13 16 (rep CW = 0) 9 + (6 + T)n 5 5 5 –– –– 22 to 63 8 Bit field manipulation instructions 5 13 8 reg8, reg8' 5 31 to 72 16 23 to 64 INS 8 reg8, imm4 31 to 72 –– –– 22 to 63 16 23 to 64 8 reg8, reg8' 19 + 2T to 48 + 4T –– –– 19 to 41 16 19 to 42 + 2T EXT 8 reg8, imm4 19 + 2T to 48 + 4T –– 16 * 5 16 + T 8 STM Other Access –– 19 to 41 19 to 42 + 2T 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width Remark n: Number of repetitions 87 µPD70433 Mnemonic Operands Bus Width *1 Instruction Group Table 17-9. Number of Clock Cycles (4/20) Byte Processing Word Processing On-Chip RAM Access Other Access On-Chip RAM Access –– 7+T –– 8 Input/output instructions acc8, imm8 Other Access 10 + 2T 16 7+T IN*2 8 acc, DW 10 + 2T –– 7+T –– 16 7+T 8 imm8, acc –– 5 –– 5 –– 5 –– 5 20 + 2T 21 + 2T 17 + T 18 + T 9 + (13 + 2T)n 9 + (17 + 4T)n 5 5 17 + T 18 + T 9 + (10 + T)n 9 + (11 + 2T)n 5 5 17 + 2T 23 + 4T 9 + (10 + 2T)n 9 + (16 + 4T)n 5 5 14 + T 17 + 2T 9 + (7 + T)n 9 + (10 + 2T)n 5 5 16 OUT*2 8 DW, acc 16 Primitive input/output instructions 8 (rep) 9 + (10 + T)n dst-block, DW INM*2 16 9 + (11 + 2T)n (rep CW = 0) 5 5 14 + T 17 + 2T 8 OUTM*2 (rep) 9 + (7 + T)n DW, src-block 16 (rep CW = 0) 5 * 1. 8 9 + (10 + 2T)n 5 : 8-bit width 16 : 16-bit width 2. When IBRK = 1. As shown in the next page when IBRK = 0. Remark 88 n: Number of repetitions µPD70433 Mnemonic Operands Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (5/20) Byte Processing On-Chip RAM Access 8 acc8, imm8 Input/output instructions On-Chip RAM Access 60 + 10T –– 16 Other Access 60 + 10T –– 40 + 5T 40 + 5T IN 8 acc, DW 60 + 10T –– 16 60 + 10T –– 40 + 5T 8 imm8, acc 40 + 5T 60 + 10T –– 16 60 + 10T –– 40 + 5T 40 + 5T OUT 8 DW, acc 60 + 10T –– Primitive input/ output instructions 16 * Other Access Word Processing 40 + 5T 8 INM dst-block, DW 40 + 5T 60 + 10T –– 16 60 + 10T –– 40 + 5T 8 DW, src-block 40 + 5T 60 + 10T –– 16 OUTM 60 + 10T –– 60 + 10T –– 40 + 5T 40 + 5T 8 : 8-bit width 16 : 16-bit width 89 µPD70433 Mnemonic Operands reg, reg' Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (6/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 Byte Processing Word Processing 8 mem, reg EA + 10 + 2T 16 EA + 7 + T 8 reg, mem ADD EA + 9 + 2T EA + 2 EA + 6 + T EA + 2 16 reg, imm –– EA + 6 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 8 mem, imm EA + 10 + 2T Addition/subtraction instructions 16 EA + 7 + T acc, imm –– 2 2 2 2 reg, reg' –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 8 mem, reg EA + 10 + 2T 16 EA + 7 + T 8 ADDC reg, mem EA + 9 + 2T EA + 2 EA + 6 + T EA + 2 16 reg, imm –– EA + 6 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 8 mem, imm EA + 7 + T acc, imm –– 2 2 2 2 reg, reg' –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 8 mem, reg EA + 10 + 2T 16 EA + 7 + T 8 reg, mem SUB EA + 9 + 2T EA + 2 EA + 6 + T EA + 2 16 reg, imm –– EA + 6 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 8 mem, imm acc, imm –– 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 2 EA + 10 + 2T 16 90 2 EA + 10 + 2T 16 * 2 EA + 7 + T 2 2 2 2 µPD70433 Mnemonic Operands reg, reg' Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (7/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 Byte Processing Word Processing Addition/subtraction instructions 8 EA + 10 + 2T mem, reg 16 EA + 7 + T 8 EA + 9 + 2T reg, mem EA + 2 EA + 6 + T EA + 2 16 SUBC reg, imm EA + 6 + T –– 2 2 2 EA + 4 EA + 7 + T EA + 4 8 EA + 10 + 2T mem, imm 16 acc, imm BCD operation instructions ADD4S SUB4S CMP4S dst-string, src-string dst-string, src-string 2 EA + 7 + T –– 2 2 2 2 6 + (15 + T)n 6 + (19 + 3T)n –– –– 6 + (16 + T)n 6 + (20 + 3T)n –– –– 6 + (15 + T)n 6 + (18 + 2T)n –– –– 8 16 8 16 8 dst-string, src-string 16 reg8 8 5 5 –– –– mem8 16 EA + 5 EA + 8 + T –– –– reg8 8 5 5 –– –– mem8 16 EA + 5 EA + 8 + T –– –– reg8 –– 2 2 –– –– EA + 3 EA + 7 + T EA + 3 ROL4 Increment/decrement instructions ROR4 8 INC mem 16 EA + 7 + T reg16 –– –– –– 2 2 reg8 –– 2 2 –– –– EA + 3 EA + 7 + T EA + 3 8 DEC mem EA + 10 + 2T 16 reg16 * EA + 10 + 2T –– EA + 7 + T –– –– 2 2 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width Remark n: Half of number of BCD digits 91 µPD70433 Mnemonic Operands reg8 Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (8/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 11 11 15 15 EA + 12 EA + 14 + T EA + 16 Byte Processing Word Processing 8 mem8 EA + 21 + 2T 16 EA + 18 + T MULU reg16 –– 11 11 15 EA + 12 EA + 14 + T EA + 16 8 mem16 EA + 21 + 2T 16 Multiplication instructions reg8 10 10 14 EA + 11 EA + 13 + T EA + 15 reg16 –– EA + 17 + T 10 10 14 EA + 11 EA + 13 + T EA + 15 8 mem16 reg16, reg16', imm16/reg16, imm16 reg16, mem16, imm1616 –– EA + 17 + T –– –– 14 –– –– EA + 15 8 EA + 17 + T –– –– 14 –– –– EA + 15 8 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 14 EA + 20 + 2T 16 –– 14 EA + 20 + 2T 16 reg16, reg16', imm8/reg16, imm8 14 EA + 20 + 2T 16 reg16, mem16, imm8 92 EA + 18 + T 8 mem8 MUL * –– 15 14 EA + 20 + 2T EA + 17 + T µPD70433 Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (9/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access 8 15/62 + 10T 15/62 + 10T 23/57 + 10T 23/57 + 10T 16 15/42 + 5T 15/42 + 5T 23/42 + 5T 23/42 + 5T 8 EA + 16/63 + 10T EA + 18 + T/63 + 10T EA + 24/58 + 10T EA + 30 + 2T/58 + 10T 16 EA + 16/43 + 5T EA + 18 + T/63 + 5T EA + 24/43 + 5T EA + 26 + T/43 + 5T 8 15/62 + 10T 15/62 + 10T 23/57 + 10T 23/57 + 10T 16 15/42 + 5T 15/42 + 5T 23/42 + 5T 23/42 + 5T 8 EA + 16/63 + 10T EA + 18 + T/63 + 10T EA + 24/58 + 10T EA + 30 + 2T/58 + 10T 16 EA + 16/43 + 5T EA + 18 + T/43 + 5T EA + 24/43 + 5T EA + 26 + T/43 + 5T 8 17/64 + 10T 17/64 + 10T 25/59 + 10T 25/59 + 10T 16 17/44 + 5T 17/44 + 5T 25/44 + 5T 25/44 + 5T 8 EA + 18/65 + 10T EA + 20 + T/65 + 10T EA + 26/60 + 10T EA + 31 + 2T/60 + 10T 16 EA + 18/45 + 5T EA + 20 + T/45 + 5T EA + 26/45 + 5T EA + 28 + T/45 + 5T 8 17/64 + 10T 17/64 + 10T 25/59 + 10T 25/59 + 10T 16 17/44 + 5T 17/44 + 5T 25/44 + 5T 25/44 + 5T 8 EA + 18/65 + 10T EA + 20 + T/65 + 10T EA + 26/60 + 10T EA + 31 + 2T/60 + 10T 16 EA + 18/45 + 5T EA + 20 + T/45 + 5T EA + 26/45 + 5T EA + 28 + T/45 + 5T 8 6 9 –– –– 16 9 –– 3 3 –– –– 8 6 6 –– –– 16 9 9 ADJ4S –– 3 3 –– –– CVTBD –– 18 18 –– –– CVTDB –– 8 8 –– –– CVTBW –– 3 3 –– –– CVTWL –– –– –– 3 3 Mnemonic Operands Byte Processing Word Processing reg8 mem8 DIVU Division instructions reg16 mem16 reg8 mem8 DIV reg16 Data conversion instructions BCD adjustment instructions mem16 * ADJBA ADJ4A ADJBS 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width Remark Figures on right of / (slash) apply in case of a divide error. 93 µPD70433 Mnemonic Operands reg, reg' Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (10/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 3 3 3 3 EA + 4 EA + 6 + T EA + 4 Byte Processing Word Processing 8 Comparison instructions mem, reg EA + 9 + 2T 16 EA + 6 + T 8 CMP reg, mem EA + 9 + 2T EA + 2 EA + 6 + T EA + 2 16 reg, imm –– EA + 6 + T 2 2 2 EA + 4 EA + 6 + T EA + 4 8 mem, imm EA + 9 + 2T Complement operation instructions 16 EA + 6 + T acc, imm –– 2 2 2 2 reg –– 2 2 2 2 EA + 3 EA + 7 + T EA + 3 8 NOT mem EA + 10 + 2T 16 reg –– EA + 7 + T 2 2 2 EA + 3 EA + 7 + T EA + 3 8 NEG mem reg, reg' –– EA + 7 + T 3 3 3 EA + 4 EA + 6 + T EA + 4 8 mem, reg/ reg, mem 16 reg, imm –– EA + 6 + T 2 2 2 EA + 4 EA + 6 + T EA + 4 Logical operation instructions EA + 6 + T acc, imm –– 2 2 2 2 reg, reg' –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 8 mem, reg EA + 10 + 2T 16 EA + 7 + T 8 reg, mem EA + 9 + 2T EA + 2 EA + 6 + T EA + 2 16 reg, imm –– EA + 6 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 8 mem, imm acc, imm 94 –– 2 EA + 10 + 2T 16 * 2 EA + 9 + 2T 16 AND 3 EA + 9 + 2T 8 mem, imm 2 EA + 10 + 2T 16 TEST 2 EA + 7 + T 2 2 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 2 2 µPD70433 Mnemonic Operands reg, reg' Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (11/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 Byte Processing Word Processing 8 mem, reg EA + 10 + 2T 16 EA + 7 + T 8 reg, mem OR EA + 9 + 2T EA + 2 EA + 6 + T EA + 2 16 reg, imm –– EA + 6 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 Logical operation instructions 8 mem, imm EA + 10 + 2T 16 EA + 7 + T acc, imm –– 2 2 2 2 reg, reg' –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 8 mem, reg EA + 10 + 2T 16 EA + 7 + T 8 reg, mem XOR EA + 9 + 2T EA + 2 EA + 6 + T EA + 2 16 reg, imm –– EA + 6 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 8 mem, imm EA + 7 + T acc, imm –– 2 2 2 2 reg8, CL –– 3 3 3 3 EA + 4 EA + 6 + T EA + 4 8 mem8, CL EA + 9 + 2T 16 Bit manipulation instructions 2 EA + 10 + 2T 16 reg16, CL –– EA + 6 + T 3 3 3 EA + 4 EA + 6 + T EA + 4 8 mem16, CL 3 EA + 9 + 2T 16 EA + 6 + T TEST1 reg8, imm3 –– 2 2 2 EA + 4 EA + 6 + T EA + 4 8 mem8, imm3 –– EA + 6 + T 2 2 2 EA + 4 EA + 6 + T EA + 4 8 mem16, imm4 2 EA + 9 + 2T 16 reg16, imm4 2 EA + 9 + 2T 16 * 2 EA + 6 + T 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 95 µPD70433 Mnemonic Operands reg8, CL Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (12/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 Byte Processing Word Processing 8 mem8, CL EA + 10 + 2T 16 reg16, CL –– EA + 7 + T 3 3 3 EA + 4 EA + 7 + T EA + 4 8 mem16, CL EA + 10 + 2T 16 NOT1 reg8, imm3 –– EA + 7 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 8 mem8, imm3 Bit manipulation instructions –– EA + 7 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 8 mem16, imm4 EA + 7 + T CY –– 2 2 2 2 reg8, CL –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 8 mem8, CL EA + 10 + 2T 16 reg16, CL –– EA + 7 + T 3 3 3 EA + 4 EA + 7 + T EA + 4 8 mem16, CL reg8, imm3 –– EA + 7 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 8 mem8, imm3 –– EA + 7 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 8 mem16, imm4 2 EA + 10 + 2T 16 EA + 7 + T CY –– 2 2 2 2 DIR –– 2 2 2 2 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 96 2 EA + 10 + 2T 16 reg16, imm4 3 EA + 10 + 2T 16 * 2 EA + 10 + 2T 16 CLR1 2 EA + 10 + 2T 16 reg16, imm4 3 µPD70433 Mnemonic Operands reg8, CL Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (13/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 3 3 3 3 EA + 4 EA + 7 + T EA + 4 Byte Processing Word Processing 8 mem8, CL EA + 10 + 2T 16 reg16, CL –– EA + 7 + T 3 3 3 EA + 4 EA + 7 + T EA + 4 3 8 Bit manipulation instructions mem16, CL EA + 10 + 2T 16 reg8, imm3 –– EA + 7 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 2 SET1 8 mem8, imm3 EA + 10 + 2T 16 reg16, imm4 –– EA + 7 + T 2 2 2 EA + 4 EA + 7 + T EA + 4 2 8 mem16, imm4 EA + 10 + 2T 16 EA + 7 + T CY –– 2 2 2 2 DIR –– 2 2 2 2 8 EA + 8 + 3n + T EA + 8 + 3n + T EA + 11 + 3n + 2T EA + 11 + 3n + 2T 16 EA + 8 + 3n + T EA + 8 + 3n + T EA + 8 + 3n + T EA + 8 + 3n + T reg –– 4 + 3n 4 + 3n 4 + 3n 4 + 3n reg, 1 –– 3 3 3 3 EA + 3 EA + 7 + T EA + 3 mem BSCH 8 mem, 1 EA + 10 + 2T Shift instructions 16 reg, CL SHL –– EA + 7 + T 5+n 5+n 5+n EA + 5 + n EA + 8 + T + n EA + 6 + n 8 mem, CL 5+n EA + 11 + 2T + n 16 reg, imm8 –– EA + 8 + T + n 5+n 5+n 5+n EA + 6 + n EA + 8 + T + n EA + 6 + n 8 mem, imm8 5+n EA + 11 + 2T + n 16 * EA + 8 + T + n 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width Remark Number of shifts (n in a bit manipulation instruction indicates the bit number searched for) 97 µPD70433 Mnemonic Operands reg, 1 Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (14/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 3 3 3 3 EA + 3 EA + 7 + T EA + 3 Byte Processing Word Processing 8 mem, 1 EA + 10 + 2T 16 reg, CL SHR –– EA + 7 + T 5+n 5+n 5+n EA + 5 + n EA + 8 + T + n EA + 6 + n 8 mem, CL 5+n EA + 11 + 2T + n 16 reg, imm8 –– EA + 8 + T + n 5+n 5+n 5+n EA + 6 + n EA + 8 + T + n EA + 6 + n Shift instructions 8 mem, imm8 5+n EA + 11 + 2T + n 16 reg, 1 –– EA + 8 + T + n 3 3 3 EA + 3 EA + 7 + T EA + 3 3 8 mem, 1 EA + 10 + 2T 16 reg, CL SHRA –– EA + 7 + T 5+n 5+n 5+n EA + 5 + n EA + 8 + T + n EA + 6 + n 8 mem, CL 5+n EA + 11 + 2T + n 16 reg, imm8 –– EA + 8 + T + n 5+n 5+n 5+n EA + 6 + n EA + 8 + T + n EA + 6 + n 8 mem, imm8 5+n EA + 11 + 2T + n 16 reg, 1 –– EA + 8 + T + n 3 3 3 EA + 3 EA + 7 + T EA + 3 3 8 Rotate instructions mem, 1 EA + 10 + 2T 16 reg, CL ROL –– EA + 7 + T 5+n 5+n 5+n EA + 5 + n EA + 8 + T + n EA + 6 + n 8 mem, CL 5+n EA + 11 + 2T + n 16 reg, imm8 –– EA + 8 + T + n 5+n 5+n 5+n EA + 6 + n EA + 8 + T + n EA + 6 + n 8 mem, imm8 5+n EA + 11 + 2T + n 16 * 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width Remark 98 Number of shifts (n in a bit manipulation instruction indicates the bit number searched for) EA + 8 + T + n µPD70433 Mnemonic Operands reg, 1 Bus Width* Instruction Group Table 17-9. Number of Clock Cycles (15/20) On-Chip RAM Access Other Access On-Chip RAM Access Other Access –– 3 3 3 3 EA + 3 EA + 7 + T EA + 3 Byte Processing Word Processing 8 mem, 1 EA + 10 + 2T 16 reg, CL ROR –– EA + 7 + T 5+n 5+n 5+n EA + 5 + n EA + 8 + T + n EA + 6 + n 8 mem, CL EA + 11 + 2T + n 16 reg, imm8 –– EA + 8 + T + n 5+n 5+n 5+n EA + 6 + n EA + 8 + T + n EA + 6 + n 8 mem, imm8 –– EA + 8 + T + n 3 3 3 EA + 3 EA + 7 + T EA + 3 8 mem, 1 Rotate instructions ROLC –– EA + 7 + T 5+n 5+n 5+n EA + 5 + n EA + 8 + T + n EA + 6 + n 8 mem, CL –– EA + 8 + T + n 5+n 5+n 5+n EA + 6 + n EA + 8 + T + n EA + 6 + n 8 mem, imm8 –– EA + 8 + T + n 3 3 3 EA + 3 EA + 7 + T EA + 3 8 mem, 1 RORC –– EA + 7 + T 5+n 5+n 5+n EA + 5 + n EA + 8 + T + n EA + 6 + n 8 mem, CL –– EA + 8 + T + n 5+n 5+n 5+n EA + 6 + n EA + 8 + T + n EA + 6 + n 8 mem, imm8 16 * 5+n EA + 11 + 2T + n 16 reg, imm8 3 EA + 10 + 2T 16 reg, CL 5+n EA + 11 + 2T + n 16 reg, 1 5+n EA + 11 + 2T + n 16 reg, imm8 3 EA + 10 + 2T 16 reg, CL 5+n EA + 11 + 2T + n 16 reg, 1 5+n 5+n EA + 11 + 2T + n EA + 8 + T + n 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width Remark Number of shifts 99 µPD70433 Mnemonic Operands Bus Width *1 Instruction Group Table 17-9. Number of Clock Cycles (16/20) Byte Processing Word Processing On-Chip RAM Access Other Access On-Chip RAM Access –– –– –– 8 near-proc 19 + 2T 16 16 + T 8 regptr16 18 + 2T –– –– –– 16 15 + T 8 CALL memptr16 –– Subroutine control instructions EA + 19 + 2T EA + 24 + 4T EA + 16 + T EA + 18 + 2T –– 16 8 far-proc 29 + 4T –– –– –– 16 23 + 2T 8 memptr32 –– EA + 32 + 4T EA + 44 + 8T EA + 26 + 2T EA + 32 + 4T –– 16 8 18 + 2T –– –– –– 16 15 + T 8 pop-value Other Access 19 + 2T –– –– –– 16 16 + T RET 8 *2 26 + 4T –– –– –– 16 20 + 2T 8 pop-value*2 27 + 4T –– –– –– 16 21 + 2T 8 mem16 EA + 13 + 2T –– –– EA + 7 Stack manipulation instructions 16 reg16 –– –– –– –– 7 sreg –– –– –– –– 7 xsreg/VPC –– –– –– –– 7 PSW –– –– –– –– 6 –– –– –– PUSH 8 R 57 + 14T 16 * 1. 8 36 + 7T imm8 –– –– –– –– 6 imm16 –– –– –– –– 6 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 2. Segment-external Remark n: Number of shifts 100 EA + 10 + T µPD70433 Mnemonic Operands Bus Width *1 Instruction Group Table 17-9. Number of Clock Cycles (17/20) Byte Processing Word Processing On-Chip RAM Access Other Access –– –– 8 mem16 16 On-Chip RAM Access Other Access EA + 13 + 2T EA + 14 + 2T EA + 10 + T EA + 11 + T 8 reg16 10 + 2T –– –– –– Stack manipulation instructions 16 7+T 8 sreg 10 + 2T –– –– –– 16 7+T POP 8 xsreg/VPC 10 + 2T –– –– –– 16 7+T 8 PSW 11 + 2T –– –– –– 16 8+T 8 R 76 + 16T –– –– –– 16 PREPARE*2 imm16, imm8 –– 52 + 8T –- –– –– –– –– –– 8 DISPOSE 10 + 2T Branch instructions 16 7+T near-label –– –– –– –– 9 short-label –– –– –– –– 9 regptr16 –– –– –– –– 8 –– –– EA + 9 8 BR 9 memptr16 EA + 14 + 2T 16 far-label –– EA + 11 + T –– –– –– –– –– EA + 12 8 memptr32 9 EA + 24 + 4T 16 EA + 18 + 2T * 1. 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 2. When imm8 = 0. As shown below when imm8 ≥ 1. 8 PREPARE imm16, imm8 15+2T+(16+4T)n –– 16 –– –– 14 + (12 + T)n n : imm8 101 µPD70433 Bus Width* Conditional branch instructions Instruction Group Table 17-9. Number of Clock Cycles (18/20) On-Chip RAM Access BV short-label –– –– –– 9/3 9/3 BNV short-label –– –– –– 9/3 9/3 BC/BL short-label –– –– –– 9/3 9/3 BNC/BNL short-label –– –– –– 9/3 9/3 BE/BZ short-label –– –– –– 9/3 9/3 BNE/BNZ short-label –– –– –– 9/3 9/3 BNH short-label –– –– –– 9/3 9/3 BH short-label –– –– –– 9/3 9/3 BN short-label –– –– –– 9/3 9/3 BP short-label –– –– –– 9/3 9/3 BPE short-label –– –– –– 9/3 9/3 BPO short-label –– –– –– 9/3 9/3 BLT short-label –– –– –– 9/3 9/3 BGE short-label –– –– –– 9/3 9/3 BLE short-label –– –– –– 9/3 9/3 BGT short-label –– –– –– 9/3 9/3 DBNZNE short-label –– –– –– 10/5 10/5 DBNZE short-label –– –– –– 10/5 10/5 DBNZ short-label –– –– –– 10/5 10/5 BCWZ short-label –– –– –– 10/5 10/5 BTCLR sfr, imm3 short-label –– 21/14 –– –– –– 20/13 –– –– Mnemonic BTCLRL * Operands sfrl, imm3 short-label Word Processing Other Access On-Chip RAM Access Other Access 8 16 8 16 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 102 Byte Processing µPD70433 Mnemonic Bus Width *1 Instruction Group Table 17-9. Number of Clock Cycles (19/20) Operands Byte Processing Word Processing On-Chip RAM Access Other Access On-Chip RAM Access –– –– –– 8 3 Other Access 50 + 10T 16 36 + 4T + t BRK*2 8 imm8 (≠3) 52 + 10T –– –– –- Interrupt instructions 16 38 + 4T + t 8 BRKV*2 51 + 10 T –– –– –– 16 37 + 4T + t 8 RETI 28 + 4T –– –– –– 16 22 + 2T RETRBI –– –– –– –– 9 FINT — 3 3 3 3 –– –– EA + 11 8 CHKIND*3 EA + 21 + 4T 16 EA + 15 + 2T BRKCS reg16 –– –– –– 12 12 TSKSW reg16 –– –– –– 13 13 HALT –– –– –– –– –– STOP –– –– –– –– –– IDLE –– –– –– –– –– POLL –– –– –– –– –– DI –– 3 3 3 3 EI –– 3 3 3 3 BUSLOCK –– 0 to 1 0 to 1 0 to 1 0 to 1 CPU control instructions *4 * 1. 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 2. When BRK = 1, add 50 + 10T in case of 8-bit bus width, and 34 + 4T in case of 16-bit bus. 3. When (mem32) > reg16 or (mem32 + 2) < reg16, add 50 + 10T in case of 8-bit bus width, and 34 + 4T + t in case of 16-bit bus width. 4. Register bank switching instructions Remarks When T ≥ 2, t = T – 1 103 µPD70433 Mnemonic Operands Bus Width *1 Instruction Group Table 17-9. Number of Clock Cycles (20/20) Byte Processing Word Processing On-Chip RAM Access Other Access On-Chip RAM Access — –– –– 8 fp-op 50 + 10T CPU control instructions 16 36 + 4T + t FPO1 8 fp-op, mem EA + 50 + 10 T –– –– –– 16 EA + 36 + 4T + t 8 fp-op 50 + 10T — –– –– 16 36 + 4T + t FPO2 8 fp-op, mem EA + 50 + 10 T –– –– –– 16 NOP –– EA + 36 + 4T + t 4 8 *2 RSTWDT imm8, imm8' Dedicated fax instructions Queue manipulation instructions *4 4 4 4 –– –– 9/54 + 10T*3 –– 16 9/40 + 4T + t*3 –– 0 to 1 0 to 1 0 to 1 0 to 1 QHOUT imm16 –– — –– –– –– QOUT imm16 –– — –– –– –– QTIN imm16 –– –– –– –– –– ALBIT –– –– –– –– –– COLTRP –– –– –– –– –– MHENC –– –– –– –– –– MRENC –– –– –– –– –– SCHEOL –– –– –– –– –– GETBIT –– –– –– –– –– MHDEC –– –– –– –– –– MRDEC –– –– –– –– –– CNVTRP –– –– –– –– –– * 1. 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width 2. Watchdog timer manipulation instruction 3. Figure after / (slash) applies when word processing is performed during data error. When T ≥ 2, t = T – 1 4. Segment override prefix instructions (DS0:, DS1:, PS:, SS:) Extended segment override prefix instructions (DS2: DS3:) Register file space access override prefix instruction (IRAM) 104 Other Access Instruction Group Data transfer instructions Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg, reg' 1 0 0 0 1 0 1W 1 1 mem, reg 1 0 0 0 1 0 0W reg, mem mem, imm reg, imm reg Operation AC CY V reg' 2 mod reg mem 2 to 4 (mem)←reg 1 0 0 0 1 0 1W mod reg mem 2 to 4 reg←(mem) 1 1 0 0 0 1 1W mod0 0 0 mem 3 to 6 (mem)←imm 2 to 3 reg←imm 1 0 1 1 W reg reg←reg' acc, dmem 1 0 1 0 0 0 0W 3 If W = 0, AL←(dmem) If W = 1, AH←(dmem + 1), AL←(dmem) dmem, acc 1 0 1 0 0 0 1W 3 If W = 0, (dmem)← AL If W = 1, (dmem + 1)←AH, (dmem)←AL sreg, reg16 1 0 0 0 1 1 1 0 1 1 0 sreg reg 2 sreg←reg16 xsreg, reg16* 1 0 0 0 1 1 1 0 1 1 1 xsreg reg 2 xsreg←reg16 sreg, mem16 1 0 0 0 1 1 1 0 mod 0 sreg mem 2 to 4 sreg←(mem16) xsreg, mem16* 1 0 0 0 1 1 1 0 mod 1 xsreg mem 2 to 4 xsreg←(mem16) reg16, sreg 1 0 0 0 1 1 0 0 1 1 0 sreg reg 2 reg16←sreg reg16, xsreg* 1 0 0 0 1 1 0 0 1 1 1 xsreg reg 2 reg16←xsreg mem16, sreg 1 0 0 0 1 1 0 0 mod 0 sreg mem 2 to 4 (mem16)←sreg mem16, xsreg* 1 0 0 0 1 1 0 0 mod 1 xsreg mem 2 to 4 (mem16)←xsreg 1 1 0 0 0 1 0 1 mod reg mem 2 to 4 1 1 0 0 0 1 0 0 mod reg mem 2 to 4 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 P S Z sreg : SS, DS0, DS1 xsreg : DS2, DS3 sreg : SS, DS0, DS1 MOV DS0, reg16, mem32 DS1, reg16, mem32 DS2, reg16*, mem32 mod reg mod reg 3 to 5 reg16←(mem32) DS2←(mem32 + 2) 3 to 5 reg16←(mem32) DS3←(mem32 + 2) mem 0 0 0 0 1 1 1 1 mem 105 This instruction is newly added to the V25 or V35. reg16←(mem32) DS0←(mem32 + 2) reg16←(mem32) DS1←(mem32 + 2) 0 0 1 1 0 1 1 0 µPD70433 DS3, reg16*, mem32 * Flags Operand(s) 17.3 INSTRUCTION SET TABLE Operation Code Mnemonic Instruction Group Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 Operation 7 6 5 4 3 2 1 0 AC CY V AH, PSW 1 0 0 1 1 1 1 1 1 AH←S, Z, F1, AC, F0, P, IBRK, CY PSW, AH 1 0 0 1 1 1 1 0 1 S, Z, F1, AC, F0, P, IBRK, CY←AH reg16, mem16 1 0 0 0 1 1 0 1 src-table 1 1 0 1 0 1 1 1 reg, reg' 1 0 0 0 0 1 1W P S Z × × × Data transfer instructions MOV LDEA TRANS TRANSB*1 XCH mem, reg reg, mem AW, reg16 reg16, AW MOVSPA*2 MOVSPB*2 1 0 0 0 0 1 1W 1 0 0 1 0 mod reg 1 1 reg mod reg mem reg' mem reg 0 0 0 0 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 1 reg16 1 1 1 1 1 Repeat prefixes 106 Operation Code Mnemonic 2 to 4 reg16←mem16 1 AL←(BW + AL) 2 reg↔reg' 2 to 4 (mem)↔reg 1 AW↔reg16 2 New register bank SS, SP ← Old register bank SS, SP 3 SS, SP of register bank indicated by reg16 ← current register bank SS, SP reg REPC 0 1 1 0 0 1 0 1 1 While CW ≠ 0, the following byte primitive block transfer instruction is executed and CW is decremented (–1). If there is a pending interrupt, it is serviced. If CY ≠ 1, the loop is exited. REPNC 0 1 1 0 0 1 0 0 1 Same as above. If CY ≠ 0, the loop is exited. 1 1 1 1 0 0 1 1 1 While CW ≠ 0, the following byte primitive block transfer instruction is executed and CW is decremented (–1). If there is a pending interupt, it is serviced. If the primitive block transfer instruction is CMPBK or CMPM, and Z ≠ 1, the loop is exited. 1 1 1 1 0 0 1 0 1 Same as above. If Z ≠ 0, the loop is exited. REP REPE REPZ REPNE REPNZ 2. This instruction is newly added to the V20 or V30. × µPD70433 * 1. The operand can be omitted in the case of the TRANS instruction. The TRANSB instruction has no operand. × Instruction Group Operation Code Mnemonic CMPBK CMPBKB CMPBKW CMPM CMPMB CMPMW LDM LDMB LDMW STM STMB STMW dst-block, src-block src-block, dst-block Flags Bytes 7 6 5 4 3 2 1 0 MOVBK MOVBKB MOVBKW Primitive block transfer instructions Operand(s) Operation 7 6 5 4 3 2 1 0 AC CY V P S Z If W = 0, (IY)←(IX) DIR = 0: IX←IX + 1, IY←IY + 1 DIR = 1: IX←IX – 1, IY←IY – 1 1 0 1 0 0 1 0W 1 If W = 1, (IY + 1, IY)←(IX + 1, IX) DIR = 0: IX←IX + 2, IY←IY + 2 DIR = 1: IX←IX – 2, IY←IY – 2 If W = 0, (IX) – (IY) DIR = 0: IX←IX + 1, IY←IY + 1 DIR = 1: IX←IX – 1, IY←IY – 1 1 0 1 0 0 1 1W 1 × × × × × × × × × × × × If W = 1, (IX + 1, IX) – (IY + 1, IY) DIR = 0: IX←IX + 2, IY←IY + 2 DIR = 1: IX←IX – 2, IY←IY – 2 If W = 0, AL – (IY) DIR = 0: IY←IY + 1 ; DIR = 1: IY←IY – 1 dst-block 1 0 1 0 1 1 1W 1 If W = 1, AW – (IY + 1, IY) DIR = 0: IY←IY + 2 ; DIR = 1: IY←IY – 2 If W = 0, AL←(IX) DIR = 0: IX←IX + 1 ; DIR = 1: IX←IX – 1 src-block 1 0 1 0 1 1 0W 1 If W = 1, AW + (IX + 1, IX) DIR = 0: IX + 2 ; DIR = 1: IX←IX – 2 If W = 0, (IY)←AL DIR = 0: IY←IY + 1 ; DIR = 1: IY←IY – 1 dst-block 1 0 1 0 1 0 1W 1 If W = 1, AW – (IY + 1, IY)←AW DIR = 0: IY←IY + 2 ; DIR = 1: IY←IY – 2 µPD70433 107 Instruction Group Operand(s) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 1 1 Bit field manipulation instructions Flags Bytes reg8, reg8' reg' Operation AC CY V 3 16-bit field←AW 4 16-bit field←AW 3 AW←16-bit field 4 AW←16-bit field P S Z reg INS 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 reg8, imm4 1 1 0 0 0 reg 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 reg8, reg8' 1 1 reg' reg EXT 0 0 0 0 1 1 1 1 reg8, imm4 1 1 0 0 0 0 0 1 1 1 0 1 1 reg acc, imm8 1 1 1 0 0 1 0W 2 If W = 0, AL←(imm8) If W = 1, AH←(imm8 + 1), AL←(imm8) acc, DW 1 1 1 0 1 1 0W 1 If W = 0, AL←(DW) If W = 1, AH←(DW + 1), AL←(DW) imm8, acc 1 1 1 0 0 1 1W 2 If W = 0, (imm8)←AL If W = 1, (imm8 + 1)←AH, (imm8)←AL DW, acc 1 1 1 0 1 1 1W 1 If W = 0, (DW)←AL If W = 1, (DW + 1)←AH, (DW)←AL Input/output instructions IN* OUT* Primitive input /output instructions 108 Operation Code Mnemonic OUTM* dst-block, DW DW, src-block 0 1 1 0 1 1 0W 1 If W = 1, (IY + 1, IY)←(DW + 1, DW) DIR = 0: IY←IY + 2 ; DIR = 1: IY←IY – 2 If W = 0, (DW)←(IX) DIR = 0: IX←IX + 1 ; DIR = 1: IX←IX – 1 0 1 1 0 1 1 1W 1 If W = 1, (DW + 1, DW)←(IX + 1, IX) DIR = 0: IX←IX + 2 ; DIR = 1: IX←IX – 2 When IBRK = 0, a software interrupt is generated automatically and the instruction is not executed. µPD70433 * INM* If W = 0, (IY)←(DW) DIR = 0: IY←IY + 1 ; DIR = 1: IY←IY – 1 Instruction Group Operation Code Mnemonic Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg, reg' 0 0 0 0 0 0 1W 1 1 mem, reg 0 0 0 0 0 0 0W reg, mem reg Operation AC CY V × × × × × 2 to 4 (mem)←(mem) + reg × × × × × × mem 2 to 4 reg←reg + (mem) × × × × × × reg 3 to 4 reg←reg + imm × × × × × × 3 to 6 (mem)←(mem) + imm × × × × × × 2 to 3 If W = 0, AL←AL + imm If W = 1, AW←AW + imm × × × × × × reg←reg + reg' + CY × × × × × × mod reg mem 0 0 0 0 0 0 1W mod reg reg, imm 1 0 0 0 0 0 sW 1 1 0 0 0 mem, imm 1 0 0 0 0 0 sW mod 0 0 0 mem acc, imm 0 0 0 0 0 1 0W reg, reg' 0 0 0 1 0 0 1W mem, reg 0 0 0 1 0 0 0W reg, mem ADD Addition/subtraction instructions Z × 2 reg S reg←reg + reg' reg' 1 1 P reg' 2 mod reg mem 2 to 4 (mem)←(mem) + reg + CY × × × × × × 0 0 0 1 0 0 1W mod reg mem 2 to 4 reg←reg + (mem) + CY × × × × × × reg, imm 1 0 0 0 0 0 sW 1 1 0 1 0 reg 3 to 4 reg←reg + imm + CY × × × × × × mem, imm 1 0 0 0 0 0 sW mod 0 1 0 mem 3 to 6 (mem)←(mem) + imm + CY × × × × × × acc, imm 0 0 0 1 0 1 0W 2 to 3 If W = 0, AL←AL + imm + CY If W = 1, AW←AW + imm + CY × × × × × × reg, reg' 0 0 1 0 1 0 1W reg←reg – reg' × × × × × × mem, reg 0 0 1 0 1 0 0W reg, mem ADDC 1 1 reg reg' 2 mod reg mem 2 to 4 (mem)←(mem) – reg × × × × × × 0 0 1 0 1 0 1W mod reg mem 2 to 4 reg←reg – (mem) × × × × × × reg, imm 1 0 0 0 0 0 sW 1 1 1 0 1 reg 3 to 4 reg←reg – imm × × × × × × mem, imm 1 0 0 0 0 0 sW mod 1 0 1 mem 3 to 6 (mem)←(mem) – imm × × × × × × acc, imm 0 0 1 0 1 1 0W 2 to 3 If W = 0, AL←AL – imm If W = 1, AW←AW – imm × × × × × × reg, reg' 0 0 0 1 1 0 1W reg←reg – reg' – CY × × × × × × mem, reg 0 0 0 1 1 0 0W reg, mem SUB 1 1 reg 2 mod reg mem 2 to 4 (mem)←(mem) – reg – CY × × × × × × 0 0 0 1 1 0 1W mod reg mem 2 to 4 reg←reg – (mem) – CY × × × × × × reg, imm 1 0 0 0 0 0 sW 1 1 0 1 1 reg 3 to 4 reg←reg – imm – CY × × × × × × mem, imm 1 0 0 0 0 0 sW mod 0 1 1 mem 3 to 6 (mem)←(mem) – imm – CY × × × × × × acc, imm 0 0 0 1 1 1 0W 2 to 3 If W = 0, AL←AL – imm – CY If W = 1, AW←AW – imm – CY × × × × × × SUBC 109 µPD70433 reg' Instruction Group BCD operation instructions Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Operation AC CY V P S Z ADD4S*1 (dst-string, src-string) 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 2 dst BCD string←dst BCD string + src BCD string*2 U × U U U × SUB4S*1 (dst-string, src-string) 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 2 dst BCD string←dst BCD string – src BCD string*2 U × U U U × CMP4S*1 (dst-string, src-string) 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 2 dst BCD string – src BCD string*2 U × U U U × reg8 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 3 0 0 1 0 1 0 0 0 3 to 5 0 0 1 0 1 0 1 0 3 0 0 1 0 1 0 1 0 3 to 5 1 1 0 0 0 reg AL L Highorder mem8 AL L Highorder AL L Highorder AL L Highorder Loworder reg ROL4 0 0 0 0 1 1 1 1 mem Loworder mod 0 0 0 mem reg8 0 0 0 0 1 1 1 1 1 1 0 0 0 reg mem8 Loworder reg ROR4 0 0 0 0 1 1 1 1 mem Loworder mod 0 0 0 mem Increment/decrement instructions 110 Operation Code Mnemonic INC DEC reg8 1 1 1 1 1 1 1 0 1 1 0 0 0 reg mem 1 1 1 1 1 1 1W mod 0 0 0 mem reg16 0 1 0 0 0 reg8 1 1 1 1 1 1 1 0 1 1 0 0 1 mem 1 1 1 1 1 1 1W mod 0 0 1 mem reg16 0 1 0 0 1 reg reg reg reg8←reg8 + 1 × × × × × (mem)←(mem) + 1 × × × × × 1 reg16←reg16 + 1 × × × × × 2 reg8←reg8 – 1 × × × × × (mem)←(mem) – 1 × × × × × reg16←reg16 – 1 × × × × × 2 2 to 4 2 to 4 1 * 1. The operand can be omitted. 2. The number of BCD digits is given by the CL register: a value between 1 and 254 can be set. µPD70433 Instruction Group Operation Code Mnemonic Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 reg8 1 1 1 1 0 1 1 0 1 1 1 0 0 mem8 1 1 1 1 0 1 1 0 mod 1 0 0 mem reg16 1 1 1 1 0 1 1 1 1 1 1 0 0 mem16 1 1 1 1 0 1 1 1 mod 1 0 0 mem reg8 1 1 1 1 0 1 1 0 1 1 1 0 1 mem8 1 1 1 1 0 1 1 0 mod 1 0 1 mem reg16 1 1 1 1 0 1 1 1 1 1 1 0 1 mem16 1 1 1 1 0 1 1 1 mod 1 0 1 mem reg16, (reg16',)* imm8 0 1 1 0 1 0 1 1 1 1 reg16, mem16, imm8 0 1 1 0 1 0 1 1 reg16, (reg16',)* imm16 0 1 1 0 1 0 0 1 reg16, mem16, imm16 0 1 1 0 1 0 0 1 reg Multiplication instructions reg reg * mod reg 1 1 reg mod reg S Z AW←AL × reg8 AH = 0: CY←0, V←0 AH ≠ 0: CY←1, V←1 U × × U U U 2 to 4 AW←AL × (mem8) AH = 0: CY←0, V←0 AH ≠ 0: CY←1, V←1 U × × U U U DW, AW←AW × reg16 DW = 0: CY←0, V←0 DW ≠ 0: CY←1, V←1 U × × U U U DW, AW←AW × (mem16) DW = 0: CY←0, V←0 DW ≠ 0: CY←1, V←1 U × × U U U 2 AW←AL × reg8 AH = AL sign extension: CY←0, V←0 AH ≠ AL sign extension: CY←1, V←1 U × × U U U 2 to 4 AW←AL × (mem8) AH = AL sign extension: CY←0, V←0 AH ≠ AL sign extension: CY←1, V←1 U × × U U U 2 DW, AW←AW × reg16 DW = AW sign extension: CY←0, V←0 DW ≠ AW sign extension: CY←1, V←1 U × × U U U 2 to 4 DW, AW←AW × (mem16) DW = AW sign extension: CY←0, V←0 DW ≠ AW sign extension: CY←1, V←1 U × × U U U 2 2 to 4 MUL reg P 2 MULU reg AC CY V reg' 3 reg16←reg16' × imm8 Product ≤ 16 bits: CY←0, V←0 Product > 16 bits: CY←1, V←1 U × × U U U mem 3 to 5 reg16←(mem16) × imm8 Product ≤ 16 bits: CY←0, V←0 Product > 16 bits: CY←1, V←1 U × × U U U reg' 4 reg16←reg16' × imm16 Product ≤ 16 bits: CY←0, V←0 Product > 16 bits: CY←1, V←1 U × × U U U mem 4 to 6 reg16←(mem16) × imm16 Product ≤ 16 bits: CY←0, V←0 Product > 16 bits: CY←1, V←1 U × × U U U The 2nd operand can be omitted, in which case the same register as the 1st operand is taken as being specified. 111 µPD70433 7 6 5 4 3 2 1 0 Operation Instruction Group Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 reg8 Unsigned division instructions 112 Operation Code Mnemonic mem8 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 Operation 7 6 5 4 3 2 1 0 1 1 1 1 0 reg mod 1 1 0 mem AC CY V P S Z 2 temp←AW If temp ÷ reg8 ≤ FFH AH←temp%reg8, AL←temp ÷ reg8 If temp ÷ reg8 > FFH (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0, PS←(3, 2), PC←(1, 0) U U U U U U 2 to 4 temp←AW If temp ÷ (mem8) ≤ FFH AH←temp%(mem8), AL←temp ÷ (mem8) If temp ÷ (mem8) > FFH (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0, PS←(3, 2), PC←(1, 0) U U U U U U 2 temp←DW, AW If temp ÷ reg16 ≤ FFFFH DW←temp%reg16, AW←temp ÷ reg16 If temp ÷ reg16 > FFFFH (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0, PS←(3, 2), PC←(1, 0) U U U U U U 2 to 4 temp←DW, AW If temp ÷ (mem16) ≤ FFFFH DW←temp%(mem16), AW←temp ÷ (mem16) If temp ÷ (mem16) > FFFFH (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0, PS←(3, 2), PC←(1, 0) U U U U U U DIVU reg16 mem16 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 reg mod 1 1 0 mem µPD70433 Instruction Group Operation Code Mnemonic Bytes 7 6 5 4 3 2 1 0 reg8 Signed division instructions Flags Operand(s) mem8 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 Operation 7 6 5 4 3 2 1 0 1 1 1 1 1 reg mod 1 1 1 mem AC CY V 2 2 to 4 P S Z temp←AW If temp ÷ reg8 > 0 and temp ÷ reg8 ≤ 7FH; or if temp ÷ reg8 < 0 and temp ÷ reg8 > 0 – 7FH – 1 AH←temp%reg8, AL←temp ÷ reg8 If temp ÷ reg8 > 0 and temp ÷ reg8 > 7FH; or if temp ÷ reg8 < 0 and temp ÷ reg8 ≤ 0 – 7FH – 1 (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0, PS←(3, 2), PC←(1, 0) U U U U U U temp←AW If temp ÷ (mem8) > 0 and temp ÷ (mem8) ≤ 7FH; or if temp ÷ (mem8) < 0 and temp ÷ (mem8) > 0 – 7FH – 1 AH←temp%(mem8), AL←temp ÷ (mem8) If temp ÷ (mem8) > 0 and temp ÷ (mem8) > 7FH; or if temp ÷ (mem8) < 0 and temp ÷ (mem8) ≤ 0 – 7FH – 1 (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0, PS←(3, 2), PC←(1, 0) U U U U U U temp←DW, AW If temp ÷ reg16 > 0 and temp ÷ reg16 ≤ 7FFFH; or if temp ÷ reg16 < 0 and temp ÷ reg16 > 0 – 7FFFH – 1 DW←temp%reg16, AW←temp ÷ reg16 If temp ÷ reg16 > 0 and temp ÷ reg16 > 7FFFH; or if temp ÷ reg16 < 0 and temp ÷ reg16 ≤ 0 – 7FFFH – 1 (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0, PS←(3, 2), PC←(1, 0) U U U U U U temp←DW, AW If temp ÷ (mem16) > 0 and temp ÷ (mem16) ≤ 7FFFH; or if temp ÷ (mem16) < 0 and temp ÷ (mem16) > 0 – 7FFFH – 1 AH←temp%(mem16), AW←temp ÷ (mem16) If temp ÷ (mem16) > 0 and temp ÷ (mem16) > 7FFFH; or if temp ÷ (mem16) < 0 and temp ÷ (mem16) ≤ 0 – 7FFFH – 1 (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0, PS←(3, 2), PC←(1, 0) U U U U U U DIV reg16 mem16 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 reg mod 1 1 1 mem 2 2 to 4 µPD70433 113 Instruction Group BCD adjustment instructions Data conversion instructions Comparison instruction 114 Operation Code Mnemonic Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 Operation 7 6 5 4 3 2 1 0 AC CY V P S Z ADJBA 0 0 1 1 0 1 1 1 1 If AL ∧ 0FH > 9 or AC = 1: AL←AL + 6 AH←AH + 1, AC←1, CY←AC, AL←AL ∧ 0FH × × U U U U ADJ4A 0 0 1 0 0 1 1 1 1 If AL ∧ 0FH > 9 or AC = 1: AL←AL + 6, AC←1 If AL > 9FH or CY = 1: AL←AL + 60H, CY←1 × × U × × × ADJBS 0 0 1 1 1 1 1 1 1 If AL ∧ 0FH > 9 or AC = 1: AL←AL – 6, AC←1 CY←AC, AL←AL ∧ 0FH × × U U U U ADJ4S 0 0 1 0 1 1 1 1 1 If AL ∧ 0FH > 9 or AC = 1: AL←AL – 6, CY←CY ∨ AC, AC←1 If AL > 9FH or CY = 1: AL←AL – 60H, CY←1 × × U × × × CVTBD 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 2 AH←AH ÷ 0AH, AL←AL%0AH U U U × × × CVTDB 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 2 AL←AH × 0AH + AL, AH←0 U U U × × × CVTBW 1 0 0 1 1 0 0 0 1 If AL < 80H: AH←0, otherwise: AH←FFH CVTWL 1 0 0 1 1 0 0 1 1 If AW < 8000H: DW←0, otherwise: DW←FFFFH 2 reg – reg' × × × × × × CMP reg, reg' 0 0 1 1 1 0 1W 1 1 reg reg' mem, reg 0 0 1 1 1 0 0W mod reg mem 2 to 4 (mem)– reg × × × × × × reg, mem 0 0 1 1 1 0 1W mod reg mem 2 to 4 reg – (mem) × × × × × × reg, imm 1 0 0 0 0 0 sW 1 1 1 1 1 3 to 4 reg – imm × × × × × × mem, imm 1 0 0 0 0 0 sW 3 to 6 (mem) – imm × × × × × × acc, imm 0 0 1 1 1 1 0W 2 to 3 If W = 0, AL – imm If W = 1, AW – imm × × × × × × reg 1 1 1 1 0 1 1W mem 1 1 1 1 0 1 1W reg 1 1 1 1 0 1 1W 1 1 0 1 1 reg←reg + 1 × × × × × × mem 1 1 1 1 0 1 1W mod0 1 1mem (mem)←(mem) + 1 × × × × × × reg mod 1 1 1 mem 1 1 0 1 0 reg 2 reg←reg NOT mod 0 1 0 mem 2 to 4 (mem) – (mem) * reg 2 NEG µPD70433 * Complement operation instructions 2 to 4 Instruction Group Operation Code Mnemonic TEST Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg, reg' 1 0 0 0 0 1 0W 1 1 mem, reg reg, mem 1 0 0 0 0 1 0W reg, imm AC CY V Z 0 0 × × × 2 to 4 (mem) ∧ reg U 0 0 × × × 3 to 4 reg ∧ imm U 0 0 × × × 3 to 6 (mem) ∧ imm U 0 0 × × × 2 to 3 If W = 0, AL ∧ imm8 If W = 1, AW ∧ imm16 U 0 0 × × × reg←reg ∧ reg' U 0 0 × × × mod reg mem 1 1 1 1 0 1 1W 1 1 0 0 0 reg mem, imm 1 1 1 1 0 1 1W mod 0 0 0 mem acc, imm 1 0 1 0 1 0 0W reg, reg' 0 0 1 0 0 0 1W mem, reg 0 0 1 0 0 0 0W reg, mem reg' 2 mod reg mem 2 to 4 (mem)←(mem) ∧ reg U 0 0 × × × 0 0 1 0 0 0 1W mod reg mem 2 to 4 reg←reg ∧ (mem) U 0 0 × × × reg, imm 1 0 0 0 0 0 0W 1 1 1 0 0 reg 3 to 4 reg←reg ∧ imm U 0 0 × × × mem, imm 1 0 0 0 0 0 0W mod 1 0 0 mem 3 to 6 (mem)←(mem) ∧ imm U 0 0 × × × 2 to 3 If W = 0, AL←AL ∧ imm8 If W = 1, AW←AW ∧ imm16 U 0 0 × × × reg←reg ∨ reg' U 0 0 × × × AND Logical operation instructions S U 2 reg P reg ∧ reg' reg 1 1 reg' Operation acc, imm 0 1 0 0 1 0W reg, reg' 0 0 0 0 1 0 1W mem, reg 0 0 0 0 1 0 0W reg, mem 1 1 reg reg' 2 mod reg mem 2 to 4 (mem)←(mem) ∨ reg U 0 0 × × × 0 0 0 0 1 0 1W mod reg mem 2 to 4 reg←reg ∨ (mem) U 0 0 × × × reg, imm 1 0 0 0 0 0 0W 1 1 0 0 1 reg 3 to 4 reg←reg ∨ imm U 0 0 × × × mem, imm 1 0 0 0 0 0 0W mod 0 0 1 mem 3 to 6 (mem)←(mem) ∨ imm U 0 0 × × × acc, imm 0 0 0 0 1 1 0W 2 to 3 If W = 0, AL←AL ∨ imm8 If W = 1, AW←AW ∨ imm16 U 0 0 × × × reg, reg' 0 0 1 1 0 0 1W reg←reg v reg' U 0 0 × × × mem, reg 0 0 1 1 0 0 0W reg, mem OR 1 1 reg 2 mod reg mem 2 to 4 (mem)←(mem) v reg' U 0 0 × × × 0 0 1 1 0 0 1W mod reg mem 2 to 4 reg←reg v (mem) U 0 0 × × × reg, imm 1 0 0 0 0 0 0W 1 1 1 1 0 reg 3 to 4 reg←reg v imm U 0 0 × × × mem, imm 1 0 0 0 0 0 0W mod 1 1 0 mem 3 to 6 (mem)←(mem) v imm U 0 0 × × × acc, imm 0 0 1 1 0 1 0W 2 to 3 If W = 0, AL←AL v imm8 If W = 1, AW←AW v imm16 U 0 0 × × × XOR 115 µPD70433 reg' Instruction Group Flags Operand(s) reg8, CL Bit manipulation instructions 116 Operation Code Mnemonic Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 mem8, CL 0 0 0 0 reg16, CL 0 0 0 1 mem16, CL 0 0 0 1 reg8, imm3 1 0 0 0 mem8, imm3 1 0 0 0 reg16, imm4 1 0 0 1 mem16, imm4 1 0 0 0 reg8, CL 0 1 1 0 mem8, CL 0 1 1 0 reg16, CL 0 1 1 1 mem16, CL 0 1 1 1 reg8, imm3 1 1 1 0 mem8, imm3 1 1 1 0 reg16, imm4 1 1 1 1 mem16, imm4 1 1 1 1 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem Operation AC CY V P S Z reg8 bit NO.CL = 0 : Z←1 reg8 bit NO.CL = 1 : Z←0 U 0 0 U U × (mem)8 bit NO.CL = 0 : Z←1 (mem)8 bit NO.CL = 1 : Z←0 U 0 0 U U × reg16 bit NO.CL = 0 : Z←1 reg16 bit NO.CL = 1 : Z←0 U 0 0 U U × (mem16) bit NO.CL = 0 : Z←1 (mem16) bit NO.CL = 1 : Z←0 U 0 0 U U × reg8 bit NO.imm3 = 0 : Z←1 reg8 bit NO.imm3 = 1 : Z←0 U 0 0 U U × (mem8) bit NO.imm3 = 0 : Z←1 (mem8) bit NO.imm3 = 1 : Z←0 U 0 0 U U × reg16 bit NO.imm4 = 0 : Z←1 reg16 bit NO.imm4 = 1 : Z←0 U 0 0 U U × 4 to 6 (mem16) bit NO.imm4 = 0 : Z←1 (mem16) bit NO.imm4 = 1 : Z←0 U 0 0 U U × 3 reg8 bit NO.CL←reg8 bit NO.CL 3 3 to 5 3 3 to 5 TEST1 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 4 4 to 6 4 3 to 5 3 3 to 5 (mem8) bit NO.CL←(mem8) bit NO.CL reg16 bit NO.CL←reg16 bit NO.CL (mem16) bit NO.CL←(mem16) bit NO.CL NOT1 2nd byte * CY 1 1 1 1 0 1 0 1 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 3rd byte * 4 4 to 6 4 4 to 6 * 1 reg8 bit NO.imm3←reg8 bit NO.imm3 (mem8) bit NO.imm3←(mem8) bit NO.imm3 reg16 bit NO.imm4←reg16 bit NO.imm4 (mem16) bit NO.imm4←(mem16) bit NO.imm4 1st byte = 0FH CY←CY × µPD70433 NOT1 1 1 0 0 0 Instruction Group Operation Code Mnemonic Flags Operand(s) reg8, CL Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 mem8, CL 0 0 1 0 reg16, CL 0 0 1 1 mem16, CL 0 0 1 1 reg8, imm3 1 0 1 0 mem8, imm3 1 0 1 0 reg16, imm4 1 0 1 1 mem16, imm4 1 0 1 1 reg8, CL 0 1 0 0 mem8, CL 0 1 0 0 reg16, CL 0 1 0 1 mem16, CL 0 1 0 1 reg8, imm3 1 1 0 0 mem8, imm3 1 1 0 0 reg16, imm4 1 1 0 1 mem16, imm4 1 1 0 1 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem Operation AC CY V 3 3 to 5 3 3 to 5 P S Z reg8 bit NO.CL←0 (mem8) bit NO.CL←0 reg16 bit NO.CL←0 (mem16) bit NO.CL←0 Bit manipulation instructions CLR1 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 4 4 to 6 4 4 to 6 3 3 to 5 3 3 to 5 reg8 bit NO.imm3←0 (mem8) bit NO.imm3←0 reg16 bi NO.imm4←0 (mem16) bit NO.imm4←0 reg8 bit NO.CL←1 (mem8) bit NO.CL←1 reg16 bit NO.CL←1 (mem16) bit NO.CL←1 SET1 2nd byte * 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 3rd byte * 4 4 to 6 4 4 to 6 * reg8 bit NO.imm3←1 (mem8) bit NO.imm3←1 reg16 bi NO.imm4←1 (mem16) bit NO.imm4←1 1st byte = 0FH CY 1 1 1 1 1 0 0 0 1 CY←0 DIR 1 1 1 1 1 1 0 0 1 DIR←0 CY 1 1 1 1 1 0 0 1 1 CY←1 DIR 1 1 1 1 1 1 0 1 1 DIR←0 0 CLR1 1 SET1 µPD70433 117 Instruction Group 118 Operation Code Mnemonic Operand(s) 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 Bit manipulation instruction reg 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 mem8 mod 0 0 0 mem BSCH* 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 1 reg16 1 1 0 0 0 reg 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 1 mem16 Queue manipulation instructions mod 0 0 0 mem * AC CY V 3 1 1 0 0 0 Operation 7 6 5 4 3 2 1 0 reg8 <1> CL← 0 <2> [When reg8 bit No.CL=0] if CL<7, re-executed from CL← CL+1, <2> if CL=7 Z← 1 Z← 0 U [When reg8 bit No.CL=1] <1> CL← 0 <2> [When mem8 bit No.CL=0] if CL<7, re-executed from CL← CL+1, <2> 3 to 5 U if CL=7 Z← 1 [When mem8 bit No.CL=1] Z← 0 <1> CL← 0 <2> [When reg16 bit No.CL=0] if CL<15, re-executed from CL← CL+1, <2> 3 U if CL=15 Z← 1 [When reg16 bit No.CL=1] Z← 0 <1> CL← 0 <2> [When mem16 bit No.CL=0] if CL<15, re-executed from CL← CL+1, <2> 3 to 5 U if CL=15 Z← 1 [When mem16 bit No.CL=1] Z← 0 P S Z U U U U × U U U U × U U U U × U U U U × imm16 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 4 Removes block queued at head of queue and stores its segment address in P2. U U U U U × QOUT* imm16 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 4 Removes queue block indicated by P2. U U U U U × QTIN* imm16 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 0 4 Queues block indicated by P2 at end of queue. QHOUT * Flags Bytes This instruction is newly added to the V25 or V35. Remarks P2: Parameter table (in register file) µPD70433 Instruction Group Operation Code Mnemonic Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 reg, 1 1 1 0 1 0 0 0W 1 1 1 0 0 mem, 1 1 1 0 1 0 0 0W mod 1 0 0 mem reg, CL 1 1 0 1 0 0 1W 1 1 1 0 0 mem, CL 1 1 0 1 0 0 1W mod 1 0 0 mem reg, imm8 1 1 0 0 0 0 0W 1 1 1 0 0 mem, imm8 1 1 0 0 0 0 0W mod 1 0 0 mem reg, 1 1 1 0 1 0 0 0W 1 1 1 0 1 mem, 1 1 1 0 1 0 0 0W mod 1 0 1 mem reg, CL 1 1 0 1 0 0 1W 1 1 1 0 1 mem, CL 1 1 0 1 0 0 1W mod 1 0 1 mem reg, imm8 1 1 0 0 0 0 0W 1 1 1 0 1 mem, imm8 1 1 0 0 0 0 0W mod 1 0 1 mem reg reg Shift instructions reg reg S Z U × × × × × CY←(mem) MSB, (mem)←(mem) × 2 If (mem) MSB ≠ CY, V←1 If (mem) MSB = CY, V←0 U × × × × × 2 temp←CL, while temp ≠ 0, the following operations are repeated: CY←reg MSB, reg←reg × 2 temp←temp – 1 U × U × × × 2 to 4 temp←CL, while temp ≠ 0, the following operations are repeated: CY←(mem) MSB, (mem)←(mem) × 2 temp←temp – 1 U × U × × × 3 temp←imm8, while temp ≠ 0, the following operations are repeated: CY←reg MSB, reg←reg × 2 temp←temp – 1 U × U × × × 3 to 5 temp←imm8, while temp ≠ 0, the following operations are repeated: CY←(mem) MSB, (mem)←(mem) × 2 temp←temp – 1 U × U × × × CY←reg LSB, reg←reg ÷ 2 If reg MSB ≠ bit after reg MSB: V←1 If reg MSB = bit after reg MSB: V←0 U × × × × × CY←(mem) LSB, (mem)←(mem) ÷ 2 If (mem) MSB ≠ bit after (mem) MSB: V←1 If (mem) MSB = bit after (mem) MSB: V←0 U × × × × × 2 temp←CL, while temp ≠ 0, the following operations are repeated: CY←reg LSB, reg←reg ÷ 2 temp←temp – 1 U × U × × × 2 to 4 temp←CL, while temp ≠ 0, the following operations are repeated: CY←(mem) LSB, (mem)←(mem) ÷ 2 temp←temp – 1 U × U × × × 3 temp←imm8, while temp ≠ 0, the following operations are repeated: CY←reg LSB, reg←reg ÷ 2 temp←temp – 1 U × U × × × 3 to 5 temp←imm8, while temp ≠ 0, the following operations are repeated: CY←(mem) LSB, (mem)←(mem) ÷ 2 temp←temp – 1 U × U × × × 2 to 4 2 2 to 4 SHR reg P CY←reg MSB, reg←reg × 2 If reg MSB ≠ CY, V←1 If reg MSB = CY, V←0 2 SHL reg AC CY V 119 µPD70433 7 6 5 4 3 2 1 0 Operation Instruction Group Shift instruction Rotate instruction 120 Operation Code Mnemonic Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg, 1 1 1 0 1 0 0 0W 1 1 1 1 1 mem, 1 1 1 0 1 0 0 0W mod 1 1 1 mem reg, CL 1 1 0 1 0 0 1W 1 1 1 1 1 mem, CL 1 1 0 1 0 0 1W mod 1 1 1 mem reg, imm8 1 1 0 0 0 0 0W 1 1 1 1 1 mem, imm8 1 1 0 0 0 0 0W mod 1 1 1 mem reg, 1 1 1 0 1 0 0 0W 1 1 0 0 0 mem, 1 1 1 0 1 0 0 0W mod 0 0 0 mem reg, CL 1 1 0 1 0 0 1W 1 1 0 0 0 mem, CL 1 1 0 1 0 0 1W mod 0 0 0 mem reg, imm8 1 1 0 0 0 0 0W 1 1 0 0 0 mem, imm8 1 1 0 0 0 0 0W mod 0 0 0 mem reg reg reg reg P S Z U × 0 × × × CY←(mem) LSB, (mem)←(mem) ÷ 2, V←0 MSB of operand is unchanged. U × 0 × × × 2 temp←CL, while temp ≠ 0, the following operations are repeated: CY←reg LSB, reg←reg ÷ 2 temp←temp – 1, MSB of operand is unchanged. U × U × × × 2 to 4 temp←CL, while temp ≠ 0, the following operations are repeated: CY←(mem) LSB, (mem)←(mem) ÷ 2 temp←temp – 1, MSB of operand is unchanged. U × U × × × 3 temp←imm8, while temp ≠ 0, the following operations are repeated: CY←reg LSB, reg←reg ÷ 2 temp←temp – 1, MSB of operand is unchanged. U × U × × × 3 to 5 temp←imm8, while temp ≠ 0, the following operations are repeated: CY←(mem) LSB, (mem)←(mem) ÷ 2 temp←temp – 1, MSB of operand is unchanged. U × U × × × CY←reg MSB, reg←reg × 2 + CY reg MSB ≠ CY: V←1 reg MSB = CY: V←0 × × CY←(mem) MSB, (mem)←(mem) × 2 + CY (mem) MSB ≠ CY: V←1 (mem) MSB = CY: V←0 × × 2 temp←CL, while temp ≠ 0, the following instructions are repeated: CY←reg MSB, reg←reg × 2 + CY temp←temp – 1 × U 2 to 4 temp←CL, while temp ≠ 0, the following instructions are repeated: CY←(mem) MSB, (mem)←(mem) × 2 + CY temp←temp – 1 × U 3 temp←imm8, while temp ≠ 0, the following instructions are repeated: CY←reg MSB, reg←reg × 2 + CY temp←temp – 1 × U 3 to 5 temp←imm8, while temp ≠ 0, the following instructions are repeated: CY←(mem) MSB, (mem)←(mem) × 2 + CY temp←temp – 1 × U 2 to 4 2 2 to 4 ROL reg AC CY V CY←reg LSB, reg←reg ÷ 2, V←0 MSB of operand is unchanged. 2 SHRA reg Operation µPD70433 Instruction Group Operation Code Mnemonic Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg, 1 1 1 0 1 0 0 0W 1 1 0 0 1 mem, 1 1 1 0 1 0 0 0W 1 1 0 1 0 0 1W mem, CL 1 1 0 1 0 0 1W reg, imm8 1 1 0 0 0 0 0W mem, imm8 1 1 0 0 0 0 0W reg, 1 1 1 0 1 0 0 0W mem, 1 1 1 0 1 0 0 0W reg, CL 1 1 0 1 0 0 1W mem, CL 1 1 0 1 0 0 1W mod 0 0 1 mem 1 1 0 0 1 reg AC CY V CY←reg LSB, reg←reg ÷ 2 reg MSB←CY reg MSB ≠ bit after reg MSB: V←1 reg MSB = bit after reg MSB: V←0 × × CY←(mem) LSB, (mem)←(mem) ÷ 2 (mem) MSB←CY (mem) MSB ≠ bit after (mem) MSB: V←1 (mem) MSB = bit after (mem) MSB: V←0 × × 2 temp←CL, while temp ≠ 0, the following operations are repeated: CY←reg LSB, reg←reg ÷ 2 reg MSB←CY temp←temp – 1 × U 2 to 4 temp←CL, while temp ≠ 0, the following operations are repeated: CY←(mem) LSB, (mem)←(mem) ÷ 2 (mem) MSB←CY temp←temp – 1 × U 3 temp←imm8, while temp ≠ 0, the following operations are repeated: CY←reg LSB, reg←reg ÷ 2 reg MSB←CY temp←temp – 1 × U 3 to 5 temp←imm8, while temp ≠ 0, the following operations are repeated: CY←(mem) LSB, (mem)←(mem) ÷ 2 (mem) MSB←CY temp←temp – 1 × U tmpcy←CY, CY←reg MSB reg←reg × 2 + tmpcy reg MSB ≠ CY: V←1 reg MSB = CY: V←0 × × tmpcy←CY, CY←(mem) MSB (mem)←(mem) × 2 + tmpcy (mem) MSB ≠ CY: V←1 (mem) MSB = CY: V←0 × × 2 temp←CL, while temp ≠ 0, the following operations are repeated: tmpcy←CY, CY←reg MSB reg←reg × 2 + tmpcy temp←temp – 1 × U 2 to 4 temp←CL, while temp ≠ 0, the following operations are repeated: tmpcy←CY, CY←(mem) MSB (mem)←(mem) × 2 + tmpcy temp←temp – 1 × U 2 2 to 4 Rotate instructions ROR mod 0 0 1 mem 1 1 0 0 1 reg mod 0 0 1 mem 1 1 0 1 0 reg mod 0 1 0 mem 2 2 to 4 ROLC 1 1 0 1 0 reg mod 0 1 0 mem P S Z 121 µPD70433 reg, CL reg Operation Instruction Group Flags Operand(s) Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg, imm8 1 1 0 0 0 0 0W 1 1 0 1 0 mem, imm8 1 1 0 0 0 0 0W reg reg, 1 mem, 1 reg, CL 1 1 0 1 0 0 0W 1 1 0 1 0 0 0W 1 1 0 1 0 0 1W mod 0 1 0 mem 1 1 0 1 1 reg mod 0 1 1 mem 1 1 0 1 1 reg 3 temp←imm8, while temp ≠ 0, the following instructions are repeated: tmpcy←CY, CY←reg MSB reg←reg × 2 + tmpcy temp←temp – 1 × U 3 to 5 temp←imm8, while temp ≠ 0, the following instructions are repeated: tmpcy←CY, CY←(mem) MSB (mem)←(mem) × 2 + tmpcy temp←temp – 1 × U tmpcy←CY, CY←reg LSB reg←reg ÷ 2 reg MSB←tmpcy reg MSB ≠ bit after reg MSB: V←1 reg MSB = bit after reg MSB: V←0 × × tmpcy←CY, CY←(mem) LSB (mem)←(mem) ÷ 2 (mem) MSB←tmpcy (mem) MSB ≠ bit after (mem) MSB: V←1 (mem) MSB = bit after (mem) MSB: V←0 × × 2 temp←CL, while temp ≠ 0, the following operations are repeated: tmpcy←CY, CY←reg LSB reg←reg ÷ 2 reg MSB←tmpcy temp←temp – 1 × U 2 to 4 temp←CL, while temp ≠ 0, the following operations are repeated: tmpcy←CY, CY←(mem) LSB (mem)←(mem) ÷ 2 (mem) MSB←tmpcy temp←temp – 1 × U 3 temp←imm8, while temp ≠ 0, the following operations are repeated: tmpcy←CY, CY←reg LSB reg←reg ÷ 2 reg MSB←tmpcy temp←temp – 1 × U 3 to 5 temp←imm8, while temp ≠ 0, the following operations are repeated: tmpcy←CY, CY←(mem) LSB (mem)←(mem) ÷ 2 (mem) MSB←tmpcy temp←temp – 1 × U 2 2 to 4 RORC mem, CL reg, imm8 mem, imm8 1 1 0 1 0 0 1W 1 1 0 0 0 0 0W 1 1 0 0 0 0 0W mod 0 1 1 mem 1 1 0 1 1 reg mod 0 1 1 mem Operation AC CY V ROLC Rotate instructions 122 Operation Code Mnemonic P S Z µPD70433 Instruction Group Operation Code Mnemonic Bytes 7 6 5 4 3 2 1 0 Subroutine control instructions CALL Flags Operand(s) near-proc 1 1 1 0 1 0 0 0 regptr16 1 1 1 1 1 1 1 1 memptr16 1 1 1 1 1 1 1 1 far-proc 1 0 0 1 1 0 1 0 memptr32 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 1 1 0 1 0 reg mod 0 1 0 mem mod 0 1 1 mem AC CY V 3 (SP – 1, SP – 2)←PC, SP←SP – 2 PC←PC + disp 2 (SP – 1, SP – 2)←PC, SP←regptr16 SP←SP – 2 2 to 4 5 (SP – 1, SP – 2)←PS, (SP – 3, SP – 4)←PC SP←SP – 4 PC←seg, PC←offset 2 to 4 (SP – 1, SP – 2)←PS, (SP – 3, SP – 4)←PC SP←SP – 4 PC←(memptr32 + 2), PC←(memptr32) 1 PC←(SP + 1, SP) SP←SP + 2 1 1 0 0 0 0 1 0 3 PC←(SP + 1, SP) SP←SP + 2, SP←SP + pop-value 1 1 0 0 1 0 1 1 1 PC←(SP + 1, SP) PS←(SP + 3, SP + 2) SP←SP + 4 pop-value 1 1 0 0 1 0 1 0 3 PC←(SP + 1, SP) PS←(SP + 3, SP + 2) SP←SP + 4, SP←SP + pop-value mem16 1 1 1 1 1 1 1 1 RET reg 1 (SP – 1, SP – 2)←reg16 SP←SP – 2 123 0 0 0 sreg 1 1 0 1 (SP – 1, SP – 2)←sreg SP←SP – 2 PSW 1 0 0 1 1 1 0 0 1 (SP – 1, SP – 2)←PSW SP←SP – 2 R 0 1 1 0 0 0 0 0 1 Push registers on the stack imm8 0 1 1 0 1 0 1 0 2 (SP – 1, SP – 2)←imm8 sign extension SP←SP – 2 imm16 0 1 1 0 1 0 0 0 3 (SP – 1, SP – 2)←imm16 SP←SP – 2 2 (SP – 1, SP – 2)←DS2 SP←SP – 2 * 0 0 0 0 1 1 1 1 This instruction is newly added to the V25 or V35. 0 0 1 1 1 1 1 0 Z (SP – 1, SP – 2)←(mem16) SP←SP – 2 sreg DS2 * 0 1 0 1 0 2 to 4 S µPD70433 Stack manipulation instruction reg16 mod 1 1 0 mem P (SP – 1, SP – 2)←PC, SP←SP – 2 PC←(memptr16) 1 1 0 0 0 0 1 1 pop-value PUSH Operation Instruction Group Stack manipulation instructions PUSH PREPARE * Operation 7 6 5 4 3 2 1 0 DS3/VPC* 0 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 2 (SP – 1, SP – 2)←DS3/VPC SP←SP – 2 mem16 1 0 0 0 1 1 1 1 mod 0 0 0 mem 2 to 4 SP←SP + 2 (mem16)←(SP – 1, SP – 2) 0 1 0 1 1 reg AC CY V 1 SP←SP + 2 reg16←(SP – 1, SP – 2) sreg 0 0 0 sreg 1 1 1 1 SP←SP + 2 sreg16←(SP – 1, SP – 2) PSW 1 0 0 1 1 1 0 1 1 SP←SP + 2 PSW←(SP – 1, SP – 2) R 0 1 1 0 0 0 0 1 1 Pop registers from the stack DS2* 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 2 SP←SP + 2 DS2←(SP – 1, SP – 2) 0 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 2 SP←SP + 2 DS3/VPC←(SP – 1, SP – 2) 1 1 0 0 1 0 0 0 4 Prepare New Stack Frame 1 1 0 0 1 0 0 1 1 Dispose of Stack Frame near-label 1 1 1 0 1 0 0 1 3 PC←PC + disp short-label 1 1 1 0 1 0 1 1 2 PC←PC + ext-disp8 regptr16 1 1 1 1 1 1 1 1 2 PC←regptr16 memptr16 1 1 1 1 1 1 1 1 far-label 1 1 1 0 1 0 1 0 memptr32 1 1 1 1 1 1 1 1 * imm16, imm8 DISPOSE BR Bytes 7 6 5 4 3 2 1 0 reg16 POP Flags Operand(s) DS3/VPC Branch instruction 124 Operation Code Mnemonic 1 1 1 0 0 reg mod 1 0 0 mem 2 to 4 5 mod 1 0 1 mem 2 to 4 P S Z R R R sreg : SS, DS0, DS1 R R R PC←(memptr16) PS←seg PC←offset PS←(memptr32 + 2) PC←(memptr32) This instruction is newly added to the V25 or V35. µPD70433 Instruction Group Conditional branch instructions Operation Code Mnemonic Operand(s) Flags Bytes 7 6 5 4 3 2 1 0 Operation 7 6 5 4 3 2 1 0 AC CY V short-label 0 1 1 1 0 0 0 0 2 if V = 1 PC←PC + ext-disp8 BNV short-label 0 0 0 1 2 if V = 0 PC←PC + ext-disp8 BC BL short-label 0 0 1 0 2 if CY = 1 PC←PC + ext-disp8 BNC BNL short-label 0 0 1 1 2 if CY = 0 PC←PC + ext-disp8 BE BZ short-label 0 1 0 0 2 if Z = 1 PC←PC + ext-disp8 BNE BNZ short-label 0 1 0 1 2 if Z = 0 PC←PC + ext-disp8 BNH short-label 0 1 1 0 2 if CY ∨ Z = 1 PC←PC + ext-disp8 BH short-label 0 1 1 1 2 if CY ∨ Z = 0 PC←PC + ext-disp8 BN short-label 1 0 0 0 2 if S = 1 PC←PC + ext-disp8 BP short-label 1 0 0 1 2 if S = 0 PC←PC + ext-disp8 BPE short-label 1 0 1 0 2 if P = 1 PC←PC + ext-disp8 BPO short-label 1 0 1 1 2 if P = 0 PC←PC + ext-disp8 BLT short-label 1 1 0 0 2 if S ∨ V = 1 PC←PC + ext-disp8 BGE short-label 1 1 0 1 2 if S ∨ V = 0 PC←PC + ext-disp8 BLE short-label 1 1 1 0 2 if (S ∨ Z) ∨ Z = 1 PC←PC + ext-disp8 BGT short-label 1 1 1 1 2 if (S ∨ V) ∨ Z = 0 PC←PC + ext-disp8 DBNZNE short-label 1 1 1 0 0 0 0 0 2 CW = CW – 1 if Z = 0 and CW ≠ 0 PC←PC + ext-disp8 DBNZE short-label 0 0 0 1 2 CW = CW – 1 if Z = 1 and CW ≠ 0 PC←PC + ext-disp8 DBNZ short-label 0 0 1 0 2 CW = CW – 1 if CW ≠ 0 PC←PC + ext-disp8 BCWZ short-label 0 0 1 1 2 if CW = 0 PC←PC + ext-disp8 BTCLR*1 sfr, imm3, short-label 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 5 If (sfr) bit No. imm3 = 1: PC←PC + ext-disp8, (sfr) bit No.imm3←0 BTCLRL*2 sfrl, imm3, short-label 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 5 If (sfrl) bit No. imm3 = 1: PC←PC + ext-disp8, (sfrl) bit No.imm3←0 125 * 1. This instruction is newly added to the V20 or V30. 2. This instruction is newly added to the V25 or V35. S Z µPD70433 BV P Instruction Group Operand(s) Flags Bytes 7 6 5 4 3 2 1 0 Operation 7 6 5 4 3 2 1 0 AC CY V 3 1 1 0 0 1 1 0 0 1 (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0 PS←(15, 14), PC←(13, 12) imm8 (≠ 3) 1 1 0 0 1 1 0 1 2 (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0 PS←(n × 4 + 3, n × 4 + 2), PC←(n × 4 + 1, n × 4) n = imm8 P S Z Interrupt instructions BRK Register bank switching instructions BRKV * If V = 1: (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0 PS←(19, 18), PC←(17, 16) 1 1 0 0 1 1 1 0 1 RETI 1 1 0 0 1 1 1 1 1 PC←(SP + 1, SP), PS←(SP + 3, SP + 2) PSW←(SP + 5, SP + 4), SP←SP + 6 R R R R R R RETRBI* 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 2 PC←Value of PC save area in currently selected bank register, PSW←Value of PSW save area in currently selected bank register R R R R R R FINT* 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 0 2 Indicates to interrupt controller incorporated in CPU that interrupt servicing has ended. 3 PSW save area in currently selected register bank←PSW PC save area in currently selected register bank←PC RB3-0←reg16 low-order 4 bits PSW←Value of PSW save area in newly selected register bank PC←Value of PC save area in newly selected register bank × × × × × × U × U U U × CHKIND reg, mem32 BRKCS* reg16 0 1 1 0 0 0 1 0 mod reg mem 0 0 0 0 1 1 1 1 0 0 1 0 1 1 0 1 3 1 1 0 0 0 reg 0 0 0 0 1 1 1 1 TSKSW* 2 to 4 1 0 0 1 0 1 0 0 reg16 1 1 1 1 1 reg If (mem32) > reg16 or (mem32 + 2) < reg16 (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC, SP←SP – 6 IE←0, BRK←0 PS←(23, 22), PC←(21, 20) temp←PSW RB3 to 0←reg16 low–order 4 bits, IE←0, BRK←0 PSW save area in newly selected register bank←temp PC save area in newly selected register bank←PC ALBIT 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 0 2 If CH + CL ≥ 16: BW, DW→DS1:IY output to transmit buffer If CH + CL < 16: CH + CL→ CH, BW, DW→BW Part exceeding 16 bits: CH+CL–16→CH, BW, DW→BW COLTRP 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 2 Stores 1 line pixel data change point information in change point table (start white run length). MHENC 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 1 2 Generates MH code from change point table. U × U U U × MRENC 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 2 Generates MR code from change point table. U × U U U × This instruction is newly added to the V20 or V30. µPD70433 Dedicated fax instructions 126 Operation Code Mnemonic Instruction Group Dedicated fax instructions CPU control instructions Operation Code Mnemonic Flags Operand(s) Bytes Operation 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 AC CY V P S Z SCHEOL 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 2 "EOL" detection in MH/MR code U × U U U × GETBIT 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 1 2 Fetches pixel data start bit and sets it to CY flag. U × U U U × MHDEC 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 2 Generates change point table from MH code. U × U U U × MRDEC 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 1 2 Generates change point table from MR code. U × U U U × CNVTRP 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 0 2 Converts 1 line change point information in change point table to pixel data. HALT 1 1 1 1 0 1 0 0 1 CPU Halt STOP*1 0 0 0 0 1 1 1 1 2 CPU Stop POLL 1 0 0 1 1 0 1 1 1 Poll and wait DI 1 1 1 1 1 0 1 0 1 IE←0 EI 1 1 1 1 1 0 1 1 1 IE←1 BUSLOCK 1 1 1 1 0 0 0 0 1 Bus Lock Prefix (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS 1 0 0 1 1 1 1 0 fp-op 1 1 0 1 1 X XX 1 1 YYY Z Z Z 2 fp-op, mem 1 1 0 1 1 X XX mod Y Y Y mem 2 to 4 fp-op 0 1 1 0 0 1 1 X 1 1 YYY Z Z Z 2 fp-op, mem 0 1 1 0 0 1 1 X mod Y Y Y mem 2 to 4 FPO1 (SP – 5, SP – 6)←PC – x*6, SP←SP – 6 IE←0, BRK←0 FPO2 NOP *3 1 No Operation 4 When imm8 = imm8’ WDM register←imm8 When imm8 ≠ imm8’ (SP – 1, SP – 2)←PSW, (SP – 3, SP – 4)←PS (SP – 5, SP – 6)←PC – x*6, SP←SP – 6 IE←0, BRK←0 PC←(20H, 21H), PS←(22H, 23H) 0 0 1 sreg 1 1 0 1 Segment override prefix DS2: *2 0 1 1 0 0 0 1 1 1 Extended segment override prefix DS3: *2 1 1 0 1 0 1 1 0 1 Extended segment override prefix IRAM: *2 1 1 1 1 0 0 0 1 1 Register file override prefix RSTWDT*2 *4 *5 1 0 0 1 0 0 0 0 PC←(01DH; 01CH), PS←(01FH, 01EH) 0000 1 1 1 1 1 0 0 1 0 110 imm8 imm8 imm8, imm8 2. This instruction is newly added to the V25 or V35. 3. Watchdog timer manipulation instruction 127 4. Four kinds: DS0:, DS1:, PS:, SS: 5. Register file space access override prefix instruction 6. x: Number of instruction bytes + number of prefixes µPD70433 * 1. This instruction is newly added to the V20 or V30. µPD70433 18. ELECTRICAL SPECIFICATIONS This section shows the electrical specifications of the V55PITM using the three categories below. µPD70433GD/R/GJ-12: µPD70433-12 µPD70433GD/R/GJ-16: µPD70433-16 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) PARAMETER SYMBOL TEST CONDITIONS RATINGS UNIT VDD –0.5 to +7.0 V AVDD –0.5 to VDD + 0.5 V AVSS –0.5 to +0.5 V AVREF –0.5 to AVDD + 0.3 V Input voltage VI –0.5 to VDD + 0.5 V Output voltage VO –0.5 to VDD + 0.5 V One pin 4.0 mA Output current low IOL Total of all pins 100 mA One pin –1.0 mA Total of all pins –20 mA Supply voltage Output current high IOH Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Notes 1. The IC product output (or input/output) pins should not be directly connected between VDD, VCC or GND. However, direct connection between the open-drain pins or betwen the open collector pins is possible. Direct connection is also possible for an external circuit via timing design that avoids collision of output at pins which become high impedance. 2. Exceeding the absolute maximum ratings even in one of the parameters even for an instant may affect the product quality. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore avoid using the product close to the rated values. The specifications and conditions shown in the DC characteristics and AC characteristics comprise the normal operation and guaranteed quality range. 128 µPD70433 DC Characteristics (TA = –40 to +85 °C, VDD = +5.0 V ± 10 %) PARAMETER Input voltage low Input voltage high Schmitt-triggered input threshold voltage SYMBOL MIN. TYP. MAX. UNIT VIL1 *1 0 0.8 V VIL2 *2 0 0.2VDD V VIH1 *1 2.2 VDD V VIH2 *2 0.8VDD VDD V VT VT Schmitt-triggered input hysteresis width TEST CONDITIONS + – + V T – VT – *3, rise 3.3 V *3, fall 1.6 V *3 0.5 V Output voltage low VOL IOL = 2.0 mA Output voltage high VOH IOH = –0.4 mA Input leakage current ILI 0 V ≤ VI ≤ VDD ±10 µA Output leakage current ILO 0 V ≤ VO ≤ VDD ±10 µA VDD supply current*4 IDD1 Operating mode IDD2 HALT mode 3.7 fX 3.7fX + 20 mA IDD3 STOP mode 10 50 µA AIDD1 Operating mode 1.5 2.5 mA AIDD2 HALT mode 0.6 1 mA AIDD3 STOP mode 10 50 µA AVDD supply current 0.45 V VDD –1.0 V 5.4fX + 30 5.4fX + 50 mA * 1. Other than *2 2. RESET, P10/NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/RxD0/SB1/SI0, P32/TxC/SCK0, P33/CTS0, P35/RxD1/SI1, P36/SCK1/CTS1 3. RESET, P10/NMI, P11/INTP0 to P16/INTP5 4. The unit for the constants 5.4 and 3.7 is mA/MHz. CAPACITANCE (TA = 25 °C, VDD = 0 V) PARAMETER SYMBOL Input capacitance CI Output capacitance CO I/O capacitance CIO TEST CONDITIONS MIN. fC = 1 MHz Unmeasured pins are returned to 0 V. TYP. MAX. UNIT 10 pF 20 pF 20 pF OPERATING CONDITIONS PART NUMBER INT. CLOCK FREQUENCY OPERATING TEMPERATURE (TA) SUPPLY VOLTAGE (VDD) µPD70433-12 0.25 MHz ≤ fX ≤ 12.5 MHz –40 to +85 °C +5.0 V ± 10 % µPD70433-16 0.25 MHz ≤ fX ≤ 12.5 MHz 129 µPD70433 RECOMMENDED OSCILLATION CIRCUIT The circuit shown below is recommended for a clock input. (1) Ceramic resonator connection (TA = –40 to +85 ˚C ± 10 %, VDD = 5 V ± 10 %) X1 X2 C1 MANUFACTURER C2 OSCILLATOR FREQUENCY fXX [MHz] PRODUCT NAME 25 32 Murata Mfg. Co., Ltd. RECOMMENDED CONSTANTS C1 [pF] C2 [pF] CSA25.00MXZ040 5 5 CSA32.00MXZ040 3 3 Notes 1. The oscillator should be located as close to the X1 and X2 pins as possible. 2. Other signal lines should not cross the dotted area. 3. When matching the µPD70433 with a resonator, careful evaluation is required. (2) Crystal resonator connection (a) Basic-wave recommended condition (TA = –10 to +70 ˚C, V X1 DD = 5 V ± 10 %) X2 R C1 MANUFACTURER Kinseki C2 OSCILLATOR FREQUENCY fXX [MHz] PRODUCT NAME RECOMMENDED CONSTANTS 25 HC–49/U–S C1 [pF] C2 [pF] R [Ω] 5 5 200 10 10 – Notes 1. The oscillator should be located as close to the X1 and X2 pins as possible. 2. Other signal lines should not cross the dotted area. 3. When matching the µPD70433 with a resonator, careful evaluation is required. 130 µPD70433 (b) 3rd-overtone recommended condition (TA = –20 to +70 ˚C, V X1 MANUFACTURER Kinseki = 5 V ± 10 %) X2 C3 C1 DD R C2 L OSCILLATOR FREQUENCY fXX [MHz] 25 32 RECOMMENDED CONSTANTS PRODUCT NAME HC–49/U C1 [pF] C2 [pF] C3 [pF] L [µH] R [Ω] 15 15 1000 3.3 100 10 5 1000 3.3 100 Notes 1. The oscillator should be located as close to the X1 and X2 pins as possible. 2. Other signal lines should not cross the dotted area. 3. When matching the µPD70433 with a resonator, careful evaluation is required. (3) External clock input X1 X2 Open 131 µPD70433 AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5.0 V ± 10 %) (1) µPD70433-12 PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT 250 ns X1 input cycle time 1 tCYX 40 X1 input high-level width 2 tWXH 15 ns X1 input low-level width 3 tWXL 15 ns X1 input rise time 4 tXR 10 ns X1 input fall time 5 tXF 10 ns CLKOUT output cycle time 6 tCYK 80 4000 ns CLKOUT output high-level width 7 tWKH 0.5T – 5 ns CLKOUT output low-level width 8 tWKL 0.5T – 5 ns CLKOUT output rise time 9 tKR 7 ns CLKOUT output fall time 10 tKF 7 ns 11 tIR1 *1 10 ns 12 tIR2 *2 20 ns 13 tIF1 *1 10 ns 14 tIF2 *2 20 ns Output rise time 15 tOR 10 ns Output fall time 16 tOF 10 ns CLKOUT delay time from X1↑ 118 tDXK 18 ns Address delay time from CLKOUT↑ 17 tDKA 5 27 ns 18 tHKA1 0 ns 19 tHKA2 0 ns Address float delay time from CLKOUT↑ 20 tFKA tHKA1 Address setup time (to ASTB↓) 21 tSAST (n + 0.5)T – 25 ns Address hold time (from ASTB↓) 22 tHSTA 0.5T – 15 ns ASTB↓ delay time from CLKOUT↓ 23 tDKSTL 0 22 ns ASTB↑ delay time from CLKOUT↓ 24 tDKSTH 0 22 ns ASTB high-level width 25 tWSTH (n + 1)T – 15 RD↓ delay time from CLKOUT↑ 26 tDKRL 0 22 ns RD↑ delay time from CLKOUT↑ 27 tDKRH 0 22 ns RD low-level width 28 tWRL (N + 1.5)T – 15 ns RD↓ delay time from address float 29 tFARL 0 ns Address delay time from RD↑ 30 tDRA 0.5T ns Input rise time Input fall time X2: open Address hold time (from CLKOUT↑) 36 ns ns n : Number of address wait states N : Number of data wait states T : tCYK * 1. Other than *2 2. RESET, P10 NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/RXD0/SB1/SI0, P32/TXC/SCK0, P33/ CTS0, P35/RXD1/SI1, P36/SCK1/CTS1 Remark 132 Numbers in the Symbol column correspond to numbers in the timing charts. µPD70433 PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT ASTB↑ delay time from RD↑, IORD↑ 119 tDRSTH 0 ns RD↑, IORD↑ delay time from WRL↑, WRH↑, IOWR↑ 120 tDWRH 0 ns DEX delay time from CLKOUT↓ 31 tDKDX 0 DEX hold time (from CLKOUT↓) 32 tHKDX 0 ns Data input setup time (to CLKOUT↓) 33 tSDK 11 ns Data input hold time (from CLKOUT↓) 34 tHKDR 0 ns WR↓ delay time from CLKOUT↓ 35 tDKWL 0 22 ns WR↑ delay time from CLKOUT↓ 36 tDKWH 0 22 ns WR low-level width 37 tWWL (N + 1)T – 12 Data output delay time from CLKOUT↑ 38 tDKD 3 Data output hold time (from CLKOUT↓) 39 tHKDW 0 ns ASTB↑ delay time from WR↑ 40 tDWSTH 0 ns RAS↓ delay time from CLKOUT↑ 41 tDKRAL nT nT + 22 ns RAS↑ delay time from CLKOUT↑ 42 tDKRAH 0 22 ns RAS high-level width 43 tWRAH (n + 1)T – 15 ns RAS↑ delay time from WRH↓, WRL↓ 121 tDWRAH (N + 0.5)T – 10 ns Address setup time (to RAS↓) 122 tSARAL nT – 12 ns READY setup time (to CLKOUT↓) 44 tSRYHK 18 ns READY hold time (from CLKOUT↓) 45 tHKRYL 12 ns READY setup time (to CLKOUT↓) 46 tSRYLK 18 ns READY hold time (from CLKOUT↓) 47 tHKRYH 12 ns 48 tWRSL1 STOP release/power-on reset 30 ms 49 tWRSL2 System reset 1000 + 2T ns NMI high-level width 50 tWNIH 5 µs NMI low-level width 51 tWNIL 5 µs INTPm setup time (to CLKOUT↓) 52 tSIQK m = 0 to 5 25 ns INTPm high-level width 53 tWIQH m = 0 to 5 10T ns INTPm low-level width 54 tWIQL m = 0 to 5 10T ns POLL setup time (to CLKOUT↓) 55 tSPLK 25 ns HLDRQ setup time (to CLKOUT↓) 56 tSHQK 25 ns HLDAK↓ delay time from CLKOUT↑ 57 tDKHA 0 HLDAK↓ delay time from bus float 58 tFCHA 0 ns Bus output delay time from HLDAK↑ 59 tDHAC T – 22.5 ns 27 ns ns 27 ns RESET low-level width 27 ns n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts. 133 µPD70433 PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT 3.5T + 35 ns HLDAK↑ delay time from HLDRQ↓ 60 tDHQHA 0.5T – 15 Bus output delay time from HLDRQ↓ 61 tDHQC 0.5T + 45 ns HLDRQ low-level width 62 tWHQL 2T ns HLDAK low-level width 63 tWHAL 3T – 10 ns BUSLOCK delay time from CLKOUT↑ 64 tDKBL 0 DMARQm setup time (to CLKOUT↓) 65 tSDQK Except demand release mode; m = 0, 1 25 ns DMARQm high-level width 66 tWDQH Except demand release mode; m = 0, 1 2T ns DMARQm low-level width 67 tWDQL Except demand release mode; m = 0, 1 2T ns DMARQm setup time (to CLKOUT↑) 68 tSKDQ Demand release mode; m = 0 or 1 DMARQm low-level hold time (from CLKOUT↓) 69 tHKDQ Demand release mode; m = 0 or 1 12 DMAAKm↓ delay time from CLKOUT↑ 70 tDKDA m = 0 or 1 0 DMAAKm low-level width 71 tWDAL m = 0 or 1 (3 + n + N)T – 10 TCEm↓ delay time from CLKOUT↑ 72 tDKTE m = 0 or 1 0 TCEm low-level width 73 tWTCL m = 0 or 1 T – 10 ns TOUT high-level width 74 tWTOH 8T – 10 ns TOUT low-level width 75 tWTOL 8T – 10 ns WDTOUT low-level width 76 tWWTL 32T – 10 ns 8T ns SCK cycle time 77 tCYSK Output 8T – 10 ns Input 4T – 10 ns Output 4T – 10 ns Input 4T – 10 ns Output 4T – 10 ns Input SCK high-level width SCK low-level width 78 79 27 5 ns ns ns 27 ns ns 27 ns tWSKH tWSKL SI, SB setup time (to SCK↑) 80 tSSSK 50 ns SI, SB hold time (from SCK↑) 81 tHSKS 150 ns 82 tDSKSB1 IOE mode (CMOS push-pull output) 0 90 ns 83 tDSKSB2 SBI mode (open-drain output, RL = 1 kΩ) 0 190 ns 84 tHSKSB SO, SB delay time from SCK↓ SB high-level hold time (from SCK↑) 4T ns SBI mode SB low-level setup time (to SCK↓) 85 tSSBSK 4T ns SB high-level width 86 tWSBH 4T ns SB low-level width 87 tWSBL 4T ns n : Number of address wait states N : Number of data wait states T : tCYK Remark 134 Numbers in the Symbol column correspond to numbers in the timing charts. µPD70433 PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT CTS high-level width 88 tWCTH 2T ns CTS low-level width 89 tWCTL 2T ns Transmit/receive data cycle 90 tCYD 32T ns TXC output clock cycle 91 tCYC 32T ns TXC output clock high-level width 92 tWCH 16T – 10 ns TXC output clock low-level width 93 tWCL 16T – 10 ns TXD delay time from TXC↓ 94 tDTCTD TXD delay time from CTS↓ 95 tDCTTD DATASTB setup time 96 tSDSK Input mode 25 ns 97 tWDSL1 Input mode 2T ns 98 tWDSL2 Output mode 99 tSPDDS1 Input mode UART UART 0 90 ns 2tCYC ns DATASTB low-level width PD setup time (to DATASTB↓) PD hold time (from DATASTB↓) 100 tHDSPD1 BUSY delay time from DATASTB↓ 101 tDDSBY1 PD setup time (to DATASTB↑) 102 tSPDDS2 (DATASTB↓ latch mode) 2T – 10 512T 45 ns 4T ns 4T Input mode (DATASTB↑ latch mode) ns ns 45 ns 4T ns PD hold time (from DATASTB↑) 103 tHDSPD2 BUSY delay time from DATASTB↑ 104 tDDSBY2 DATASTB↓ delay time from PD 105 tDPDDSL 2T – 30 DATASTB setup time (to ACK↓) 106 tSDSAK 0 ns ACK input low-level width 107 tWAKL 2T ns DATASTB setup time (to BUSY↑) 108 tSDSBY 0 ns BUSY input high-level width 109 tWBYH 2T ns Port output delay time (from CLKOUT↓) 123 tDKP 8 Port input setup time (to CLKOUT↓) 124 tSPK 25 ns Port input hold time (from CLKOUT↓) 125 tHKP 16 ns DMARQm high-level hold time (from ASTB↓) 126 tHSTDQ 0 ns REFRQ↓ delay time from CLKOUT↑ 127 tDKREL 0 25 ns REFRQ↑ delay time from CLKOUT↑ 128 tDKREH 0 25 ns RAS delay time from REFRQ↓ 129 tDRERA nT – 5 ns RD↓ delay time from ASTB↓ 130 tDSTLRL 0.5T – 5 ns Output mode Demand release mode; m = 0 or 1 4T ns 512T ns 50 ns n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts. 135 µPD70433 (2) µPD70433-16 PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT 250 ns X1 input cycle time 1 tCYX 31.25 X1 input high-level width 2 tWXH 12 ns X1 input low-level width 3 tWXL 12 ns X1 input rise time 4 tXR 5 ns X1 input fall time 5 tXF 5 ns CLKOUT output cycle time 6 tCYK 62.5 4000 ns CLKOUT output high-level width 7 tWKH 0.5T – 5 ns CLKOUT output low-level width 8 tWKL 0.5T – 5 ns CLKOUT output rise time 9 tKR 5 ns CLKOUT output fall time 10 tKF 5 ns 11 tIR1 *1 10 ns 12 tIR2 *2 20 ns 13 tIF1 *1 10 ns 14 tIF2 *2 20 ns Output rise time 15 tOR 10 ns Output fall time 16 tOF 10 ns CLKOUT delay time from X1↓ 118 tDXK 18 ns Address delay time from CLKOUT↑ 17 tDKA 5 27 ns 18 tHKA1 0 ns 19 tHKA2 0 ns Address float delay time from CLKOUT↑ 20 tFKA tHKA1 Address setup time (to ASTB↓) 21 tSAST (n + 0.5)T – 25 ns Address hold time (from ASTB↓) 22 tHSTA 0.5T – 15 ns ASTB↓ delay time from CLKOUT↓ 23 tDKSTL 0 22 ns ASTB↑ delay time from CLKOUT↓ 24 tDKSTH 0 22 ns ASTB high-level width 25 tWSTH (n + 1)T – 15 RD↓ delay time from CLKOUT↑ 26 tDKRL 0 22 ns RD↑ delay time from CLKOUT↓ 27 tDKRH 0 22 ns RD low-level width 28 tWRL (N + 1.5)T – 15 ns RD↓ delay time from address float 29 tFARL 0 ns Address delay time from RD↑ 30 tDRA 0.5T ns Input rise time Input fall time X2: open Address hold time (from CLKOUT↑) 36 ns ns n : Number of address wait states N : Number of data wait states T : tCYK * 1. Other than *2 2. RESET, P10 NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/RXD0/SB1/SI0, P32/TXC/SKC0, P33/ CTS0, P35/RXD1/SI1, P36/SCK1/CTS1 Remark 136 Numbers in the Symbol column correspond to numbers in the timing charts. µPD70433 PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT ASTB↑ delay time from RD↑, IORD↑ 119 tDRSTH 0 ns RD↑, IORD↑ delay time from WRL↑, WRH↑, IOWR↑ 120 tDWRH 0 ns DEX delay time from CLKOUT↓ 31 tDKDX 0 DEX hold time (from CLKOUT↓) 32 tHKDX 0 ns Data input setup time (to CLKOUT↓) 33 tSDK 11 ns Data input hold time (from CLKOUT↓) 34 tHKDR 0 ns WR↓ delay time from CLKOUT↓ 35 tDKWL 0 22 ns WR↑ delay time from CLKOUT↓ 36 tDKWH 0 22 ns WR low-level width 37 tWWL (N + 1)T – 12 Data output delay time from CLKOUT↑ 38 tDKD 3 Data output hold time (from CLKOUT↓) 39 tHKDW 0 ns ASTB↑ delay time from WR↑ 40 tDWSTH 0 ns RAS↓ delay time from CLKOUT↑ 41 tDKRAL nT nT + 22 ns RAS↑ delay time from CLKOUT↑ 42 tDKRAH 0 22 ns RAS high-level width 43 tWRAH (n + 1)T – 15 ns RAS↑ delay time from WRH↓, WRL↓ 121 tDWRAH (N + 0.5)T – 10 ns Address setup time (to RAS↓) 122 tSARAL nT – 12 ns READY setup time (to CLKOUT↓) 44 tSRYHK 18 ns READY hold time (from CLKOUT↓) 45 tHKRYL 12 ns READY setup time (to CLKOUT↓) 46 tSRYLK 18 ns READY hold time (from CLKOUT↓) 47 tHKRYH 12 ns 48 tWRSL1 STOP release/power-on reset 30 ms 49 tWRSL2 System reset 1000 + 2T ns NMI high-level width 50 tWNIH 5 µs NMI low-level width 51 tWNIL 5 µs INTPm setup time (to CLKOUT↓) 52 tSIQK m = 0 to 5 25 ns INTPm high-level width 53 tWIQH m = 0 to 5 10T ns INTPm low-level width 54 tWIQL m = 0 to 5 10T ns POLL setup time (to CLKOUT↓) 55 tSPLK 25 ns HLDRQ setup time (to CLKOUT↓) 56 tSHQK 25 ns HLDAK↓ delay time from CLKOUT↑ 57 tDKHA 0 HLDAK↓ delay time from bus float 58 tFCHA 0 ns Bus output delay time from HLDAK↑ 59 tDHAC T – 22.5 ns 27 ns ns 27 ns RESET low-level width 27 ns n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts. 137 µPD70433 PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT 3.5T + 35 ns HLDAK↑ delay time from HLDRQ↓ 60 tDHQHA 0.5T – 15 Bus output delay time from HLDRQ↓ 61 tDHQC 0.5T + 45 ns HLDRQ low-level width 62 tWHQL 2T ns HLDAK low-level width 63 tWHAL 3T – 10 ns BUSLOCK delay time from CLKOUT↑ 64 tDKBL 0 DMARQm setup time (to CLKOUT↓) 65 tSDQK Except demand release mode; m = 0 or 1 25 ns DMARQm high-level width 66 tWDQH Except demand release mode; m = 0 or 1 2T ns DMARQm low-level width 67 tWDQL Except demand release mode; m = 0 or 1 2T ns DMARQm setup time (to CLKOUT↑) 68 tSKDQ Demand release mode; m = 0 or 1 DMARQm low-level hold time (from CLKOUT↓) 69 tHKDQ Demand release mode; m = 0 or 1 12 DMAAKm↓ delay time from CLKOUT↑ 70 tDKDA m = 0 or 1 0 DMAAKm low-level width 71 tWDAL m = 0 or 1 (3 + n + N)T – 10 TCEm↓ delay time from CLKOUT↑ 72 tDKTE m = 0 or 1 0 TCEm low-level width 73 tWTCL m = 0 or 1 T – 10 ns TOUT high-level width 74 tWTOH 8T – 10 ns TOUT low-level width 75 tWTOL 8T – 10 ns WDTOUT low-level width 76 tWWTL 32T – 10 ns 8T ns SCK cycle time 77 tCYSK Output 8T – 10 ns Input 4T – 10 ns Output 4T – 10 ns Input 4T – 10 ns Output 4T – 10 ns Input SCK high-level width SCK low-level width 78 79 27 5 ns ns ns 27 ns ns 27 ns tWSKH tWSKL SI, SB setup time (to SCK↑) 80 tSSSK 50 ns SI, SB hold time (from SCK↑) 81 tHSKS 150 ns 82 tDSKSB1 IOE mode (CMOS push-pull output) 0 90 ns 83 tDSKSB2 SBI mode (open-drain output, RL = 1 kΩ) 0 190 ns 84 tHSKSB SO, SB delay time from SCK↓ SB high-level hold time (from SCK↑) 4T ns SBI mode SB low-level setup time (to SCK↓) 85 tSSBSK 4T ns SB high-level width 86 tWSBH 4T ns SB low-level width 87 tWSBL 4T ns n : Number of address wait states N : Number of data wait states T : tCYK Remark 138 Numbers in the Symbol column correspond to numbers in the timing charts. µPD70433 PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT CTS high-level width 88 tWCTH 2T ns CTS low-level width 89 tWCTL 2T ns Transmit/receive data cycle 90 tCYD 32T ns TXC output clock cycle 91 tCYC 32T ns TXC output clock high-level width 92 tWCH 16T – 10 ns TXC output clock low-level width 93 tWCL 16T – 10 ns TXD delay time from TXC↓ 94 tDTCTD TXD delay time from CTS↓ 95 tDCTTD DATASTB setup time 96 tSDSK Input mode 25 ns 97 tWDSL1 Input mode 2T ns 98 tWDSL2 Output mode 99 tSPDDS1 Input mode UART UART 0 90 ns 2tCYC ns DATASTB low-level width PD setup time (to DATASTB↓) PD hold time (from DATASTB↓) 100 tHDSPD1 BUSY delay time from DATASTB↓ 101 tDDSBY1 PD setup time (to DATASTB↑) 102 tSPDDS2 (DATASTB↓ latch mode) 2T – 10 512T 45 ns 4T ns 4T Input mode (DATASTB↑ latch mode) ns ns 45 ns 4T ns PD hold time (from DATASTB↑) 103 tHDSPD2 BUSY delay time from DATASTB↑ 104 tDDSBY2 DATASTB↓ delay time from PD 105 tDPDDSL 2T – 30 DATASTB setup time (to ACK↓) 106 tSDSAK 0 ns ACK input low-level width 107 tWAKL 2T ns DATASTB setup time (to BUSY↑) 108 tSDSBY 0 ns BUSY input high-level width 109 tWBYH 2T ns Port output delay time (from CLKOUT↓) 123 tDKP 8 Port input setup time (to CLKOUT↓) 124 tSPK 25 ns Port input hold time (from CLKOUT↓) 125 tHKP 16 ns DMARQm high-level hold time (from ASTB↓) 126 tHSTDQ 0 ns REFRQ↓ delay time from CLKOUT↑ 127 tDKREL 0 25 ns REFRQ↑ delay time from CLKOUT↑ 128 tDKREH 0 25 ns RAS delay time from REFRQ↓ 129 tDRERA nT – 5 ns RD↓ delay time from ASTB↓ 130 tDSTLRL 0.5T – 5 ns TI high-level width 131 tWTIH 4T ns TI low-level width 132 tWTIL 4T ns TOm setup time (to CLKOUT↓) 133 tDKT Output mode Demand release mode; m = 0 or 1 m = 00, 01, 20, 21, 30 5 4T ns 512T ns 50 30 ns ns n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts. 139 µPD70433 A/D CONVERTER CHARACTERISTICS (TA= –40 to +85 °C, VDD = +5.0 V ± 10 %, AVSS = 0 V, VDD – 0.5 V ≤ AVDD ≤ VDD) PARAMETER SYMBOL TEST CONDITIONS MIN. Resolution TYP. MAX. UNIT 8 Total error *1 Bit 3.4 V ≤ AVREF ≤ AVDD 0.8 % 4.5 V ≤ AVREF ≤ AVDD 0.6 % ±1/2 LSB Quantization error 80 ns ≤ T ≤ 125 ns (for µPD70433, 70433-12) Conversion time tCONV Sampling time tSAMP 160T ns 125 ns ≤ T ≤ 250 ns 120T ns 80 ns ≤ T ≤ 125 ns (for µPD70433, 70433-12) 32T ns 24T ns 65 ns ≤ T ≤ 125 ns (for µPD70433-16) 65 ns ≤ T ≤ 125 ns (for µPD70433-16) 125 ns ≤ T ≤ 250 ns Analog input voltage VIAN Analog input impedance –0.3 Non-sampling AVREF + 0.3 1000 V MΩ RAN Sampling Reference voltage AVREF AVREF current AIREF *2 3.4 T = 80 ns 1.5 AVDD V 5.0 mA T: tCYK * 1. Excluding quantization error 2. Analog input impedance is identical with the equivalent circuit shown below. (The values in the figure are not guaranteed, but are TYP. values) 20 kΩ Analog Input Pin 30 pF (Input Capacitance Included) 5 pF DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85 °C) PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT 5.5 V Data retention supply voltage 115 VDDDR 2.5 Supply voltage rise time 116 tRVD 200 µs Supply voltage fall time 117 tFVD 200 µs Remark 140 Numbers in the Symbol column correspond to number in the timing chart. µPD70433 AC Test Input Waveform *1 2.4 V 2.2 V 0.4 V 0.8 V Test Points 2.2 V 0.8 V 13 11 * 1. Except *2 AC Test Input Waveform *2 VDD 0.8VDD 0.4 V 0.8 V Test Points 0.8VDD 0.8 V 14 12 * 2. RESET, P10/NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/RxD0/SB1/SI0, P32/TxC/SCK0, P33/CTS0, P35/RXD1/SI1, P36/SCK1/CTS1 AC Test Output Test Points 2.2 V 0.8 V Test Points 2.2 V 0.8 V Load Conditions CL = 100 pF DUT Note If the load capacitance exceeds 100 pF due to the configuration of the circuit, the load capacitance of this device should be reduced to 100 pF or less by insertion of a buffer, etc. Remark DUT: Measured device 141 µPD70433 Clock Input/Output Timing 1 0.8 VDD X1 0.8 V 2 4 3 5 7 8 118 2.2 V CLKOUT 0.8 V 9 10 6 Output Waveform (Except CLKOUT) 2.2 V 2.2 V 0.8 V 0.8 V 16 142 15 µPD70433 Read Timing T1 T2 T3 CLKOUT 20 17 A16-A23, AD8-AD15 (With 8-Bit External Bus) 19 Address 33 34 18 29 AD0-AD7, AD8-AD15 (With 16-Bit External Bus) Address Data 24 21 22 30 25 ASTB 42 23 43 122 RAS*1 41 130 119 26 27 30 RD, IORD 28 WRL, WRH, IOWR 31 32 DEX*2 * 1. Only activated when memory block 1 or 4 (set by the MBS register) is accessed. 2. Only valid when the external bus width is 16 bits. Remark The dotted line indicates high-impedance. 143 µPD70433 Write Timing T1 T2 T3 CLKOUT A16-A23, AD8-AD15 (With 8-Bit External Bus) 19 17 Address 18 38 AD0-AD7, AD8-AD15 (With 16-Bit External Bus) 39 Address 21 Data 22 24 25 ASTB 23 42 43 122 RAS*1 41 121 RD, IORD 35 40 36 WRL, WRH, IOWR 37 31 DEX*2 * 1. Only activated when memory block 1 or 4 (set by the MBC register) is accessed. 2. Only valid when the external bus width is 16 bits. Remark 144 The dotted line indicates high-impedance. 32 µPD70433 Refresh Timing T1 T2 T3 CLKOUT 20 17 A16-A23, AD8-AD15 (With 8-Bit External Bus) 19 Address 18 AD0-AD7, AD8-AD15 (With 16-Bit External Bus) Address 24 21 22 25 ASTB 23 42 43 122 RAS 41 27 RD, IORD 36 WRL, WRH, IOWR 31 32 DEX* 129 127 128 REFRQ * Only valid when the external bus width is 16 bits. Remark The dotted line indicates high-impedance. 145 µPD70433 Ready Input Timing (1) 1 data wait inserted T1 T2 TW1 T3 TW1 TW2 CLKOUT 44 45 READY (2) 2 data waits inserted T1 T2 T3 47 CLKOUT 45 46 44 READY n data waits inserted (n ≥ 3) (3) T1 T2 TWn–2 TWn–1 TWn T3 47 CLKOUT 45 46 44 READY Remark 146 The READY input becomes valid when the corresponding field of the PWCn register (n = 0 or 1) is other than "00" (binary). µPD70433 DMA Timing (External Memory → External I/O) T1 T2 T3 CLKOUT 17 19 20 A16-A23, AD8-AD15 (With 8-Bit External Bus) Address 18 AD0-AD7, AD8-AD15 (With 16-Bit External Bus) Address 24 30 22 25 ASTB 23 42 43 122 119 RAS *1 30 41 29 27 130 RD 26 28 WRL, WRH, IORD 120 35 36 IOWR 37 70 70 71 DMAAK0, DMAAK1 72 TCE0, *2 TCE1 31 73 32 DEX *3 * 1. Only activated when a DMA transfer is performed on memory block 1 or 4 (set by the MBC register). 2. The bus is activated at the last transfer in intelligent DMA mode-2, 2-channel operating mode (stop in termination), or memory-to-memory transfer mode (stop in termination). 3. Only valid when the external bus width is 16 bits. Remark The dotted line indicates high-impedance. 147 µPD70433 DMA Timing (External I/O → External Memory) T1 T2 T3 CLKOUT A16-A23, AD8-AD15 (With 8-Bit External Bus) 17 20 19 Address 18 AD0-AD7, AD8-AD15 (With 16-Bit External Bus) Address 24 30 21 22 25 ASTB 23 42 43 122 RAS *1 41 121 RD, IOWR 40 35 36 WRL, WRH 30 37 29 120 IORD 130 26 70 28 27 70 71 DMAAK0, DMAAK1 72 TCE0, *2 TCE1 73 31 32 DEX *3 * 1. Only activated when a DMA transfer is performed on memory block 1 or 4 (set by the MBC register). 2. The bus is activated at the last transfer in intelligent DMA mode–2, 2–channel operating mode (stop in termination), or memory-to-memory transfer mode (stop in termination). 3. Only valid when the external bus width is 16 bits. Remark 148 The dotted line indicates high-impedance. µPD70433 INRPm Input Timing (m = 0 to 5) CLKOUT 52 52 INTP0-INTP5 53 54 NMI Input Timing CLKOUT NMI 50 51 POLL Input Timing CLKOUT 55 55 POLL 149 µPD70433 DMARQm Input Timing (m = 0 or 1) (1) In demand release mode (I/O-to-memory transfer) (a) Address wait not inserted T1 T2 T3 T1 T2 T3 CLKOUT ASTB 70 DMAAK0, DMAAK1 69 70 126 68 DMARQ0, DMARQ1 68 (b) Address wait inserted TAW T1 T2 T3 T1 TAW T2 T3 CLKOUT ASTB 70 DMAAK0, DMAAK1 69 126 68 DMARQ0, DMARQ1 68 (2) In the mode other than demand release mode CLKOUT 65 65 DMARQ0, DMARQ1 66 150 67 70 µPD70433 Timer Output Timing CLKOUT 131 132 TI1 133 133 TO00, TO01, TO20 TO21, TO30 74 75 WDTOUT Output Timing WDTOUT 76 BUSLOCK Output Timing CLKOUT 64 64 BUSLOCK Data Retention Timing (STOP Mode) VDD 115 117 116 151 µPD70433 Hold Request/Acknowledge Timing (1) In normal mode CLKOUT 56 56 HLDRQ 57 62 Bus Control Signal* Hi-Z 60 58 HLDAK 63 * ASTB, RD, WRH, WRL, DEX, RAS, BUSLOCK, IORD, IOWR, AD0 to AD15, A16 to A23 (2) Release of hold mode for refresh cycle insertion CLKOUT 56 HLDRQ 62 Bus Control Signal* Hi-Z 57 61 HLDAK * 152 ASTB, RD, WRH, WRL, DEX, RAS, BUSLOCK, IORD, IOWR, AD0 to AD15, A16 to A23 59 µPD70433 RESET Input Timing (1) STOP mode release/power-on reset CLKOUT 48 RESET (2) System reset CLKOUT 49 RESET CTSm Input Timing (m = 0 or 1) CTS0, CTS1 88 89 153 µPD70433 Serial Interface Timing (1) 3-wire serial I/O mode 79 78 SCK0, SCK1 77 80 SI0, SI1 81 Input Data 82 SO0, SO1 (2) Output Data SBI mode Bus release signal transfer timing SCK0 84 87 86 85 SB0, SB1 Command signal transfer timing 79 78 SCK0 84 SB0, SB1 154 85 77 83 80 Input/Output Data 81 µPD70433 (3) UART mode Transmit timing 91 93 92 T×C 94 90 T×D0 Output Data 90 T×D1 Output Data Receive timing 90 Input Data R×D0, R×D1 Transmission enale timing CTS0, CTS1 95 T×D0, T×D1 Start Bit 155 µPD70433 Parallel Interface Timing (1) Input mode CLKOUT 96 97 DATASTB 99 100 102 PD0–PD7 103 Input Data 104 101 BUSY (2) Output mode DATASTB 105 98 PD0–PD7 Output Data 106 107 ACK 108 BUSY 156 109 µPD70433 Port Input/Output Timing T2/TI T3 T1/TI CLKOUT 124 Input Port 125 Output Port 123 157 µPD70433 19. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) IOH vs (VDD – VOH) (TA = 25 °C, VDD = 5.0 V) High-Level Output Current I OH [mA] –3.0 –2.0 –1.0 0 0 0.2 0.4 Supply Voltage – High-Level Output Voltage 0.6 VDD – VOH [V] IOL vs VOL (TA = 25 °C, VDD = 5.0 V) Low-Level Output Current I OL [mA] 6.0 4.0 2.0 0 0 0.2 Low-Level Output Voltage 158 0.4 VOL [V] 0.6 µPD70433 20. PACKAGE DRAWINGS 120 PIN PLASTIC QFP ( 28) A B 90 91 61 60 F 120 1 G 5°±5° Q D C S detail of lead end 31 30 H I M J M P K N L P120GD-80-5BB-3 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 32.0 ± 0.4 1.260 ± 0.016 B 28.0 ± 0.2 1.102+0.009 –0.008 C 28.0 ± 0.2 1.102+0.009 –0.008 D 32.0 ± 0.4 1.260 ± 0.016 F 2.4 0.094 G 2.4 0.094 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 2.0 ± 0.2 0.079 –0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 3.7 0.146 Q 0.1 ± 0.1 0.004 ± 0.004 S 4.0 MAX. 0.157 MAX. +0.009 159 µPD70433 120 PIN PLASTIC QFP (FINE PITCH) ( 20) A B 90 61 91 60 Q R D C S detail of lead end 31 F 120 1 G 30 H I M J M P K N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 22.0±0.2 INCHES 0.866±0.008 B 20.0±0.2 0.787 +0.009 –0.008 C 20.0±0.2 0.787 +0.009 –0.008 D 22.0±0.2 0.866±0.008 F G 2.75 2.75 0.108 0.108 H 0.22 +0.05 –0.04 0.009±0.002 I 0.10 0.004 J 0.5 (T.P.) 0.020 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N P 0.10 2.7 0.004 0.106 Q 0.125±0.075 0.005±0.003 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S120GJ-50-3EB-2 160 µPD70433 132 PIN CERAMIC PGA A (Bottom View) D 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P N M L K J H G F E D C B A I Orientation pin H G J Index mark E K L φM M F X132R-100A-1 NOTE Each lead centerline is located within φ 0.5 mm ( φ 0.020 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 35.56 ± 0.3 1.400 ± 0.012 D 35.56 ± 0.3 1.400 ± 0.012 E 1.27 0.050 F 2.54 (T.P.) 0.100 (T.P.) G 2.8 ± 0.3 0.110 ± 0.012 H 0.9 MIN. 0.035 MIN. I 2.95 0.116 J 4.57 MAX. 0.180 MAX. K φ 1.2 ± 0.2 φ 0.047+0.009 –0.008 L φ 0.46 ± 0.05 φ 0.018 ± 0.002 M 0.254 0.010 161 µPD70433 21. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and conditions other than those recommended, contact our sales personnel. Table 21-1. Surface Mount Type Soldering Conditions (1) µPD70433GD-xx-5BB : 120-Pin Plastic QFP (28 × 28 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Within twice, Time limit: 7 days* (thereafter 36 hours 125 °C prebanking required) IR35-367-2 VPS Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above), Number of times: Within twice, Time limit: 7 days* (thereafter 36 hours 125 °C prebanking required) VP15-367-2 Wave soldering Solder bath temperature: 260 °C or less, Time: 10 sec. max., Number of times: Once, Time limit: 7 days* (thereafter 35 hours 125 °C prebanking required), Preheating temperature: 120 °C max. (Package surface temperature) WS60-367-1 Partial heating Pin temperature: 300 °C or below, Duration: 3 sec. max. (per pin row) ––– For the storage period after dry-pack decompression, storage conditions are max. 25 °C, 65 % RH. * Note Use of more than one soldering method should be avoided (except in the case of partial heating method). (2) µPD70433GJ-xx-3EB : 120-Pin Plastic QFP (Fine Pitch) (20 × 20 mm) Soldering Method Note Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Within twice IR35-00-2 VPS Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above), Number of times: Within twice VP15-00-2 Partial heating Pin temperature: 300 °C or below, Duration: 3 sec. max. (per pin row) ––– Use of more than one soldering method should be avoided (except in the case of partial heating method). Table 21-2. Insertion Type Soldering Conditions µPD70433R-xx : 132-Pin Ceramic PGA Soldering Method Note 162 Soldering Conditions Wave soldering (lead part only) Solder temperature: 260 °C or less, Duration: 10 sec. max. Partial heating Pin temperature: 300 °C or less, Duration: 3 sec. max. (per pin row) Wave soldering is used on the lead part only, and care must be taken to prevent solder from coming into direct contact with the body. µPD70433 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 163 µPD70433 [MEMO] 164 µPD70433 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 165 µPD70433 [MEMO] The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. V20, V30, V25, V35, V25+, V55PI are trademarks of NEC Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5