NEC UPD7225G01

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD7225
PROGRAMMABLE LCD CONTROLLER/DRIVER
The µPD7225 is a software-programmable LCD (Liquid Crystal Display) controller/driver. The µPD7225 can be
serially interfaced with the CPU in a microcomputer and can directly drive 2, 3, or 4-time division LCD. The µPD7225
contains a segment decoder which can generate specific segment patterns. In addition, the µPD7225 can be used to
control on/off (blinking) operation of a display.
FEATURES
• Can directly drive LCD
• Programmable time-division multiplexing
•
Static drive
•
Divide-by-2, 3, or -4 time division multiplexing
• Number of digits displayed
•
7-segment
Divide-by-4
time division ............... 16 digits
Divide-by-3
time division ............... 10 2/3 digits
Divide-by-2
time division ............... 8 digits
Static................................................. 4 digits
•
14-segment
Divide-by-4
time division ............... 8 digits
• Bias method
Static, 1/2, 1/3
• Segment decoder output
•
7-segment : Numeric characters 0 to 9, six symbols
•
14-segment : 36 alphanumeric characters, 13 symbols
• Blinking operation
• Multi-chip configuration possible
• 8-bit serials interface
75X series and 78K series compatible
• CMOS
• Single power supply
ORDERING INFORMATION
Part Number
Package
µPD7225G00
52-pin plastic QFP (14 × 14 mm)
µPD7225G01
52-pin plastic QFP (straight) (
µPD7225GB-3B7
56-pin plastic QFP (10 × 10 mm)
µPD7225GC-AB6
52-pin plastic QFP (14 × 14 mm)
14 mm)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14308EJ6V0DS00 (6th edition)
(O.D. No. IC-1555)
Date Published June 1999 N CP (K)
Printed in Japan
The mark
shows major revised points.
©
1986, 1999
µPD7225
PIN CONFIGURATION: (Top View)
µPD7225G00
µPD7225G01
52-pin plastic QFP (14 × 14 mm)
µPD7225GC-AB6
52-pin plastic QFP (14 × 14 mm)
S27
S26
S25
S24
48
47
46
45
44 43
3
37
S17
VLC2
4
36
S16
VLC3
5
35
S15
VSS
6
34
S14
VDD
7
33
VDD
/SCK
8
32
S13
SI
9
31
S12
/CS
10
30
S11
/BUSY
11
29
S10
C, /D
12
28
S9
S8
18
19
20
21
22 23
24 25
27
26
SI
: Serial Input
CL1
: External Resistor 1 (External Clock)
/SCK
: Serial Clock
CL2
: External Resistor 2
: Reset
C, /D
: Command/Data
RESET
/CS
: Chip Select
VLC1-VLC3 : Power Supply For LCD Drive
/BUSY
: Busy
VDD
: Power Supply
SYNC
: Sync
VSS
: Ground
S0-S31
: Segment
IC
: Internally Connected
COM0-COM3 : Common
NC
Remark
2
S6
17
S4
15 16
COM1
NC
13
14
S7
VLC1
S5
S18
S3
38
S2
2
S1
/SYNC
S0
S19
COM3
40
39
COM2
1
COM0
CL2
/RESET
42 41
S20
S28
49
S21
S29
51 50
S22
S30
52
S23
S31
14 mm)
CL1
52-pin plastic QFP (straight) (
: Non-connection
/××× indicates active low signal.
Data Sheet S14308EJ6V0DS00
µPD7225
Note
IC
S19
S18
S17
S16
S15
S14
VDD
S13
S12
S11
S10
S9
S8
µPD7225GB-3B7 56-pin plastic QFP (10 × 10 mm)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
39
S5
S24
5
38
S4
S25
6
37
S3
S26
7
36
S2
S27
8
35
S1
S28
9
34
S0
S29
10
33
COM3
S30
11
32
COM2
S31
12
31
COM1
CL1
13
30
COM0
IC
14
16
17
18
19
20
21
22
23
24
25
26
27
29
28
NC
IC
15
/RESET
4
C, /D
S23
/BUSY
S6
/CS
40
SI
3
/SCK
S22
VDD
S7
VSS
41
VLC3
2
VLC2
S21
VLC1
IC
/SYNC
1
CL2
S20
IC Pin must be connected to VDD or left unconnected.
Data Sheet S14308EJ6V0DS00
3
µPD7225
BLOCK DIAGRAM
S31
S30
S29
S1
VLC1
VLC2
S0
COM
COM
COM
COM
3
2
1
0
LCD DRIVER
LCD
TIMING
VLC3
CONTROL
DISPLAY DATA LATCH
/SYNC
CL1
OSC
CL2
SEGMENT
DATA
DATA
DECODER
MEMORY
POINTER
BLINKING
DATA
MEMORY
VDD
VSS
/RESET
/CS
C, /D
/BUSY
COMMAND/DATA REGISTER
WRITE
COMMAND
CONTROL
DECODER
SERIAL INTERFACE
SI
4
/SCK
Data Sheet S14308EJ6V0DS00
µPD7225
1.
PIN FUNCTIONS
1.1 SI (Serial Input)……
……Input
……
This pin is used for inputting serial data (commands/data).
Data to be displayed as well as 19 deffernet
commands for controlling the operation of the µPD7225 can be input to this pin.
1.2 /SCK (Serial Clock)……
……Input
……
This pin is used for inputting the shift clock for serial data (SI input). The content of the SI input is read into the
serial register at the rising edge of this clock one bit at a time. /SCK input is effective when /CS = 0 and /BUSY = 1.
If /BUSY = 0, this input is ignored. If /CS = 1, this signal is ignored regardless of the /BUSY status.
1.3 C, /D (Command/Data)……
……Input
……
This input indicates whether the signal input from the SI pin is a command or data. A low level indicates data; a
high level indicates a command.
1.4 /BUSY……
output
……Tri-state
……
This is an active-low output pin that is used to control serial data input disable/enable. A low level disables serial
data input; a high level enables serial data input. This pin becomes high impedance when /CS = 1.
1.5 /CS (Chip Select)……
……Input
……
When /CS is changed from high level to low level, the SCK counter in the µPD7225 is cleared and serial data
input is enabled. At the same time, the data pointer is initialized to address 0. When /CS is set to high level after
serial data is input, the contents of the data memory are transferred to the display latch and displayed on the LCD.
1.6 /SYNC (SYNChronous)……
……Input/Output
……
The /SYNC pin is used to make a wired-OR connection when the common pins are shared or when blinking
operation is synchronized in a multi-chip configuration.
When the µPD7225 is reset (/RESET = 0), the /SYNC pin outputs the clock frequency (fCL) divided by four (refer to
Figure 1-1), and synchronizes the system clock (fCL/4) of the µPD7225. When the reset is released (/RESET =1), the
display timing of each µPD7225 is synchronized with the common drive signal timing shown in Figure 1-2.
Figure 1-1. /SYNC Pin Status During Reset (/RESET = 0)
fCL
/SYNC
Data Sheet S14308EJ6V0DS00
5
µPD7225
Figure 1-2. /SYNC Pin Status after Reset (/RESET = 1)
1 frame
Static
COM0
/SYNC
Divie-by-2
time division
1 frame
COM0
/SYNC
1 frame
Divie-by-3
time division
COM0
/SYNC
1 frame
Divie-by-4
time division
COM0
/SYNC
1.7 /RESET……
……Input
……
This is an active low reset input pin.
1.8 S0-S31 (Segment)……
……Output
……
These pins output segment drive signals.
1.9 COM0-COM3 (COMmon)……
……Output
……
These pins output common drive signals.
1.10 CL1, CL2 (Clock)
A resistor is connected across these pins for internal clock generation. When inputting an external clock, use the
CL1 pin for input.
1.11 VLC1, VLC2, VLC3
LCD driver power supply pin.
6
Data Sheet S14308EJ6V0DS00
µPD7225
1.12 VDD
Positive power supply pin. Either pin 7 or pin 33 can be used.
1.13 VSS
GND pin.
Data Sheet S14308EJ6V0DS00
7
µPD7225
2.
INTERNAL SYSTEM CONFIGURATION
2.1 Serial Interface
The serial interface consists of an 8-bit serial register and a 3-bit SCK counter.
The serial register clocks in the serial data from the SI pin at the rising edge of /SCK. At the same time, the SCK
counter increments (+1) the serial clock. As a result, if an overflow occurs (when eight pulses are counted), input
from the SI pin is disabled (/BUSY = 0), and the contents of the serial register is output to the command/data register.
The /SCK should be set to high before serial data is input and after the data has been input (after eight clocks are
input to /SCK).
Serial data must be input to the SI pin beginning with MSB first.
LSB
MSB
SI pin
D7
D6
D5
D4
D3
D2
D1
D0
µ PD7225
2.2 Command/Data Register
The command/data register latches the contents of the serial register in order to process the serial data clocked
into the serial register.
After the serial data is latched, if the clocked in data is specified as command, the
command/data register transfers its contents to the command decoder. If specified as data the command/data
register transfers its contents to data memory or the segment decoder.
2.3 Command Decoder
When the contents of the command/data register are specified as a command (C, /D was high when data was
input), the command decoder, clocks in the contents of the command/data register and controls the µPD7225.
2.4 Segment Decoders
The µPD7225 has a 7-segment decoder for use with divide-by-3 and divide-by-4 time division, and a 14-segment
decoder for use divide-by-4 time division.
The 7-segment decoder can generate signals for numeric characters 0 to 9 and six different symbols. The 14segment decoder can generate signals for 36 alphanumeric characters and 13 different symbols. When the WITH
SEGMENT DECODER command is executed, if the contents of the command/data register are specified as data, the
contents will be input to the segment decoder, and converted to display codes, and then automatically written to the
data memory.
Whether to select the 7-segment decoder or 14-segment decoder is determined by the most
significant bit (bit 7) of the data input to the segment decoder. It the most significant bit is 0, the 7-segment decoder
will be selected. If it is 1, the 14-segment decoder will be selected. If the 7-segment decoder is selected (however,
divide-by-3 and divide-by-4 time division), the lower 4 bits (bit 3 to bit 0) of the input data (C, /D = 0) will be decoded
and written to the data memory.
If the 14- segment decoder is selected (however, divide-by-4 time division), the lower 7 bits of the input data (C, /D
= 0) will be decoded and written to the data memory.
8
Data Sheet S14308EJ6V0DS00
µPD7225
7
3
0
7
0
6
0
1
Decode data
Decode data
Specifies 7-segment
decoder
Specifies 14-segment
decoder
When displaying the output of the segment decoder (display data) on the LCD, use an LCD configured as shown
in Figure 2-1 or Figure 2-2.
If another type of LCD is used, the displayed pattern will be different.
,,
,
Figure 2-1. 7-Segment Type LCD
When configuring the LCD for divide-by-3 time division mode, connect as follows:
SEGn + 1
SEGn + 2
COM0
,,,
,,
,,
,,,
,,
,,
,,,,
SEGn
COM1
COM2
a
b
f
g
e
c
d
DP
SEGn
SEGn +1
SEGn + 2
COM0
COM1
COM2
Data Sheet S14308EJ6V0DS00
: b, c, DP
: a, d, g
: e, f
: a, b, f
: c, e, g
: d, DP
9
µPD7225
When configuring the LCD for divide-by-4 time division mode, connect as follows:
,,,,
,
SEGn
COM0
COM2
,,
,,
,,
,,
SEGn + 1
a
b
f
g
e
c
d
10
DP
SEGn
: a, b, c, DP
SEGn + 1 : d, e, f, g
COM0
: a, f
COM1
: b, g
COM2
: c, e
COM3
: d, DP
Data Sheet S14308EJ6V0DS00
COM1
COM3
µPD7225
Figure 2-2. 14-Segment LCD
The 14-segment type LCD can be used only in the divide-by-4 time division mode. For the 14-segment LCD type,
,,,
,
,
,
,,,
,,,
,,,
,,
,
,, ,,,
,
,,
,,
,,,, ,,
,,,,,
,
,,
connect segments and commons as follows:
SEGn + 3
SEGn + 2
SEGn + 1 SEGn
g
h
j
e
i
b
COM1
COM2
COM3
k
l
m
n
COM1
COM2
COM3
SEGn
: h, i, k, n
SEGn + 1 : d, e, f
SEGn + 2 : a, b, c, DP
SEGn + 3 : g, j, l, m
COM0
: a, g, h
a
f
COM0
: b, i, j, f
: c, e, k, l
: d, m, n, DP
c
DP
d
The following shows the input data and display pattern, and the configuration of the display data which is
automatically written into the data memory. For the 7-segment type, the lower 4 bits (D3 to D0) are decoded. For the
14-segment type, the input data and display pattern correspond to 8-bit ASCII code. The first address to which the
display data is written is indicated as address N.
Data Sheet S14308EJ6V0DS00
11
µPD7225
Figure 2-3. 7-Segment LCD
Data memory
Data
(HEX)
12
Display
pattern
Divide-by-3
time division
N +2 N +1 N
Data memory
Divide-by-4
time division
N +1 N
Data
(HEX)
Display
pattern
Divide-by-3
time division
N +2 N +1 N
Divide-by-4
time division
N +1 N
00
3
5
3
D
7
08
3
7
3
F
7
01
0
0
3
0
6
09
1
7
3
B
7
02
2
7
1
E
3
0A
0
2
0
2
0
03
0
7
3
A
7
0B
3
7
0
F
1
04
1
2
3
3
6
0C
3
5
0
D
1
05
1
7
2
B
5
0D
0
6
0
A
0
06
3
7
2
F
5
0E
2
6
2
E
4
07
0
1
3
0
7
0F
0
0
0
0
0
Data Sheet S14308EJ6V0DS00
µPD7225
Figure 2-4. 14-Segment LCD
Upper bit
Data
(HEX)
B
C
D
Data memory
Display
pattern N+3 N+2 N+1 N
Data memory
Display
pattern N+3 N+2 N+1 N
Data memory
Display
pattern N+3 N+2 N+1 N
Data memory
Display
pattern N+3 N+2 N+1 N
4
7
E
2
A
7
C
0
2
3
6
4
1
0
6
0
0
2
7
6
4
0
7
E
8
2
2
3
C
4
8
7
8
5
2
3
6
C
3
2
7
8
4
0
1
E
0
1
5
8
4
4
2
6
2
4
8
7
8
1
8
1
0
1
5
2
5
A
4
2
1
E
4
0
6
E
0
6
2
5
E
4
2
1
6
4
4
0
6
2
0
Lower bits
A
0
0
0
0
7
0
0
0
2
0
7
0
0
0
5
E
4
4
6
6
8
8
0
0
0
A
2
7
E
4
2
6
6
4
5
0
0
A
9
5
0
0
0
2
7
A
4
8
1
8
1
9
0
0
2
A
F
0
0
F
0
6
C
0
4
1
8
2
B
A
0
0
5
2
0
6
A
1
0
0
8
C
D
2
0
0
4
E
F
4
0
0
4
0
8
2
0
0
E
0
2
0
8
4
1
6
6
2
1
0
8
8
1
6
6
8
0
7
E
0
2
Data Sheet S14308EJ6V0DS00
13
µPD7225
2.5 Data Memory/Data Pointer
The data memory is a memory which stores display data (32 × 4 bits). Data input by serial transfer, command
immediate data, etc., is written to the data memory.
Specified by data pointer
Address
0
1
2
3
4
5
6
7
8
9 10
29 30 31
0
1
Bit
2
3
In the data memory, either data from the serial register (when the segment decoder is not used) or data from the
segment decoder (when the segment decoder is used) is written as display data.
When the segment decoder is not used, all bits or the lower 4 bits of the serial data (C, /D = 0) input to the serial
register are assigned and written to the specific bits in location 2 to location 4 in the data memory according to the
specified time division. When the segment decoder is used, the contents of the serial register (C, /D = 0) are
decoded by the segment decoder, and the corresponding display data are allocated to the location specified in data
memory by the time division specification (devide-by-3, -4 time division) and the MSB (Most Significant Bit) of the
serial data. (1) to (4) below describe these operations.
The contents of the data memory can be modified in 4-bit units or in bit units using a command.
(1) Static
The lower 4 bits of the contents of the serial register are written to bit 0 in each address (the upper 4 bits are
ignored).
bit3
D3
n+3
D2
n+2
bit0
D1
D0
n+1
Address n
Only the content of bit 0 in each address are effective as display data.
After the data is written, the data pointer points to address n + 4.
(2) Divide-by-2 time division
The contents of the 4 even bits of the serial register are written to bit 0 in the four addresses, and the contents
of 4 odd bits of the serial register are written to bit 1.
bit3
D7 D6
n+3
D5 D4
n+2
D3 D2
n+1
The contents of bits 0 and 1 of each address are effective as display data.
After the data is written, the data pointer points to address n + 4.
14
Data Sheet S14308EJ6V0DS00
bit0
D1 D0
Address n
µPD7225
(3) Divide-by-3 time division
The contents of the 8 bits of the serial register of the segment decoder output (8 bits) are written to bits 0, 1, and
2 of each address. In this case, 0 will be automatically written to bit 2 of address n + 2. For segment decoder
output, 0 will also be automatically written to bit 2 (D2) of address n.
bit3
0
D7 D6
D5 D4 D3
n+2
bit0
D2
0
n+1
D1 D0
Address n
The contents of bits 0, 1, and 2 of each address are effective as display data.
After the data is written, the data pointer points to address n + 3.
The segment decoder output written to the data memory corresponds to segments (a to g, DP) shown in Figure
2-1 as follows:
bit3
e
f
d
n+2
g
a
bit0
DP
n+1
c
b
Address n
(4) Divide-by-4 time division
The contents of the 8 bits of the serial register or the segment decoder output (8 bits) are written to bits 0, 1, 2,
and 3 of each address. For segment decoder output, 0 is automatically written to bit 3 (D3) of address n.
bit3
D7 D6 D5 D4
D3
0
n+1
bit0
D2 D1 D0
Address n
The contents of all bits of each address are effective as display data.
After the data is written, the data pointer points to address n + 2.
When 7 segments are used, the segment decoder output written to the data memory corresponds to segments
(a to g, DP) shown in Figure 2-1 as follows:
bit3
d
e
g
f
DP
n+1
bit0
c
b
a
Address n
When 14 segments are used, the segment decoder output is written to bits 0, 1, 2, and 3 of each address. In
this case, 0s are automatically written to bit 3 of address n + 2, and bit 0 of address n+ 1.
bit3
D15 D14 D13 D12
D11
D10 D9 D8
D7 D6 D5
D4
0
bit0
D3 D2 D1 D0
0
n+3
n+2
n+1
Data Sheet S14308EJ6V0DS00
Address n
15
µPD7225
All bits of each address are effective. After the data is written, the data pointer points to address n + 4.
The segment decoder output written to the data memory corresponds to segments (a to n, DP) shown in Figure
2-2 as follows:
m
l
j
g
DP
c
n+3
b
a
d
e
n+2
f
n+1
0
n
k
i
h
Address n
All contents of the 32 × 4-bit data memory are transferred to the 32 × 4-bit display data latch when the /CS is set
to high. In this case, if the DISPLAY ON command has been set, the contents of the display data latch are
converted to the segment drive signal in 32-bit units in synchronization with COM0-COM3 signals, and output
from the segment pins.
The figure below shows the relationship of the data memory, segment pins, and common signal selection
timing.
Figure 2-5. Data Memory, Segment Pins, and Common Signal Selection Timing
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
S28 S29 S30 S31
COM 0
0
COM 1
1
COM 2
2
COM 3
3
0
1
2
3
4
5
6
7
8
9 10
Bit
28 29 30 31
Address
The data pointer (5 bits) specifies the address (0-31) of the data memory to which the display data will be
written (at the same time, the data pointer specifies the blinking data memory address (0-31)). The LOAD
DATA POINTER command is used to set the address to the data pointer (the data pointer can be initialized by
setting the /CS to low). When the data pointer is counted up to 31, it then becomes 0 at the next count, and
thus it repeats the operation shown below.
0
31
It should be noted that, if display data is written sequentially from address 0 in the divide-by-3 time division
mode, addresses 30 and 31 will not be written. However, if the data is written in the divide-by-3 time division
mode again, data will be written from addresses 30, 31, followed by 0 so that the display data previously written
to address 0 will be modified.
16
Data Sheet S14308EJ6V0DS00
µPD7225
2.6 Blinking Data Memory
The blinking data memory stores blinking data used to control display on/off operation (blinking).
Blinking
operation can be performed in segment units. Each bit in blinking data memory corresponds to a bit in the data
memory; if a bit in the blinking data memory is set to 1, the corresponding segment will blink.
The blinking data memory is addressed by the data pointer at the same time the data memory is addressed. Data
is written by using the WRITE BLINKING DATA MEMORY command, and bit manipulation can be performed by
using the AND BLINKING DATA MEMORY, or OR BLINKING DATA MEMORY command.
The BLINKING ON
command is used to initiate blinking operation or select the blinking interval (refer to 3.2 Blinking Frequency
Setting)
2.7 Display Data Latch
The display data latch stores the data of the 32 × 4-bit segment driver.
Each bit of the display data latch
corresponds to a bit in the data memory. All contents of the data memory are transferred to the display data latch at
the rising edge of /CS, and the contents displayed on the LCD are modified. If blinking is set, the contents of data
memory are modified by the contents of blinking data memory and the resulting values are transferred to the display
data latch.
The display data written to the display data latch is successively selected by the control function performed by the
LCD timing control, and converted to segment drive signal before output.
2.8 LCD Driver
The LCD driver consists of the segment driver and the common driver, and generates the segment drive signal
and common drive signal.
The segment driver outputs a segment signal so that the relationship with the common drive signal is select level if
the drive data stored in the display data latch is 1. If the drive data stored in the display data latch is 0, the output of
the segment driver will be non-select level.
The common drive signal sequentially drives the LCD common poles according to the time divison specificaion.
2.9 LCD Timing Control
The LCD timing control generates the LCD drive timing according to the number of time divisions, the frequency
division ratio, and bias method, and supplies it to the LCD driver. In addition, the LCD timing control outputs a /SYNC
signal from the /SYNC pin in order to synchronize the display timing of each µPD7225 when configured in a multichip configuration.
In a multi-chip configuration, the common signal can be used in common or blinking operation can be
synchronized by making a wired-OR connection with the /SYNC pin of each µPD7225.
Data Sheet S14308EJ6V0DS00
17
µPD7225
3.
FRAME FREQUENCY AND BLINKING FREQUENCY SETTING
3.1 Frame Frequency Setting
The frame frequency is set according to M1, M0 (number of time-divisions setting), and F1, F0 (frequency division
ratio) as indicated in the figure below.
Figure 3-1. Frame Frequency Setting
Divide- by-2 time
division
Static
M1, M0
F1,F0
0
1
1
1
Divide- by-3 time
division
1
0
0
0
0
0
fCL
7
2
fCL
7
2 ×2
fCL
7
2 ×3
fCL
7
2 ×4
0
1
fCL
8
2
fCL
8
2 ×2
fCL
8
2 ×3
fCL
8
2 ×4
1
0
fCL
9
2
fCL
9
2 ×2
fCL
9
2 ×3
fCL
9
2 ×4
1
1
fCL
11
2
fCL
11
2 ×2
fCL
11
2 ×3
fCL
11
2 ×4
Remark fCL = Clock oscillation frequency
3.2 Blinking Frequency Setting
The blinking frequency can be set in two settings by K0 in the BLINKING ON command.
Figure 3-2. Blinking Frequency Setting
K0
Blinking frequency
0
fCL
17
2
1
fCL
16
2
Remark fCL = Clock oscillation frequency
18
Divide- by-4 time
division
Data Sheet S14308EJ6V0DS00
µPD7225
4.
LCD DRIVE POWER SUPPLY PIN VOLTAGE SETTING
The bias method for setting the LCD drive power supply pin allows a different voltage to be supplied to each pin.
Figure 4-1. Voltage Setting
VLC1
VLC2
VLC3
VDD
VDD − VLCD
VDD − VLCD
Static
1/2 bias
VDD −
1
VLCD
2
VDD −
1
VLCD
2
VDD − VLCD
1/3 bias
VDD −
1
VLCD
3
VDD −
1
VLCD
3
VDD − VLCD
Remark
VLCD : LCD voltage
The following shows a circuit example which supplies voltages between VDD and VSS as the LCD drive reference
voltage.
(1) Static
VLCD
VDD
R1 =
VDD
µ PD7225
VLC1
R1
VLC2
VDD − VLCD
× R2
•
VLCD: LCD drive voltage
•
R2 is used for contrast adjustment.
VLC3
VSS
R2
GND
(2) Divide-by-2, -3 time division (1/2 bias)
VDD
VDD
µ PD7225
VLC1
VLC2
VLCD
R1 =
R1
2(VDD − VLCD)
× R2
R1
VLC3
VSS
R2
GND
Data Sheet S14308EJ6V0DS00
19
µPD7225
(3) Divide-by-3, -4 time division (1/3 bias)
VDD
VDD
µ PD7225
VLC1
VLC2
VLCD
R1 =
R1
3(VDD − VLCD)
R1
R1
VLC3
VSS
R2
GND
20
Data Sheet S14308EJ6V0DS00
× R2
µPD7225
5.
CLOCK CIRCUIT
The clock oscillator can be configured by connecting a resistor (R) across the CL1 and CL2 clock pins. When
using the external clock, CL1 can be used to input the external clock (CL2: Open).
Figure 5-1. External Circuit for Clock Oscillation Pins
µ PD7225
µ PD7225
CL1
OSC
fCL
To LCD timing
control
Remark
CL1
R
fCL
To LCD timing
control
CL2
External clock
OSC
CL2
Open
fCL = Clock oscillation frequency (when using the external clock, this frequency is same as that of the
external clock frequency.)
When configuring a multi-chip system using the /SYNC pin, a clock with the same frequency and same phase
must be supplied to the CL1 pin of each µPD7225.
Data Sheet S14308EJ6V0DS00
21
µPD7225
6.
RESET FUNCTION
When a low level of 12 clock cycles or more is input to the /RESET pin, the µPD7225 will be reset to the following
conditions:
• This condition is the same as when M2 − M0 = 0, F1, F0 = 0 are executed by the MODE SET command.
• Display data transfer from the data memory to the display data latch −−− This condition is the same as when
the UNSYNCHRONIZED TRANSFER command is executed.
• Command/data register output −−− This condition is the same as when the WITHOUT SEGMENT DECODER
command is executed.
• LCD display −−− This condition is the same as when the DISPLAY OFF or the BRINKING OFF command is
executed.
Function when the µPD7225 is reset
• S0-S31 and COM0-COM3 pins output VDD
• Serial data input −−− Disabled (/BUSY = 0) (However, /CS = 0)
When used in a multi-chip system, the reset state must be released (rising edge of /RESET) within 5 µs.
Figure 6-1. Reset Signal in Multi-Chip System
0.7VDD
/RESET
0.3VDD
12 clock cycles
22
5 µ s max.
Data Sheet S14308EJ6V0DS00
µPD7225
7.
SERIAL DATA INPUT
Serial data is input to the SI pin with MSB first in synchronization with the serial clock in 8-bits units. When /CS is
set to low, the µPD7225 sets the /BUSY to low (this initializes the SCK counter and the data pointer to 0) in order to
perform internal processing. Therefore, after the µPD7225 completes internal processing, the first bit (MSB) should
be input in synchronization with the /SCK after the /BUSY signal is set to high. The serial data is transferred to the
serial register in bit units at the rising edge of /SCK. Inputting eight serial clocks completes the transfer of all 8 bits of
data to the serial register. At the rising edge of the eighth serial clock, the /BUSY is set to low, and the status of the
C, /D pin is clocked in to specify whether the data is a command or data. Afterwards, the contents of the serial
register are clocked into the command/data register.
When successively inputting 2 or more bytes of serial data, /CS must be set to low until all bytes of data are input.
The /BUSY is set to low each time a byte of data is input. The /BUSY becomes high when the serial data is clocked
in from the serial register to the command/data register, so that the next serial data can be input.
When input of all serial data is complete, the data memory contents can be displayed by setting /CS to high. /CS
must not be set to high while display data is being transferred (before eight clocks has elapsed.) If it becomes
necessary to interrupt serial data transfer when transferring two or more bytes of data due to an interrupt for the CPU
interrupt, execute the PAUSE TRANSFER command after checking that the byte has been transferred, then set /CS
to high. In this case, even if /CS is set to high, the contents of the data memory will not be transferred to the display
data latch.
To resume serial data transfer, set /CS to low in the same way as when initiating a normal transfer. However, in
this case, the contents of the data pointer are not cleared so that data write operation starts from the next data
memory address when serial data transfer is resumed (C, /D = 0).
Note
In a multi-chip system in which the /BUSY pins of chips are made a wired-OR connection, avoid setting the
/CS pins of two or more chips simultaneously.
Figure 7-1. Inputting Byte
Serial data
(SI pin)
D7
D6
D5
D2
D1
D0
/SCK
/CS
/BUSY
High
impedance
High
impedance
C, /D
Data Sheet S14308EJ6V0DS00
23
µPD7225
Figure 7-2. Inputting 5 Bytes Successively
Serial data
Byte 1
Byte 2
Byte 3
/CS
/BUSY
24
Data Sheet S14308EJ6V0DS00
Byte 4
Byte 5
µPD7225
8.
COMMAND
8.1 MODE SET
0
1
0
M2 M1 M0 F1 F0
This command sets the number of time divisions for the LCD display static drive or the time-division drive, bias
method, and frame frequency.
(1) M1 and M0 specify the number of time divisions for static drive or time-division drive.
M1 M0
0
0 ------------------- Divide-by-4 time division drive
1
0 ------------------- Divide-by-3 time division drive
1
1 ------------------- Divide-by-2 time division drive
0
1 ------------------- Static drive
(2) M2 specifies the bias method.
M2
0 -------------------------- 1/3 bias method
1 -------------------------- 1/2 bias method
0/1 ------------------------- Static
(3) F1 and F0 specify the frequency division ratio which determines the frame frequency (refer to Figure 3-1).
F1
F0
Frequency division ratio
0
0 ------------------- 1/2
7
0
1 ------------------- 1/2
8
1
0 ------------------- 1/2
9
1
1 ------------------- 1/2
11
8.2 SYNCHRONIZED TRANSFER
0
0
1
1
0
0
0
1
This command controls display data modification.
Normally, modification of display data is performed at the rising edge of the /CS signal (transferring display data
from the data memory to the display data latch). However, after this command is executed, display data is modified
at the first alternate current drive cycle (Frame frequency x Number of time divisions) after the /CS signal is set to
high.
Data Sheet S14308EJ6V0DS00
25
µPD7225
8.3 UNSYNCHRONIZED TRANSFER
0
0
1
1
0
0
0
0
This command controls display data modification.
After this command is executed, display data is modified at the rising edge of the /CS pin.
8.4 PAUSE TRANSFER
0
0
1
1
1
0
0
0
This command disables display data modification.
After this command is executed, display data can not be modified at the first rising edge of the /CS pin; instead,
modification is put off until the second rising edge of the /CS pin. In addition, the data pointer is not cleared at the
first rising edge of the /CS pin (refer to 2.5 Data Memory/Data Pointer).
This command is used when it becomes necessary to set the /CS pin to high due to an interrupt for the CPU in the
middle of serial data input operation.
8.5 BLINKING ON
0
0
0
1
1
0
1
K0
This command sets the blinking operation status. The blinking frequency is set by the least significant bit of the
command (bit K0).
K0
Blinking frequency (Hz)
0
fCL/2
1
fCL/2
17
16
fCL: Clock oscillation frequency
Remark
8.6 BLINKING OFF
0
0
0
1
1
0
0
0
0
1
This command stops blinking operation.
8.7 DISPLAY ON
0
0
0
1
0
0
After this command is executed, LCD display operation starts according to the display data contained in the
display data latch.
26
Data Sheet S14308EJ6V0DS00
µPD7225
8.8 DISPLAY OFF
0
0
0
1
0
0
0
0
When this command is executed, the relationship of all common drive signals and segment drive signals enters
the non-select state. As a result, the display is turned off. Transferring display data from the data memory to the
display data latch is not affected by this command execution.
8.9 WITH SEGMENT DECODER
0
0
0
1
0
1
0
1
After this command is executed, input data is sent to the segment decoder, and the decoded code is written to the
data memory.
8.10 WITHOUT SEGMENT DECODER
0
0
0
1
0
1
0
0
After this command is executed, input data is written to the data memory without going through the segment
decoder.
8.11 LOAD DATA POINTER
1
1
1
D4 D3 D2 D1 D0
This command sets immediate data D4-D0 to the data pointer.
8.12 WRITE DATA MEMORY
1
1
0
1
D3 D2 D1 D0
This command stores immediate data D3-D0 to the data memory addressed by the data pointer, and increments
(+1) the contents of the data pointer.
8.13 OR DATA MEMORY
1
0
1
1
D3 D2 D1 D0
This command ORs the contents of the data memory addressed by the data pointer and immediate data D3-D0,
and stores the result to the data memory, then increments (+1) the contents of the data pointer.
Data Sheet S14308EJ6V0DS00
27
µPD7225
8.14 AND DATA MEMORY
1
0
0
1
D3 D2 D1 D0
This command ANDs the contents of the data memory addressed by the data pointer and immediate data D3-D0,
and stores the result to the data memory, then increments (+1) the contents of the data pointer.
8.15 CLEAR DATA MEMORY
0
0
1
0
0
0
0
0
This command clears the contents of the data memory and the data pointer.
8.16 WRITE BLINKING DATA MEMORY
1
1
0
0
D3 D2 D1 D0
This command stores immediate data D3-D0 to the blinking data memory addressed by the data pointer, and
increments (+1) the contents of the data pointer.
8.17 OR BLINKING DATA MEMORY
1
0
1
0
D3 D2 D1 D0
This command ORs the contents of the blinking data memory addressed by the data pointer and immediate data
D3-D0, and stores the result to the blinking data memory, then increments (+1) the contents of the data pointer.
8.18 AND BLINKING DATA MEMORY
1
0
0
0
D3 D2 D1 D0
This command ANDs the contents of the blinking data memory addressed by the data pointer and immediate data
D3-D0, and stores the result to the blinking data memory, then increments (+1) the contents of the data pointer.
8.19 CLEAR BLINKING DATA MEMORY
0
0
0
0
0
0
0
0
This command clears the contents of the blinking data memory and the data pointer.
28
Data Sheet S14308EJ6V0DS00
µPD7225
9.
DISPLAY OUTPUT
The following describes the serial data organization, display data organization in the data memory, segment drive
signal, and common drive signal when the display is active in the static and divide-by-2, -3, -4 time division modes.
9.1 Static
When displaying just the digit “6” in the static mode:
(1) Serial data organization: 0D, 07
(2) Display data organization in the data memory
Address
Bit
Contents of bit 0
n+7
n+6
n+5
n+4
n +3
n+2
n+1
n
0
1
1
1
1
1
0
1
(3) Power supply (static)
VLC0 = VLC1 = VDD
VLC2 = VLC3 = VDD − VLCD
(4) Relationship between common and segment
SEGn
SEGn + 5
SEGn + 1
SEGn + 6
SEGn + 4
SEGn + 2
SEGn +7
SEGn + 3
COM0
Data Sheet S14308EJ6V0DS00
29
µPD7225
(5) Segment and common drive signals
VLC0
SEGn, SEGn + 2 − SEGn + 6
VLC3
VLC0
SEGn + 1, SEGn + 7
VLC3
VLC0
COM0
VLC3
VLC0
COM0 − SEGn
0
−VLC0
COM0 − SEGn + 1
30
Data Sheet S14308EJ6V0DS00
0
µPD7225
9.2 Divide-by-2 Time Division
When displaying just the digit “6” in the divide-by-2 time division mode:
(1) Serial data organization: F5
(2) Display data organization in the data memory
Address
n +3
n+2
n+1
n
Contents of bit 0
1
1
1
1
Contents of bit 1
1
1
0
0
Bit
(3) Power supply (1/2 bias)
VLC0 = VDD
VLC1 = VLC2 = VDD − 1/2 VLCD
VLC3 = VDD − VLCD
(4) Relationship between common and segment
SEGn + 3
SEGn + 2
,,
,,
,,
,,
,,
SEGn
SEGn + 1
COM0
COM1
Data Sheet S14308EJ6V0DS00
31
µPD7225
(5) Segment and common drive signals
t0
t1
t2
t3
t0 t1
t2 t3
t0
t1
VLC0
SEGn
VLC3
VLC0
SEGn + 1
VLC3
VLC0
SEGn + 2
VLC3
VLC0
SEGn + 3
VLC3
VLC0
VLC1
COM0
VLC3
VLC0
VLC1
COM1
VLC3
VLC0
VLC1
COM0 − SEGn + 3
0
−VLC1
−VLC0
VLC1
0
COM1 − SEGn
−VLC1
32
Data Sheet S14308EJ6V0DS00
µPD7225
9.3 Divide-by-3 Time Division
When displaying the digit “6.” in the divide-by-3 time division mode:
(1) Serial data organization
• Without segment decoder: FE
• With segment decoder
: 06
(However, the floating point is set to “1” by command.)
(2) Display data organization in the data memory
Address
Bit
n+2
n+1
n
Contents of bit 0
1
1
0
Contents of bit 1
1
1
1
Contents of bit 2
0
1
1
(3) Power supply (1/3 bias)
VLC0 = VDD
VLC1 = VDD − 1/3 VLCD
VLC2 = VDD − 2/3 VLCD
VLC3 = VDD − VLCD
(4) Relationship between common and segment
,
,
,
,,
SEGn + 1
SEGn + 2
SEGn
,,
,,
,,,,,
,,,
COM0
COM1
COM2
Data Sheet S14308EJ6V0DS00
33
µPD7225
(5) Segment and common drive signals
t0
t1
t2
t3
t4 t5
t0 t1
t2
t3
VLC0
VLC1
SEGn
VLC2
VLC3
VLC0
VLC1
SEGn + 1
VLC2
VLC3
VLC0
VLC1
SEGn + 2
VLC2
VLC3
VLC0
VLC1
COM0
VLC2
VLC3
VLC0
VLC1
COM1
VLC2
VLC3
VLC0
VLC1
COM2
VLC2
VLC0
VLC0
VLC2
COM1 − SEGn + 2
0
−VLC2
−VLC0
VLC2
COM2 − SEGn + 2
0
−VLC2
34
Data Sheet S14308EJ6V0DS00
µPD7225
9.4 Divide-by-4 Time Division
When displaying the digit “6.” in the divide-by-4 time division mode:
(1) Serial data organization
• Without segment decoder: FD
• With segment decoder
: 06
(However, the floating point is set to “1” by command.)
Address
n+1
n
Contents of bit 0
1
1
Contents of bit 1
1
0
Contents of bit 2
1
1
Contents of bit 3
1
1
Bit
(2) Power supply (1/3 bias)
VLC0 = VDD
VLC1 = VDD − 1/3 VLCD
VLC2 = VDD −2/3 VLCD
VLC3 = VDD − VLCD
(3) Relationship between common and segment
,
,,
,,
,
SEGn
SEGn + 1
COM0
COM2
,,
,,
,,
,,
COM1
COM3
Data Sheet S14308EJ6V0DS00
35
µPD7225
(4) Segment and common drive signals
t7
t0
t1
t2
t3
t4
t5
t6
t7
t0
t1
t2
VLC0
VLC1
SEGn
VLC2
VLC3
VLC0
VLC1
SEGn + 1
VLC2
VLC3
VLC0
VLC1
COM0
VLC2
VLC3
VLC0
VLC1
COM3
VLC2
VLC3
VLC0
VLC1
COM1
VLC2
VLC3
VLC0
VLC1
COM2
VLC2
VLC3
VLC0
VLC2
COM0 − SEGn + 1
0
−VLC2
−VLC0
VLC2
COM1 − SEGn
0
−VLC2
36
Data Sheet S14308EJ6V0DS00
µPD7225
10. ELECTRICAL CHARACTERISTICS
Absolute Maximum Rating (TA = 25 °C)
Item
Rating
Units
VDD
−0.3 to +7.0
V
Input voltage
VI
−0.3 to VDD +0.3
V
Output voltage
VO
−0.3 to VDD +0.3
V
Operating ambient temperature
TA
−10 to +70
°C
Storage temperature
Tstg
−65 to +150
°C
Power supply voltage
Caution
Symbol
Condition
If the absolute maximum rating of even one of the above parameters is exceeded
even momentarily, the quality of the product may be degraded. Absolute maximum
ratings, therefore, specify the values exceeding which the product may be physically
damaged. Be sure to use the product within the range of the absolute maximum
ratings.
Capacitance (TA = 25 °C, VDD = 0 V)
Item
Input capacitance
Symbol
Condition
CIN
Output capacitance
COUT1
Except /BUSY
Output capacitance
COUT2
/BUSY
CIO
/SYNC
Input/output capacitance
f = 1 MHz pins
other than those
used for
measurement
MIN.
TYP.
MAX.
Units
10
pF
20
pF
15
pF
15
pF
30
pF
are 0 V.
Clock capacitance
CC
CL1
Data Sheet S14308EJ6V0DS00
37
µPD7225
DC Characteristics (TA = −10 to +70 °C, VDD = 5 V ± 10%)
Item
Symbol
Condition
MIN.
TYP.
MAX.
Unit
High level input voltage
VIH
0.7 VDD
VDD
V
Low level input voltage
VIL
0
0.3 VDD
V
High level output voltage
VOH
/SYNC, /BUSY, IOH = −10 µA
Low level output voltage
VOL1
/BUSY, IOL = 100 µA
0.5
V
VOL2
/SYNC, IOL = 900 µA
1.0
V
−300
µA
VDD − 0.5
V
Output short-circuit current
IOS
/SYNC, VO = 1 V
High level input leakage current
ILIH
VI = VDD
2
µA
Low level input leakage current
ILIL
VI = 0 V
−2
µA
High level output leakage current
ILOH
VO = VDD
2
µA
Low level output leakage current
ILOL
VO = 0 V
−2
µA
5
7
kΩ
7
14
kΩ
100
250
µA
TYP.
MAX.
Units
Common output impedance
Segment output impedance
Power supply voltage
RCOM
RSEG
IDD
, VDD ≥ VLCD
Note 1
COM0 to COM3
, VDD ≥ VLCD
Note 1
S0 to S31
CL1 external clock, fC = 200 kHz
Note 2
Notes 1. Applies to Static, 1/2 bias, 1/3 bias
2. Abnormal current will flow if the external clock supply is removed.
DC Characteristics (TA = 0 to +70 °C, VDD = 2.7 to 5.5 V)
Item
High level input voltage
Symbol
Condition
MIN.
VIH1
Except /SCK
0.7 VDD
VDD
V
VIH2
/SCK
0.8 VDD
VDD
V
VIL1
Except /SCK
0
0.3 VDD
V
VIL2
/SCK
0
0.2 VDD
V
High level output voltage
VOH
/SYNC, /BUSY, IOH = −7 µA
Low level output voltage
VOL1
/BUSY, IOL = 100 µA
0.5
V
VOL2
/SYNC, IOL = 400 µA
0.5
V
−200
µA
Low level input voltage
VDD − 0.75
V
Output short-circuit current
IOS
/SYNC, VO = 0.5 V
High level input leakage current
ILIH
VI = VDD
2
µA
Low level input leakage current
ILIL
VI = 0 V
−2
µA
High level output leakage current
ILOH
VO = VDD
2
µA
Low level output leakage current
ILOL
VO = 0 V
−2
µA
Common output impedance
Segment output impedance
Power supply voltage
RCOM
RSEG
IDD
, VDD ≥ VLCD
Note 1
COM0 to COM3
, VDD ≥ VLCD
Note 1
S0 to S31
CL external clock, VDD = 3 V ± 10%,
Note 2
fC = 140 kHz
Notes 1. Applies to Static and 1/3 bias
2. Abnormal current will flow if the external clock supply is removed.
38
Data Sheet S14308EJ6V0DS00
6
kΩ
12
kΩ
30
100
µA
µPD7225
AC Characteristics (TA = −10 to +70 °C, VDD = 5 V ± 10%)
Item
Symbol
Condition
MIN.
TYP.
Units
200
kHz
175
kHz
Operating frequency
fC
Oscillation frequency
fOSC
R = 180 kΩ ± 5%
85
High level clock pulse width
tWHC
CL1, external clock
2
16
µs
Low level clock pulse width
tWLC
CL1, external clock
2
16
µs
/SCK frequency
tCYK
900
ns
High level /SCK pulse width
tWHK
400
ns
Low level /SCK pulse width
tWLK
400
ns
/BUSY ↑→ /SCK ↓ hold time
tHBK
0
ns
SI set time (against /SCK ↑)
tSIK
100
ns
SI hold time (against /SCK ↑)
tHKI
200
ns
8th pulse of /SCK ↑→ /BUSY ↓
delay time
tDKB
CL = 50 pF
/CS ↓→ /BUSY ↓ delay time
tDCSB
CL = 50 pF
tWLB
tWHCS ≥ 48/fC
/BUSY low level time
50
MAX.
Note 1
CL = 50 pF
4
130
3
µs
1.5
µs
44 (57)
1/fC
Note 2
C, /D set time (against 8th pulse
of SCK ↑)
tSDK
9
µs
C, /D hold time (against 8th pulse
of SCK ↑)
tHKD
1
µs
/CS hold time (against 8th pulse of
SCK ↑)
tHKCS
1
µs
High level /CS pulse width
tWHCS
Note 3
µs
Low level /CS pulse width
tWLCS
Note 3
µs
/SYNC load capacitance
CLSY
tCYC = 5 µs
50
pF
Notes 1. UNSYNCHRONIZED TRANSFER MODE
For SYNCHRONIZED TRANSFER MODE,
tWHCS ≥ (48/fC + AC driver frequency)
2. BLINKING ON
3. 8/fc
Data Sheet S14308EJ6V0DS00
39
µPD7225
AC Characteristics (TA = 0 to +70 °C, VDD = 2.7 V to 5.5 V)
Item
Symbol
Condition
MIN.
TYP.
Unit
140
kHz
140
kHz
Operating frequency
fC
Oscillation frequency
fOSC
R = 180 kΩ ± 5%, VDD = 3 V ± 10 %
50
High level clock pulse width
tWHC
CL1, external clock
3
16
µs
Low level clock pulse width
tWLC
CL1, external clock
3
16
µs
/SCK frequency
tCYK
4
µs
High level /SCK pulse width
tWHK
1.8
µs
Low level /SCK pulse width
tWLK
1.8
µs
/BUSY ↑→ /SCK hold time
tHBK
0
ns
SI set time (against /SCK ↑)
tSIK
1
µs
SI hold time (against /SCK ↑)
tHKI
1
µs
8th pulse of /SCK ↑→ /BUSY ↓
delay time
tDKB
CL = 50 pF
/CS ↓→ /BUSY ↓ delay time
tDCSB
CL = 50 pF
tWLB
tWHCS ≥ 48/fC
/BUSY low level time
50
MAX.
Note 1
CL = 50 pF
4
100
5
µs
5
µs
44 (57)
1/fC
Note 2
C, /D set time (against 8th pulse
of SCK ↑)
tSDK
18
µs
C, /D hold time (against 8th pulse
of SCK ↑)
tHKD
1
µs
/CS hold time (against 8th pulse of
SCK ↑)
tHKCS
1
µs
High level /CS pulse width
tWHCS
Note 3
µs
Low level /CS pulse width
tWLCS
Note 3
µs
/SYNC load capacitance
CLSY
tCYC = 7.1 µs
50
Notes 1. UNSYNCHRONIZED TRANSFER MOD
For SYNCHRONIZED TRANSFER MODE,
tWHCS ≥ (48/fC + AC driver frequency)
2. BLINKING ON
3. 8/fc
AC Timing Measurement Voltage
0.7VDD
0.3VDD
40
Measurement
points
Data Sheet S14308EJ6V0DS00
0.7VDD
0.3VDD
pF
µPD7225
Timing Wave-Form
tCYC (1/fe)
tWHC
CL1
tWLC
tWHCS
tWLCS
tDCSB
/CS
tHKCS
Note 1
/BUSY
0.5 V
0.5 V
tHBK
tCYK
tDKB tWLR
tWLK
Note 2
/SCK
Note 3
tWHK
tSIK
tHKI
SI
tSDK
tHKD
C, /D
Notes 1. VDD − 0.5 V when VDD = 5 V ± 10 %, VDD − 0.75 V when VDD = 2.7 to 5.5 V
2. 0.8 V when VDD = 2.7 V to 5.5 V
3. 0.2 V when VDD = 2.7 V to 5.5 V
Data Sheet S14308EJ6V0DS00
41
µPD7225
Typical Characteristic Curve (Ta = 25 °C)
External resistor and oscillation frequency
CL2
Power supply voltage and oscillation frequency
CL2
CL1
CL1
VDD = 5 V
Oscillation frequency (kHz)
Oscillation frequency (kHz)
140
R
200
100
R
R = 180 kΩ
120
100
50
VDD = 3 V
200
100
80
500
External resistor R (k ohms)
3
4
5
Power supply voltage VDD (V)
Power supply voltage and operating current
CL2
CL1
Operating current ( µ A)
External clock
fC = 200 kHz
100
fC = 140 kHz
50
20
3
4
5
6
Power supply voltage VDD (V)
42
Data Sheet S14308EJ6V0DS00
6
µPD7225
11. PACKAGE DRAWINGS
µPD7225G00
52 PIN PLASTIC QFP (14x14)
A
B
detail of lead end
27
26
39
40
S
C D
Q
52
1
14
13
F
J
G
H
I
P
M
K
S
N
S
L
M
NOTES
1. Controlling dimension
ITEM
millimeter.
2. Each lead centerline is located within 0.20 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
INCHES
A
21.0±0.4
0.827±0.016
B
14.0±0.2
0.551 +0.009
−0.008
C
14.0±0.2
0.551 +0.009
−0.008
D
21.0±0.4
0.827±0.016
F
1.0
0.039
G
1.0
0.039
H
0.42±0.08
0.017 +0.003
−0.004
I
0.20
0.008
J
1.0 (T.P.)
0.039
K
3.5±0.2
0.138 +0.008
−0.009
L
2.2±0.2
0.087 +0.008
−0.009
M
0.17 +0.08
−0.07
0.007 +0.003
−0.004
N
0.15
0.006
P
2.6 +0.2
−0.1
0.102 +0.009
−0.004
Q
0.1±0.1
0.004±0.004
S
3.0 MAX.
0.119 MAX.
P52G-100-00-3
Data Sheet S14308EJ6V0DS00
43
µPD7225
µPD7225G01
52PIN PLASTIC QFP (STRAIGHT) ( 14)
A
27
26
521
1314
F
C
39
40
G
H
D
B
J
I
M
T
M
P
U
K
NOTE
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
22.0±0.4
INCHES
0.866±0.016
B
14.0±0.2
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
22.0±0.4
0.866±0.016
F
1.0
0.039
G
1.0
0.039
H
0.40±0.10
0.016 +0.004
–0.005
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P.)
K
4.0±0.2
0.157 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
P
2.6 +0.2
–0.1
0.102 +0.009
–0.004
T
1.0
0.039
U
1.45
0.057
P52G-100-01-2
44
Data Sheet S14308EJ6V0DS00
µPD7225
µPD7225GB-3B7
56 PIN PLASTIC QFP (10 10)
A
B
39
40
27
26
detail of lead end
C D
S
R
Q
52
1
14
13
F
J
G
H
I
M
K
P
M
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
13.2±0.4
INCHES
0.520±0.016
B
C
10.0±0.2
10.0±0.2
0.394±0.008
0.394±0.008
D
13.2±0.4
0.520±0.016
F
G
0.75
0.75
0.030
0.030
H
0.30±0.10
0.012 +0.004
–0.005
I
0.13
0.005
J
K
0.65 (T.P.)
1.6±0.2
0.026 (T.P.)
0.063±0.008
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
Q
2.7
0.1±0.1
0.106
0.004±0.004
R
5°±5°
5°±5°
S
3.0 MAX.
0.119 MAX.
S56GB-65-3B7-3
Data Sheet S14308EJ6V0DS00
45
µPD7225
µPD7225GC-AB6
52 PIN PLASTIC QFP (14×14)
A
B
27
26
39
40
detail of lead end
C
D
S
R
Q
52
1
14
13
F
G
J
I
H
M
K
P
M
N
L
NOTE
ITEM
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
MILLIMETERS
INCHES
A
17.6±0.4
0.693±0.016
B
14.0±0.2
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.6±0.4
0.693±0.016
F
1.0
0.039
G
1.0
0.039
H
0.40±0.10
0.016 +0.004
–0.005
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P.)
K
1.8±0.2
0.071 +0.008
–0.009
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.6
0.102
Q
0.1±0.1
0.004±0.004
R
5°±5°
5°±5°
S
3.0 MAX.
0.119 MAX.
P52GC-100-AB6-4
46
Data Sheet S14308EJ6V0DS00
µPD7225
12. RECOMMENDED SOLDERING CONDITIONS
When mounting the µPD7225 by soldering, soldering should be performed under the following recommended
conditions.
Should other than recommended conditions be used, consult with our sales personnel.
Surface Mount Type
µPD7225G00
: 52-pin plastic QFP (14 × 14 mm)
µPD7225G01
: 52-pin plastic QFP (straight) (
14 mm)
µPD7225GC-AB6 : 52-pin plastic QFP (14 × 14 mm)
Soldering Method
Partial Heating
µPD7225GB-3B7
Soldering Condition
Pin temperature: 300 °C MAX., Time: 3 seconds MAX. (Per side of device)
Symbol of
Recommended
Soldering Condition
−
: 56-pin plastic QFP (10 × 10 mm)
Soldering Method
Soldering Condition
Symbol of
Recommended
Soldering Condition
Infrared reflow
Package peak temperature: 235 °C, Time: 30 seconds MAX. (210 °C MIN.),
Number of times: 3 MAX.
IR35-00-3
VPS
Package peak temperature: 215 °C, Time: 40 seconds MAX. (200 °C MIN),
Number of times: 3 MAX.
VP-15-00-3
Wave soldering
Solder bath temperature: 260 °C MAX., Time: 10 seconds MAX., Number of
times: 1, Preheating temperature: 120 °C MAX. (Package surface)
WS-60-00-1
Caution
Do not use two or more soldering methods in combination (except the partial heating method).
Reference Documents
NEC Semiconductor Device Reliability / Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
Semiconductor Device Mounting Technology Manual (C10535E)
Data Sheet S14308EJ6V0DS00
47
µPD7225
[MEMO]
48
Data Sheet S14308EJ6V0DS00
µPD7225
[MEMO]
Data Sheet S14308EJ6V0DS00
49
µPD7225
[MEMO]
50
Data Sheet S14308EJ6V0DS00
µPD7225
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14308EJ6V0DS00
51
µPD7225
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8