DATA SHEET MOS INTEGRATED CIRCUIT µPD75104A, 75108A 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION µPD75108A is a 4-bit single-chip CMOS microcomputer having a data processing capability comparable to that of an 8-bit microcomputer. Operating at high speeds, the microcomputer allows data to be manipulated in units of 1, 4, or 8 bits. In addition, various bit manipulation instructions are provided to reinforce I/O manipulation capability. Equipped with I/Os for interfacing with peripheral circuits operating on a different supply voltage, outputs that can directly drive LEDs, and analog inputs, µPD75108A is suitable for controlling such small equipments as cameras and VCRs. Detailed functions are described in the following user’s manual. Be sure to read it for designing. µPD751XX Series User’s Manual: IEM-922 FEATURES • Internal memory • Program memory (ROM) : 8064 × 8 bits (µ PD75108A) : 4096 × 8 bits (µ PD75104A) • Data memory (RAM) : 512 × 4 bits ( µPD75108A) : 320 × 4 bits ( µPD75104A) • Architecture “75X” rivaling 8-bit microcomputers • 43 systematically organized instructions • A wealth of bit manipulation instructions • 8-bit data transfer, compare, operation, increment, and decrement instructions • 1-byte relative branch instructions • GETI instruction executing 2-/3-byte instruction with one byte • High speed. Minimum instruction execution time: 0.95 µs (at 4.19 MHz, 5V) • Instruction execution time change function: 0.95 µs/1.91 µs/15.3 µ s (at 4.19 MHz) • I/O port pins as many as 58 • Three channels of 8-bit timers • 8-bit serial interface • Multiplexed vector interrupt function Unless there are differences among µPD75104A and 75108A functions, µPD75108A is treated as the representative model throughout this manual. The information in this document is subject to change without notice. Document No. IC-2568A (O. D. No. IC-7080B) Date Published January 1994 P Printed in Japan The mark ★ shows major revised points. NEC Corporation 1989 µPD75104A, 75108A ORDERING INFORMATION Part Number Package Quality Grade µPD75104AGC-xxx-AB8 64-pin plastic QFP ( 14 mm) Standard µPD75108AGC-xxx-AB8 64-pin plastic QFP ( 14 mm) Standard Remarks: xxx is ROM code number. Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 µPD75104A, 75108A FUNCTIONAL OUTLINE Item Specifications Number of Basic Instructions 43 Minimum Instruction Changeable in three steps: 0.95 µs, 1.91 µs, and 15.3 µs at 4.19 MHz Execution Time ROM 8064 × 8 bits (µPD75108A), 4096 × 8 bits (µPD75104A) RAM 512 × 4 bits (µPD75108A), 320 × 4 bits (µPD75104A) Internal Memory General-Purpose Register (4 bits × 8 ) × 4 banks or (8 bis x 4 ) x 4 banks Accumulator Three accumulators selectable according to the bit length of manipulated data: • 1-bit accumulator (CY), 4-bit accumulator (A), and 8-bit accumulator (XA) I/O Port 58 port pins • CMOS input pins (Pull-up resistor can be conneced to 4 out of 10 pins in bit units.): 10 • CMOS I/O pins (can directly drive LEDs. Pull-up resistors can be connected to 24 out of 32 pins in bit units.): 32 • Medium voltage N-ch open-drain I/O pins: 12 (can directly drive LEDs. Pull-up resistors can be connected in bit units.) • Comparator input pins (4-bit accuracy): 4 Timer/Counter • 8-bit timer/event counter × 2 • 8-bit basic interval timer (can be used as watchdog timer) • 8 bits Serial Interface • LSB first/MSB first mode selectable • Two transfer modes (transfer/reception and reception only modes) Vector Interrupt External: 3, Internal: 4 Test Input External: 2 Standby • STOP and HALT modes Instruction Set • • • • Others • Power-ON reset circuit (mask option) • Bit manipulation memory (bit sequential buffer: 16 bits) Package • 64-pin plastic QFP ( Various bit manipulation instructions (set, reset, test, Boolean operation) 8-bit data transfer, compare, operation, increment, and decrement 1-byte relative branch instructions GETI instruction constituting 2 or 3-byte instruction with 1 byte 14 mm) 3 µPD75104A, 75108A CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ............................................................................................... 6 2. BLOCK DIAGRAM ........................................................................................................................... 7 3. PIN FUNCTIONS .............................................................................................................................. 8 3.1 PORT PINS ............................................................................................................................................. 8 3.2 PINS OTHER THAN PORTS ................................................................................................................. 9 3.3 PIN INPUT/OUTPUT CIRCUITS ........................................................................................................... 10 3.4 RECOMMENDED PROCESSING OF UNUSED PINS .......................................................................... 12 3.5 NOTES ON USING THE P00/INT4, AND RESET PINS ...................................................................... 13 4. MEMORY CONFIGURATION .......................................................................................................... 14 5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 19 5.1 PORTS .................................................................................................................................................... 19 5.2 CLOCK GENERATOR CIRCUIT ............................................................................................................ 20 5.3 CLOCK OUTPUT CIRCUIT .................................................................................................................... 21 5.4 BASIC INTERVAL TIMER ..................................................................................................................... 22 5.5 TIMER/EVENT COUNTER ..................................................................................................................... 22 5.6 SERIAL INTERFACE .............................................................................................................................. 24 5.7 PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) .................................................... 26 5.8 BIT SEQUENTIAL BUFFER .... 16 BITS ............................................................................................... 27 5.9 POWER-ON FLAG (MASK OPTION) .................................................................................................... 27 6. INTERRUPT FUNCTIONS ................................................................................................................ 27 7. STANDBY FUNCTIONS .................................................................................................................. 29 8. RESET FUNCTION ........................................................................................................................... 30 9. INSTRUCTION SET ......................................................................................................................... 33 10. APPLICATION EXAMPLES .............................................................................................................. 42 10.1 4 VCR CAMERA ........................................................................................................................................ 42 11. MASK OPTION SELECTION ........................................................................................................... 43 µPD75104A, 75108A 12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 44 13. CHARACTERISTIC DATA (REFERENCE VALUE) .......................................................................... 54 14. PACKAGE DRAWINGS ................................................................................................................... 59 15. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 60 APPENDIX A. FUNCTIONAL DIFFERENCES AMONG THIS SERIES PRODUCTS ........................ 61 APPENDIX B. DEVELOPMENT TOOLS .............................................................................................. 62 APPENDIX C. 63 RELATED DOCUMENTS .............................................................................................. 5 µPD75104A, 75108A PIN CONFIGURATION (TOP VIEW) P53 P40 P52 P50 P51 RESET X2 X1 P62 P63 P61 P60 P72 P73 14 mm) P70 • 64-Pin Plastic QFP ( P71 1. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 P41 2 47 P42 P81 3 46 P43 P80 4 45 P30 P93 5 44 P31 P92 6 43 P32 P91 7 42 P33 P90 8 V SS 9 P13/INT3 10 P12/INT2 11 P11/INT1 12 P10/INT0 13 PTH03 14 35 P130 PTH02 15 34 P131 PTH01 16 33 P132 µ PD75104AGC-xxx-AB8 1 P82 µ PD75108AGC-xxx-AB8 P83 41 VDD 40 NC 39 P140 38 P141 37 P142 36 P143 6 P133 P120 P121 P122 P123 P01/SCK P00/INT4 P03/SI P02/SO P20/PTO0 P21/PTO1 P23 P22/PCL TI1 TI0 PTH00 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P00-P03 : Port 0 SCK : Serial Clock Input/Output P10-P13 : Port 1 SO : Serial Output P20-P23 : Port 2 SI : Serial Input P30-P33 : Port 3 PTO0, PTO1 : Timer Output P40-P43 : Port 4 PCL : Clock Output P50-P53 : Port 5 PTH00-PTH03 : Comparator Input P60-P63 : Port 6 INT0, INT1, INT4 : External Vector Interrupt Input P70-P73 : Port 7 INT2, INT3 P80-P83 : Port 8 TI0, TI1 : Timer Input P90-P93 : Port 9 X1, X2 : Oscillation Pin P120-P123 : Port 12 RESET : Reset Input P130-P133 : Port 13 NC : No Connection P140-P143 : Port 14 VDD : Positive Power Supply VSS : GND : External Test Input 2. PROGRAM COUNTER* INTBT TI0 CY ALU SP (8) TIMER/EVENT COUNTER #0 PTO0/P20 TIMER/EVENT COUNTER #1 PTO1/P21 SERIAL INTERFACE DECODE AND CONTROL INTSIO INT0/P10 INT1/P11 INT2/P12 INT4/P00 PORT 1 4 P10 - P13 PORT 2 4 P20 - P23 PORT 3 4 P30 - P33 PORT 4 4 P40 - P43 PORT 5 4 P50 - P53 PORT 6 4 P60 - P63 PORT 7 4 P70 - P73 PORT 8 4 P80 - P83 PORT 9 4 P90 - P93 PORT 12 4 P120 - P123 PORT 13 4 P130 - P133 PORT 14 4 P140 - P143 f X/2 N 4 PROGRAMMABLE THRESHOLD PORT #0 CLOCK OUTPUT CONTROL PCL/P22 *: 13 bits: µ PD75108A 12 bits: µ PD75104A CLOCK DIVIDER CLOCK GENERATOR X1 X2 STAND BY CONTROL CPU CLOCK Φ V DD V SS RESET 7 µPD75104A, 75108A PTH00-PTH03 RAM DATA MEMORY 512 × 4BITS : µ PD75108A 320 × 4BITS : µ PD75104A INTERRUPT CONTROL INT3/P13 P00 - P03 GENERAL REG. ROM PROGRAM MEMORY 8064 × 8BITS : µ PD75108A 4096 × 4BITS : µ PD75104A INTT1 SI/P03 SO/P02 SCK/P01 4 BANK INTT0 TI1 PORT 0 BLOCK DIAGRAM BIT SEQ. BUFFER (16) BASIC INTERVAL TIMER µPD75104A, 75108A 3. PIN FUNCTIONS 3.1 PORT PINS Pin Name I/O Shared with: P00 Input INT4 P01 I/O SCK Function 8-Bit I/O I/O P03 Input I/O Circuit Type*1 B F 4-bit input port (PORT 0) P02 At Reset Input SO E SI B x P10 INT0 P11 INT1 Input P12 Input*2 B -A Input E Input E Input*2 E-A Input*2 E-A Input*2 E-A 4-bit I/O port (PORT 7) Input*2 E-A 4-bit I/O port (PORT 8) 2 E-A 2 E-A 4-bit input port (PORT 1) INT2 P13 INT3 P20* 3 P21* 3 P22* 3 PTO0 PTO1 I/O 4-bit I/O port (PORT 2) PCL x P23*3 — 4-bit programmable I/O port (PORT 3) P30-P33*3 I/O — Can be specified for input or output bitwise. P40-P43*3 I/O — 4-bit I/O port (PORT 4) o P50-P53*3 I/O — P60-P63*3 I/O — 4-bit I/O port (PORT 5) 4-bit programmable I/O port (PORT 6) Can be specified for input or output bitwise. P70-P73*3 P80-P83* 3 P90-P93* 3 I/O I/O — o Input* o I/O — 4-bit I/O port (PORT 9) Input* 4-bit N-ch open-drain I/O port (PORT 12) Built-in pull-up resistors can be specified in bit P120-P123* 3 I/O — Input*2 M Input*2 M Input*2 M units (by mask option). Open-drain withstanding voltage: 12 V o 4-bit N-ch open-drain I/O port (PORT 13) P130-P133*3 Built-in pull-up resistors can be specified in bit I/O — units (by mask option). Open-drain withstanding voltage: 12 V 4-bit N-ch open-drain I/O port (PORT 14) P140-P143*3 Built-in pull-up resistors can be specified in bit I/O — – units (by mask option). Open-drain withstanding voltage: 12 V *1: Circles indicate Schmitt trigger input pins. 2: With pull-up resistor connected: high level Without pull-up resistor connected: high impedance 3: Can directly drive LEDs. 8 µPD75104A, 75108A 3.2 PINS OTHER THAN PORTS Pin Name I/O Shared with: PTH00-PTH03 Input — TI0 At Reset I/O Circuit Type*1 — N — B Outputs for timer/event counter Input E Function 4-bit variable threshold voltage analog input port External event pulse inputs for timer/event counter. Input — Also serves as edge-detected vector interrupt input. TI1 1-bit input also possible. PTO0 P20 I/O PTO1 P21 SCK I/O P01 Serial clock I/O Input F SO I/O P02 Serial data output Input E SI Input P03 Serial data input Input B INT4 Input P00 Input B Input*2 B -A Input*2 B -A Input E — — Edge-detected vectored interrupt input (both rising and falling edges detected) INT0 P10 Edge-detected vectored interrupt inputs (valid P11 edge selectable) Input INT1 INT2 P12 Input INT3 PCL Edge-detected testable inputs (rising edge detected) P13 I/O P22 Clock output Crystal/ceramic system clock oscillator connections. X1, X2 — — Input external clock to X1, and signal in reverse phase with X1 to X2. RESET Input — System reset input (low level active type) — B NC — — No Connection — — VDD — — Positive power supply — — VSS — — GND — — *1: Circles indicate Schmitt trigger input pins. 2: With pull-up resistor connected: high level Without pull-up resistor connected: high impedance 9 µPD75104A, 75108A 3.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µPD75108A. TYPE D TYPE A VDD VDD data P-ch P–ch OUT IN N–ch Input buffer of CMOS standard output disable N-ch Push – pull output that can be set in a output high– impedance state (both P –ch and N –ch are off) TYPE E TYPE B data IN IN/OUT Type D output disable Type A Schmitt trigger input with hysteresis characteristics TYPE D I/O circuit consisting of Type D push-pull output circuit and Type A input buffer TYPE E-A V DD Pull-up resistor (mask option) V DD Pull-up resistor (mask option) data IN/OUT Type D IN output disable Type A Schmitt trigger input with hysteresis characteristics 10 I/O circuit consisting of Type D push-pull output and Type A input buffer µPD75104A, 75108A TYPE F TYPE N Comparator data IN/OUT IN + Type D output disable – Type B V REF (threshold voltage) I/O circuit consisting of Type D push-pull output circuit and Type B Schmitt trigger input TYPE M V DD Pull-up resistor (mask option) IN/OUT data N-ch (+12 V withstand) output disable Medium-voltage input buffer (+12 V withstand) 11 µPD75104A, 75108A 3.4 RECOMMENDED PROCESSING OF UNUSED PINS Pin Recommended connections PTH00-PTH03 TI0 Connect to VSS or VDD TI1 P00 Connect to VSS P01-P03 Connect to VSS or VDD P10-P13 • Connect to VDD when a pull-up resistor is provided. • Connect to VSS when a pull-up resistor is not provided. P20-P23 • Input: Connect to VSS P30-P33 • Output: Open • When a pull-up resistor is provided: P40-P43 P50-P53 P60-P63 Input: Connect to VDD P70-P73 Output: Open P80-P83 • When a pull-up resistor is not provided: P90-P93 Input: Connect to VSS or VDD P120-P123 Output: Open P130-P133 P140-P143 RESET Connect to VDD* NC Open or connect to VDD *: Connect this pin to the VDD pin only when a power-ON reset circuit is provided as a mask option. 12 µPD75104A, 75108A 3.5 NOTES ON USING THE P00/INT4, AND RESET PINS In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode, in which the internal fuctions of the µPD75108A are tested (solely used for IC tests), is provided to the P00/ INT4 and RESET pins. If a voltage exceeding VDD is applied to either of these pins, the µPD75108A is put into test mode. Therefore, even when the µ PD75108A is in normal operation, if noise exceeding the VDD is input into any of these pins, the µPD75108A will enter the test mode, and this will cause problems for normal operation. As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up to these pins and the above montioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. • Connect a diode across P00/INT4 and RESET , and VDD . • Connect a capacitor across P00/INT4 and RESET , and VDD . VDD VDD VDD VDD P00/INT4, RESET P00/INT4, RESET 13 µPD75104A, 75108A 4. MEMORY CONFIGURATION • Program memory (ROM) ... 8064 × 8 bits (0000H-1F7FH) : µPD75108A ... 4096 × 8 bits (0000H-0FFFH) : µPD75104A • 0000H, 0001H : Vector table to which address from which program is started is written after reset • 0002H-000BH: Vector table to which address from which program is started is written after interrupt • 0020H-007FH : Table area referenced for GETI instruction • Data memory (RAM) • Data area ....512 × 4 bits (000H–1FFH) : µPD75108A 320 × 4 bits (000H-13FH) : µPD75104A • Peripheral hardware area .... 128 × 4 bits (F80H–FFFH) 14 µPD75104A, 75108A (a) µ PD75108A Address 7 0000H 6 MBE RBE 5 0 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE 0 INTBT/INT4 start address (upper 5 bits) CALL ! addr instruction subroutine entry address INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE 0 INT0/INT1 start address (upper 5 bits) INT0/INT1 start address (lower 8 bits) 0006H MBE RBE 0 INTSIO start address (upper 5 bits) INTSIO start address (lower 8 bits) 0008H MBE RBE 0 CALLF ! faddr instruction entry address INTT0 start address (upper 5 bits) BR $addr instruction relational branch address -15 to -1, +2 to +16 INTT0 start address (lower 8 bits) 000AH MBE RBE 0 BR ! addr instruction branch address INTT1 start address (upper 5 bits) INTT1 start address (lower 8 bits) 0020H GETI instruction reference table 007FH 0080H BRCB ! caddr instruction branch address Branch destination address and subroutine entry address for GETI instruction 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 1F7FH Fig. 4-1 Program Memory Map (1/2) Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction. 15 µPD75104A, 75108A (b) µ PD75104A Address 7 0000H 6 MBE RBE 5 4 0 0 0 Internal reset start address (upper 4 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE 0 0 INTBT/INT4 start address (upper 4 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE 0 0 INT0/INT1 start address (upper 4 bits) INT0/INT1 start address (lower 8 bits) 0006H MBE RBE 0 0 INTSIO start address (upper 4 bits) INTSIO start address (lower 8 bits) 0008H MBE RBE 0 0 CALLF ! faddr instruction entry address INTT0 start address (upper 4 bits) CALL ! addr instruction subroutine entry address BR $addr instruction relational branch address -15 to -1, +2 to +16 INTT0 start address (lower 8 bits) 000AH MBE RBE 0 0 INTT1 start address (upper 4 bits) INTT1 start address (lower 8 bits) BRCB ! caddr instruction branch address 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address for GETI instruction 07FFH 0800H 0FFFH Fig. 4-1 Program Memory Map (2/2) Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction. 16 µPD75104A, 75108A (a) µ PD75108A Data memory General-purpose register area 000H Memory bank (32 × 4) 01FH Stack area Bank 0 256× 4 Data memory Static RAM (512 × 4) 0FFH 100H 256× 4 Bank 1 1FFH Not provided F80H 128× 4 Peripheral hardware area Bank 15 FFFH Fig. 4-2 Data Memory Map(1/2) 17 µPD75104A, 75108A (b) µ PD75104A Data memory General-purpose register area 000H Memory bank (32 × 4) 01FH Stack area Bank 0 Data area Static RAM (320 × 4) 256× 4 0FFH 100H 64 × 4 Bank 1 13FH Not provided F80H 128× 4 Peripheral hardware area FFFH Fig. 4-2 Data Memory Map(2/2) 18 Bank 15 µPD75104A, 75108A 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports are classified into the following 3 kinds: • CMOS input (PORT0, 1) : 8 • CMOS input/output (PORT2, 3, 4, 5, 6, 7, 8, 9) : 32 • N-ch open-drain input/output (PORT12, 13, 14) : 12 Total : 52 Table 5-1 Port Function Port (Symbol) Function Operation and Features Remarks Shared witn SI, SO, SCK, and PORT0 4-bit input Can always be read or tested regardless of operation INT4 pins mode of shared pin Shared with INT0 to 3 pins each bit can be connected to pull-up PORT1 resistor by mask otion. Each bit of Port 6 pins can be PORT3 Can be set in input or output mode bitwise PORT6 connected to pull-up resistor by mask option Shared with PTO0, PTO1, and PORT2 PCL pins. PORT4 4-bit I/O* Can be set in input or output mode in 4-bit units. PORT5 Ports 4 and 5, 6 and 7, 8 and 9 can be used in pairs PORT7 to input or output 8-bit data Each bit can be connected to pullup resistor by mask option PORT8 PORT9 PORT12 4-bit I/O* PORT13 PORT14 Can be set in input or output mode in 4-bit units. Each bit can be connected to (N-ch open-drain. Ports 12 and 13 can be used in pairs to input or pull-up resistor by mask option 12V) output 8-bit data *: Can directly drive LED. 19 µPD75104A, 75108A 5.2 CLOCK GENERATOR CIRCUIT The clock generator circuit generates clocks to control CPU operation modes by supplying clocks to the CPU and peripheral hardware. In addition, this circuit can change the instruction execution time. • 0.95 µs/1.91 µs/15.3 µs (operating at 4.19 MHz) · Basic interval timer (BT) · Clock output circuit · Timer/event counter · Serial interface X1 X1 1/8 to 1/4096 System clock generator circuit f XX or Frequency divider fX 1/2 1/16 X2 X2 Oscillation stops Selector Frequency divider 1/4 Φ · CPU · Clock output circuit PCC Internal bus PCC0 PCC1 4 HALT F/F PCC2 S HALT* PCC3 STOP* R Clears PCC2, PCC3 Q STOP F/F Q Wait release signal from BT S RES (internal reset) signal R Standby release signal from interrupt control circuit Remarks 1: f XX = Crystal/ceramic oscillator 2: f X = External clock frequency 3: * indicates the instruction execution 4: PCC: Processor clock control register 5: One clock cycle (t CY) of Φ is one machine cycle of an instruction. For tCY, refer to AC ★ characteristics in 12. ELECTRICAL SPECIFICATIONS. Fig. 5-1 Clock Generator Block Diagram 20 µPD75104A, 75108A 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output clock pulses to the remote control output, peripheral LSIs, etc. • Clock output (PCL) : Φ, 524 kHz, 262 kHz (operating at 4.19 MHz) From the clock generator Φ f XX/23 Output buffer Selector PCL/P22 f XX/24 PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Fig. 5-2 Clock Output Circuit Configuration 21 µPD75104A, 75108A 5.4 BASIC INTERVAL TIMER The basic interval timer has these functions: • Interval timer operation which generates a reference time interrupt • Watchdog timer application which detects a program runaway • Selects the wait time for releasing the standby mode and counts the wait time • Reads out the count value From the clock generator Clear Clear fXX/25 fXX/27 Set signal Basic interval timer (8-bit frequency divider circuit) MPX fXX/29 BT f XX/212 3 BTM3 *SET1 BT interrupt request flag BTM2 Vector interrupt request IRQBT signal Wait release signal for standby release BTM1 BTM0 BTM 8 4 Internal bus Remarks : *: Instruction execution Fig. 5-3 Basic Interval Timer Configuration 5.5 TIMER/EVENT COUNTER µPD75108A contains two channels of timer/event counters. These two channels are almost identical in terms of configuration and function except the count pulse (CP) that can be selected and the function to supply clocks to the serial interface. The functions of the timer/event counter include: • Programmable interval timer operation • Output of square wave at an arbitrary frequency to PTOn pin • Event counter operation • Input of TIn pin signal as external interrupt input signal • Dividing TIn pin input by N to output to PTOn pin (frequency divider operation) • Supply of serial shift clock to serial interface circuit (channel 0 only) • Reading counting status 22 Internal bus 8 SET1* TMn 8 8 TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0 TMODn TOEn To enable flag Modulo register (8) TOFn TIn 8 Coincidence TOUT F/F Comparator (8) 8 Input buffer TOn PORT2.n Bit 2 of PGMB P2n Port 2 output I/O latch mode To serial interface (channel 0 only) P2n/PTOn To selector Output buffer Tn INTTn TIn From clock generator circuit CP MPX Edge detector circuit Count register (8) Clear TMn1 Timer operation start RES Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1) TMn0 IRQTn clear signal 23 µPD75104A, 75108A *: SET1: Execution of the instruction IRQTn set signal µPD75104A, 75108A 5.6 SERIAL INTERFACE The µPD75108A is equipped with clock 8-bit serial interface that operates in the following two modes: • Operation stop mode • Three-line serial I/O mode 24 Internal bus 8 SET1* 8 8 SIO0 SIO7 SIOM SIO P03/SI Shift register (8) SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0 P02/SO Serial clock counter (3) INTSIO IRQSIO set signal Overflow Clear IRQSIO clear signal Serial start P01/SCK R Q Φ S f XX /2 10 TOF0 (from timer channel 0) *: Execution of the instruction Fig. 5-5 Serial Interface Block Diagram 25 µPD75104A, 75108A f XX /2 4 MPX µPD75104A, 75108A 5.7 PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) µPD75108A is equipped with a 4-bit analog input port (consisting of PTH00 to PTH03 pins) whose threshold voltage is programmable. This programmable threshold port is configured as shown in Figure 5-6. The threshold voltage (VREF) can be changed in 16 steps (VDD × 0.5/16 – VDD × 15.5/16), and analog signals can be directly input. When VREF is set to VDD × 7.5/16, the programmable threshold port can also be used as a digital signal input port. Input buffer + PTH00 Programmable threshold port input latch (4) – + PTH01 – + PTH02 – PTH03 – Operates /stops Internal bus + PTH0 V DD PTHM7 1 2R PTHM6 R PTHM5 R MPX V REF PTHM4 8 PTHM3 PTHM2 1 2R 4 PTHM1 PTHM0 PTHM Fig. 5-6 Programmable Threshold Port Configuration 26 µPD75104A, 75108A 5.8 BIT SEQUENTIAL BUFFER .... 16 BITS The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. FC3H Address bit 3 Symbol L register 2 FC2H 1 0 3 BSB3 L=F 2 FC1H 1 0 3 BSB2 L=C L=B 2 FC0H 1 0 3 BSB1 L=8 L=7 2 1 0 BSB0 L=4 L=3 L=0 DECS L INCS L Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register. Fig. 5-7 Bit Sequential Buffer Format 5.9 POWER-ON FLAG (MASK OPTION) The power-ON flag (PONF) is set to only when the power-ON reset circuit operates and power-ON reset signal has been generated (see Fig. 8-1). The PONF flag is mapped at bit 0 of memory space address FD1H, and can be manipulated by a bit manipulation instruction. However, it cannot be set by the SET1 instruction. 6. INTERRUPT FUNCTIONS The µ PD75108A has 7 different interrupt sources and can perform multiplexed interrupt processing with priority assigned. In addition to that, the µ PD75108A is also provided with two types of edge detection testable inputs. The interrupt control circuit of the µ PD75108A has these functions: • Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt enable flag (IExxx) and interrupt master enable flag (IME). • The interrupt start address can be arbitrarily set. • Multiplexed interrupt function that can specify priority by the interrupt priority selector register (IPS). • Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). • Standby mode release (Interrupts to be released can be selected by the interrupt enable flag). 27 28 Internal bus 2 2 IM1 IM0 9 INT BT Edge detection circuit Edge detection circuit Edge detection circuit INT4 /P00 INT0 /P10 INT1 /P11 INT2 /P12 IPS IST Decoder IRQBT IRQ4 IRQ0 IRQ1 INTSIO IRQSIO INTT0 IRQT0 INTT1 IRQT1 Edge detection circuit Edge detection circuit IME 2 Priority control circuit Vector table address generator IRQ2 Standby release signal IRQ3 Interrupt request flag Fig. 6-1 Interrupt Control Block Diagram µPD75104A, 75108A INT3 /P13 Interrupt enable flag (IE ××× ) 4 µPD75104A, 75108A 7. STANDBY FUNCTIONS The µ PD75108A has two different standby modes (STOP mode and HALT mode) to reduce the power consumption of the microcomputer chip while waiting for program execution. Table 7-1 Each Status in Standby Mode STOP Mode Setting Instruction HALT Mode STOP instruction HALT instruction Clock Oscillator circuit Clock oscillation stops Only CPU clock Φ is stopped Basic Interval Timer Stops Operates (sets IRQBT at reference time intervals) Operates only when input of external Serial Interface Operation Status SCK or output of TO0 is selected as Operates when serial clock other than Φ is specified serial clock (where external TI0 is input to timer/event counter 0) Timer/Event Counter Operates only when TIn pin input signal is specified as count clock Operates Clock output circuit Stops Outputs when clock other than CPU clock Φ is used CPU Stops Stops Release Signal Interrupt request signal enabled by interrupt enable flag, or RESET input 29 µPD75104A, 75108A 8. RESET FUNCTION The reset ( RES ) signal generator circuit is configured as shown in Figure 8-1. RESET Internal reset signal (RES) Power-ON reset generator circuit SWB SWA Power-ON flag (PONF) Execution of bit manipulation instruction* Internal bus Mask option *: PONF cannot be set to 1 by SET1 instruction. Fig. 8-1 Reset Signal Generator Circuit The Power-ON reset generator circuit generates an internal reset signal when the supply voltage rises. This pulse can be used in three ways by specifying a mask option through SWA and SWB shown in Fig. 8-1. (Refer to 11. MASK OPTION SELECTION.) The reset operations performed by the Power-On reset circuit and the RESET input signal are illustrated in Figs. 8-2 and 8-3, respectively. Supply voltage 0V Wait* (approx. 31.3 ms: 4.19 MHz) Internal reset signal (RES) HALT mode Operation mode Internal reset operation *: The wait time does not include the time required after the RES signal has been generated until the oscillation starts. Fig. 8-2 Reset by Power-ON Reset Circuit 30 µPD75104A, 75108A Wait* (31.3 ms: 4.19 MHz) RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation *: The wait time does not include the time required after the RES signal has been generated until the oscillation starts. Fig. 8-3 Reset by RESET Signal The status of each internal hardware device after the reset operation has been performed is shown in Table 81. Table 8-1 Hardware Device Status After Reset (1/2) RESET input during standby mode Power-ON Reset or RESET Input during Operation Lower 5 bits of program memory address 0000H are set to PC12-8,* 1 and contents of address 0001H are set to PC 7-0. Lower 5 bits of program memory address 0000H are set to PC12-8,* 1 and contents of address 0001H are set to PC7-0. Retained Undefined Skip Flags (SK0-SK2) 0 0 Interrupt Status Flags (IST0, IST1) 0 0 Bit 6 of program memory address 0000H is set in RBE, and bit 7 is set in MBE. Bit 6 of program memory address 0000H is set in RBE, and bit 7 is set in MBE. Stack Pointer (SP) Undefined Undefined Data Memory (RAM) Retained*2 Undefined Retained Undefined Hardware Program Counter (PC) Carry Flag (CY) PSW Bank Enable Flags (MBE, RBE) General-Purpose Registers (X,A,H,L,D,E,B,C) Bank Selector Registers (MBS, RBS) Basic interval timer Timer/Event Counter (n = 0, 1) Counter (BT) 0, 0 Undefined Undefined Mode Register (BTM) 0 0 Counter (Tn) 0 0 FFH FFH 0 0 Modulo Register (TMODn) Mode Register (TMn) TOEn, TOFn Serial Interface 0, 0 Shift Register (SIO) Mode Register (SIOM) 0, 0 0, 0 Retained Undefined 0 0 *1: PC11-8 for µPD75104A 2: Data at data memory addresses 0F8H to 0FDH become undefined when the RESET signal has been input. 31 µPD75104A, 75108A Table 8-1 Hardware Device Status After Reset (2/2) Hardware Clock Generator Circuit, Clock Output Circuit 0 0 Clock Output Mode Register (CLOM) 0 0 Reset (0) Reset (0) 0 0 Interrupt Enable Flags (IExxx) Digital Port Priority Selector Register (IPS) 0 0 INT0, 1 Mode Registers (IM0, IM1) 0, 0 0, 0 Output Buffer Off Off Output Latch Cleared (0) Cleared (0) 0 0 Undefined Undefined 0 0 Retained 1 or undefined* 0 0 I/O Mode Registers (PMGA, PMGB, PMGC) PTH00-PTH03 Input Latches Analog Port Mode Register (PTHM) Power-ON Flag (PONF) Bit Sequential Buffer (BSB0-BSB3) *: Power-ON reset: 1 RESET input during operation: undefined 32 Power-ON Reset or RESET Input during Operation Processor Clock Control Register (PCC) Interrupt Request Flags (IRQxxx) Interrupt RESET input during standby mode µPD75104A, 75108A 9. INSTRUCTION SET (1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and – are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols in the register and flag symbols can be described as labels in the places of mem, fmem, pmem, and bit (for details, refer to µPD751XX Series User‘s Manual (IEM-922)). However, fmem and pmem restricts the label that can be described. Representation Description reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label* 2-bit immediate data or label fmem pmem FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr µPD75104A 0000H to 0FFFH immediate data or label µPD75108A 0000H to 1F7FH immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H to 7FH immediate data (where bit0 = 0) or label PORTn IExxx RBn MBn PORT0 - PORT9, PORT12 - PORT14 IEBT, IESIO, IET0, IET1, IE0 - IE4 RB0 - RB3 MB0, MB1, MB15 *: Only even address can be described as mem for 8-bit data processing. 33 µPD75104A, 75108A (2) Legend of operation field A : A register; 4-bit accumulator B : B register; 4-bit accumulator C : C register; 4-bit accumulator D : D register; 4-bit accumulator E : E register; 4-bit accumulator H : H register; 4-bit accumulator L : L register; 4-bit accumulator X : X register; 4-bit accumulator XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC); 8-bit accumulator DE : Register pair (DE); 8-bit accumulator HL : Register pair (HL); 8-bit accumulator XA' : Expansion register pair (XA') BC' : Expansion register pair (BC') DE' : Expansion register pair (DE') HL' : Expansion register pair (HL') PC : Program counter SP : Stack pointer CY : Carry flag; or bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 - 9, 12 - 14) 34 IME : Interrupt mask enable flag IPS : Interrupt priority selection register IExxx : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC . : Processor clock control register (xx) : Contents addressed by xx xxH : Hexadecimal data : Delimiter of address and bit µPD75104A, 75108A (3) Symbols in addressing area field *1 MB = MBE . MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 µPD75104A addr = 0000H-0FFFH µPD75108A addr = 0000H-1F7FH Data memory addressing *7 addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 Program memory *8 µPD75104A caddr = 0000H-0FFFH (PC 11 = 0) addressing µPD75108A caddr = 0000H-0FFFH (PC 12 = 0) or 1000H-1F7FH (PC12 = 1) *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH Remarks • MB indicates memory bank that can be accessed. • In *2, MB = 0 regardless of MBE and MBS. • In *4 and *5, MB = 15 regardless of MBE and MBS. • *6 to *10 indicate areas that can be addressed. (4) Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: • When no instruction is skipped ........................................................................ S=0 • When 1-byte or 2-byte instruction is skipped ................................................. S=1 • When 3-byte instruction (BR ! adder or CALL ! adder) is skipped .............. S=2 Note : The GETI instruction is skipped in one machine cycle. One machine cycle equals to one cycle of the CPU clock Φ, (= tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC). 35 µPD75104A, 75108A Instructions Mnemonics Transfer MOV XCH Table MOVT Operand Machine Bytes Cycles Operation Skip Conditions A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 String effect A @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' XA, @PCDE 1 3 • µPD75104A Refer- XA ← (PC11-8+DE)ROM ence • µPD75108A XA ← (PC12-8+DE)ROM XA, @PCXA 1 3 • µPD75104A XA ← (PC11-8+XA)ROM • µPD75108A XA ← (PC12-8+XA)ROM 36 Addressing Area µPD75104A, 75108A Instructions Mnemonics Operand Bytes Machine Cycles Bit MOV1 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem. 2 2 CY ← (H+mem3-0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7-2+L 3-2.bit(L1-0)) ← CY *5 @H+mem.bit, 2 2 (H+mem3-0.bit) ← CY *1 A, #n4 1 1+S A ← A+n4 carry XA, #n8 2 2+S XA ← XA+n8 carry transfer Operation Addressing Area Skip Conditions bit CY Arith- ADDS metic opera- A, @HL 1 1+S A ← A+(HL) tion XA, rp’ 2 2+S XA ← XA+rp’ carry rp’1, XA 2 2+S rp’1 ← rp’1+XA carry A, @HL 1 1 A, CY ← A+(HL)+CY XA, rp’ 2 2 XA, CY ← XA+rp’+CY ADDC SUBS SUBC *1 carry *1 rp’1, CY ← rp’1+XA+CY rp’1, XA 2 2 A, @HL 1 1+S A ← A-(HL) XA, rp’ 2 2+S XA ← XA-rp’ borrow rp’1, XA 2 2+S rp’1 ← rp’1-XA borrow A, @HL 1 1 A, CY ← A-(HL)-CY XA, rp’ 2 2 XA, CY ← XA-rp’-CY rp’1, XA 2 2 rp’1,CY ← rp’1-XA-CY A, #n4 2 2 A, @HL 1 1 XA, rp’ 2 2 rp’1, XA 2 2 A, #n4 2 2 A, @HL 1 1 XA, rp’ 2 2 rp’1, XA 2 2 A, #n4 2 2 A, @HL 1 1 XA, rp’ 2 2 *1 borrow *1 rp’1, XA 2 2 ∧ n4 A ← A ∧ (HL) XA ← XA ∧ rp’ rp’1 ← rp’1 ∧ XA A ← A ∨ n4 A ← A ∨ (HL) XA ← XA ∨ rp’ rp’1 ← rp’1 ∨ XA A ← A ∨ n4 A ← A ∨ (HL) XA ← XA ∨ rp’ rp’1 ← rp’1 ∨ XA Accumulator RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An Manipulation NOT A 2 2 A←A INCS reg 1 1+S reg ← reg+1 reg = 0 ment/ rp1 1 1+S rp1 ← rp1+1 rp1 = 00H decre- @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 ment mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0 reg 1 1+S reg ← reg-1 reg = FH rp’ 2 2+S rp’ ← rp’-1 rp’ = FFH AND OR XOR Incre- DECS A←A *1 *1 *1 37 µPD75104A, 75108A Instructions Mnemonics Com- SKE pare Operand Machine Bytes Cycles Operation Addressing Area Skip Conditions reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp’ 2 2+S Skip if XA = rp’ XA = rp’ Carry SET1 CY 1 1 CY ← 1 flag CLR1 CY 1 1 CY ← 0 Manipu- SKT CY 1 1+S lation CY 1 1 CY ← CY mem.bit 2 2 (mem.bit) ← 1 *3 Bit fmem.bit 2 2 (fmem.bit) ← 1 *4 Manipu- pmem.@L 2 2 (pmem7-2 + L 3-2.bit(L1-0)) ← 1 *5 lation @H+mem.bit 2 2 (H + mem 3-0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem 7-2 + L 3-2.bit(L1-0)) ← 0 *5 @H+mem.bit 2 2 (H+mem3-0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L3-2 .bit (L1-0 )) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 0 *1 (@H+mem.bit) = 0 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 2 2+S Skip if (pmem 7-2+L 3-2.bit *5 (pmem.@L) = 1 *1 (@H+mem.bit) = 1 NOT1 Memory/ SET1 CLR1 SKT SKF SKTCLR fmem.bit pmem.@L Skip if CY = 1 CY = 1 (L 1-0)) = 1 and clear AND1 OR1 XOR1 38 @H+mem.bit 2 2+S CY, fmem.bit 2 2 CY, pmem.@L 2 2 CY, @H+mem.bit 2 2 CY, fmem.bit 2 2 ∧ (fmem.bit) CY ← CY ∧ (pmem 7-2+L 3-2.bit(L1-0)) CY ← CY ∧ (H+mem 3-0.bit) CY ← CY ∨ (fmem.bit) CY, pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L 3-2.bit (L1-0)) CY, @H+mem.bit 2 2 CY ← CY CY, fmem.bit 2 CY, pmem.@L CY, @H+mem.bit Skip if (H+mem 3-0.bit) = 1 and clear CY ← CY *4 *5 *1 *4 *5 2 ∨ (H+mem 3-0.bit) CY ← CY ∨ (fmem.bit) *4 2 2 CY ← CY ∨ (pmem7-2+L 3-2.bit (L1-0)) *5 2 2 CY ← CY ∨ (H+mem 3-0.bit) *1 *1 µPD75104A, 75108A Instructions Mnemonics Branch BR Operand addr Machine Bytes Cycles — Addressing Area Operation • µPD75104A — Skip Conditions *6 PC11-0 ← addr The most suitable instruction is selectable from among BRCB ! caddr, and BR $ addr depending on the assembler. • µPD75108A PC12-0 ← addr The most suitable instruction is selectable from among BR ! addr, BRCB ! caddr, and BR $ addr depending on the assembler. ! addr 3 3 • µPD75108A *6 PC12-0 ← addr $ addr 1 2 • µPD75104A *7 PC11-0 ← addr • µPD75108A PC12-0 ← addr BRCB ! caddr 2 2 • µPD75104A *8 PC11-0 ← caddr 11-0 • µPD75108A PC12-0 ← PC12 + caddr11-0 BR PCDE 2 3 • µPD75104A PC11-0 ← PC11-8 + DE • µPD75108A PC12-0 ← PC12-8 + DE PCXA 2 3 • µPD75104A PC11-0 ← PC11-8 + XA • µPD75108A PC12-0 ← PC12-8 + XA Subrou- CALL ! addr 3 3 • µPD75104A tine/ (SP-4)(SP-1)(SP-2) ← PC11-0 Stack (SP-3) ← MBE, RBE, 0, 0 Control PC11-0 ← addr, SP ← SP-4 *6 • µPD75108A (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, 0, PC12 PC12-0 ← addr, SP ← SP-4 39 µPD75104A, 75108A Instructions Mnemonics Subrou- CALLF Operand ! faddr Machine Bytes Cycles 2 2 Operation • µPD75104A tine/ (SP-4)(SP-1)(SP-2) ← PC11-0 Stack (SP-3) ← MBE, RBE, 0, 0 Control PC11-0 ←0, faddr, SP ← SP-4 (Cont‘d) Addressing Area Skip Conditions *9 • µPD75108A (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, 0, PC12 PC12-0 ← 00, faddr, SP ← SP-4 RET 1 3 • µPD75104A MBE, RBE, x, x ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4 • µPD75108A MBE, RBE, x, PC 12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4 RETS 1 3+S • µPD75104A MBE, RBE, x, x ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally • µPD75108A MBE, RBE, x, PC 12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally RETI 1 3 • µPD75104A MBE, RBE, x, x ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 • µPD75108A MBE, RBE, x, PC 12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 PUSH rp 1 1 BS 2 2 (SP-1)(SP-2) ← rp, SP ← SP-2 (SP-1) ← MBS, (SP-2) ← RBS, SP ← SP-2 POP rp 1 1 BS 2 2 rp ← (SP+1)(SP), SP ← SP+2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 40 Unconditioned µPD75104A, 75108A Instructions Mnemonics Inter- EI rupt Control I/O Operand 2 IME (IPS.3) ← 1 2 2 IExxx ← 1 2 2 IME (IPS.3) ← 0 IExxx 2 2 IExxx ← 0 A, PORTn 2 2 A ← PORTn XA, PORTn 2 2 XA ← PORTn+1,PORTn (n = 4, 6, 8, 12) PORTn, A 2 2 PORTn ← A PORTn, XA 2 2 PORT n+1, PORT n ← XA(n = 4, 6, 8, 12) DI OUT* Operation 2 IExxx IN* Machine Bytes Cycles (n = 2-9, 12-14) HALT 2 2 Set HALT Mode (PCC.2 ← 1) Control STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n (n = 0-3) MBn 2 2 MBS ← n (n = 0, 1, 15) taddr 1 3 SEL GETI Skip Conditions (n = 0-9, 12-14) CPU Special Addressing Area • µPD75104A *10 • Where TBR instruction, PC11-0 ← (taddr)3-0+(taddr+1) ......................................................... • Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, 0, 0 PC11-0 ← (taddr)3-0+(taddr+1) SP ← SP-4 ......................................................... • Except for TBR and TCALL ............................. Depends on instructions, referenced Instruction execution of instruction (taddr)(taddr+1) • µPD75108A • Where TBR instruction, PC12-0 ← (taddr)4-0+(taddr+1) ......................................................... • Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, 0, PC12 PC12-0 ← (taddr)4-0+(taddr+1) SP ← SP-4 ......................................................... • Except for TBR and TCALL ............................. Depends on instructions, referenced Instruction execution of instruction (taddr)(taddr+1) *: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. ★ Remarks: TBR and TCALL instructions are assembler instructions for GETI instruction table definition. 41 µPD75104A, 75108A 10. APPLICATION EXAMPLES 10.1 VCR CAMERA µ PD75108A Highcurrent output Operation mode LED indicator Key matrix (including message input) System control/ editing function Reel pulse INT Servo system control circuit Battery sensor Comparator input Sensor circuit Exposure sensor Tape start/end sensor Motor plunger driver circuit, etc. INT On-screen display controller 12 V Audio video system control circuit 42 Powerdown detector µPD75104A, 75108A 11. MASK OPTION SELECTION µPD75108A has the following mask options. Options to be built in can be selected. (1) Pin Pin Mask Option P10 - P13 P40 - P43 P50 - P53 P60 - P63 P70 - P73 Pull-down resistor can be built in bitwise. P80 - P83 P90 - P93 P120 - P123 P130 - P133 P140 - P143 (2) Power-ON reset generation circuit, power-ON flag (PONF) One from the following three ways can be selected. Mask Option Specification Switching Selection (Refer to Fig. 8-1.) Internal Reset Signal Power-On Reset Power-On Flag Generator Circuit (PONF) SWA SWB Provided Provided ON ON Generates automatically Not provided Provided ON OFF Not generate autoamtically Not provided Not provided OFF OFF — (RES) 43 µPD75104A, 75108A 12. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Parameter Supply Voltage Symbol Ratings VDD VI1 Input Voltage Conditions VI2* 1 Other than ports 12 to 14 Ports 12 to 14 w/pull-up resistor Open drain Output Voltage VO High-Level Output Current IOH Low-Level Output IOL*2 Unit -0.3 to +7.0 V -0.3 to V DD+0.3 V -0.3 to V DD+0.3 -0.3 to +13 V V -0.3 to V DD+0.3 V 1 pin -15 mA All pins -30 mA 1 pin Current Total of ports 0, 2 to 4, 12 to 14 Total of ports 5 to 9 Peak 30 mA rms 15 mA Peak 100 mA rms 60 mA Peak 100 mA 60 mA Operating Temperature Topt rms -40 to +85 °C Storage Temperature Tstg -65 to +150 °C *1: The power supply impedance (pull-up resistor) must be 50 kΩ or higher when a voltage higher than 10 V is applied to ports 12 to 14. 2: rms = Peak value x √Duty Note: Even if one of the parametrs exceed its absolute maximum rating even momentarily, the quality ★ of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. 44 µPD75104A, 75108A OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Recommended Constants Oscillator Ceramic Item Oscillation frequency(fXX)* 1 X1 X2 C1 C2 Crystal Conditions VDD = Oscillation voltage range Oscillation stabiliza- After VDD come to tion time*2 MIN. of oscillation voltage range Oscillation frequency (fXX)* 1 X1 X2 C1 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2 MIN. TYP. MAX. 5.0 * 2.0 3 4 2.0 Unit MHz ms 4.19 5.0 * 3 MHz 10 ms 30 ms C2 External Clock X1 input frequency (f X)*1 X1 X2 µ PD74HCU04 X1 input high-, low-level widths (t XH, t XL) 2.0 5.0 *3 100 250 MHz ns *1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD has come to MIN. of oscillation voltage range or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fxx ≤ 5.0 MHz, do not select PCC = 0011 as the ★ instruction execution time: otherwise, one machine cycle is set to less than 0.95 µs, falling short of the rated minimum value of 0.95 µs. Note: ★ When using the oscillation circuit of the system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. Also, do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the osccillator circuit at the same potential as VSS . Do not connect the ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 45 µPD75104A, 75108A RECOMMENDED OSCILLATOR CIRCUITS CONSTANTS RECOMMENDED CERAMIC OSCILLATORS Manufacturer Product Name External Oscillation Capacitance (pF) Voltage Range (V) C1 C2 MIN. MAX. CSA 2.00MG 30 30 2.7 6.0 Murata Mfg. CSA 4.19MG 30 30 3.0 6.0 Co., Ltd. CSA 4.19MGU 30 30 2.7 6.0 CST 4.19T Provided Provided 3.0 6.0 KBR-2.0MS 100 100 3.0 6.0 Kyoto Ceramic KBR-4.0MS 33 33 3.0 6.0 Co., Ltd. KBR-4.19MS 33 33 3.0 6.0 KBR-4.9152M 33 33 3.0 6.0 RECOMMENDED CRYSTAL OSCILLATOR Manufacturer Kinseki Product Name HC-49/U External Capacitance (pF) C1 C2 MIN. MAX. 22 22 2.7 6.0 Note: Use a crystal oscillator with an equivalent series resistance of 80Ω or less. 46 Oscillation Voltage Range (V) µPD75104A, 75108A DC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V) Item Symbol High-Level Input Voltage Low-Level Input Voltage Conditions MIN. Low-Level Output Voltage 0.7VDD VDD V VIH2 Ports 0, 1, TI0, 1, RESET 0.8 V DD VDD V VIH3 Ports 12 to 14 Pull-up resistor 0.7 VDD VDD V Open drain 0.7 VDD 12 V VDD-0.5 VDD V VIH4 X1, X2 VIL1 Other than below 0 0.3 VDD V VIL2 Ports 0, 1, TI0, 1, RESET 0 0.2 V DD V VIL3 X1, X2 0 0.4 V VOH IOH = -100 µA VDD-1.0 V VDD-0.5 V VDD = Ports 0, 2 to 9, I OL = 15 mA 0.35 2.0 V 4.5 to 6.0 V Ports 12 to 14, IOL = 10 mA 0.35 2.0 V 0.4 V 0.5 V Other than below 3 µA X1,X2 20 µA Ports 12 to 14 (open drain) 20 µA Other than X1, X2 –3 µA –20 µA 3 µA 20 µA –3 µA 70 kΩ 80 kΩ VOL IOL = 400 µA Current ILIH1 VIN = VDD ILIH2 ILIH3 Low-Level Input Unit Other than below VDD = 4.5 to 6.0 V, IOL = 1.6 mA High-Level Input Leakage MAX. VIH1 VDD = 4.5 to 6.0 V,IOH = -1 mA High-Level Output Voltage TYP. VIN = 12 V ILIL1 VIN = 0 V Leakage Current ILIL2 X1, X2 High-Level Output ILOH1 VOUT = V DD Other than below Leakage Current ILOH2 VOUT = 12 V Ports 12 to 14 (open drain) Low-Level Output Leakage Current ILOL VOUT = 0 V Internal Pull-Up Resistor RL Ports 1, 4 to 9, VDD = 5 V±10% and 12 to 14 IDD1 Supply Current*1 IDD2 IDD3 15 40 10 4.19MHz VDD = 5 V±10%* 2 3 9 mA crystal VDD = 3 V±10%* 3 0.55 1.5 mA oscillator HALT VDD = 5 V±10% 600 1800 µA C1 = C2 = 22pF mode VDD = 3 V±10% 200 600 µA 0.1 10 µA STOP mode, VDD = 3 V±10% *1: The current flowing into the internal pull-up resistor, power-ON reset circuit (mask option), and comparator circuit is not included. 2: When the high-speed mode is set by setting the processor clock control register (PCC) to 0011. 3: When the low-speed mode is set by setting the PCC to 0000. 47 µPD75104A, 75108A CAPACITANCE (Ta = 25°C, VDD = 0 V) Parameter Symbol Input Capacitance CIN Output Capacitance COUT Input/Output Capacitance CIO Conditions MIN. TYP. f = 1 MHz MAX. 15 Pins other than thosemeasured are at 0 V Unit pF 15 pF 15 pF MAX. Unit ±100 mV V ° COMPARATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 4.5 to 6.0 V) Parameter Comparison Accuracy Symbol Conditions MIN. TYP. VACOMP Threshold Voltage VTH 0 V DD PTH Input voltage VIPTH 0 V DD Comparator circuit current dissipation PTHM7 is set to “1” 1 V mA POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = -40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power-On Reset High-Level VDDH 4.5 6.0 V VDDL 0 0.2 V tr 10 *1 µs toff 1 Operating Voltage Power-On Reset Low-Level Operating Voltage Supply Voltage Rise Time Supply Voltage s Off Time Power-On Reset Circuit Current Dissipation*2 IDDPR VDD = 5 V±10% 10 100 µA VDD = 2.5 V 2 20 µA 17 *1: 2 /fXX (31.3 ms at fXX = 4.19 MHz) 2: Current flowing when power-ON reset circuit or power-ON Flag is incorporeated. V DDH V DD V DDL t off Note: Apply power gradually and smoothly. 48 tr µPD75104A, 75108A AC CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Parameter Symbol Conditions MIN. MAX. Unit 0.95 32 µs 3.8 32 µs VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz VDD = 4.5 to 6.0 V 0.48 µs 1.8 µs Input 0.8 µs Output 0.95 µs Input 3.2 µs Output 3.8 µs Input 0.4 µs tKCY /2-50 ns VDD = 4.5 to 6.0 V CPU Clock Cycle Time* (Minimum Instruction Execution Time = 1 Machine Cycle) tCY TI0, TI1 Input Frequency fTI TI0, TI1 Input High-/ Low-Level Width tTIH , tTIL VDD = 4.5 to 6.0 V SCK Cycle Time tKCY VDD = 4.5 to 6.0 V SCK High-/Low-Level Width tKH, Output tKL Input Output TYP. 1.6 µs tKCY /2-150 ns SI Setup Time (vs. SCK↑) tSIK 100 ns SI Hold Time (vs. SCK↑) tKSI 400 ns SCK ↓→ SO Output delay Time tKSO INT0 to INT4 tINTH, High-/Low-Level Width tINTL RESET Low-Level Width tRSL VDD = 4.5 to 6.0 V *: The cycle time of the CPU clock (Φ) is 300 ns 1000 ns 5 µs 5 µs tCY vs. VDD determined by the input frequency of 40 the ceramic or crystal oscillator circuit 32 and the set value of the processor clock 7 6 control register. The tCY vs. VDD characteristics are as 5 shown on the right. Operation guaranteed range t CY [µs] 4 3 2 1 0.5 0 1 2 3 4 5 6 V DD [V] 49 µPD75104A, 75108A AC TIMING MEASURING POINTS (excluding Ports 0, 1, TI0, TI1, X1, X2, and RESET) 0.7 VDD 0.7 VDD Measuring points 0.3 VDD 0.3 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD –0.5 0.4 TI INPUT TIMING 1/fTI tTIL TI0, TI1 tTIH 0.8 VDD 0.2 VDD 50 µPD75104A, 75108A SERIAL TRANSFER TIMING tKCY tKL tKH 0.8 V DD SCK 0.2 V DD tSIK tKSI 0.8 V DD SI Input data 0.2 V DD tKSO Output data SO INTERRUPT INPUT TIMING tINTL tINTH 0.8 V DD INT0 to INT4 0.2 V DD RESET INPUT TIMING tRSL RESET 0.2 V DD 51 µPD75104A, 75108A LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = –40 to +85°C) Parameter Symbol Data Retention Supply Voltage VDDDR Data Retention Supply Current*1 IDDDR Release Signal Set Time tSREL Oscillation Stabilization tWAIT Conditions MIN. TYP. 2.0 VDDDR = 2.0 V 0.1 MAX. Unit 6.0 V 10 µA µs 0 Released by RESET Wait Time*2 Released by interrupt request 217/fX ms *3 ms *1: The current flowing through internal pull-up resistor, power-ON reset circuit (mask option), and comparator circuit is not included 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 BTM2 BTM1 BTM0 – 0 0 0 2 20/fXX (approx. 250 ms) – 0 1 1 2 17/fXX (approx. 31.3 ms) – 1 0 1 2 15/fXX (approx. 7.82 ms) – 1 1 1 2 13/fXX (approx. 1.95 ms) DATA RETENTION TIMING Wait time ( ): f XX = 4.19 MHz (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT 52 µPD75104A, 75108A DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 53 µPD75104A, 75108A 13. CHARACTERISTIC DATA (REFERENCE VALUE) IDD vs. VDD Characteristics (crystal oscillation) (Ta = 25˚C) 5000 High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] 1000 HALT mode [0100] Supply current IDD [µ A] 500 100 50 STOP mode [1000] When power-ON reset circuit and power-ON flag are incorporated. 10 5 Figure in [ ] indicates set values of PCC. X1 X2 Crystal oscillation 4.194304 MHz 22 pF 22 pF 1 0.5 0 1 2 3 4 5 Supply voltage VDD [V] 6 I DD vs. f XX Characteristics (crystal oscillation) (VDD = 5.0 V, Ta = 25˚C) 3.0 Figure in [ ] indicates set values of PCC. X1 X2 High-speed mode [0011] 2.5 C2 Supply current IDD [mA] C1 2.0 Medium-speed mode [0010] 1.5 Low-speed mode [0000] 1.0 HALT mode [0100] 0.5 0 54 0 1 2 3 4 f XX [MHz] 5 µPD75104A, 75108A I DD vs. V DD Characteristics (ceramic oscillation) (Ta = 25˚C) 5000 High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] HALT mode [0100] 1000 Supply current IDD [ µ A] 500 100 50 STOP mode [1000] When power-ON reset circuit and power-ON flag are incorporated. 10 5 Figure in [ ] indicates set values of PCC. X1 X2 Ceramic oscillation 4.19 MHz 30 pF 30 pF 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] I DD vs. f XX Characteristics (ceramic oscillation) (VDD = 5.0 V, Ta = 25˚C) 3.0 Figure in [ ] indicates set values of PCC. X1 X2 High-speed mode [0011] 2.5 Supply current IDD [mA] C1 C2 Medium-speed mode [0010] 2.0 Low-speed mode [0000] 1.5 1.0 HALT mode [0100] 0.5 0 0 1 2 3 4 f XX [MHz] 5 55 µPD75104A, 75108A I DD vs. f X Characteristics (external clock) (VDD = 5.0 V, Ta = 25˚C) 3.0 Figures in [ ] indicates set values of PCC. X1 X2 2.5 Supply current IDD [µ A] µ PD74HCU04 High-speed mode [0011] 2.0 Medium-speed mode [0010] 1.5 Low-speed mode [0000] 1.0 0.5 HALT mode [0100] 0 0 1 2 3 4 f X [MHz] 5 TIn input frequency f TI [kHz] f TI vs. V DD Characteristics 1000 500 Operation guaranteed range 100 50 0 56 1 2 3 4 V DD [V] 5 6 7 µPD75104A, 75108A V OL vs. I OL (Ports 0 and 2 to 9) Characteristics V DD = 6 V V DD = 5 V Low-level output current of port 0 and 2 to 9 I OL [mA] 30 V DD = 4 V V DD = 3 V 20 10 0 0 1 2 V OL [V] 3 4 VOL vs. IOL (Ports 12 to 14) Characteristics V DD = 6 V V DD = 5 V 30 Low-level output current of ports 12 to 14 I OL [mA] V DD = 4 V 20 V DD = 3 V 10 0 0 1 2 V OL [V] 3 4 57 µPD75104A, 75108A V OH vs. I OH (Ports 0 and 2 to 9) Characteristics V DD = 6 V –15 V DD = 5 V High-level output current of port 0 and 2 to 9 IOH [mA] V DD = 4 V –10 V DD = 3 V –5 0 0 1 2 V DD - V OH [V] 58 3 4 µPD75104A, 75108A PACKAGE DRAWINGS 64 PIN PLASTIC QFP ( 14) A B 33 32 48 49 F Q 5°±5° S C detail of lead end D 14. 64 1 G 17 16 H I M J M P K N L P64GC-80-AB8-3 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.6 ± 0.4 0.693 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 1.0 0.039 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.55 0.100 Q 0.1 ± 0.1 0.004 ± 0.004 S 2.85 MAX. 0.112 MAX. 59 µPD75104A, 75108A 15. RECOMMENDED SOLDERING CONDITIONS It is recommended that µPD75104A, 75106A, and 75108A be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). For other soldering methods and conditions, please consult NEC. Table 15-1 Soldering Conditions of Surface Mount Type (1) µ PD75108AGC - xxx - AB8: 64-pin plastic QFP ( Soldering Method 14 mm) Soldering Conditions Symbol for Recommended Condition Infrared Reflow Package peak temperature: 230°C, time: 30 seconds max. (210°C min.), number of times: 1 IR30-00-1 VPS Package peak temperature: 215°C, time: 40 seconds max. (200°C min.), number of times: 1 VP15-00-1 Wave Soldering Soldering bath temperature: 260°C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120°C max. (package surface temperature) WS60-00-1 Pin Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per side) (2) µ PD75104AGC - xxx - AB8: 64-pin plastic QFP ( Soldering Method Infrared Reflow — 14 mm) Soldering Conditions Symbol for Recommended Condition Package peak temperature: 230°C, time: 30 seconds max. * (210°C min.), number of times: 1, number of days: 2 days , IR30-162-1 (afterwards, 16 hours of prebaking at 125°C is required.) VPS Package peak temperature: 215°C, time: 40 seconds max. * (200°C min.), number of times: 1, number of days: 2 days , VP15-162-1 (afterwards, 16 hours of prebaking at 125°C is required.) Wave Soldering Soldering bath temperature: 260°C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120°C WS60-162-1 max. (package surface temperature), number of days: * 2 days , (afterwards, 16 hours of prebaking at 125°C is required.) Pin Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per side) — *: This means the number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max. Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235°C, number of times: 2, and an extended number of days) is also available. For details, consult NEC. 60 APPENDIX A. FUNCTIONAL DIFFERENCES AMONG THIS SERIES PRODUCTS Item Program Memory Data Memory µ PD75104 µ PD75106 µ PD75108 µ PD75112 • Mask ROM • Mask ROM • Mask ROM • Mask ROM • Mask ROM • Mask ROM • Mask ROM • 0000H-0FFFH • 0000H-177FH • 0000H-1F7FH • 0000H-2F7FH • 0000H-3F7FH • 0000H-0FFFH • 0000H-1F7FH • 0000H-1F7FH • 0000H-3F7FH • 4096 x 8 bits • 6016 x 8 bits • 8064 x 8 bits • 12160 x 8 bits • 16256 x 8 bits • 4096 x 8 bits • 8064 x 8 bits • 8064 x 8 bits • 16256 x 8 bits Lines µ PD75108A µ PD75P108B µ PD75P116 • One-time PROM • One-time PROM 512 x 4 bits 320 x 4 bits 512 x 4 bits Bank 0: 256 x 4 Bank 0: 256 x 4 Bank 0: 256 x 4 Bank 0: 256 x 4 Bank 1: 64 x 4 Bank 1: 256 x 4 Bank 1: 64 x 4 Bank 1: 256 x 4 Provided with BR !addr instruction except for µ PD75104 and 75104A Total I/O µ PD75104A 320 x 4 bits Instruction Set I/O µ PD75116 58 • CMOS I/O: 32 • CMOS I/O: 32 • CMOS I/O: 32 • +12 V withstand open-drain output: 12 (pull-up resistor as mask option: 24) • +12 V withstand open-drain output • +12 V open-drain output: 12 (pull-up resistor as mask option) LED direct drive: 44 : 12 (pull-up resistor as mask option) LED direct drive: 44 LED direct drive: 44 Input • CMOS input: 10 • CMOS input: 10 • CMOS input: 10 (pull-up resistor as mask option: 4) • Comparator input: 4 • Comparator input: 4 • Comparator input: 4 Power-ON Reset Circuit Provided (mask option) Not provided Power-ON Flag 2.7 to 6.0 V Voltage Range Depends on package. Only µ PD75P116 has VPP pin. Pin Connections Package 5V ± 10% • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20 mm) • 64-pin plastic QFP ( 14 mm) • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20 mm) 61 µPD75104A, 75108A Operating µPD75104A, 75108A APPENDIX B. DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using µPD75108A: Hardware Software IE-75000-R* 1 IE-75001-R In-circuit emulator for 75X series IE-75000-R-EM*2 Emulation board for IE-75000-R and IE-75001-R EP-75108AGC-R EV-9200GC-64 IE Control Program Emulation prove for µPD75104AGC and 75108AGC. It is provided with a 64pin conversion socket, EV-9200GC-64 Host machine RA75X Relocatable Assembler PC-9800 series (MS-DOS IBM PC/AT TM (PC DOS TM TM Ver.3.30 to Ver.5.00A* 3) Ver.3.1) *1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151). 62 µPD75104A, 75108A APPENDIX C. RELATED DOCUMENTS ★ 63 µPD75104A, 75108A [MEMO] 64 µPD75104A, 75108A GENERAL NOTES ON CMOS DEVICES ➀ STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly . ➁ PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY) Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to “Processing of Unused Pins” in the documents of each devices. ➂ STATUS BEFORE INITIALIZATION (ALL MOS DEVICES) The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application. 65 µPD75104A, 75108A [MEMO] No p art of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. 66