DATA SHEET MOS INTEGRATED CIRCUIT µPD75304B,75306B,75308B 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75308B is a 75X Series 4-bit single-chip microcomputer capable of the same data processing as an 8-bit microcomputer. It is a low voltage operation version of the µPD75308 with on-chip LCD controller/driver. Operation at an ultra-low voltage of 2.0 V is possible. An ultra small-sized plastic QFP (12 × 12 mm) is also provided and it is perfect for small-sized set that uses an LCD panel. Functions, etc., are described in detail in the User's Manual. Please be sure to read this manual when carrying out design work. µPD75308 User's Manual: IEM-5016 FEATURES • Ultra-low-voltage operation possible: VDD = 2.0 to 6.0 V • Can be driven by two 1.5 V manganese batteries. • On-chip memory • Program memory (ROM) : 8064 × 8 bit (µ PD75308B) : 6016 × 8 bit (µ PD75306B) : 4096 × 8 bit (µ PD75304B) • Data memory (RAM) : 512 × 4 bit • Instruction execution time adjustment function convenient in high-speed operation and power saving • 0.95 µs, 1.91 µs, 15.3 µs (4.19 MHz operation) • 122 µs (32.768 kHz operation) • Built-in programmable LCD controller/driver • LCD drive voltage: 2.0 V to VDD • An ultra small-sized plastic QFP (12 × 12 mm) is provided. • Suitable for small-sized set, such as a camera. • On-chip PROM products available • On-chip one-time PROM products : µPD75P308, 75P316A • On-chip EPROM products : µPD75P308, 75P316B APPLICATIONS Remote control, integrated camera type VCR, camera, gas meter, etc. Unless there are any particular functional differences, the µPD75308B is described in this document as a representative product. The information in this document is subject to change without notice. Document No. IC-2913C (O. D. No. IC-8082D) Date Published January 1994 P Printed in Japan The mark ★ shows major revised points. © NEC Corporation 1991 µPD75304B,75306B,75308B ORDERING INFORMATION Ordering Code µPD75304BGC-×××-3B9 µPD75304BGF-×××-3B9 µPD75304BGK-×××-BE9 µPD75306BGC-×××-3B9 µPD75306BGF-×××-3B9 µPD75306BGK-×××-BE9 µPD75308BGC-×××-3B9 µPD75308BGF-×××-3B9 µPD75308BGK-×××-BE9 Remarks Package 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin plastic plastic plastic plastic plastic plastic plastic plastic plastic QFP (■ ■ 14 mm) QFP (14 × 20 mm) TQFP(fine pitch)(■ ■ 12 mm) QFP (■ ■ 14 mm) QFP (14 × 20 mm) TQFP(fine pitch)(■ ■ 12 mm)) QFP (■ ■ 14 mm) QFP (14 × 20 mm) TQFP(fine pitch)(■ ■ 12 mm) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard ××× is the ROM code number. Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 µPD75304B,75306B,75308B FUNCTION OUTLINE (1/2) Item Function Number of basic instructions 41 Instruction cycle 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz operation) 122 µs (subsystem clock: 32.768 kHz operation) ROM 8064 × 8 bits (µPD75308B), 6016× 8 bits (µPD75306B), 4096× 8 bits (µPD75304B) RAM 512 × 4 bits On-chip memory General register • 4-bit manipulation: 8 (B, C, D, E, H, L, X, A) • 8-bit manipulation: 4 (BC, DE, HL, XA) Accumulators • Bit accumulator (CY) • 4-bit accumulator (A) • 8-bit accumulator (XA) Instruction set • • • • Various bit manipulation instructions Efficient 4-bit data manipulation instructions 8-bit data transfer instructions GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte 8 CMOS input 16 CMOS input/output 8 CMOS output Used with segment pin 8 N-ch open-drain input/output 10 V withstand voltage, pull-up by mask option possible : 8 Pull-up by software possible : 23 I/O lines 40 LCD controller/driver • Number of segments selection: 24/28/32 segments (4/8 can be switched at bit port output.) • Display mode selection: Static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty • LCD drive division resistor can be incorporated by mask option Supply voltage range VDD = 2.0 to 6.0 V • 8-bit timer/event counter • Clock source: 4 stages • Event count possible Timer 3 channels • 8-bit basic interval timer • Standard clock generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms (4.19 MHz operation) • Watchdog timer application possible 3 µPD75304B,75306B,75308B FUNCTION OUTLINE (2/2) Item Function • Watch timer • 0.5 seconds time interval generation • Count clock source: Main system clock and subsystem clock switchable • Fast watch mode (3.9 ms time interval generation) • Buzzer output possible (2 kHz) Timer 3 channels 8-bit serial interface • Three modes application possible • 3-wire serial I/O mode • 2-wire serial I/O mode • SBI mode • LSB top/MSB top switchable Bit sequential buffer Special bit manipulation memory: 16 bits • Perfect for remote control application Timer/event counter output (PTO0): Arbitrary frequency square wave output Clock output function Clock output (PCL): Φ, 524, 262, 65.5 kHz (4.19 MHz operation) Buzzer output (BUZ): 2 kHz (4.19 MHz or 32.768 kHz operation) 4 Vectored interrupt • External: 3 • Internal: 3 Test input • External: 1 • Internal: 1 System clock oscillator • Main system clock oscillation ceramic/crystal oscillation circuit: 4.194304 MHz • Subsystem clock oscillation crystal oscillation circuit: 32.768 kHz Standby STOP/HALT mode Package • 80-pin plastic QFP (14 × 20 mm) • 80-pin plastic QFP (■ ■ 14 mm) • 80-pin plastic TQFP (fine pitch) (■ ■ 12 mm) µPD75304B,75306B,75308B CONTENTS 1. PIN CONFIGURATION (TOP VIEW)............................................................................................... 6 2. BLOCK DIAGRAM............................................................................................................................ 8 3. PIN FUNCTIONS .............................................................................................................................. 9 3.1 3.2 3.3 PORT PINS .............................................................................................................................................. NON-PORT PINS ..................................................................................................................................... PIN INPUT/OUTPUT CIRCUITS .............................................................................................................. 9 11 13 3.4 3.5 RECOMMENDED CONNECTION OF UNUSED PINS ............................................................................. PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN ........................................................... 15 16 4. MEMORY CONFIGURATION .......................................................................................................... 16 5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 21 5.1 5.2 PORTS ..................................................................................................................................................... CLOCK GENERATOR ............................................................................................................................... 21 22 5.3 5.4 5.5 5.6 CLOCK OUTPUT CIRCUIT ....................................................................................................................... BASIC INTERVAL TIMER ........................................................................................................................ WATCH TIMER ........................................................................................................................................ TIMER/EVENT COUNTER ....................................................................................................................... 23 24 25 26 5.7 5.8 5.9 SERIAL INTERFACE ................................................................................................................................. LCD CONTROLLER/DRIVER .................................................................................................................... BIT SEQUENTIAL BUFFER ...................................................................................................................... 28 30 32 6. INTERRUPT FUNCTION ................................................................................................................. 32 7. STANDBY FUNCTION .................................................................................................................... 34 8. RESET FUNCTION .......................................................................................................................... 35 9. INSTRUCTION SET ......................................................................................................................... 37 10. MASK OPTION SELECTION ............................................................................................................ 45 11. ELECTRICAL SPECIFICATIONS ...................................................................................................... 46 12. PACKAGE INFORMATION .............................................................................................................. 64 13. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 67 APPENDIX A. DIFFERENCES AMONG SERIES PRODUCTS .............................................................. 70 APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 72 APPENDIX C. RELATED DOCUMENTS .............................................................................................. 73 5 µPD75304B,75306B,75308B P61/KR1 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 S6 S5 S4 S3 S2 8079787776 757473 7271 70696867666564636261 S12 S13 S14 S15 S16 1 4 5 60 59 58 57 56 S17 6 7 8 9 55 54 53 52 XT1 VDD P33 P32 51 50 49 48 47 46 45 44 43 P31/SYNC P30/LCDCL P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 19 42 P10/INT0 20 2122232425 262728 2930 31323334353637383940 41 P03/SI/SB1 P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 COM0 S31/BP7 P40 P41 P42 P43 VSS S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 COM3 BIAS VLC0 VLC1 VLC2 S23 S24/BP0 10 11 12 13 14 15 16 17 18 COM1 COM2 S22 2 3 µPD75304BGC-×××-3B9 µPD75304BGK-×××-BE9 µPD75306BGC-×××-3B9 µPD75306BGK-×××-BE9 µPD75308BGC-×××-3B9 µPD75308BGK-×××-BE9 S18 S19 S20 S21 6 S9 S8 S7 S11 S10 1. PIN CONFIGURATION (TOP VIEW) P60/KR0 X2 X1 NC XT2 80797877767574737271706968676665 1 2 3 4 5 6 7 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 COM0 COM1 COM2 COM3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25262728293031323334353637383940 : : : : : : : : : : : : : : : P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 X2 X1 NC XT2 XT1 VDD P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1 VLC0 VLC1 VLC2 P40 P41 P42 P43 VSS P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 BIAS µPD75304BGF-×××-3B9 µPD75306BGF-×××-3B9 µPD75308BGF-×××-3B9 P00 to 03 P10 to 13 P20 to 23 P30 to 33 P40 to 43 P50 to 53 P60 to 63 P70 to 73 BP0 to 7 KR0 to 7 SCK SI SO SB0,1 RESET S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 S11 µPD75304B,75306B,75308B Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Bit Port Key Return Serial Clock Serial Input Serial Output Serial Bus 0, 1 Reset Input S0 to 31 COM0 to 3 VLC0-2 BIAS LCDCL SYNC TI0 PTO0 BUZ PCL INT0, 1, 4 INT2 X1, 2 XT1, 2 NC : : : : : : : : : : : : : : : Segment Output 0 to 31 Common Output 0 to 3 LCD Power Supply 0 to 2 LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0 Programmable Timer Output 0 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 No Connection 7 INTBT PROGRAM COUNTER * SP(8) TIMER/EVENT COUNTER #0 TI0/P13 PTO0/P20 ALU BANK WATCH TIMER INTW SI/SB1/P03 f LCD CLOCKED SERIAL INTERFACE SO/SB0/P02 SCK/P01 PROGRAM MEMORY (ROM) 8064×8BITS : µPD75308B 6016×8BITS : µPD75306B 4096×8BITS : µPD75304B 4 P00-P03 PORT 1 4 P10-P13 PORT 2 4 P20-P23 PORT 3 4 P30-P33 PORT 4 4 P40-P43 PORT 5 4 P50-P53 PORT 6 4 P60-P63 PORT 7 4 P70-P73 CY INTT0 BUZ/P23 PORT 0 GENERAL REG. DECODE AND CONTROL DATA MEMORY (RAM) 512 × 4 BITS INTCSI 24 2. BLOCK DIAGRAM 8 BASIC INTERVAL TIMER S0-S23 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 –KR7/P73 8 N fX / 2 BIT SEQ. BUFFER (16) CLOCK OUTPUT CONTROL PCL/P22 * LCD CONTROLLER /DRIVER 13bits : µPD75306B, 75308B 12bits : µPD75304B CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN XT1 XT2 X1 X2 CPU CLOCK STAND BY CONTROL VDD VSS RESET fLCD 8 S24/BP0 –S31/BP7 4 COM0–COM3 3 VLC0–VLC2 BIAS LCDCL/P30 SYNC/P31 µPD75304B,75306B,75308B INTERRUPT CONTROL µPD75304B,75306B,75308B 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Name Input/Output DualFunction Pin P00 Input INT4 P01 Input/output SCK P02 Input/output SO/SB0 P03 Input/output SI/SB1 INT0 P10 Input P12 INT2 P13 TI0 P20 PTO0 — P21 Input/output P22 PCL P23 BUZ P30 *2 LCDCL P31 *2 SYNC Input/output P32 *2 — P33 *2 — P40 to P43 *2 P50 to P53 *2 1. 8-bit I/O After Reset I/O Circuit Type *1 B 4-bit input port (PORT 0) On-chip pull-up resistor can be specified for P01 to P03 as a 3-bit unit by software. F -A × Input F -B M-C With noise elimination function INT1 P11 * Function Input/output Input/output × Input B -C 4-bit input/output port (PORT 2) On-chip pull-up resistor can be specified as a 4-bit unit by software. × Input E-B Programmable 4-bit input/output port (PORT 3) Input/output can be specified bit-wise. On-chip pull-up resistor can be specified as a 4-bit unit by software. × Input E-B 4-bit input port (PORT 1) On-chip pull-up resistor can be specified as a 4-bit unit by software. — N-ch open-drain 4-bit input/output port (PORT 4) On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: 10 V withstand voltage High level (onchip pull-up resistor) or highimpedance — N-ch open-drain 4-bit input/output port (PORT 5) On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: 10 V withstand voltage High level (onchip pull-up resistor) or highimpedance M M : Schmitt trigger input 2. LED direct drive possible 9 µPD75304B,75306B,75308B 3.1 PORT PINS (2/2) Pin Name Input/Output DualFunction Pin P60 KR0 P61 KR1 Input/output P62 KR2 P63 KR3 P70 KR4 P71 KR5 Input/output P72 KR6 P73 KR7 BP0 S24 BP1 Function 8-bit I/O Programmable 4-bit input/output port (PORT 6) Input/output can be specified bit-wise. On-chip pull-up resistor can be specified as a 4-bit unit by software. 4-bit input/output port (PORT 7) On-chip pull-up resistor can be specified as a 4-bit unit by software. After Reset I/O Circuit Type *1 Input F -A Input F -A *2 G-C S25 Output BP2 S26 BP3 S27 BP4 S28 BP5 1-bit output port (BIT PORT) Also used as segment output pin. × S29 Output * BP6 S30 BP7 S31 1. : Schmitt trigger input 2. BP0 to BP7 select V LC1 as the input source. However, the output level depends on BP0 to BP7 and VLC1 external circuit. Example BP0 to BP7 are connected mutually within the µPD75308B. Therefore, the output level of BP0 to BP7 is determined by the value of R1, R2 and R3. µPD75308B VDD R2 BP0 ON VLC1 R1 BP1 ON 10 R3 µPD75304B,75306B,75308B 3.2 NON-PORT PINS Pin Name Input/Output DualFunction Pin After Reset I/O Circuit Type *1 TI0 Input P13 External event pulse input pin to timer/event counter Input B -C PTO0 Input/output P20 Timer/event counter output pin Input E-B PCL Input/output P22 Clock output pin Input E-B BUZ Input/output P23 Fixed frequency output pin (for buzzer or system clock trimming) Input E-B SCK Input/output P01 Serial clock input/output pin Input F -A SO/SB0 Input/output P02 Serial data output pin Serial bus input/output pin Input F -B SI/SB1 Input/output P03 Serial data input pin Serial bus input/output pin Input M -C INT4 Input P00 Edge detection vectored interrupt input pin (both rising edge and falling edge detection effective) Input B Input B -C Input B -C P10 INT0 Input INT1 * P11 Function Edge detection vectored interrupt input pin (detection edge selectable) Edge detection testable input pin (rising edge detection) Clock synchronous system Asynchronous INT2 Input P12 KR0 to KR3 Input/output P60 to P63 Parallel falling edge detection testable input pin Input F -A KR4 to KR7 Input/output P70 to P73 Parallel falling edge detection testable input pin Input F -A S0 to S23 Output — Segment signal output pin *2 G-A S24 to S31 Output BP0 to BP7 Segment signal output pin *2 G-C COM0 to COM3 Output — Common signal output pin *2 G-B VLC0 to VLC2 — — LCD drive power supply pin On-chip split resistor (mask option) — — BIAS Output — External split resistor cut output pin *3 — LCDCL *4 Input/output P30 External expansion driver drive clock output pin Input E-B SYNC *4 Input/output P31 External expansion driver synchronization clock output pin Input E-B X1, X2 Input — Main system clock oscillation crystal/ceramic connection pin. For external clock, the external clock signal is input to X1 and its opposite phase is input to X2. — — XT1 Input — — — XT2 — — Subsystem clock oscillation crystal connection pin. For external clock, the external clock signal is input to XT1 and XT2 is opened. XT1 can be used as a 1-bit input (test) pin. RESET Input — System reset input pin — B NC *5 — — NO CONNECTION — — VDD — — Positive power supply pin — — VSS — — GND potential pin — — 1. Asynchronous : Schmitt trigger input 2. Display outputs are selected with VLCX shown below as the input source. S0 to S31: VLC1, COM0 to COM2: V LC2, COM3: VLC0 However, the level of each display output depends on the display output and VLCX external circuit. 11 µPD75304B,75306B,75308B * 3. On-chip split resistor ........ Low level No on-chip split resistor ... High-impedance 4. Pins provided for system expansion. Currently, only used as P30 and P31. 5. If a printed wiring board is shared with the µPD75P316A/75P316B, the NC pin should be connected to VDD. 12 µPD75304B,75306B,75308B 3.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the µPD75308B are shown by in abbreviated form. TYPE D (For TYPE E-B, F-A) TYPE A (For TYPE E-B) VDD VDD data P-ch OUT P-ch IN output disable N-ch N-ch Push-pull output that can be made high-impedance output CMOS Standard Input Buffer TYPE B (P-ch and N-ch OFF) TYPE E-B VDD P.U.R. P.U.R. enable P-ch data IN IN/OUT Type D output disable Type A P.U.R.:Pull-Up Resistor Schmitt-Trigger Input with Hysteresis Characteristic TYPE B-C TYPE F-A VDD P.U.R. VDD P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch data IN/OUT Type D output disable IN Type B P.U.R. : Pull-Up Resistor P.U.R.:Pull-Up Resistor 13 µPD75304B,75306B,75308B TYPE F-B TYPE G-C VDD P.U.R. P.U.R. enable VDD P-ch P-ch VDD output disable (P) VLC0 P-ch VLC1 IN/OUT P-ch data output disable SEG data/Bit Port data N-ch output disable (N) OUT N-ch VLC2 N-ch P.U.R.:Pull-Up Resistor TYPE G-A TYPE M VDD P.U.R. enable (Mask Option) IN/OUT VLC0 P-ch data VLC1 N-ch P-ch SEG data output disable OUT N-ch VLC2 N-ch Middle-High Voltage Input Buffer (+10 V Withstand Voltage) P.U.R.:Pull-Up Resistor TYPE G-B TYPE M-C VDD VLC0 P-ch P.U.R. VLC1 P.U.R. enable P-ch N-ch IN/OUT OUT COM data N-ch P-ch P-ch data N-ch output disable VLC2 N-ch P.U.R.:Pull-Up Resistor 14 µPD75304B,75306B,75308B 3.4 ★ RECPMMENDED CONNECTION OF UNUSED PINS Table 3-1 Connection of Unused Pins Pin P00/INT4 Recommended Connection Connect to VSS P01/SCK P02/SO/SB0 Connect to VSS or VDD P03/SI/SB1 P10/INT0-P12/INT2 Connect to VSS P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30/LCDCL P31/SYNC Input state : Outputstate : Connect to VSS or V DD Leave open P32 P33 P40 to P43 P50 to P53 P60/KR0 to P63/KR3 P70/KR4 to P73/KR7 S0 to S23 S24/BP0 to S31/BP7 Leave open COM0 to COM3 VLC0 to VLC2 BIAS Connect to VSS Connect to VSS only when VLC0 to VLC2 are all unused; otherwise leave open XT1 Connect to VSS or VDD XT2 Leave open 15 µPD75304B,75306B,75308B ★ 3.5 PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN In addition to the functions shown in 3.1 and 3.2, the P00/INT4 pin and RESET pin are also used to set the test mode for testing internal µPD75308B operation (for IC testing). The test mode is set when a voltage greater than VDD is applied to either of these pins. Consequently, if noise exceeding VDD is applied during normal operation, the test mode may be entered, making it impossible for normal operation to continue. For example, misoperation may result if inter-wiring noise is applied to the P00/INT4 or RESET pin due to the length of the wiring from these pins, and the pin voltage exceeds VDD. Wiring should therefore be carried out so that inter-wiring noise is suppressed as far as possible. If it is completely impossible to suppress noise, noise prevention measures should be taken using an external component as shown below. o Diode connected between P00/INT4 or RESET and VDD o Capacitor connected between P00/INT4 or RESET and VDD VDD VDD Diode with VDD VDD Small VF P00/INT4, RESET P00/INT4, RESET 4. MEMORY CONFIGURATION • Program memory (ROM) ... 8064 × 8 bits (0000H to 1F7FH): µPD75308B 6016 × 8 bits (0000H to 177FH): µPD75306B 4096 × 8 bits (0000H to 0FFFH): µPD75304B • 0000H to 0001H: Vector table in which the program start address after a reset is written. • 0002H to 000BH: Vector table in which program start addresses in case of interrupts are written. • 0020H to 007FH: Table area referenced by the GETI instruction. • Data memory • Data area ... 512 × 4 bits (000H to 1FFH) • Peripheral hardware area ... 128 × 4 bits (F80H to FFFH) 16 µPD75304B,75306B,75308B Fig. 4-1 Program Memory Map (a) µPD75308B Address 7 0000H 6 5 0 MBE 0 0 Internal Reset Start Address (High-Order 5 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE 0 0 INTBT/INT4 Start Address (High-Order 5 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE 0 0 INT0 Start Address (High-Order 5 Bits) CALLF ! faddr Instruction Entry Address INT0 Start Address (Low-Order 8 Bits) 0006H MBE 0 0 INT1 Start Address (High-Order 5 Bits) INT1 Start Address (Low-Order 8 Bits) 0008H MBE 0 0 INTCSI Start Address (High-Order 5 Bits) BR !addr Instruction Branch Address INTCSI Start Address (Low-Order 8 Bits) 000AH MBE 0 0 BRCB ! caddr Instruction Branch Address INTT0 Start Address (High-Order 5 Bits) INTT0 Start Address (Low-Order 8 Bits) ≈ CALL !addr Instruction Subroutine Entry Address BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) ≈ 0020H GETI Instruction Reference Table 007FH 0080H ≈ ≈ ≈ ≈ Branch Destination Address and Subroutine Entry Address by GETI Instruction 07FFH 0800H 0FFFH 1000H ≈ ≈ BRCB ! caddr Instruction Branch Address 1F7FH 17 µPD75304B,75306B,75308B (b) µPD75306B Address 7 0000H 6 5 0 MBE 0 0 Internal Reset Start Address (High-Order 5 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE 0 0 INTBT/INT4 Start Address (High-Order 5 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE 0 0 INT0 Start Address (High-Order 5 Bits) CALLF ! faddr Instruction Entry Address INT0 Start Address (Low-Order 8 Bits) 0006H MBE 0 0 INT1 Start Address (High-Order 5 Bits) INT1 Start Address (Low-Order 8 Bits) 0008H MBE 0 0 INTCSI Start Address (High-Order 5 Bits) BR !addr Instruction Branch Address INTCSI Start Address (Low-Order 8 Bits) 000AH MBE 0 0 BRCB ! caddr Instruction Branch Address INTT0 Start Address (High-Order 5 Bits) INTT0 Start Address (Low-Order 8 Bits) ≈ CALL !addr Instruction Subroutine Entry Address BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) ≈ 0020H GETI Instruction Reference Table 007FH 0080H ≈ ≈ ≈ ≈ Branch Destination Address and Subroutine Entry Address by GETI Instruction 07FFH 0800H 0FFFH 1000H ≈ 177FH 18 ≈ BRCB ! caddr Instruction Branch Address µPD75304B,75306B,75308B (c) µPD75304B Address 7 0000H 6 5 0 MBE 0 0 Internal Reset Start Address (High-Order 4 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE 0 0 INTBT/INT4 Start Address (High-Order 4 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE 0 0 INT0 Start Address (High-Order 4 Bits) CALLF ! faddr Instruction Entry Address INT0 Start Address (Low-Order 8 Bits) 0006H MBE 0 0 INT1 Start Address (High-Order 4 Bits) INT1 Start Address (Low-Order 8 Bits) 0008H MBE 0 0 INTCSI Start Address (High-Order 4 Bits) BR !caddr Instruction Branch Address INTCSI Start Address (Low-Order 8 Bits) 000AH MBE 0 0 CALL !addr Instruction Subroutine Entry Address INTT0 Start Address (High-Order 4 Bits) INTT0 Start Address (Low-Order 8 Bits) ≈ ≈ BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) 0020H GETI Instruction Reference Table 007FH 0080H ≈ ≈ ≈ ≈ 07FFH Branch Destination Address and Subroutine Entry Address by GETI Instruction 0800H 0FFFH 19 µPD75304B,75306B,75308B Fig. 4-2 Data Memory Map Data Memory General Register Area Memory Bank 000H (8 × 4) 007H 008H 0 Stack Area 256 × 4 (248 × 4) 0FFH Data Area Static RAM (512 × 4) 100H 256 × 4 (224 × 4) 1 1DFH 1E0H (32 × 4) Display Data Memory Area 1FFH Not On-Chip F80H 128 × 4 Peripheral Hardware Area FFFH 20 15 µPD75304B,75306B,75308B 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS There are four kinds of I/O ports, as follows. • • • • CMOS input (PORT0, 1) CMOS input/output (PORT2, 3, 6, 7) : 8 : 16 N-ch open drain (PORT4, 5) CMOS output (BP0 to BP7) : 8 : 8 Total 40 Fig. 5-1 Port Functions Port (Symbol) Function PORT 0 4-bit input Operation/Features Always readable or testable irrespective of dual-function pin operating mode. Remarks Dual function as INT4, SCK, SO/ SB0 & SI/SB1 pins Dual function as pins INT0 to INT2 & TI0 PORT 1 PORT 2 Can be set to input or output mode as 4-bit unit. Ports 6 & 7 can be paired for 8-bit data input/output. PORT 7 Dual function as PTO0, PCL & BUZ pins Dual function as pins KR4 to KR7 4-bit input/output Dual function as LCDCL & SYNC pins PORT 3 * Can be set to input or output mode bit-wise. Dual function as pins KR0 to KR3 PORT 6 PORT 4 * PORT 5 * BP0 to BP7 * 4-bit input/output (N-ch open-drain 10 V withstand voltage) 1-bit output Can be set to input or output mode as 4-bit unit. Ports 4 & 5 can be paired for 8-bit data input/output. Incorporation of pull-up resistor can be specified bit-wise by mask option. Outputs data bit-wise. Switchable by software with LCD drive segment outputs S24 to S31. Small drive capability. For CMOS load drive. Direct LED drive capability 21 µPD75304B,75306B,75308B 5.2 CLOCK GENERATOR The operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). There are two kinds of clock, the main system clock and subsystem clock, and the instruction execution time can be changed. • 0.95 µs/1.91 µs/15.3 µs (4.19 MHz main system clock operation) • 122 µs (32.768 kHz subsystem clock operation) Fig. 5-1 Clock Generator Block Diagram • Basic Interval Timer (BT) • Timer/Event Counter • Serial Interface • Watch Timer • LCD Controller/Driver • INT0 Noise Elimination Circuit • Clock Output Circuit XT1 VDD XT2 Subsystem Clock Oscillation Circuit fXT Main System Clock Oscillation Circuit fX LCD Controller/ Driver Watch Timer X1 VDD X2 1/8 to 1/4096 Frequency Divider Oscillation Stop Selector WM. 3 SCC Selector 1/2 1/16 SCC3 Internal Bus SCC0 Frequency Divider 1/4 Φ • CPU • INT0 Noise Elimination Circuit • Clock Output Circuit PCC PCC0 PCC1 4 HALT F/F HALT * PCC2 S PCC3 STOP * R PCC2, PCC3 Clear STOP F/F Q Q Wait Release Signal from BT S RESET Signal R Remarks ★ 22 Standby Release Signal from Interrupt Control Circuit 1. 2. 3. 4. fX = Main system clock frequency fXT = Subsystem clock frequency PCC: Processor clock control register SCC: System clock control register 5. 6. * indicates instruction execution. One Φ clock cycle (t CY) is one machine cycle. See "AC CHARACTERISTICS" in 11. "ELECTRICAL SPECIFICATIONS" for details of tCY. µPD75304B,75306B,75308B 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit is a circuit which outputs a clock pulse from P22/PCL pin and is used to supply clock pulses to remote control outputs or peripheral LSI’s. • Clock output (PCL) : Φ 524, 262, 65.5 kHz (at 4.19 MHz operation) • Buzzer output (BUZ): 2 kHz (at 4.19 MHz or 32.768 kHz operation) The configuration of the clock output circuit is shown below. Fig. 5-2 Clock Output Circuit Configuration From Clock Generator Φ fX/2 3 Output Buffer Selector fX/2 fX/2 4 PCL/P22 6 PORT2.2 CLOM3 0 CLOM1CLOM0 CLOM P22 Output Latch Bit 2 of PMGB Bit Specified In Port 2 Input/Output Mode 4 Internal Bus Remarks Consideration is given so that a low amplitude pulse is not output when switching between clock output enable and disable. 23 µPD75304B,75306B,75308B 5.4 BASIC INTERVAL TIMER The basic interval timer includes the following functions. • • • • It operates as an interval timer which generates reference time interrupts. It can be applied as a watchdog timer which detects when a program is out of control. Selects and counts wait times when the standby mode is released. It reads count contents. Fig. 5-3 Basic Interval Timer Configuration From Clock Generator fX/2 fX/2 Clear 5 7 fX/2 Set Basic Interval Timer (8-Bit Frequency Divider) MPX fX/2 Clear 9 BT 12 3 BTM3 *SET1 BTM2 BTM1 Wait Release Signal During Standby Release BTM0 BTM 8 4 Internal Bus Remarks 24 * indicates instruction execution. BT Interrupt Request Flag IRQBT Vectored Interrupt Request Signal µPD75304B,75306B,75308B 5.5 WATCH TIMER The µPD75308B incorporates a single watch timer channel. The watch timer has the following functions. • Sets test flags (IRQW) at 0.5 second intervals. The standby mode can be released with IRQW. • 0.5 sec. time intervals can be created in either the main system clock or the subsystem clock. • In the fast watch mode, time intervals which are 128 times normal (3.91 ms) can be set, making this function convenient for program debugging and testing. • A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin for use in generating buzzer sounds and trimming system clock oscillation frequencies. • The frequency divider can be cleared, so this clock can be started at 0 second. Fig. 5-4 Watch Timer Block Diagram fW 6 2 (512 Hz : 1.95 ms) fLCD fW (256 Hz : 3.91 ms) 7 2 From Clock Generator fW 128 (32.768 kHz) Selector fW 14 2 fW Frequency Divider (32.768 kHz) fXT (32.768 kHz) INTW IRQW Set Signal Selector 2Hz 0.5 sec fW 16 (2.048 kHz) Clear Output Buffer P23/BUZ WM WM7 PORT2.3 0 0 0 WM3 WM2 WM1 WM0 8 P23 Output Latch Bit 2 of PMGB Port 2 Input/Output Mode Bit Test Instruction Internal Bus Remarks Values in parentheses are when fX = 4.194304 MHz and fXT = 32.768 kHz. 25 µPD75304B,75306B,75308B 5.6 TIMER/EVENT COUNTER The µPD75308B incorporates a single timer/event counter channel. The timer/event counter has the following functions. • • • • • • 26 Operates as a programmable interval timer. Outputs square waves in the desired frequency to the PTO0 pin. Operates as an event counter. Divides the TI0 pin input into N divisions and outputs it to the PTO0 pin (frequency divider operation). Supplies a serial shift clock to the serial interface circuit. Count status read function. Fig. 5-5 Timer/Event Counter Block Diagram Internal Bus SET1 8 *1 8 8 TM0 TMOD0 Modulo Register (8) TM06 TM05 TM04 TM03 TM02 8 PORT1.3 Input Buffer To Serial Interface TOUT F/F 8 Reset P13/TI0 T0 Count Register (8) MPX PORT2.0 Bit 2 of PGMB Port 2 P20 Input/ Output Output Latch Mode Match Comparator (8) *2 From Clock Generator TOE0 TO Enable Flag CP P20/PTO0 Output Buffer INTT0 IRQT0 Set Signal Clear RESET IRQT0 Clear Signal * 1 SET1: Instruction execution 2 For detail, see Fig. 5-1. 27 µPD75304B,75306B,75308B Timer Operation Start µPD75304B,75306B,75308B 5.7 SERIAL INTERFACE The µPD75308B incorporates a clocked 8-bit serial interface. The serial interface has the following three modes. • 3-wire serial I/O mode • 2-wire serial I/O mode • SBI mode (serial bus interface mode) 28 Fig. 5-6 Serial Interface Block Diagram Internal Bus 8/4 Bit Test CSIM 8 8 Bit Manipulation Slave Address Register (SVA) Addres Comparator (8) (8) RELT CMDT SO SET CLR Latch D Q ACKT ACKE BSYE Shift Register (SIO) SBIC Match Signal (8) P03/SI/SB1 Selector Bit Test 8 Selector P02/SO/SB0 Busy/ Acknowledge Output Circuit Bus Release/ Command/ Acknowledge Detection Circuit P01/SCK P01 Output Latch INTCSI INTCSI Control Circuit IRQCSI Set Signal 3 Serial Clock Control Circuit Serial Clock Slector fX/24 fX/2 6 fX/2 TOUT F/F (From Timer/ Event Counter) External SCK 29 µPD75304B,75306B,75308B Serial Clock Counter RELD CMDD ACKD µPD75304B,75306B,75308B 5.8 LCD CONTROLLER/DRIVER The µPD75308B has an on-chip display controller which generates segment signals and common signals in accordance with data in display data memory as well as a segment driver and common driver capable of directly driving the LCD panel. The configuration of the LCD controller/driver is shown in Fig. 5-7 The functions of the on-chip LCD controller/driver of the µPD75308B are as follows. • Display data memory are read automatically through DMA operations and segment signals and common signals are generated. • 5 different display modes can be selected. ➀ Static ➁ 1/2 duty (1/2 bias) ➂ 1/3 duty (1/2 bias) 4 1/3 duty (1/3 bias) ➄ 1/4 duty (1/3 bias) • In each of the display modes, 4 types of frame frequency can be selected. • The segment signal output is a maximum of 32 segments (S0 to S31) and 4 common outputs (COM0 to COM3). • Segment signal outputs (S24 to S27, S28 to S31) are in 4-segment units and they can be switched for use as output ports (BP0 to BP3, BP4 to BP7). • Split resistors can be built-in for the LCD driver power supply (mask option). • Conformity to various bias methods and LCD driver voltages is possible. • When the display is OFF, the current flowing to the split resistors is cut. • Display data memory not used for the display can be used as ordinary data memory. • Operation by the subsystem clock is also possible. . 30 Fig. 5-7 LCD Controller/Driver Block Diagram 4 Display Data Memory 1FFH 1FEH 1E9H 1E0H 1E8H 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8 4 4 8 Display Mode Register Display Control Register Port 3 Output Latch 1 0 Port Mode Register Group A 1 0 Timing Controller fLCD Multiplexer Common Driver Segment Driver S31/PB7 S30/PB6 S24/PB0 S23 S0 LCD Driver Voltage Control COM3 COM2COM1COM0 V LC2 VLC1 VLC0 P31/ P30/ SYNC LCDCL 31 µPD75304B,75306B,75308B Selector µPD75304B,75306B,75308B 5.9 BIT SEQUENTIAL BUFFER ..... 16 BITS The bit sequential buffer is special data memory for bit manipulations and can be used easily particularly for bit manipulations where addresses and bit specifications are changed sequentially, so it is convenient for processing data with long bit lengths bit-wise. Fig. 5-8 Bit Sequential Buffer Format Address Bit FC3H 3 Symbol 2 1 FC2H 0 3 2 BSB3 L Register L = F 1 FC1H 0 3 2 BSB2 L=CL=B 1 0 FC0H 3 2 1 BSB1 L=8L=7 0 BSB0 L=4 L=3 L=0 DECS L INCS L Remarks In pmem.@L addressing, the specified bit corresponding to the L register is moved. 6. INTERRUPT FUNCTION The µPD75218has 8 interrupt sources, and prioritized multiple interrupts are possible. There are also two test sources, of which INT2 is an edge-detected testable input. The µPD75218 interrupt control circuit has the following functions • Hardware control vectored interrupt function that can control interrupt acceptance by interrupt flag • • • • 32 (IE×××) and interrupt master enable flag (IME). Arbitrary setting of interrupt start address. Multiple interrupt function with priority specifiable by the interrupt priority selection register (IPS). Interrupt request flag (IRQ×××) test function (interrupt generation confirmation by software possible). Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible). Fig. 6-1 Interrupt Control Circuit Block Diagram Internal Bus 2 1 3 IM2 IM1 IM0 Interrupt Enable Flag (IE XXX ) INT1 /P11 Both Edges Detection Circuit * Edge Detection Circuit IRQ1 IRQCSI INTT0 IRQT0 INTW IRQW KR0/P60 Falling Edge Detection Circuit Priority Control Circuit Vector Table Address Generator IRQ2 Standby Release Signal IM2 * Noise elimination circuit 33 µPD75304B,75306B,75308B INTCSI Rising Edge Detection Circuit VRQn IRQ4 IRQ0 Edge Detection Circuit INT2 /P12 KR7/P73 IRQBT Selector INT0 /P10 IST0 Decoder INT BT INT4 /P00 IME µPD75304B,75306B,75308B 7. STANDBY FUNCTION To reduce the power consumption during program wait, the µPD75308B has two standby modes: STOP mode and HALT mode. Table 7-1 Operation Status at Standby Mode STOP Mode STOP instruction HALT instruction System clock at setting Only main system clock settable Main system clock or subsystem clock settable Clock oscillator Only main system clock oscillation stopped Only CPU clock Φ stopped (oscillation continued) Basic interval timer Stopped Operating (IRQBT set at reference time intervals)* Serial interface Operable only when external SCK input selected as serial clock Operable* Timer/event counter Operable only when TI0 pin input specified as count clock Operable* Operation Status Setting instruction Operable only when fXT selected as Watch timer 34 count clock LCD controller Operable only when fXT selected as LCDCL External interrupt INT1, 2, 4: Operable Only INT0 inoperable CPU Stopped Release signal * HALT Mode Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input In-operable only with main system clock oscillation stopped. Operable Operable Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input µPD75304B,75306B,75308B 8. RESET FUNCTION The µPD75308B is reset and the hardware is initialized as shown in Table 8-1 by RESET input. The reset operation timing is shown in Fig. 8-1. Fig. 8-1 Reset Operation by RESET Input Wait (31.3 ms/4.19 MHz) RESET Input Operating Mode or Standby Mode HALT Mode Operating Mode Internal Reset Operation Table 8-1 Status of Each Hardware after Resetting (1/2) Hardware Program counter (PC) Carry flag (CY) PSW Low-order 5(4)*1 bits of program memory address 0000H are set in PC12(11)*1 to 8 and the contents of address 0001H are set in PC7 to 0. RESET Input during Operation Low-order 5(4)*1 bits of program memory address 0000H are set in PC12(11)*1 to 8 and the contents of address 0001H are set in PC7 to 0. Held Undefined Skip flag (SK0 to 2) 0 0 Interrupt status flag (IST0) 0 0 Bank enable flag (MBE) Bit 7 of program memory address 0000H is set in MBE. Bit 7 of program memory address 0000H is set in MBE. Undefined Undefined Data memory (RAM) Held*2 Undefined General register (X, A, H, L, D, E, B, C) Held Undefined 0 0 Stack pointer (SP) Bank selection register (MBS) * RESET Input in Standby Mode 1. Figures in parentheses apply to the µPD75304B. 2. Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input. 35 µPD75304B,75306B,75308B Table 8-1 Status of Each Hardware after Resetting (2/2) RESET Input in Standby Mode RESET Input during Operation Undefined Undefined Mode register (BTM) 0 0 Counter (To) 0 0 FFH FFH 0 0 0,0 0,0 0 0 Held Undefined Operating mode register (CSIM) 0 0 SBI control register (SBIC) 0 0 Held Undefined Processor clock control register (PCC) 0 0 System clock control register (SCC) 0 0 Clock output mode register (CLOM) 0 0 Display mode register (LCDM) 0 0 Display control register (LCDC) 0 0 Interrupt request flag (IRQ×××) Reset (0) Reset (0) Interrupt enable flag (IE×××) 0 0 Interrupt master enable flag (IME) 0 0 0, 0, 0 0, 0, 0 Output buffer OFF OFF Output latch Clear (0) Clear (0) I/O mode register (PMGA, B) 0 0 Pull-up resistor specification register (POGA) 0 0 Held Undefined Hardware Counter (BT) Basic interval timer Timer/event counter Modulo register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Watch timer Mode register (WM) Shift register (SIO) Serial interface Slave address register (SVA) Clock generator, clock output circuit LCD controller Interrupt function INT0, 1, 2 mode registers (IM0, 1, 2) Digital port Bit sequential buffer (BSB0 to 3) 36 µPD75304B,75306B,75308B 9. INSTRUCTION SET (1) Operand identifier and description The operand is described in the operand field of each instruction in accordance with the description for the operand identifier of the instruction. (See the RA75X Assembler Package User's Manual Language Volume (EEU-730) for details.) When there are multiple elements in the description, one of the elements is selected. Upper case letters and symbols (+,–) are keywords and are described unchanged. For immediate data, a suitable value or label is described. Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (See the µ PD75308 User’s Manual (IEM-5016) for details). However, there are restrictions on the labels for which fmem and pmem can be used (see the table on the previous page). Identifier * Description reg regl X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rpl XA, BC, DE, HL BC, DE, HL rp2 BC, DE rpa rpal HL, DE, DL DE, DL n4 4-bit immediate data or label n8 8-bit immediate data or label mem* bit 8-bit immediate data or label 2-bit immediate data or label fmem FB0H to FBFH, FF0H to FFFH immediate data or label pmem FC0H to FFFH immediate data or label µPD75304B 0000H to 0FFFH immediate data or lebel addr µPD75306B 0000H to 177FH immediate data or lebel µPD75308B 0000H to 1F7FH immediate data or lebel caddr faddr 12-bit immediate data or label 11-bit immediate data or label taddr 20H to 7FH immediate data (however, bit0 = 0) or label PORTn IE××× MBn PORT 0 to PORT 7 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW MB0, MB1, MB15 Only an even address can be written for mem in the case of 8-bit data processing. 37 µPD75304B,75306B,75308B (2) Operation description legend A : A register; 4-bit accumulator B : B register; 38 C D E H : : : : C register; D register; E register; H register; L X XA BC : : : : L register; X register; 4-bit accumulator Register pair (XA); 8-bit accumulator Register pair (BC) DE HL PC SP : : : : Register pair (DE) Register pair (HL) Program counter Stack pointer CY PSW MBE PORTn : : : : Carry flag; bit accumulator Program status word Memory bank enable flag Portn (n = 0 to 7) IME IE××× MBS PCC : : : : Interrupt master enable flag Interrupt enable flag Memory bank selection register Processor clock control register • (××) ××H : Address, bit delimiter : Contents addressed by ×× : Hexadecimal data µPD75304B,75306B,75308B (3) Description of addressing area field symbols *1 MB = MBE • MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 *7 µPD75304B addr=0000H to 0FFFH µPD75306B addr=0000H to 177FH µPD75308B addr=0000H to 1F7FH addr = (Current PC) –15 to (Current PC) –1 (Current PC) + 2 to (Current PC) + 16 µPD75304B *8 Data memory addressing caddr= 0000H to 0FFFH µPD75306B caddr= 0000H to 0FFFH (PC12=0) or µPD75308B caddr=0000H to 0FFFH (PC12=0) or 1000H to 177FH (PC12=1) *9 faddr = 0000H to 07FFH *10 taddr = 0020H to 007FH Remarks Program memory addressing 1000H to 1F7FH (PC12=1) 1. MB indicates the accessible memory bank. 2. For *2, MB = 0 without regard to MBE and MBS. 3. For *4 and *5, MB = 15 without regard to MBE and MBS. 4. *6 to *10 indicate the addressable area. (4) Explanation of machine cycle field S shows the number of machine cycles required when skip is performed by an instruction with skip. The value of S changes as follows: • No skip ....................................................................................................................................................................... S = 0 • When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1 • When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instruction) ............................. S = 2 Note One machine cycle is required to skip a GETI instruction. One machine cycle is equivalent to one cycle (=tCY) of the CPU clock Φ. Three times can be selected by PCC setting. 39 µPD75304B,75306B,75308B Note Mnemonic Transfer MOV XCH Addressing Area Bytes Machine Cycles A, #n4 1 1 A ← n4 regl, #n4 2 2 regl ← n4 XA, #n8 2 2 XA ← n8 Stack A HL, #n8 2 2 HL ← n8 Stack B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @rpal 1 1 A ← (rpal) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp 2 2 XA ← rp regl, A 2 2 regl ← A rpl, XA 2 2 rpl ← XA A, @HL 1 1 A ↔ (HL) *1 A, @rpal 1 1 A ↔ (rpal) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A,regl 1 1 A ↔ regl XA, rp 2 2 XA ↔ rp Operand Operation Skip Condition Stack A Operation Table reference ● µPD75304B XA ← (PC11–8 + DE)ROM Note 40 XA, @PCDE 1 3 MOVT ● µPD75306B, 75308B XA ← (PC12–8 + DE)ROM ● µPD75304B XA ← (PC11–8 + XA)ROM XA, @PCXA 1 3 A, #n4 1 1+S A ← A + n4 A, @HL 1 1+S A ← A + (HL) *1 ADDC A, @HL 1 1 A, CY ← A + (HL) + CY *1 SUBS A, @HL 1 1+S A ← A – (HL) *1 SUBC A, @HL 1 1 A, CY ← A – (HL) – CY *1 ADDS Instruction Group ● µPD75306B, 75308B XA ← (PC12–8 + XA)ROM carry carry borrow µPD75304B,75306B,75308B Note Mne1 monic Bytes Machine Cycles A, #n4 2 2 A ← A ∧ n4 A, @HL 1 1 A ← A ∧ (HL) A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← A n NOT A 2 2 A←A reg 1 1+S reg ← reg + 1 @HL 2 2+S (HL) ← (HL) + 1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem) + 1 *3 (mem) = 0 reg 1 1+S reg ← reg – 1 reg = FH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) Skip if A = reg Operation AND Operand OR Note 3 Note 2 XOR INCS Note 4 Comparison DECS SKE Memory bit manipulation Addressing Area Skip Condition *1 *1 *1 reg = 0 A = reg A, reg 2 2+S SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 CY ← CY mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem.@L 2 2 (pmem7–2 + L3–2.bit (L1–0)) ← 1 *5 @H + mem.bit 2 2 (H + mem3–0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem7–2 + L3–2.bit (L1–0)) ← 0 *5 @H + mem.bit 2 2 (H + mem3–0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2 + L3–2.bit (L1–0)) = 1 *5 (pmem.@L) = 1 @H + mem.bit 2 2+S Skip if (H + mem3–0.bit) = 1 *1 (@H + mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7–2 + L3–2.bit (L1–0)) = 0 *5 (pmem.@L) = 0 @H + mem.bit 2 2+S Skip if (H + mem3–0.bit) = 0 *1 (@H + mem.bit) = 0 SET1 CLR1 SKT SKF Note Operation CY = 1 Skip if CY = 1 1. Instruction Group 2. Accumulator operation 3. Increment and decrement 4. Carry flag operation 41 µPD75304B,75306B,75308B Note Mnemonic Bytes Machine Cycles 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 2 2+S Skip if (pmem7–2 + L3–2.bit (L1–0)) = 1 and clear *5 (pmem.@L) = 1 @H + mem.bit 2 2+S Skip if (H + mem3–0.bit) = 1 and clear *1 (@H + mem.bit) = 1 CY, fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∧ (pmem7–2 + L 3–2.bit (L1–0)) *5 CY, @H + mem.bit 2 2 CY ← CY ∧ (H + mem3-0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2 + L 3–2.bit (L1–0)) *5 CY, @H + mem.bit 2 2 CY ← CY ∨ (H + mem3-0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2 + L 3–2.bit (L1–0)) *5 CY, @H + mem.bit 2 2 CY ← CY ∨ (H + mem3-0.bit) *1 Operand fmem.bit Memory bit manipulation SKTCLR pmem.@L AND1 OR1 XOR1 Operation Addressing Area ● µPD75304B PC11–0 ← addr (The assembler selects the optimum instruction from among the BRCB !caddr, and BR $addr instructions.) addr — — Branch BR !addr $addr Subroutine stack control BRCB Note 42 CALL !caddr !addr Instruction Group 3 3 ● µPD75306B, 75308B PC12–0 ← addr (The assembler selects the optimum instruction from among the BR !addr, BRCB !caddr, and BR $addr instructions.) ● µPD75306B, 75308B PC12–0 ← addr *6 *6 ● µPD75304B PC11–0 ← addr 1 2 ● µPD75306B, 75308B PC12–0 ← addr *7 ● µPD75304B PC11–0 ← caddr11–0 2 2 ● µPD75306B, 75308B PC12–0 ← PC 12 + caddr11–0 *8 ● µPD75304B (SP – 4) (SP – 1) (SP – 2) ← PC11–0 (SP – 3) ← MBE, 0, 0, 0 PC11–0 ← addr, SP ← SP – 4 3 3 ● µPD75306B, 75308B (SP – 4) (SP – 1) (SP – 2) ← PC11–0 (SP – 3) ← MBE, 0, 0, PC12 PC12–0 ← addr, SP ← SP – 4 *6 Skip Condition µPD75304B,75306B,75308B Note Mnemonic 1 Operand Bytes Machine Cycles Operation Addressing Area Skip Condition ● µPD75304B (SP – 4) (SP – 1) (SP – 2) ← PC11–0 (SP – 3) ← MBE, 0, 0, 0 PC11–0 ← 0, faddr, SP ← SP – 4 CALLF !faddr 2 2 ● µPD75306B, 75308B (SP – 4) (SP – 1) (SP – 2) ← PC11–0 (SP – 3) ← MBE, 0, 0, PC12 PC12–0 ← 00, faddr, SP ← SP – 4 *9 ● µPD75304B MBE, ×, ×, × ← (SP + 1) PC11–0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 Subroutine stack control RET 1 RETS PUSH POP Note 2 ● µPD75306B, 75308B MBE, ×, ×, PC12 ← (SP + 1) PC11–0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 ● µPD75304B MBE, ×, ×, × ← (SP + 1) PC11–0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 the skip unconditionally 1 EI DI 3+S ● µPD75306B, 75308B MBE, ×, ×, PC12 ← (SP + 1) PC11–0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 the skip unconditionally Unconditional ● µPD75304B MBE, ×, ×, × ← (SP + 1) PC11–0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 RETI Note 3 1 3 ● µPD75306B, 75308B MBE, ×, ×, PC12 ← (SP + 1) PC11–0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 rp 1 1 (SP – 1) (SP – 2) ← rp, SP ← SP – 2 BS 2 2 (SP – 1) ← MBS, (SP – 2) ← 0, SP ← SP – 2 rp 1 1 rp ← (SP + 1) (SP), SP ← SP + 2 BS 2 2 MBS ← (SP + 1), SP ← SP + 2 2 2 IME ← 1 2 2 IE × × × ← 1 2 2 IME ← 0 2 2 IE × × × ← 0 IE × × × IE × × × 1. Instruction Group 2. Interrupt control 43 µPD75304B,75306B,75308B Bytes Machine Cycles A, PORTn 2 2 A ← PORTn (n = 0–7) XA, PORTn 2 2 XA ← PORTn+1, PORTn (n = 4, 6) PORTn, A 2 2 PORTn ← A (n = 2–7) PORTn, XA 2 2 PORTn+1, PORTn ← XA (n =4, 6) HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation 2 2 MBS ← n (n = 0, 1, 15) Note 2 Input/output Note Mne1 monic Operand IN* OUT* SEL MBn Addressing Area Operation Special ● µPD75304B • TBR Instruction PC11-0 ← (taddr) 3–0 + (taddr + 1) ----------------------------------------------------------------• TCALL Instruction (SP – 4) (SP – 1) (SP – 2) ← PC11–0 (SP – 3) ← MBE, 0, 0, 0 PC11–0 ← (taddr) 3–0 ← (taddr + 1) SP ← SP – 4 ----------------------------------------------------------------• Other than TBR and TCALL Instruction ----------------------------- ----------------------------Conforms to referenced instruction. Execution of an instruction addressed at (taddr) and (taddr + 1) GETI taddr 1 3 ● µPD75306, 75308BB • TBR Instruction PC12-0 ← (taddr) 4–0 + (taddr + 1) ----------------------------------------------------------------• TCALL Instruction (SP – 4) (SP – 1) (SP – 2) ← PC11–0 *10 (SP – 3) ← MBE, 0, 0, PC12 PC12–0 ← (taddr) 4–0 ← (taddr + 1) SP ← SP – 4 ----------------------------------------------------------------• Other than TBR and TCALL Instruction Execution of an instruction addressed at (taddr) and (taddr + 1) * ----------------------------- ----------------------------Conforms to referenced instruction. At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance. Note 1. Instruction Group 2. CPU control Remarks 44 Skip Condition The TBR and TCALL instructions are assembler pseudo-instructions for GETI instruction table definition. µPD75304B,75306B,75308B 10. MASK OPTION SELECTION The following pin mask options are available. Pin Functions Mask Options P40 to P43, ● Pull-up resistor incorporated (specifiable bit-wise) P50 to P53 ● No pull-up resistor (specifiable bit-wise) VLC0 to VLC2, ● LCD drive power supply split resistor incorporated (specifiable as 4-bit unit) BIAS ● No LCD drive power supply split resistor (specifiable as 4-bit unit) 45 µPD75304B,75306B,75308B 11. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) PARAMETER Power supply voltage SYMBOL TEST CONDITIONS RATING UNIT –0.3 to +7.0 V –0.3 to VDD +0.3 V –0.3 to VDD +0.3 V –0.3 to +11 V –0.3 to VDD +0.3 V One pin –15 mA All pins –30 mA Peak value 30 mA rms 15 mA Peak value 100 mA rms 60 mA Peak value 100 mA rms 60 mA VDD VI1 Except ports 4 and 5 V12 Ports 4 and 5 Input voltage On-chip pull-up resistor Open–drain Output voltage VO Output current high IOH One pin Output current low IOL* Total of ports 0, 2, 3 and 5 Total of ports 4, 6, and 7 * Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C Rms is calculated using the following expression: [rms] = [peak value] × √duty CAPACITANCE (Ta = 25 °C, VDD = 0 V) PARAMETER Input capacitance Output capacitance I/O capacitance 46 SYMBOL TEST CONDITIONS CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. UNIT 15 pF 15 pF 15 pF µPD75304B,75306B,75308B MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) RECOMMENDED CONSTANT RESONATOR PARAMETER TEST CONDITIONS Oscillator frequency (fx)*1 X1 TYP. MAX. UNIT 5.0*3 MHz 4 ms 5.0*3 MHz 10 ms 30 ms 1.0 5.0*3 MHz 100 500 ns 1.0 X2 Ceramic resonator*3 C2 C1 Oscillation stabilization time*2 VDD After VDD reached the MIN. of the oscillation voltage range Oscillator frequency (fx)*1 X1 MIN. 1.0 4.19 X2 VDD = 4.5 to 6.0 V Crystal resonator*3 C2 C1 Oscillation stabilization time*2 VDD X1 X2 External clock X1 input frequency (fx)*1 X1 input µPD74HCU04 high-/low-level width (tXH, tXL) * 1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. For the instruction execution time refer to the AC characteristics. 2. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. 3. When the oscillation frequency is 4.19 MHz < fX ≤ 5.0 MHz, PCC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 s, and the specification MIN. value of 0.95 µs will not be achieved. 47 ★ µPD75304B,75306B,75308B SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) RECOMMENDED CONSTANT RESONATOR XT1 PARAMETER Oscillator frequency (fXT) XT2 C3 C4 MIN. TYP. MAX. UNIT 32 32.768 35 kHz 1.0 2 s 10 s 32 100 kHz 5 15 µs VDD = 4.5 to 6.0 V R Crystal resonator TEST CONDITIONS Oscillation stabilization time* VDD XT1 input frequency (fXT) XT1 External clock XT2 Leave Open XT1 input high-/ low-level width (tXTH,tXTL) * This is the time required for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage range. ★ Note When the main system clock and subsystem clock oscillators are used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. • The wiring should be kept as short as possible. • No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current. • The oscillator capacitor grounding point should be at the same potential as VDD. Do not ground to a ground pattern carrying a high current. • A signal should not be taken from the oscillator. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. 48 µPD75304B,75306B,75308B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (1/2) PARAMETER SYMBOL TEST CONDITIONS TYP. MAX. UNIT VIH1 Ports 2 and 3 0.7 VDD VDD V VIH2 Ports 0,1,6,7, RESET 0.8 VDD VDD V On-chip pull-up resistor 0.7 VDD VDD V VIH3 Ports 4 and 5 Open–drain 0.7 VDD 10 V VDD –0.5 VDD V Input voltage high Input voltage low MIN. VIH4 X1, X2, XT1 VIL1 Ports 2, 3, 4 and 5 0 0.3 VDD V VIL2 Ports 0, 1, 6, 7 RESET 0 0.2 VDD V VIL3 X1, X2, XT1 0 0.4 V VOH1 Ports 0, 2,3, 6, 7, BIAS Output voltage high VOH2 BP0 to BP7 (with 2 IOH outputs) VDD = 4.5 to 6.0 V IOH = –1 mA VDD –1.0 V IOH = -100 µA VDD –0.5 V VDD = 4.5 to 6.0 V IOH = –100 µA VDD –2.0 V IOH = –30 µA VDD –1.0 V Ports 3, 4 and 5 VDD = 4.5 to 6.0 V IOL = 15 mA Ports 0, 2, 3, 4, 5, 6 and 7 VOL1 Output voltage low SB0, 1 VOL2 BP0 to BP7 (with 2 IOL outputs) I L1H1 2.0 V VDD = 4.5 to 6.0 V IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V 0.2 VDD V VDD = 4.5 to 6.0 V IOL = 100 µA 1.0 V IOL = 50 µA 1.0 V Other than below 3 µA X1, X2, XT1 20 µA Ports 4 and 5 (when open–drain) 20 µA Other than below –3 µA X1, X2, XT1 –20 µA 3 µA 20 µA –3 µA Open–drain pull-up resistor ≥ 1 kΩ 0.5 VIN = VDD Input leakage current high ILIH2 ILIH3 Input leakage current low Output leakage current high Output leakage current low VIN = 10 V ILIL1 VIN = 0 V ILIL2 ILOH1 VOUT = VDD Other than below ILOH2 VOUT = 10 V Ports 4 and 5 (when open–drain) ILOL VOUT = 0 V 49 µPD75304B,75306B,75308B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (2/2) PARAMETER SYMBOL RL1 On-chip pull-up resistor RL2 TEST CONDITIONS Ports 0, 1, 2, 3, 6 and 7 (Except P00) VIN = 0 V Ports 4 and 5 VOUT = VDD –2.0 V MIN. kΩ VDD V 150 kΩ 0 ±0.2 V 0 ±0.2 V LCD output voltage deviation (segment) VODS IO = ±1 µA VLCD0 = VLCD VLCD1 = VLCD × 2/3 VLCD2 = VLCD × 1/3 2.7 V ≤ VLCD ≤ VDD 40 100 VDD = 5 V ±10%*4 3.0 9 mA VDD = 3 V ±10%*5 0.4 1.2 mA VDD = 5 V ±10% 600 1800 µA VDD = 3 V ±10% 180 540 µA 40 120 µA 12 36 µA 1 25 µA 0.5 15 µA 0.5 5 µA HALT mode VDD = 3 V ±10% HALT mode VDD = 3 V ±10% VDD = 5 V ±10% * kΩ 60 IO = ±5 µA XT1 = 0 V STOP mode 70 10 VODC IDD5 kΩ VDD = 3.0 V ±10% LCD output voltage deviation*1 (common) IDD4 300 15 60 32 kHz*6 crystal oscillation kΩ VDD = 5.0 V ±10% RLCD IDD3 80 30 LCD split resistor Supply current*2 40 VDD = 3.0 V ±10% 2.0 IDD2 UNIT 15 VLCD 4.19 MHz*3 crystal oscillation C1 = C2 = 22 pF MAX. VDD = 5.0 V ±10% LCD drive voltage IDDI TYP. VDD = 3 V ±10% Ta = 25 °C 1. The voltage deviation is the difference between the output voltage and the segment or common output desired value (VLCDn ; n= 0, 1, 2). 2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included. 3. Including oscillation of the subsystem clock. 4. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode. 5. When PCC is set to 0000 and the device is operated in the low-speed mode. 6. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. 50 µPD75304B,75306B,75308B AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER CPU clock cycle time (minimum instruction execution time)*1 tCY TI0 input frequency fTI TI0 input width high/low tTIH, tTIL Interrupt input width high/low tINTH, tINTL RESET width low TEST CONDITIONS Operating on main system clock MIN. VDD = 4.5 to 6.0 V TYP. MAX. UNIT 0.95 64 µs 3.8 64 µs 125 µs Operating on subsystem clock 114 VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz 122 0.48 µs 1.8 µs INT0 *2 µs INT1, 2, 4 10 µs KR0 to KR7 10 µs 10 µs VDD = 4.5 to 6.0 V tRSL 1. The CPU clock (Φ ) cycle time (minimum instruction execution time) is determined by tCY vs VDD (Operating on Main System Clock) the oscillatior frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The figure at the right indicates the cycle time t CY versus supply voltage VDD characteristic with the main system clock operating. 2. 2t CY or 128/fX is set by setting the interrupt mode register (IM0). 70 64 30 6 Guaranteed 5 Operation Range 4 Cycle Time tCY [µs] * SYMBOL 3 2 1 0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V] 51 µPD75304B,75306B,75308B SERIAL TRANSFER OPERATION 2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 1600 ns 3800 ns tKCY1/2-50 ns tKCY1/2-150 ns tKCY1 VDD = 4.5 to 6.0 V SCK width high/ low tKL1 tKH1 SI setup time (to SCK↑) tSIK1 150 ns SI hold time (from SCK↑) tKSI1 400 ns SO output delay time from SCK↓ tKSO1 VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pF* 250 ns 1000 ns 2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input): (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns tKCY2 VDD = 4.5 to 6.0 V SCK width high/ low tKL2 tKH2 SI setup time (to SCK↑) tSIK2 100 ns SI hold time (from SCK ↑) tKSI2 400 ns SO output delay time from SCK↓ tKSO2 * 52 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V RL and CL are load resistor and load capacitance of the SO output line. 300 ns 1000 ns µPD75304B,75306B,75308B SBI Mode (SCK ... Internal clock output (Master)): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 1600 ns 3800 ns tKCY3/2-50 ns tKCY3/2-150 ns tKCY3 VDD = 4.5 to 6.0 V SCK width high/ low tKL3 tKH3 SB0, 1 setup time (to SCK ↑) tSIK3 150 ns SB0, 1 hold time (from SCK ↑) tKSI3 tKCY3/2 ns SB0, 1 output delay time from SCK ↓ tKSO3 SB0, 1 ↓ from SCK ↑ tKSB tKCY3 ns SCK from SB0, 1 ↓ tSBK tKCY3 ns SB0, 1 width low tSBL tKCY3 ns SB0, 1 width high tSBH tKCY3 ns VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pF* 0 250 ns 0 1000 ns SBI Mode (SCK ... External clock input (Slave)): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time * MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns tKCY4 VDD = 4.5 to 6.0 V SCK width high/ low tKL4 tKH4 SB0, 1 setup time (to SCK ↑) tSIK4 100 ns SB0, 1 hold time (from SCK ↑) tKSI4 tKCY4/2 ns SB0, 1 output delay time from SCK ↓ tKSO4 SB0, 1 ↓ from SCK ↑ tKSB tKCY4 ns SCK ↓ from SB0, 1 ↓ tSBK tKCY4 ns SB0, 1 width low tSBL tKCY4 ns SB0, 1 width high tSBH tKCY4 ns RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns RL and CL are load resistor and load capacitance of the SB0, 1 output lines. 53 µPD75304B,75306B,75308B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) (1/2) PARAMETER SYMBOL TEST CONDITIONS TYP. MAX. UNIT VIH1 Ports 2 and 3 0.8 VDD VDD V VIH2 Ports 0, 1, 6, 7, RESET 0.8 VDD VDD V On-chip pull-up resistor 0.8 VDD VDD V VIH3 Ports 4 and 5 Open–drain 0.8 VDD 10 V VDD –0.3 VDD V Input voltage high Input voltage low MIN. VIH4 X1, X2, XT1 VIL1 Ports 2, 3, 4 and 5 0 0.2 VDD V VIL2 Ports 0, 1, 6, 7, RESET 0 0.2 VDD V VIL3 X1, X2, XT1 0 0.3 V VOH1 Ports 0, 2, 3, 6, 7, BIAS IOH = –100 µA VDD –0.5 V VOH2 BP0 to BP7 (with 2 IOH outputs) IOH = –10 µA VDD –0.4 V Ports 0, 2, 3, 4, 5 6, and 7 IOL = 400 µA SB0, 1 Open–drain, pull-up resistor ≥ 1 kΩ BP0 to BP7 (with 2 IOL outputs) IOL = 10 µA Output voltage high 0.5 V 0.2 VDD V 0.4 V Other than below 3 µA X1, X2, XT1 20 µA Ports 4 and 5 (with open–drain) 20 µA Other than below –3 µA X1, X2, XT1 –20 µA VOL1 Output voltage low VOL2 ILIH1 VIN = VDD Input leakage current high ILIH2 ILIH3 Input leakage current low Output leakage current high Output leakage current low 54 VIN = 10 V ILIL1 VIN = 0 V ILIL2 ILOH1 VOUT = VDD Other than below 3 µA ILOH2 VOUT = 10 V Ports 4 and 5 (with open–drain) 20 µA ILOL VOUT = 0 V –3 µA µPD75304B,75306B,75308B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) (2/2) PARAMETER SYMBOL TEST CONDITIONS TYP. MAX. UNIT RL1 Ports 0, 1, 2, 3, 6 and 7 (Except P00) VIN = 0 V VDD = 2.5 V ±10% 50 600 kΩ RL2 Ports 4 and 5 VOUT = VDD –1.0 V VDD = 2.5 V ±10% 10 60 kΩ VDD V 150 kΩ 0 ±0.2 V 0 ±0.2 V On-chip pull-up resistor LCD drive voltage VLCD 2.0 LCD split resistor RLCD 60 LCD output voltage deviation *1 (common) VODC IO = ±5 µA LCD output voltage deviation (segment) VODS IO = ±1 µA IDDI 4.19 MHz*3 crystal oscillation C1 = C2 = 22 pF low-speed mode IDD2 IDD3 Supply current*2 32 kHz*5 crystal oscillation VLCDO = VLCD VLCD1 = VLCD × 2/3 VLCD2 = VLCD × 1/3 2.0 V ≤ V LCD ≤ V DD 0.4 1.2 mA VDD = 2.5 V ±10%*4 0.3 0.9 mA HALT VDD = 3 V ±10% 180 540 µA mode VDD = 2.5 V ±10% 120 360 µA VDD = 3 V ±10% 40 120 µA VDD = 2.5 V ±10% 25 75 µA HALT VDD = 3 V ±10% 12 36 µA mode VDD = 2.5 V ±10% 9 27 µA 0.5 15 µA 0.5 5 µA 0.4 15 µA 0.4 5 µA VDD = 3 V ±10% IDD5 XT1 = 0 V STOP mode 100 VDD = 3 V ±10%*4 IDD4 * MIN. VDD = 2.5 V ±10% Ta = 25 °C Ta = 25°C 1. The voltage deviation is the difference between the output voltage and the segment or common output desired value (VLCDn; n = 0, 1, 2). 2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included. 3. Including oscillation of the subsystem clock. 4. When PCC is set to 0000 and the device is operated in the low-speed mode. 5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. 55 µPD75304B,75306B,75308B AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER CPU clock cycle time (minimum instruction execution time)*1 SYMBOL TEST CONDITIONS Operation on main system clock tCY MIN. MAX. UNIT VDD = 2.7 to 6.0 V 3.8 64 µs VDD = 2.0 to 6.0 V 5 64 µs 3.4 64 µs 125 µs 275 kHz Ta = –40 to + 60 °C VDD = 2.2 to 6.0 V Operation on subsystem clock TI0 input frequency TYP. 114 122 fTI 0 TI0 input width high/low tTIH, tTIL 1.8 µs INT0 *2 µs Interrupt input width high/low tINTH, tINTL INT1, 2, 4 10 µs KR0 to KR7 10 µs 10 µs RESET width low * tRSL 1. The CPU clock (Φ ) cycle time (minimum instruction execution time) is determined by the oscillatior frequency of the connected tCY vs VDD (Operating on Main System Clock) 70 64 30 resonator, the system clock control register (SCC) and the processor clock control register (PCC). The figure at the right indicates the cycle time t CY versus supply voltage VDD 5 Cycle Time t CY [µs] characteristic with the main system clock operating. 2. 2t CY or 128/fX is set by setting the interrupt mode register (IM0). 6 Guaranteed 4 Operation Range 3 2 1 0.5 0 1 2 3 4 5 Supply Voltage VDD [V] 56 6 µPD75304B,75306B,75308B SERIAL TRANSFER OPERATION 2-Wired and 3-Wired Serial I/O Mode (SCK ... Internal clock output): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 1600 ns 3800 ns tKCY1/2-50 ns tKCY1/2-150 ns tKCY1 VDD = 4.5 to 6.0 V SCK width high/ low tKL1 tKH1 SI setup time (to SCK ↑) tSIK1 250 ns SI hold time (from SCK ↑) tKSI1 400 ns SO output delay time from SCK ↓ tKSO1 VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pF* 250 ns 1000 ns 2-Wired and 3-Wired Serial I/O Mode (SCK ... External clock input): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time * MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns tKCY2 VDD = 4.5 to 6.0 V SCK width high/ low tKL2 tKH2 SI setup time (to SCK↑) tSIK2 100 ns SI hold time (from SCK↑) tKSI2 400 ns SO output delay time from SCK↓ tKSO2 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 300 ns 1000 ns RL and CL are load resistor and load capacitance of the SO output line. 57 µPD75304B,75306B,75308B SBI Mode (SCK ... Internal clock output (Master)): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 1600 ns 3800 ns tKCY3/2-50 ns tKCY3/2-150 ns tKCY3 VDD = 4.5 to 6.0 V SCK width high/ low tKL3 tKH3 SB0, 1 setup time (to SCK↑) tSIK3 250 ns SB0, 1 hold time (from SCK↑) tKSI3 tKCY3/2 ns SB0, 1 output delay time from SCK↓ tKSO3 SB0, 1 ↓ from SCK↑ tKSB tKCY3 ns SCK from SB0, 1 ↓ tSBK tKCY3 ns SB0, 1 width low tSBL tKCY3 ns SB0, 1 width high tSBH tKCY3 ns VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pF* 0 250 ns 0 1000 ns SBI Mode (SCK ... External clock input (Slave)): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SCK cycle time SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns tKCY4 VDD = 4.5 to 6.0 V SCK width high/ low tKL4 tKH4 SB0, 1 setup time (to SCK ↑) tSIK4 100 ns SB0, 1 hold time (from SCK ↑) tKSI4 tKCY4/2 ns SB0, 1 output delay time from SCK ↓ tKSO4 SB0, 1 ↓ from SCK ↑ tKSB tKCY4 ns SCK↓ from SB0, 1 ↓ tSBK tKCY4 ns SB0, 1 width low tSBL tKCY4 ns SB0, 1 width high tSBH tKCY4 ns * 58 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns RL and CL are load resistor and load capacitance of the SB0, 1 output lines. µPD75304B,75306B,75308B AC Timing Test Point (Excluding X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD Clock Timings 1/fX tXL tXH VDD -0.5 V 0.4 V X1 Input 1/fXT tXTL tXTH VDD -0.5 V 0.4 V XT1 Input TI0 Timing 1/fTI tTIL tTIH TI0 59 µPD75304B,75306B,75308B Serial Transfer Timing 3-wired serial I/O mode: tKCY1 tKL1 tKH1 SCK tKSI1 tSIK1 Input Data SI tKSO1 SO Output Data 2-wired serial I/O mode: tKCY2 tKL2 tKH2 SCK tSIK2 SB0,1 tKSO2 60 tKSI2 µPD75304B,75306B,75308B Serial Transfer Timing Bus release signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 Command signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 Interrupt Input Timing tINTL tINTH INT0,1,2,4 KR0-7 RESET Input Timing tRSL RESET 61 µPD75304B,75306B,75308B DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to 85 °C) PARAMETER SYMBOL Data retention supply voltage VDDDR Data retention supply current*1 IDDDR Release signal setup time tSREL Oscillation stabilization wait time*2 tWAIT * TEST CONDITIONS MIN. TYP. 2.0 VDDDR = 2.0 V 0.3 Release by interrupt request UNIT 6.0 V 15 µA µs 0 Release by RESET MAX. 217/fx ms *3 ms 1. Current which flows in the on-chip pull-up resistor is not included. 2. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. 3. Depends on the basic interval timer mode register (BTM) setting (table below). 62 BTM3 BTM2 BTM1 BTM0 WAIT TIME (Figures in parentheses are for operation at fx = 4.19 MHz) — 0 0 0 220/fx (approx. 250 ms) — 0 1 1 217/fx (approx. 31.3 ms) — 1 0 1 215/fx (approx. 7.82 ms) — 1 1 1 213/fx (approx. 1.95 ms) µPD75304B,75306B,75308B Data Retention Timing (STOP mode release by RESET) Internal Reset Operation HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby release signal: STOP mode release by interrupt signal) HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 63 µPD75304B,75306B,75308B 12. PACKAGE INFORMATION 80 PIN PLASTIC QFP ( 14) A B 41 40 60 61 Q 5°±5° S C D detail of lead end 21 20 F 80 1 G H I M J M P K N L S80GC-65-3B9-3 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 64 ITEM MILLIMETERS INCHES A 17.2 ± 0.4 0.677 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.2 ± 0.4 0.677 ± 0.016 F 0.8 0.031 G 0.8 0.031 H 0.30 ± 0.10 0.012+0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6 ± 0.2 0.063 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. µPD75304B,75306B,75308B 80 PIN PLASTIC QFP (14×20) A B 41 40 64 65 F Q 5°±5° S C D detail of lead end 25 24 80 1 G H I M J M P K N L P80GF-80-3B9-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795 +0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 0.8 0.031 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 –0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.15 0.006 P 2.7 Q 0.1 ± 0.1 S 3.0 MAX. +0.008 0.106 0.004 ± 0.004 0.119 MAX. 65 µPD75304B,75306B,75308B 80 PIN PLASTIC TQFP (FINE PITCH) ( 12) A B 60 41 61 40 21 F 80 1 20 H I M J K M P G R Q S D C detail of lead end N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 14.0±0.2 INCHES 0.551 +0.009 –0.008 B 12.0±0.2 0.472 +0.009 –0.008 C 12.0±0.2 0.472 +0.009 –0.008 D 14.0±0.2 0.551 +0.009 –0.008 F 1.25 G 1.25 H 0.22 +0.05 –0.04 0.049 0.049 0.009±0.002 I 0.10 J 0.5 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.145 +0.055 –0.045 0.006±0.002 N 0.10 P 1.05 Q 0.05±0.05 R 5°±5° S 1.27 MAX. 0.004 0.020 (T.P.) 0.004 0.041 0.002±0.002 5°±5° 0.050 MAX. P80GK-50-BE9-4 66 µPD75304B,75306B,75308B ★ 13. RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document "Surface Mount Technology Manual (IEI 1207)". For soldering methods and conditions other than those recommended, please contact our salesman. Table 13-1 Surface Mount Type Soldering Conditions (1) µPD75304BGC-×××-3B9: 80-Pin Plastic QFP (■ ■ 14 mm) µPD75306BGC-×××-3B9: 80-Pin Plastic QFP (■ ■ 14 mm) µPD75308BGC-×××-3B9: 80-Pin Plastic QFP (■ ■ 14 mm) Soldering Method Soldering ConditionsRecommended Condition Symbol Infrared reflow Package peak temperature: 230°C Duration: 30 sec. max. (210°C or above) Number of applications: one Time limit: 7 days* (thereafter 20 hours 125°C prebaking required) IR30-207-1 VPS Package peak temperature: 215°C Duration: 40 sec. max. (200°C or above) Number of applications: one Time limit: 7 days* (thereafter 20 hours 125°C prebaking required) VP15-207-1 Pin part heating Pin part temperature: 300°C or less Duration: 3 sec. max. (per side of device) (2) µPD75304BGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm) µPD75306BGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm) µPD75308BGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm) Soldering Method * Soldering ConditionsRecommended Condition Symbol Infrared reflow Package peak temperature: 230°C Duration: 30 sec. max. (210°C or above) Number of applications: one IR30-00-1 VPS Package peak temperature: 215°C Duration: 40 sec. max. (200°C or above) Number of applications: one VP15-00-1 Wave soldering Solder bath temperature: 260°C or less Duration: 10 sec. max. Number of applications: one Preparatory heating temperature: 120°C max. (package surface temperature) WS60-00-1 Pin part heating Pin part temperature: 300°C or less Duration: 3 sec. max. (per side of device) For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH. Note Use of more than one soldering method should be avoided (except in the case of pin part heating). 67 µPD75304B,75306B,75308B (3) µPD75304BGK-×××-3B9: 80-Pin Plastic TQFP (■ ■ 12 mm) µPD75306BGK-×××-3B9: 80-Pin Plastic TQFP (■ ■ 12 mm) µPD75308BGK-×××-3B9: 80-Pin Plastic TQFP (■ ■ 12 mm) Soldering Method * Soldering ConditionsRecommended Condition Symbol Infrared reflow Package peak temperature: 230°C Duration: 30 sec. max. (210°C or above) Number of applications: one Time limit: 1 day* (thereafter 16 hours 125°C prebaking required) IR30-161-1 VPS Package peak temperature: 215°C Duration: 40 sec. max. (200°C or above) Number of applications: one Time limit: 1 day* (thereafter 16 hours 125°C prebaking required) VP15-161-1 Pin part heating Pin part temperature: 300°C or less Duration: 3 sec. max. (per side of device) For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH. Note Use of more than one soldering method should be avoided (except in the case of pin part heating). NOTICE Recommended soldering conditions have been improved for some of these products. (Improvements: Relaxation of infrared reflow peak temperature (235°C, number of applications (two), time limit, etc.) Please contact your NEC sales representative for details. 68 µPD75304B,75306B,75308B [MEMO] 69 µPD75304B,75306B,75308B ★ APPENDIX A. DIFFERENCES AMONG SERIES PRODUCTS Product Name Item µPD75304/75306/75308 Supply voltage range µPD75312/75316 2.0 to 6.0 V ROM configuration µPD75P316 5V±5% EPROM/Onetime Mask ROM Program memory (bytes) 4096/6016/8064 12160/16256 Data memory (× 4 bits) Instruction cycle µPD75P308 8064 One-time PROM 16256 512 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz operation) 122 µs (subsystem clock: 32.768 kHz operation) 8 CMOS input Pull-up resistor incorporation spesifiable by software: 23 16 CMOS input/output Input/output ports CMOS output N-ch open–drain input/output 40 8 Used with segment pin 8 10 V withstand voltage. Pull-up resistor incorporation spesifiable by mask option 10 V withstand voltage. Pull-up resistor incorporation spesifiable by mask option. (without pull-up resistor) • Common output: Static – 1/4 duty selected • Segment output: Max. 32 LCD controller/driver LCD drive split resistor can be incorporated by mask option. LCD drive voltage No LCD drive split resistor. 2.0 to VDD Timer/counter • 8-bit timer/event counter • 8-bit basic interval timer • Watch timer Serial interface • NEC standard serial bus interface (SBI) • Clock synchronous serial interface Vectored interrupt • External: 3 • Internal: 3 Test input • External: 1 • Internal: 1 Clock output (PCL) Φ, 524 kHz, 262 kHz, 65.5 kHz (main system clock: 4.19 MHz operation) Buzzer output (BUZ) 2 kHz (Main system clock: in 4.19 MHz operation or subsystem clock: in 32.768 kHz operation) Package On-chip PROM product 70 80-pin plastic QFP (14 × 20 mm) 80-pin plastic QFP 80-pin ceramic (14 × 20 mm) WQFN (LCC with window) 80-pin plastic QFP (14 × 20 mm) µPD75P308 µPD75P316 µPD75P316A µPD75304B,75306B,75308B Product Name Item µPD75304B/75306B/75308B µPD75312B µPD75P316B* µPD75P316A One-time PROM EPROM/Onetime 2.0 to 6.0 V Supply voltage range ROM configuration Mask ROM 4096/6016/8064 Program memory (bytes) 12160 16256 512 Data memory (× 4 bits) Instruction cycle µPD75316B 1024 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz operation) 122 µs (subsystem clock: 32.768 kHz operation) CMOS input 8 CMOS input/output 16 Pull-up resistor incorporation spesifiable by software: 23 Input/output ports CMOS output N-ch open–drain input/output 40 8 Used with segment pin 8 10 V withstand voltage. Pullup resistor incorporation spesifiable by mask option 10 V withstand voltage. Pull-up resistor incorporation spesifiable by mask option. (without pull-up resistor) • Common output: Static – 1/4 duty selected • Segment output: Max. 32 LCD controller/driver LCD drive split resistor can be incorporated by mask option. LCD drive voltage * No LCD drive split resistor. 2.0 to VDD Timer/counter • 8-bit timer/event counter • 8-bit basic interval timer • Watch timer Serial interface • NEC standard serial bus interface (SBI) • Clock synchronous serial interface Vectored interrupt • External: 3 • Internal: 3 Test input • External: 1 • Internal: 1 Clock output (PCL) Φ, 524 kHz, 262 kHz, 65.5 kHz (main system clock: 4.19 MHz operation) Buzzer output (BUZ) 2 kHz (Main system clock: in 4.19 MHz operation or subsystem clock: in 32.768 kHz operation) Package 80-pin plastic QFP • (14 × 20 mm) • (■ ■ 14mm) 80-pin plastic TQFP(■ ■ 12mm) On-chip PROM product GF package: µPD75P316A GC/GK package: µPD75P316B 80-pin plastic QFP (■ ■ 14mm) 80-pin plastic TQFP(■ ■ 12mm) 80-pin ceramic WQFN 80-pin plastic QFP (14 × 20 mm) µPD75P316B Under development 71 µPD75304B,75306B,75308B APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD75304B/75306B/ 75308B. IE-75000-R*1 IE-75001-R 75X series in-circuit emulator IE-75000-R-EM*2 Emulation board for the IE-75000-R or IE-75001-R EV-9200G-80 Emulation probe for the µPD75304BGF, 75306BGF and 75308BGF. An 80-pin conversion socket (EV-9200G-80) is also provided. EV-9200GC-80 Emulation probe for the µPD75304BGC, 75306BGC and 75308BGC. An 80-pin conversion socket (EV-9200GC-80) is also provided. EV-9500GK-80 Emulation probe for the µPD75304BGK, 75306BGK and 75308BGK. An 80-pin conversion adapter (EV-9200GK-80) is also provided. EP-75308GF-R Software Hardware EP-75308BGC-R * EP-75308BGK-R PG-1500 PROM programmer PA-75P308GF PROM programmer adapter for the µPD75P316AGF, connected to the PG-1500. PA-75P316BGC PROM programmer adapter for the µPD75P316BGC, connected to the PG-1500. PA-75P316BGK PROM programmer adapter for the µPD75P316BGK, connected to the PG-1500. IE Control Program Host machines PG-1500 Controller PC-9800 series (MS-DOS™ Ver. 3.30 to Ver. 5.00A*3) RA75X Relocatable Assembler IBM PC/AT™(PC DOS™ Ver. 3.1) 1. Maintenance product 2. Not incorporated in the IE-75001-R. 3. A task swapping function is provided in Ver. 5.00/5.00A, but this function cannot be used with this software. Remarks 72 Please refer to the 75X Series Selection Guide (IF-151) for third party development tools. µPD75304B,75306B,75308B APPENDIX C. RELATED DOCUMENTS Device Related Documents Document Name Document Number User's Manual IEM-5016 Instruction Application Table IEM-994 IEM-5035 Application Note IEM-5041 75X Series Selection Guide IF-151 Development Tools Documents Software Hardware Document Name Document Number IE-75000-R/IE-75001-R User's Manual EEU-846 IE-75000-R-EM User's Manual EEU-673 EP-75308GF-R User's Manual EEU-689 EP-75308BGC-R User's Manual EEU-825 EP-75308BGK-R User's Manual EEU-838 PG-1500 User's Manual EEU-651 RA75X Assembler Package User's Manual Operation EEU-731 Language EEU-730 PG-1500 Controller User's Manual EEU-704 Other Documents Document Name * Document Number Package Manual IEI-635 Surface Mount Technology Manual IEI-1207 Quality Grande on NEC Semiconductor Device IEI-1209 NEC Semiconductor Device Reliability & Quality Control IEM-5068 Electrostatic Discharge(ESD) Test MEM-539 Semiconductor Devices Quality Guarantee Guide MEI-603 Microcomputer Related Products Guide Other Manufacturers Volume MEI-604 The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 73 µPD75304B,75306B,75308B [MEMO] 74 µPD75304B,75306B,75308B 75 µPD75304B,75306B,75308B [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Special Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. : M4 92.6 MS-DOS is a trademark of MicroSoft Corporation. PC DOS, PC/AT is a trademark of IBM Corporation.