DATA SHEET MOS INTEGRATED CIRCUIT µPD75P4308 4-BIT SINGLE-CHIP MICROCONTROLLER The µPD75P4308 replaces the µPD754304’s internal mask ROM with a one-time PROM and features expanded ROM capacity. Because the µPD75P4308 supports programming by users, it is suitable for use in prototype testing for system development using the µPD754302 and 754304 products, and for use in small-lot production. Detailed descriptions of functions are provided in the following document. Be sure to read the document before designing. µPD754304 User’s Manual: U10123E FEATURES • Compatible with µPD754304 • Memory capacity: · PROM : 8192 × 8 bits · RAM : 256 × 4 bits • Can operate in the same power supply voltage as the mask version µPD754304 · VDD = 1.8 to 5.5 V • Adopts a compact shrink SOP package ORDERING INFORMATION Part Number Package µPD75P4308GS 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) Caution On-chip pull-up resistors by mask option are not provided. The information in this document is subject to change without notice. Document No. U10909EJ2V0DS00 (2nd edition) Date Published January 1997 N Printed in Japan The mark shows major revised points. © 1996 µPD75P4308 OVERVIEW OF FUNCTIONS Item Function Instruction execution time • 0.95, 1.91, 3.81, or 15.3 µs (system clock: @ 4.19 MHz) • 0.67, 1.33, 2.67, or 10.7 µs (system clock: @ 6.0 MHz) Internal memory PROM 8192 × 8 bits RAM 256 × 4 bits General-purpose register • 4-bit manipulation: 8 registers × 4 banks • 8-bit manipulation: 4 registers × 8 banks I/O ports CMOS input 8 Connection of on-chip pull-up resistors can be specified by software: 7 CMOS I/O 18 Connection of on-chip pull-up resistors can be specified by software: 18 N-ch open-drain I/O 4 13-V withstand voltage Total 30 Timers 3 channels • 8-bit timer/event counter: 2 channels (Can be used as a 16-bit timer/event counter) • 8-bit basic interval timer/watchdog timer: 1 channel Serial interface • 3-wire serial I/O mode ... MSB/LSB-first switchable • 2-wire serial I/O mode Bit sequential buffer 16 bits Clock output (PCL) • Φ, 524, 262, 65.5 kHz (system clock: @ 4.19 MHz) • Φ, 750, 375, 93.8 kHz (system clock: @ 6.0 MHz) 2 Vectored interrupts External: 3, Internal: 4 Test input External: 1 System clock oscillator Ceramic/crystal oscillator Standby functions STOP mode/HALT mode Operating ambient temperature TA = –40 to +85˚C Power supply voltage VDD = 1.8 to 5.5 V Package 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) µPD75P4308 CONTENTS 1. PIN CONFIGURATION (Top View) .................................................................................................... 4 2. BLOCK DIAGRAM .............................................................................................................................. 5 3. PIN FUNCTIONS ................................................................................................................................. 6 3.1 3.2 3.3 3.4 Port Pins ........................................................................................................................................................ 6 Non-port Pins ................................................................................................................................................ 8 Pin I/O Circuits .............................................................................................................................................. 9 Recommended Connection of Unused Pins ............................................................................................ 11 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ......................................... 12 4.1 Differences between Mk I Mode and Mk II Mode ..................................................................................... 12 4.2 Setting of Stack Bank Selection (SBS) Register ..................................................................................... 13 5. DIFFERENCES BETWEEN µPD75P4308 AND µPD754302, 754304 .......................................... 14 6. MEMORY CONFIGURATION ............................................................................................................ 15 7. INSTRUCTION SET .......................................................................................................................... 17 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ............................................... 28 8.1 8.2 8.3 8.4 Operation Modes for Program Memory Write/Verify ............................................................................... Program Memory Write Procedure ........................................................................................................... Program Memory Read Procedure ........................................................................................................... One-Time PROM Screening ....................................................................................................................... 28 29 30 31 9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 32 10. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ............................................................ 45 11. PACKAGE DRAWINGS ..................................................................................................................... 47 12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 48 APPENDIX A. COMPARISON OF µPD750004, 754304, AND 75P4308 FUNCTIONS ..................... 49 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 51 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 55 3 µPD75P4308 1. PIN CONFIGURATION (Top View) • 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) µPD75P4308GS Vss 1 36 P50/D4 X1 2 35 P51/D5 X2 3 34 P52/D6 RESET 4 33 P53/D7 P33/MD3 5 32 P60/KR0/D0 P32/MD2 6 31 P61/KR1/D1 P31/MD1 7 30 P62/KR2/D2 P30/MD0 8 29 P63/KR3/D3 P81 9 28 P70/KR4 P80 10 27 P71/KR5 P23 11 26 P72/KR6 P22/PCL 12 25 P73/KR7 P21/PTO1 13 24 P13/TI0/TI1 P20/PTO0 14 23 P12/INT2 P03/SI 15 22 P11/INT1 P02/SO/SB0 16 21 P10/INT0 P01/SCK 17 20 VDD P00/INT4 18 19 VPP Note Note Connect VPP directly to VDD during normal operations. PIN IDENTIFICATIONS 4 P00 to P03 : Port0 SI : Serial Input P10 to P13 : Port1 SO : Serial Output P20 to P23 : Port2 SB0 : Serial Bus 0 P30 to P33 : Port3 RESET : Reset P50 to P53 : Port5 TI0, 1 : Timer Input 0, 1 P60 to P63 : Port6 PTO0, 1 : Programmable Timer Output 0, 1 P70 to P73 : Port7 PCL : Programmable Clock P80, P81 : Port8 INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 KR0 to KR7 : Key Return 0 to 7 INT2 : External Test Input 2 VDD : Positive Power Supply X1, 2 : System Clock Oscillation 1, 2 VSS : GND MD0 to 3 : Mode Selection 0 to 3 VPP : Programming Power Supply D0 to D7 : Data Bus 0 to 7 SCK : Serial Clock µPD75P4308 2. BLOCK DIAGRAM BIT SEQ. BUFFER (16) BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT TOUT0 TI0/TI1/P13 PTO0/P20 PTO1/P21 8-BIT TIMER/EVENT COUNTER#0 8-BIT TIMER/EVENT COUNTER#1 INTT0 PROGRAM COUNTER ALU CASCADED 16-BIT TIMER/ EVENT COUNTER CLOCKED SERIAL INTERFACE KR0/P60/D0- 8 KR3/P63/D3 KR4/P70KR7/P73 GENERAL REG. PROM PROGRAM MEMORY 8192 × 8 BITS DECODE AND CONTROL RAM DATA MEMORY 256 × 4 BITS INTERRUPT CONTROL fx/2 N CLOCK CLOCK OUTPUT CONTROL DIVIDER PCL/P22 P00-P03 4 PORT1 4 P10-P13 4 PORT2 4 P20-P23 4 PORT3 4 P30/MD0P33/MD3 4 PORT5 4 P50/D4P53/D7 4 PORT6 4 P60/KR0/D0P63/KR3/D3 4 PORT7 4 P70-P73 2 PORT8 2 P80, P81 SBS BANK INTCSI TOUT0 INT0/P10 INT1/P11 INT2/P12 INT4/P00 4 SP (8) CY INTT1 SI/P03 SO/SB0/P02 SCK/P01 4 PORT0 CPU CLOCK Φ CLOCK GENERATOR X1 STAND BY CONTROL X2 VPP VDD Vss RESET 5 µPD75P4308 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin name I/O Alternate function P00 Input INT4 P01 I/O SCK P02 I/O SO/SB0 P03 Input SI P10 Input INT0 INT1 P12 INT2 P13 TI0/TI1 I/O PTO0 P21 PTO1 P22 PCL P23 P30 After reset I/O Circuit typeNote 1 No Input <B> <F>-A <F>-B 4-bit input port (PORT1). Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. Noise elimination circuit can be selected only for P10/INT0. No Input <B>-C 4-bit I/O port (PORT2). Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. No Input E-B Programmable 4-bit I/O port (PORT3). Input and output can be specified in singlebit units. Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. No Input E-B N-ch open-drain 4-bit input/output port (PORT5). 13-V withstand during open-drain. Data input/output pin for program memory (PROM) write/verify (upper 4 bits). No High- M-E — I/O MD0 P31 MD1 P32 MD2 P33 MD3 P50Note 2 4-bit input port (PORT0). For P01 to P03, connections of on-chip pullup resistors are software-specificable in 3bit units. 8-bit I/O <B>-C P11 P20 Function I/O D4 P51Note 2 D5 P52Note 2 D6 P53Note 2 D7 impedance Notes 1. Circuit types in brackets indicate Schmitt trigger input. 2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed. 6 µPD75P4308 3.1 Port Pins (2/2) Pin name P60 I/O I/O Alternate function KR0/D0 P61 KR1/D1 P62 KR2/D2 P63 KR3/D3 P70 I/O KR4 P71 KR5 P72 KR6 P73 KR7 P80 P81 I/O Function Programmable 4-bit I/O port (PORT6). Input and output can be specified in single-bit units. Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. Data input/output pin for program memory (PROM) write/verify (lower 4 bits). 8-bit I/O After reset I/O Circuit typeNote Yes Input <F>-A Input <F>-A Input E-B 4-bit I/O port (PORT7). Connections of on-chip pull-up resistors are software-specifiable in 4-bit units. — — 2-bit I/O port (PORT8). Connections of on-chip pull-up resistors are software-specifiable in 2-bit units. No Note Circuit types in brackets indicate the Schmitt trigger input. 7 µPD75P4308 3.2 Non-port Pins Pin name I/O Alternate function Function After reset I/O Circuit typeNote 1 TI0/TI1 Input P13 External event pulse input to timer/event counter Input <B>-C PTO0 Output P20 Timer/event counter output Input E-B Input <F>-A PTO1 P21 PCL P22 Clock output P01 Serial clock I/O P02 Serial data output Serial data bus I/O <F>-B P03 Serial data input <B>-C P00 Edge-triggered vectored interrupt input (triggered by both rising and falling edges). — <B> P10 Edge-triggered vectored interrupt input (detected edge is selectable). — <B>-C Input <F>-A SCK I/O SO/SB0 SI Input INT4 INT0 Input Noise elimination circuit selectable in INT0/P10. Asynchronous INT1 P11 INT2 P12 Rising edge-triggered test input P60/D0 to P63/D3 Falling edge-triggered testable input KR0 to KR3 Input KR4 to KR7 Noise elimination circuit appended/ asynchronous selectable Asynchronous P70 to P73 X1 Input X2 — — Ceramic/crystal connection for system clock oscillation. If using an external clock, input it to X1 and input the inverted clock to X2. — — System reset input — <B> RESET Input — MD0 to MD3 Input P30 to P33 Mode selection for program memory (PROM) write/ verify. Input E-B I/O P60/KR0 to P63/KR3 Data bus pin for program memory (PROM) write/verify. Input <F>-A D0 to D3 D4 to D7 VPPNote 2 P50 to P53 — — M-E Program supply voltage in program memory (PROM) write/verify mode. In normal operation mode, connect directly to VDD. — — Apply +12.5 V in PROM write/verify mode. VDD — — Positive power supply — — VSS — — Ground — — Notes 1. Circuit types in brackets indicate Schmitt trigger input. 2. During normal operation, the VPP pin will not operate normally unless connected to VDD pin. 8 µPD75P4308 3.3 Pin I/O Circuits The equivalent circuits for the µPD75P4308’s pin are shown in simplified schematic diagrams below. (1/2) TYPE A TYPE D VDD VDD Data P-ch OUT P-ch IN Output disable N-ch CMOS standard input buffer TYPE B N-ch Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). TYPE E-B VDD P.U.R. P.U.R. enable IN P-ch Data IN/OUT Type D Output disable Type A Schmitt trigger input with hysteresis characteristics. P.U.R.: Pull-Up Resistor TYPE B-C TYPE F-A VDD VDD P.U.R. P-ch P.U.R. P.U.R. enable P.U.R. enable P-ch Data IN/OUT Type D IN Output disable P.U.R. : Pull-Up Resistor Schmitt trigger input with hysteresis characteristics. Type B P.U.R.: Pull-Up Resistor 9 µPD75P4308 (2/2) TYPE M-E TYPE F-B VDD IN/OUT P.U.R. P.U.R. enable Output disable (P) P-ch data N-ch (+13 V withstand voltage) output disable VDD VDD Input instruction P-ch P-ch IN/OUT P.U.R.Note Data Output disable N-ch Voltage limitation (+13 V circuit withstand voltage) Output disable (N) Note P.U.R.: Pull-Up Resistor 10 Pull-up resistor that operates only when an input instruction has been executed (current flows from VDD to the pin when the pin is low). µPD75P4308 3.4 Recommended Connection of Unused Pins Pin Recommended connection P00/INT4 Connect to VSS or VDD. P01/SCK Connect individually to VSS or VDD via a resistor. P02/SO/SB0 P03/SI Connecto to VSS. P10/INT0 to P12/INT2 Connect to VSS or VDD. P13/TI0/TI1 P20/PTO0 P21/PTO1 P22/PCL Input mode : connect individually to VSS or VDD via a resistor. Output mode: open P23 P30/MD0 to P33/MD3 P50 to P53 Connect to VSS. P60/KR0 to P63/KR3 Input mode : connect individually to VSS or VDD P70/KR4 to P73/KR7 P80, P81 VPP via a resistor. Output mode: open Be sure to connect directly to VDD. 11 µPD75P4308 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE Setting a stack bank selection (SBS) register for the µPD75P4308 enables the program memory to be switched between the Mk I mode and the Mk II mode. This capability enables the evaluation of the µPD754302 or 754304 using the µPD75P4308. When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of µPD754302 and 754304) When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of µPD754302 and 754304) 4.1 Differences between Mk I Mode and Mk II Mode Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the µPD75P4308. Table 4-1. Differences between Mk I Mode and Mk II Mode Item Mk I Mode Mk II Mode Program counter PC12-0 Program memory (bytes) 8192 Data memory (bits) 256 × 4 Stack Stack bank Memory bank 0 Stack bytes 2 bytes 3 bytes Instruction BRA !addr1 CALLA !addr1 Not provided Provided Instruction CALL !addr 3 machine cycles 4 machine cycles execution time CALLF !faddr 2 machine cycles 3 machine cycles Supported mask ROM versions Mk I mode of µPD754302 and 754304 Mk II mode of µPD754302 and 754304 Caution The Mk II mode supports 16 Kbytes or more of program area in the 75X and 75XL Series. This mode allows the software compatibility with 16-Kbyte or more versions to be improved. Compared with the Mk I mode, selecting the Mk II mode increases the stack bytes by one during execution of the subroutine call instruction. When a CALL !addr or CALLF !faddr instruction is used, the instruction execution time increases by one machine cycle. Therefore, if RAM efficiency or throughput is more important than software compatibility, use the Mk I mode. 12 µPD75P4308 4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 1000B at the beginning of the program. When using the Mk II mode, be sure to initialize it to 0000B. Figure 4-1. Format of Stack Bank Selection Register Address F84H 3 2 1 0 SBS3 SBS2 SBS1 SBS0 Symbol SBS Stack area specification 0 0 Memory bank 0 Setting prohibited other than above 0 Be sure to enter “0” for bit 2. Mode selection specification 0 Mk II mode 1 Mk I mode Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When using instructions for the Mk II mode, set SBS3 to “0” to enter the Mk II mode before using the instructions. 2. When using the Mk II mode, execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register. 13 µPD75P4308 5. DIFFERENCES BETWEEN µPD75P4308 AND µPD754302, 754304 The µPD75P4308 replaces the internal mask ROM in the µPD754302 and 754304 with a one-time PROM and features expanded ROM capacity. The µPD75P4308’s Mk I mode supports the Mk I mode in the µPD754302 and 754304 and the µPD75P4308’s Mk II mode supports the Mk II mode in the µPD754302 and 754304. Table 5-1 lists differences among the µPD75P4308 and the µPD754302 and 754304. Be sure to check the differences between corresponding versions beforehand, especially when a PROM version is used for debugging or prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production. For details of CPU functions and incorporated hardware, refer to µPD754304 User’s Manual (U10123E). Table 5-1. Differences between µPD75P4308 and µPD754302, 754304 µPD754302 Item µPD754304 µPD75P4308 Program counter 11-bit 12-bit 13-bit Program memory (bytes) Mask ROM Mask ROM One-time PROM 2048 4096 8192 Data memory (× 4 bits) 256 Mask options Yes (On-chip/not on-chip specifiable) No (On-chip not possible) Yes (Selectable from 217/fX and 215/fX)Note No (fixed at 215/f X)Note Pins 5 to 8 P33-P30 P33/MD3-P30/MD0 Pin 19 IC VPP Pins 29 to 32 P63/KR3-P60/KR0 P63/KR3/D3P60/KR0/D0 Pins 33 to 36 P53-P50 P53/D7-P50/D4 Pull-up resistor for PORT5 Wait time in RESET state Pin configuration Other Noise resistance and noise radiation may differ due to the different circuit complexities and mask layouts. Note 217/fX: 21.8 ms @6.0-MHz operation, 31.3 ms @4.19-MHz operation. 215/fX: 5.46 ms @6.0-MHz operation, 7.81 ms @4.19-MHz operation. Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using a mask ROM version instead of the PROM version for processes between prototype development and full production, be sure to fully evaluate the CS (not ES) of the mask ROM version. 14 µPD75P4308 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map 7 0000H 6 MBE RBE 5 0 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE 0 INT0 start address (upper 5 bits) CALLF !faddr instruction entry address INT0 start address (lower 8 bits) 0006H MBE RBE 0 INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) 0008H MBE RBE 0 INTCSI start address (upper 5 bits) BRCB !caddr instruction branch address INTCSI start address (lower 8 bits) 000AH MBE RBE 0 INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) 000CH MBE RBE 0 INTT1 start address (upper 5 bits) INTT1 start address (lower 8 bits) Branch address for the following instructions • BR BCDE • BR BCXA • BR !addr • CALL !addr • BRA !addr1Note • CALLA !addr1 Note Branch/call address by GETI 0020H Reference table for GETI instruction 007FH 0080H BR $addr instruction relative branch address (–15 to –1, +2 to +16) 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH Note Can be used only in the Mk II mode. Remark For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to branch to addresses with changes in the PC’s lower 8 bits only. 15 µPD75P4308 Figure 6-2. Data Memory Map Data memory General register area Memory bank 000H (32 × 4) 01FH 020H Data area static RAM (256 × 4) 0 Stack area 256 × 4 (224 × 4) 0FFH Not incorporated F80H 128 × 4 Peripheral hardware area FFFH 16 15 µPD75P4308 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further description, refer to RA75X Assembler Package User’s Manual Language (EEU-1363)). When there are several codes, select and use just one. Uppercase letters, and + and – symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Instead of mem, fmem, pmem, bit, etc., a register flag symbol can be described as a label descriptor (for details, refer to µPD754304 User’s Manual (U10123E)). Labels that can be entered for fmem and pmem are restricted. Representation Coding format reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp’ rp’1 XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA’, BC’, DE’, HL’ BC, DE, HL, XA’, BC’, DE’, HL’ rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or labelNote 2-bit immediate data or label fmem pmem FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label addr 0000H-1FFFH immediate data or label addr1 0000H-1FFFH immediate data or label (in Mk II mode only) caddr faddr taddr 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (however, bit0 = 0) or label PORTn IE××× RBn MBn IEBT, IECSI, IET0, IET1, IE0-IE2, IE4 RB0-RB3 MB0, MB15 PORT0-PORT3, PORT5-PORT8 Note When processing 8-bit data, only even addresses can be specified. 17 µPD75P4308 (2) Operation legend A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC) DE : Register pair (DE) HL : Register pair (HL) XA’ : Expansion register pair (XA’) BC’ : Expansion register pair (BC’) DE’ : Expansion register pair (DE’) HL’ : Expansion register pair (HL’) PC : Program counter SP : Stack pointer CY : Carry flag; bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 to 3, 5 to 8) 18 IME : Interrupt master enable flag IPS : Interrupt priority select register IE××× : Interrupt enable flag RBS : Register bank select register MBS : Memory bank select register PCC : Processor clock control register . : Delimiter for address and bit (××) : Contents of address ×× ××H : Hexadecimal data µPD75P4308 (3) Description of symbols used in addressing area *1 MB = MBE·MBS (MBS = 0, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS Data memory addressing (MBS = 0, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr, addr1 = 0000H-1FFFH *7 addr, addr1 = (Current PC) –15 to (Current PC) –1 (Current PC) +2 to (Current PC) +16 *8 caddr = 0000H-0FFFH (PC12 = 0) or 1000H-1FFFH (PC12 = 1) *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH *11 addr1 = 0000H-1FFFH (Mk II mode only) Program memory addressing Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas. 19 µPD75P4308 (4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. • No skip ················································································ S = 0 • Skipped instruction is 1-byte or 2-byte instruction ············ S = 1 • Skipped instruction is 3-byte instructionNote ······················· S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle. One machine cycle equals one cycle (= tCY) of the CPU clock Φ. Use the PCC setting to select among four cycle times. 20 µPD75P4308 Group Transfer Mnemonic MOV XCH Table reference MOVT Operand No. of Machine bytes cycle Operation Addressing Skip condition area A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String-effect A HL, #n8 2 2 HL ← n8 String-effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L + 1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L – 1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg1 2 2 A ← reg1 XA, rp’ 2 2 XA ← rp’ reg1, A 2 2 reg1 ← A rp’1, XA 2 2 rp’1 ← XA A, @HL 1 1 A ←→ (HL) *1 A, @HL+ 1 2+S A ←→ (HL), then L ← L + 1 *1 L=0 A, @HL– 1 2+S A ←→ (HL), then L ← L – 1 *1 L = FH A, @rpa1 1 1 A ←→ (rpa1) *2 XA, @HL 2 2 XA ←→ (HL) *1 A, mem 2 2 A ←→ (mem) *3 XA, mem 2 2 XA ←→ (mem) *3 A, reg1 1 1 A ←→ reg1 XA, rp’ 2 2 XA ←→ rp’ XA, @PCDE 1 3 XA ← (PC12 - 8 + DE)ROM XA, @PCXA 1 3 XA ← (PC12 - 8 + XA)ROM XA, @BCDE 1 3 XA ← (BCDE)ROMNote *6 XA, @BCXA 1 3 XA ← (BCXA)ROMNote *6 String-effect A Note As for the B register, only the lower 1 bit is valid. 21 µPD75P4308 Group Bit transfer Operation Mnemonic MOV1 ADDS ADDC SUBS SUBC AND OR XOR 22 Operand No. of Machine bytes cycle Operation Addressing Skip condition area CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7 - 2 + L3 - 2.bit (L1 - 0)) *5 CY, @H + mem.bit 2 2 CY ← (H + mem3 - 0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7 - 2 + L3 - 2.bit (L1 - 0)) ← CY *5 @H + mem.bit, CY 2 2 (H + mem3 - 0.bit) ← CY *1 A, #n4 1 1+S A ← A + n4 carry XA, #n8 2 2+S XA ← XA + n8 carry A, @HL 1 1+S A ← A + (HL) XA, rp’ 2 2+S XA ← XA + rp’ carry rp’1, XA 2 2+S rp’1 ← rp’1 + XA carry A, @HL 1 1 A, CY ← A + (HL) + CY XA, rp’ 2 2 XA, CY ← XA + rp’ + CY rp’1, XA 2 2 rp’1, CY ← rp’1 + XA + CY A, @HL 1 1+S A ← A – (HL) XA, rp’ 2 2+S XA ← XA – rp’ borrow rp’1, XA 2 2+S rp’1 ← rp’1 – XA borrow A, @HL 1 1 A, CY ← A – (HL) – CY XA, rp’ 2 2 XA, CY ← XA – rp’ – CY rp’1, XA 2 2 rp’1, CY ← rp’1 – XA – CY A, #n4 2 2 A ← A ^ n4 A, @HL 1 1 A ← A ^ (HL) XA, rp’ 2 2 XA ← XA ^ rp’ rp’1, XA 2 2 rp’1 ← rp’1 ^ XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp’ 2 2 XA ← XA v rp’ rp’1, XA 2 2 rp’1 ← rp’1 v XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp’ 2 2 XA ← XA v rp’ rp’1, XA 2 2 rp’1 ← rp’1 v XA *1 carry *1 *1 *1 *1 *1 *1 borrow µPD75P4308 Group Mnemonic Operand No. of Machine bytes cycle Operation Addressing Skip condition area Accumulator RORC A 1 1 CY ← A0, A3 ← CY, An - 1 ← An manipulate NOT A 2 2 A←A Increment/ INCS reg 1 1+S reg ← reg + 1 reg = 0 rp1 1 1+S rp1 ← rp1 + 1 rp1 = 00H @HL 2 2+S (HL) ← (HL) + 1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem) + 1 *3 (mem) = 0 reg 1 1+S reg ← reg – 1 reg = FH rp’ 2 2+S rp’ ← rp’ – 1 rp’ = FFH reg, #n4 2 2+S Skip if reg =n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp’ 2 2+S Skip if XA = rp’ XA = rp’ decrement DECS Compare SKE Carry flag SET1 CY 1 1 CY ← 1 manipulate CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 Skip if CY = 1 CY = 1 CY ← CY 23 µPD75P4308 Group Memory bit Mnemonic SET1 manipulate CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 24 Operand No. of Machine bytes cycle Operation Addressing Skip condition area mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem.@L 2 2 (pmem7 - 2 + L3 - 2.bit(L1 - 0)) ← 1 *5 @H + mem.bit 2 2 (H+mem3 - 0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem7 - 2 + L3 - 2.bit(L1 - 0)) ← 0 *5 @H + mem.bit 2 2 (H+mem3 - 0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit)=1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7 - 2 + L3 - 2 .bit(L1 - 0 )) = 1 *5 (pmem.@L) = 1 @H + mem.bit 2 2+S Skip if (H + mem 3 - 0.bit) = 1 *1 (@H + mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7 - 2 + L3 - 2 .bit(L1 - 0 )) = 0 *5 (pmem.@L) = 0 @H + mem.bit 2 2+S Skip if (H + mem 3 - 0.bit) = 0 *1 (@H + mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7 - 2 + L3 - 2.bit (L 1 - 0)) = 1 and clear *5 (pmem.@L) = 1 @H + mem.bit 2 2+S Skip if (H + mem 3 - 0.bit) = 1 and clear *1 (@H + mem.bit) = 1 CY, fmem.bit 2 2 CY ← CY ^ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ^ (pmem7 - 2 + L3 - 2.bit(L1 - 0)) *5 CY, @H + mem.bit 2 2 CY ← CY ^ (H + mem 3 - 0.bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem 7 - 2 + L3 - 2.bit(L1 - 0)) *5 CY, @H + mem.bit 2 2 CY ← CY v (H + mem3 - 0 .bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem7 - 2 + L3 - 2.bit(L1 - 0)) *5 CY, @H + mem.bit 2 2 CY ← CY v (H + mem 3 - 0.bit) *1 µPD75P4308 Group Branch Mnemonic BRNote1 BRA Note 1 BRCB Operand No. of Machine bytes cycle Operation Addressing Skip condition area addr — — PC12 - 0 ← addr Assembler selects the most appropriate instruction among the following: • BR !addr • BRCB !caddr • BR $addr *6 addr1 — — PC12 - 0 ← addr1 Assembler selects the most appropriate instruction among the following: • BRA !addr1 • BR !addr • BRCB !caddr • BR $addr1 *11 !addr 3 3 PC12 - 0 ← addr *6 $addr 1 2 PC12 - 0 ← addr *7 $addr1 1 2 PC12 - 0 ← addr1 PCDE 2 3 PC12 - 0 ← PC12 - 8 + DE PCXA 2 3 PC12 - 0 ← PC12 - 8 + XA BCDE 2 3 PC12 - 0 ← BCDENote 2 *6 *6 BCXA 2 3 PC12 - 0 ← BCXA !addr1 3 3 PC12 - 0 ← addr1 *11 !caddr 2 2 PC12 - 0 ← PC12 + caddr11 - 0 *8 Note 2 Notes 1. Shaded areas indicate support for the Mk II mode only. 2. Only the lower 2 bit in the B register is valid. 25 µPD75P4308 Group Mnemonic Subroutine CALLANote stack control CALL Note CALLFNote RETNote Operand No. of Machine bytes cycle Operation Addressing Skip condition area !addr1 3 3 (SP – 5) ← 0, 0, 0, PC12 (SP – 6) (SP – 3) (SP – 4) ← PC11 - 0 (SP – 2) ← ×, ×, MBE, RBE PC 12 - 0 ← addr1, SP ← SP – 6 *11 !addr 3 3 (SP –4) (SP – 1) (SP – 2) ← PC11 - 0 (SP – 3) ← MBE, RBE, 0, PC12 PC 12 - 0 ← addr, SP ← SP – 4 *6 4 (SP – 5) ← 0, 0, 0, PC12 (SP – 6) (SP – 3) (SP – 4) ← PC11 - 0 (SP – 2) ← ×, ×, MBE, RBE PC 12 - 0 ← addr, SP ← SP – 6 2 (SP – 4) (SP – 1) (SP – 2) ← PC11 - 0 (SP – 3) ← MBE, RBE, 0, PC12 PC 12 - 0 ← 00 + faddr, SP ← SP – 4 3 (SP – 5) ← 0, 0, 0, PC12 (SP – 6) (SP – 3) (SP – 4) ← PC11 - 0 (SP – 2) ← ×, ×, MBE, RBE PC 12 - 0 ← 00 + faddr, SP ← SP – 6 3 MBE, RBE, 0, PC12 ← (SP + 1) PC 11 - 0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 !faddr 2 1 *9 ×, ×, MBE, RBE ← (SP + 4) 0, 0, 0, PC 12 ← (SP + 1) PC 11 - 0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 6 RETSNote 1 3+S MBE, RBE, 0, PC12 ← (SP + 1) PC 11 - 0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 then skip unconditionally Unconditional ×, ×, MBE, RBE ← (SP + 4) 0, 0, 0, PC 12 ← (SP + 1) PC 11, 0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 6 then skip unconditionally RETI 1 3 MBE, RBE, 0, PC12 ← (SP + 1) PC 11 - 0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 0, 0, 0, PC 12 ← (SP + 1) PC 11 - 0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only. 26 µPD75P4308 Group Mnemonic Subroutine 1 (SP – 1) (SP – 2) ← rp, SP ← SP – 2 BS 2 2 (SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2 rp 1 1 rp ← (SP + 1) (SP), SP ← SP + 2 BS 2 2 MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2 2 2 IME (IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME (IPS.3) ← 0 IE××× 2 2 IE××× ← 0 A, PORTn 2 2 A ← PORTn XA, PORTn 2 2 XA ← PORTn + 1, PORTn PORTn, A 2 2 PORTn ← A PORTn, XA 2 2 PORTn + 1, PORTn ← XA HALT 2 2 Set HALT Mode(PCC.2 ← 1) STOP 2 2 Set STOP Mode(PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n (n = 0 - 3) MBn 2 2 MBS ← n (n = 0, 15) taddr 1 3 • When using TBR instruction PC12 - 0 ← (taddr)4 - 0 + (taddr + 1) EI control IE××× DI IN Note 1 Note 1 OUT CPU control Special Addressing Skip condition area Operation 1 POP I/O No. of Machine bytes cycle rp PUSH stack control Interrupt Operand SEL Note 2, 3 GETI (n = 0 - 3, 5 - 8) (n = 6) (n = 2 - 3, 5 - 8) (n = 6) *10 • When using TCALL instruction (SP – 4) (SP – 1) (SP – 2) ← PC11 - 0 (SP – 3) ← MBE, RBE, 0, PC12 PC12 - 0 ← (taddr) 4 - 0 + (taddr + 1) SP ← SP – 4 • When using instruction other than TBR or TCALL Determined by referenced Execute (taddr) (taddr + 1) instructions 1 • When using TBR instruction PC12 - 0 ← (taddr)4 - 0 + (taddr + 1) 4 • When using TCALL instruction (SP – 5) ← 0, 0, 0, PC12 (SP – 6) (SP – 3) (SP – 4) ← PC11 - 0 (SP – 2) ← ×, ×, MBE, RBE PC12 - 0 ← (taddr)4 - 0 + (taddr + 1) SP ← SP – 6 3 • When using instruction other than TBR or TCALL Execute (taddr) (taddr + 1) instructions instruction *10 Determined by referenced instruction Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15. 2. TBR and TCALL are assembler pseudo-instructions for the GETI instruction’s table definitions. 3. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only. 27 µPD75P4308 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The program memory in the µPD75P4308 is a 8192 × 8-bit electrically write-enabled one-time PROM. The pins listed in the table below are used for this one-time PROM’s write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating addresses. Pin name Function VPP Pin (usually VDD) where programming voltage is applied during program memory write/verify X1, X2 Clock input pin for address updating during program memory write/ verify. Input the X1 pin’s inverted signal to the X2 pin. MD0-MD3 Operation mode selection pin for program memory write/verify D0/P60/KR0-D3/P63/KR3 (lower 4) 8-bit data I/O pin for program memory write/verify D4/P50-D7/P53 (upper 4) VDD Pin where power supply voltage is applied. Power voltage range for normal operation is 1.8 to 5.5 V. Apply 6.0 V for program memory write/verify. Caution Pins not used for program memory write/verify connect to Vss via a pull-down resistor. 8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the µPD75P4308’s VDD pin and +12.5 V is applied to its VPP pin, program write/verify modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown below. Operation mode specification VDD MD0 MD1 MD2 MD3 +12.5 V +6 V H L H L Zero-clear program memory address L H H H Write mode L L H H Verify mode H × H H Program inhibit mode × : L or H 28 Operation mode VPP µPD75P4308 8.2 Program Memory Write Procedure High-speed program memory write can be executed via the following steps. (1) Pull down unused pins to VSS via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 µs. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V to VDD and +12.5 V to VPP. (6) Write data using 1-ms write mode. (7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7). (8) X [= number of write operations from steps (6) and (7)] × 1 ms additional write (9) 4 pulse inputs to the X1 pin updates (increments +1) the program memory address. (10) Repeat steps (6) to (9) until the last address is completed. (11) Zero-clear mode for program memory addresses. (12) Apply +5 V to the VDD and VPP pins. (13) Power supply OFF The following diagram illustrates steps (2) to (9). X repetitions Write Verify Additional write Address increment VPP VPP VDD VDD + 1 VDD VDD X1 D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 Data input Data output Data input MD0/P30 MD1/P31 MD2/P32 MD3/P33 29 µPD75P4308 8.3 Program Memory Read Procedure The µPD75P4308 can read out the program memory contents via the following steps. (1) Pull down unused pins to VSS via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 µs. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V to VDD and +12.5 V to VPP. (6) Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based on a cycle of four pulse inputs. (7) Zero-clear mode for program memory addresses. (8) Apply +5 V to the VDD and VPP pins. (9) Power supply OFF The following diagram illustrates steps (2) to (7). VPP VPP VDD VDD + 1 VDD VDD X1 D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 Data output MD0/P30 MD1/P31 MD2/P32 MD3/P33 30 “L” Data output µPD75P4308 8.4 One-Time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends the screening process, that is, after the required data is written to the PROM and the PROM is stored under the high-temperature conditions shown below, the PROM should be verified. Storage temperature Storage time 125˚C 24 hours 31 µPD75P4308 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25˚C) Parameter Symbol Conditions Ratings Unit Supply voltage V DD –0.3 to +7.0 V PROM supply voltage V PP –0.3 to +13.5 V Input voltage V I1 Other than port 5 –0.3 to VDD +0.3 V V I2 Port 5 (N-ch open-drain) –0.3 to +14 V –0.3 to VDD +0.3 V Per pin –10 mA Total for all pins –30 mA Per pin 30 mA Total for all pins 220 mA Output voltage VO High-level output current IOH Low-level output current IOL Operating ambient temperature TA –40 to +85 ˚C Storage temperature Tstg –65 to +150 ˚C Caution If the absolute maximum ratings of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. Be sure that these values are never exceeded when using the product. Capacitance (TA = 25˚C, VDD = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz 15 pF Output capacitance COUT Unmeasured pins returned to 0 V 15 pF I/O capacitance CIO 15 pF 32 µPD75P4308 System Clock Oscillation Circuit Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5. V) Resonator Recommended constants Parameter Ceramic resonator Conditions Oscillation frequency (f X)Note 1 X1 C2 Crystal resonator Oscillation stabilization timeNote 2 Unit 6.0Note 3 MHz 4 ms 6.0Note 3 MHz 10 ms 30 ms 1.0 6.0Note 3 MHz 83.3 500 ns After V DD has reached MIN. value of oscillation voltage range Oscillation frequency (f X)Note 1 1.0 X2 C1 C2 External clock Oscillation stabilization timeNote 2 VDD = 5.0 V ± 10 % X1 input frequency (f X)Note 1 X1 MAX. 1.0 TYP. X2 C1 X1 MIN. X2 X1 input high-, low-level widths (t XH, tXL) Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. 3. When the oscillation frequency fX satisfies 4.19 MHz < fX ≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, do not set PCC = 0011 as an instruction execution time. If PCC = 0011 is selected, one machine cycle takes less than 0.95 µs, and the MIN. value rating of 0.95 µs is not satisfied. Caution When using the system clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: · Keep the wiring length as short as possible. · Do not cross the wiring with other signal lines. · Do not route the wiring in the vicinity of a line through which a high alternating current flows. · Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. Do not ground to a ground pattern through which a high current flows. · Do not extract signals from the oscillation circuit. 33 µPD75P4308 Recommended Oscillation Circuit Constant Ceramic Resonator (TA = –40 to +85˚C) Manufacturer Product name Recommended Oscillation voltage Frequency circuit constant (pF) range (VDD) (MHz) C1 C2 MIN. MAX. CSB1000JNote 1.0 100 100 2.6 5.5 Manufacturing CSA2.00MG 2.0 30 30 1.8 5.5 Co., Ltd. CST2.00MG — — 3.58 30 30 1.8 5.5 CST3.58MGW — — CSA3.58MGU 30 30 CST3.58MGWU — — Murata CSA3.58MG 30 30 CST4.00MGW — — CSA4.00MGU 30 30 CST4.00MGWU — — CSA4.00MG 4.0 30 30 CST4.19MGW — — CSA4.19MGU 30 30 CST4.19MGWU — — 30 30 CST6.00MGW — — CSA6.00MGU 30 30 CSA4.19MG CSA6.00MG 4.19 6.0 Rd = 5.6 kΩ On-chip capacitor On-chip capacitor 1.8 On-chip capacitor 2.0 5.5 On-chip capacitor 1.8 On-chip capacitor 1.9 5.5 On-chip capacitor 1.8 On-chip capacitor 2.9 5.5 On-chip capacitor 2.0 — — KBR-1000F/Y 1.0 100 100 1.8 5.5 KBR-2.0MS 2.0 47 47 2.4 5.5 KBR-4.0MSA 4.0 33 33 1.8 5.5 CST6.00MGWU Kyocera Corp. Remark On-chip capacitor TA = –20 to +80˚C KBR-4.0MKS — — On-chip capacitor, TA = –20 to +80˚C PBRC4.00A 33 33 TA = –20 to +80˚C — — 33 33 KBR-4.19MKS — — On-chip capacitor, TA = –20 to +80˚C PBRC4.19A 33 33 TA = –20 to +80˚C PBRC4.19B — — 33 33 KBR-6.0MKS — — On-chip capacitor, TA = –20 to +80˚C PBRC6.00A 33 33 TA = –20 to +80˚C PBRC6.00B — — On-chip capacitor, TA = –20 to +80˚C PBRC4.00B KBR-4.19MSA 4.19 On-chip capacitor, TA = –20 to +80˚C 1.8 5.5 TA = –20 to +80˚C KBR-4.19MSB KBR-6.0MSA 6.0 On-chip capacitor, TA = –20 to +80˚C 1.8 5.5 TA = –20 to +80˚C KBR-6.0MSB Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 34 µPD75P4308 Note When using a CSB1000J (1.0 MHz) of Murata Manufacturing Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 5.6 kΩ) is necessary (See diagram below). When using any other recommended resistor, it is not necessary. X1 X2 CSB1000J C1 Rd C2 35 µPD75P4308 DC Characteristics (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Low-level Symbol IOL output current High-level input VIH1 Conditions MAX. Unit Per pin 15 mA Total for all pins 150 mA VIH3 Low-level input 0.7 VDD VDD V 1.8 V ≤ V DD < 2.7 V 0.9 V DD VDD V 2.7 V ≤ V DD ≤ 5.5 V 0.8 VDD VDD V 1.8 V ≤ V DD < 2.7 V 0.9 V DD VDD V Port 5 2.7 V ≤ V DD ≤ 5.5 V 0.7 VDD 13 V (N-ch open-drain) 1.8 V ≤ V DD < 2.7 V 0.9 V DD 13 V V DD–0.1 VDD V 2.7 V ≤ V DD ≤ 5.5 V 0 0.3 VDD V 1.8 V ≤ V DD < 2.7 V 0 0.1 V DD V 2.7 V ≤ V DD ≤ 5.5 V 0 0.2 VDD V 1.8 V ≤ V DD < 2.7 V 0 0.1 V DD V 0 0.1 V Ports 0, 1, 6, 7, RESET VIH4 X1 VIL1 Ports 2, 3, 5, 8 voltage VIL2 TYP. 2.7 V ≤ V DD ≤ 5.5 V Ports 2, 3, 8 voltage VIH2 MIN. Ports 0, 1, 6, 7, RESET VIL3 X1 High-level output voltage VOH SCK, SO, Ports 2, 3, 6 to 8 Low-level output voltage VOL1 SCK, SO, Ports 2, 3, 5 to 8 IOH = –1 mA IOL = 15 mA, VDD = 5.0 V ± 10 % V DD–0.5 V 0.2 IOL = 1.6 mA 2.0 V 0.4 V 0.2 VDD V VOL2 SB0 N-ch open-drain Pull-up resistor ≥ 1 kΩ High-level input ILIH1 VI = V DD Pins other than port 5 and X1 3 µA leakage current ILIH2 X1 20 µA ILIH3 VI = 13 V Port 5 (N-ch open-drain) 20 µA Low-level input ILIL1 VI = 0 V Pins other than port 5 and X1 –3 µA leakage current ILIL2 X1 –20 µA ILIL3 Port 5 (N-ch open-drain) Other than the input instruction execution time –3 µA –30 µA Port 5 (N-ch open-drain) At the input instruction execution time 36 VDD = 5.0 V –10 –27 µA VDD = 3.0 V –3 –8 µA µPD75P4308 DC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit High-level output I LOH1 VO = V DD SCK, SO/SB0, Ports 2, 3, 6 to 8 3 µA leakage current I LOH2 VO = 13 V Port 5 (N-ch open-drain) 20 µA Low-level output leakage current I LOL VO = 0 V –3 µA On-chip pull-up resistor RL VI = 0 V 100 200 kΩ Supply current Note 1 I DD1 6.0 MHz crystal oscillation C1 = C2 = 22 pF VDD = 5.0 V ± 10 %Note 2 2.20 7.00 mA VDD = 3.0 V ± 10 %Note 3 0.43 1.30 mA 4.19 MHz crystal oscillation C1 = C2 = 22 pF I DD2 I DD1 I DD2 I DD5 Ports 0 to 3, 6 to 8 (except P00 pin) 50 HALT VDD = 5.0 V ± 10 % 0.53 1.60 mA mode VDD = 3.0 V ± 10 % 0.21 0.70 mA VDD = 5.0 V ± 10 % Note 2 1.70 5.10 mA VDD = 3.0 V ± 10 % Note 3 0.35 1.10 mA HALT VDD = 5.0 V ± 10 % 0.51 1.60 mA mode VDD = 3.0 V ± 10 % 0.19 0.60 mA STOP VDD = 5.0 V ± 10 % 0.05 10.0 µA mode VDD = 3.0 V ± 10 % 0.02 5.00 µA 0.02 3.00 µA T A = 25˚C Notes 1. The current flowing through the on-chip pull-up resistor is not included. 2. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 3. When the device operates in low-speed mode with PCC set to 0000. 37 µPD75P4308 AC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter Symbol CPU clock cycle time Note 1 (minimum instruction execution time = 1 machine cycle) tCY TI0, TI1 input frequency fTI TI0, TI1 input high-, Conditions Operates with MIN. VDD = 2.7 to 5.5 V system clock tTIH, tTIL RESET low-level width tINTH, t INTL Unit 0.67 64 µs 0.95 64 µs 0 1 MHz 0 275 kHz 0.48 µs 1.8 µs IM02 = 0 Note 2 µs IM02 = 1 10 VDD = 2.7 to 5.5 V low-level widths Interrupt input high-, low-level widths MAX. VDD = 2.7 to 5.5 V INT0 TYP. INT1, 2, 4 10 µs KR0-7 10 µs 10 µs tRSL Notes 1. The cycle time (minimum instruction tCY vs VDD execution time) of the CPU clock (Φ) is (with system clock) determined by the oscillation frequency 64 60 of the connected resonator and processor clock control register (PCC). The figure on the right shows the supply 6 voltage V DD vs. cycle time tCY character- 5 system clock. 2. 2t CY or 128/fX depending on the setting of the interrupt mode register (IM0). Operation guaranteed range Cycle time tCY [ µ s] istics when the device operates with the 4 3 2 1 0.5 0 1 2 3 4 5 Supply voltage VDD [V] 38 6 µPD75P4308 Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol t KCY1 SCK high-, low-level t KL1, tKH1 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V widths SI Note 1 SI Note 1 setup time (to SCK ↑) t SIK1 hold time (from SCK ↑) t KSI1 SCK ↓ → SO Note 1 output t KSO1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V RL = 1 kΩ, VDD = 2.7 to 5.5 V CL = 100 pFNote 2 delay time MIN. TYP. MAX. Unit 1300 ns 3800 ns tKCY1/2–50 ns tKCY1/2–150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns Notes 1. In the 2-wire serial I/O mode, read SB0 instead. 2. RL and CL are the load resistance and load capacitance of the SO output line. 2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high-, low-level Symbol t KCY2 t KL2, tKH2 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V widths SI Note 1 SI Note 1 setup time (to SCK ↑) t SIK2 hold time (from SCK ↑) t KSI2 SCK ↓ → SONote 1 output delay time t KSO2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V RL = 1 kΩ, CL = 100 pFNote 2 VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns Notes 1. In the 2-wire serial I/O mode, read SB0 instead. 2. RL and CL are the load resistance and load capacitance of the SO output line. 39 µPD75P4308 AC timing test points (except X1 input) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock timing 1/fX tXL tXH VDD – 0.1 V X1 input 0.1 V TI0, TI1 timing 1/fTI tTIL TI0, TI1 40 tTIH µPD75P4308 Serial transfer timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 Input data SI tKSO1, 2 Output data SO 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0 tKSO1, 2 41 µPD75P4308 Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET input timing tRSL RESET Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = –40 to +85˚C) Parameter Symbol Release signal set time Conditions MIN. tSREL Oscillation stabilization TYP. tWAIT Released by RESET Released by interrupt request Unit µs 0 wait timeNote 1 MAX. 215/f x ms Note 2 ms Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Set by the basic interval timer mode register (BTM). (Refer to the table below.) Wait time BTM3 – – – – 42 BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 f X = 4.19 MHz 0 220/fX 1 217/fX 1 215/fX 1 213/fX fX = 6.0 MHz (approx. 250 ms) 220/f X (approx. 175 ms) (approx. 31.3 ms) 217/f X (approx. 21.8 ms) (approx. 7.81 ms) 215/f X (approx. 5.46 ms) (approx. 1.95 ms) 213/f X (approx. 1.37 ms) µPD75P4308 Data retention timing (when STOP mode released by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data retention timing (standby release signal: when STOP mode released by interrupt signal) HALT mode STOP mode Operation mode Data retention mode VDDDR VDD tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 43 µPD75P4308 DC Programming Characteristics (TA = 25 ± 5˚C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0V) Parameter High-level input voltage Symbol Conditions MIN. MAX. Unit VDD V VDD–0.5 VDD V 0 0.3 VDD V 0 0.4 V 10 µA 0.4 V 30 mA 30 mA VIH1 Other than X1, X2 0.7 VDD VIH2 X1, X2 VIL1 Other than X1, X2 VIL2 X1, X2 ILI VIN = VIL or VIH High-level output voltage VOH IOH = – 1 mA Low-level output voltage VOL IOL = 1.6 mA Low-level input voltage Input leakage current VDD supply current IDD VPP supply current IPP TYP. VDD–1.0 V MD0 = VIL, MD1 = VIH Cautions 1. Keep VPP to within +13.5 V, including overshoot. 2. Apply VDD before VPP and turn it off after VPP. AC Programming Characteristics (TA = 25 ± 5˚C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) Parameter Symbol Note 1 tAS tAS 2 µs MD1 setup time (to MD0 ↓) tM1S tOES 2 µs Data setup time (to MD0 ↓) tDS tDS 2 µs tAH tAH 2 µs Address setup time (to MD0 ↓) Address hold time (from MD0 ↑) Note 2 Note 2 Conditions MIN. Data hold time (from MD0 ↑) tDH tDH 2 MD0 ↑ → data output float delay time tDF tDF 0 VPP setup time (to MD3 ↑) tVPS tVPS 2 VDD setup time (to MD3 ↑) tVDS tVCS 2 Initial program pulse width tPW tPW 0.95 Additional program pulse width tOPW tOPW 0.95 MD0 setup time (to MD1 ↑) tM0S tCES 2 TYP. MAX. Unit µs 130 ns µs µs 1.0 1.05 ms 21.0 ms µs µs MD0 ↓ → data output delay time tDV tDV MD0 = MD1 = VIL MD1 hold time (from MD0 ↑) tM1H tOEH tM1H + tM1R ≥ 50 µs MD1 recovery time (from MD0 ↓) tM1R tOR Program counter reset time tPCR — X1 input high-, low-level widths tXH, tXL — 0.125 X1 input frequency fX — Initial mode set time tI — 2 µs MD3 setup time (to MD1 ↑) tM3S — 2 µs MD3 hold time (from MD1 ↓) tM3H — 2 µs MD3 setup time (to MD0 ↓) tM3SR — 2 µs 1 2 µs 2 µs 10 µs When program memory is read → data output tDAD tACC When program memory is read AddressNote 2 → data output hold time tHAD tOH When program memory is read 0 MD3 hold time (from MD0 ↑) tM3HR — When program memory is read 2 MD3 ↓ → data output float delay time tDFR — When program memory is read Note 2 Address delay time Notes 1. 2. MHz 2 µs 130 ns µs 2 µs Symbol of corresponding µPD27C256A The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not connected to a pin. 44 µs 4.19 µPD75P4308 Program Memory Write Timing tVPS VPP VPP VDD VDD VDD+1 VDD tVDS tXH X1 D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 tXL Data input Data output Data input tDS tI tDS tDH tDV Data input tDH tDF tAH tAS MD0/P30 tPW tM1R tM0S tOPW MD1/P31 tPCR tM1S tM1H MD2/P32 tM3S tM3H MD3/P33 Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD+1 VDD tXH VDD X1 tXL tDAD tHAD D0/P60/KR0D3/P63/KR3 D4/P50D7/P53 Data output Data output tDV tI tDFR tM3HR MD0/P30 MD1/P31 tPCR MD2/P32 tM3SR MD3/P33 45 µPD75P4308 10. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) IDD vs VDD (System clock: 6.0 MHz crystal resonator) (TA = 25˚C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 System clock HALT mode Supply Current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 6.0 MHz 22 pF 22 pF 0.001 0 46 1 2 3 4 5 Supply Voltage VDD (V) 6 7 8 µPD75P4308 IDD vs VDD (System clock: 4.19 MHz crystal resonator) (TA = 25˚C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 System clock HALT mode Supply Current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 4.19 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 Supply Voltage VDD (V) 6 7 8 47 µPD75P4308 11. PACKAGE DRAWINGS 36 PIN PLASTIC SHRINK SOP (300 mil) 19 1 detail of lead end 5°±5° 36 18 A H J E K F G I C N D L B M M P36GM-80-300B-3 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 48 ITEM MILLIMETERS INCHES A 15.54 MAX. 0.612 MAX. B 0.97 MAX. 0.039 MAX. C 0.8 (T.P.) 0.031 (T.P.) D +0.10 0.35 –0.05 0.014+0.004 –0.003 E 0.125 ±0.075 0.005 ±0.003 F 1.8 MAX. 0.071 MAX. G 1.55 0.061 H 7.7 ±0.3 0.303 ±0.012 I 5.6 0.220 J 1.1 0.043 K 0.20 +0.10 –0.05 0.008+0.004 –0.002 L 0.6 ±0.2 0.024 –0.009 M 0.10 0.004 N 0.10 0.004 +0.008 µPD75P4308 12. RECOMMENDED SOLDERING CONDITIONS Solder the µPD75P4308 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 12-1. Soldering Conditions of Surface Mount Type µPD75P4308GS: 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) Soldering method Soldering conditions Symbol Infrared reflow Package peak temperature: 235˚C, Reflow time: 30 seconds or below (210˚C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125˚C for 10 hours) IR35-107-2 VPS Package peak temperature: 215˚C, Reflow time: 40 seconds or below (200˚C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (after that, prebaking is necessary at 125˚C for 10 hours) VP15-107-2 Wave soldering Solder temperature: 260˚C or below, Flow time: 10 seconds or below, Number of flow processes: 1 Preheating temperature: 120˚C or below (package surface temperature) Exposure limit: 7 daysNote (after that, prebaking is necessary at 125˚C for 10 hours) WS60-107-1 Pin partial heating Pin temperature: 300˚C or below, Time: 3 seconds or below (per side of device) – Note The number of days for storage after the dry pack has been opened. Storage conditions are 25˚C and 65% RH max. Caution Do not use two or more soldering methods in combination (except the pin partial heating method). 49 µPD75P4308 APPENDIX A. COMPARISON OF µPD750004, 754304, AND 75P4308 FUNCTIONS (1/2) µPD750004 Item µPD754304 Program memory Mask ROM 0000H-0FFFH (4096 × 8 bits) Mask ROM 0000H-0FFFH (4096 × 8 bits) Data memory 000H-1FFH (512 × 4 bits) 000H-0FFH (256 × 4 bits) CPU 75XL CPU µPD75P4308 One-time PROM 0000H-1FFFH (8192 × 8 bits) When main system clock is selected • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz) • 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz) When subsystem clock is selected 122 µs (@ 32.768 kHz) CMOS input 8 (connections of on-chip pull-up resistors are software-specifiable: 7) CMOS I/O 18 (connections of on-chip pull-up resistors are software-specifiable) N-ch open-drain I/O (13-V withstand) 8 (on-chip pull-up resistors 4 (on-chip pull-up resistors 4 (No mask option) are specified by mask option) are specified by mask option) Total 34 30 (No port 4 pin) Timers 4 channels • Basic interval timer/ watchdog timer • 8-bit timer/event counter • 8-bit timer • Watch timer 3 channels • Basic interval timer/watchdog timer • 8-bit timer/event counter 0 (fx/22 added) • 8-bit timer/event counter 1 (TI1, fx/22 added) (Can be used as a 16-bit timer/event counter) Clock output (PCL) • Φ, 524, 262, 65.5 kHz (main system clock: @ 4.19 MHz) • Φ, 750, 375, 93.8 kHz (main system clock: @ 6.0 MHz) BUZ output Yes No Serial interface Can support three modes • 3-wire serial I/O mode ...MSB/LSB-first switchable • 2-wire serial I/O mode • SBI mode Can support two modes • 3-wire serial I/O mode...MSB/LSB-first switchable • 2-wire serial I/O mode Watch mode register (WM) Yes No Instruction execution time I/O ports System clock control register (SCC) Sub-oscillator control register (SOS) 50 No subsystem clock µPD75P4308 (2/2) µPD750004 µPD754304 Memory bank select register (MBS) Selectable from memory Fixed at memory bank 0 Stack bank select register (SBS) banks 0 and 1 Timer/event counter mode register (TM0, TM1) Bits 0, 1, and 7 are fixed at 0 Vectored interrupts External: 3, Internal: 4 Test inputs External: 1, Internal: 1 External: 1 Test enable flag (IEW) Yes No Power supply voltage VDD = 2.2 to 5.5 V VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85˚C Package • 42-pin plastic shrink DIP (600 mil) • 44-pin plastic QFP (10 × 10 mm) Item µPD75P4308 – Test request flag (IRQW) • 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) 51 µPD75P4308 APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the µPD75P4308. In the 75XL series, the common relocatable assembler is used together with the device file of each model. RA75X relocatable assembler Host machine OS PC-9800 Series MS-DOSTM Ver.3.30 to Ver.6.2Note Device file Supply medium Part No. (name) 3.5" 2HD µS5A13RA75X 5" 2HD µS5A10RA75X IBM PC/ATTM Refer to OS for 3.5" 2HC µS7B13RA75X or compatible IBM PCs 5" 2HC µS7B10RA75X Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note Supply medium Part No. (name) 3.5" 2HD µS5A13DF754304 5" 2HD µS5A10DF754304 IBM PC/AT Refer to OS for 3.5" 2HC µS7B13DF754304 or compatible IBM PCs 5" 2HC µS7B10DF754304 Note Ver. 5.00 and above include a task swapping function, but this software is not able to use that function. Remark Operations of the assembler and the device file are guaranteed only when using the host machine and OS described above. 52 µPD75P4308 PROM Write Tools Hardware Software PG-1500 A stand-alone system can be configured of a single-chip microcontroller with on-chip PROM when connected to an auxiliary board (attached) and a programmer adapter (separately sold). Alternatively, a PROM programmer can be operated on a host machine for programming. In addition, typical PROMs in capacities ranging from 256 K to 4 Mbits can be programmed. PA-75P4308GS This is a PROM programmer adapter for the µPD75P4308GS. It can be used when connected to a PG-1500. PG-1500 controller Establishes serial and parallel connections between the PG-1500 and a host machine for hostmachine control of the PG-1500. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note Supply medium Part No. (name) 3.5" 2HD µS5A13PG1500 5" 2HD µS5A10PG1500 IBM PC/AT Refer to OS for 3.5" 2HD µS7B13PG1500 or compatible IBM PCs 5" 2HC µS7B10PG1500 Note Ver. 5.00 and above include a task swapping function, but this software is not able to use that function. Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above. 53 µPD75P4308 Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P4308. Various system configurations using these in-circuit emulators are listed below. Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. For development of the µPD754304 subseries, the IE-75000-R is used with a separately sold emulation board (IE-75300-R-EM) and emulation probe (EP-754304GS-R). These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. The IE-75000-R can include a connected emulation board (IE-75000-R-EM). IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. The IE-75001-R is used with a separately sold emulation board (IE-75300-R-EM) and emulation probe (EP-754304GS-R). These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. IE-75300-R-EM This is an emulation board for evaluating application systems that use the µPD754304 subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator. EP-754304GS-R This is an emulation probe for the µPD75P4308. EV-9500GS-36 Software IE control program When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a flexible board (EV-9500GS-36) to facilitate connections with various target systems. This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Supply medium Part No. (name) 3.5" 2HD µS5A13IE75X 5" 2HD µS5A10IE75X Ver.6.2Note 2 IBM PC/AT Refer to OS for 3.5" 2HC µS7B13IE75X or compatible IBM PCs 5" 2HC µS7B10IE75X Notes 1. This is a service part provided for maintenance purpose only. 2. Ver. 5.00 and above include a task swapping function, but this software is not able to use that function. Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described above. 2. The µPD754302, 754304, and 75P4308 are commonly referred to as the µPD754304 subseries. 54 µPD75P4308 OS for IBM PCs The following operating systems for the IBM PC are supported. OS PC DOS TM Version Ver.5.02 to Ver.6.3 J6.1/V to J6.3/V MS-DOS Ver.5.0 to Ver.6.22 5.0/V to 6.2/V IBM DOSTM J5.02/V Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function. 55 µPD75P4308 APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Device Document Number Document Name Japanese English µPD754302, 754304 Data Sheet U10797J µPD75P4308 Data Sheet U10909J µPD754304 User’s Manual U10123J U10123E µPD754304 Instruction Table IEM-5605 — 75XL Series Selection Guide U10453J U10453E U10797E U10909E (this document) Documents Related to Development Tools Document Number Document Name Hardware Software Japanese English IE-75000-R/IE-75001-R User’s Manual EEU-846 EEU-1416 IE-75300-R-EM User’s Manual U11354J U11354E EP-754304GS-R User’s Manual U10677J U10677E PG-1500 User’s Manual EEU-651 EEU-1335 RA75X Assembler Package Operation EEU-731 EEU-1346 User’s Manual Language EEU-730 EEU-1363 PG-1500 Controller User’s Manual PC9800 Series (MS-DOS) base EEU-704 EEU-1291 IBM PC/AT Series (PC DOS) base EEU-5008 U10540E Other Related Documents Document Number Document Name Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 — Guide to Quality Assurance for Semiconductor Devices MEI-603 MEI-1202 Microcomputer-Related Product Guide –Third Party Products– U11416J — Caution The related documents listed above are subject to change without notice. Be sure to use the latest documents for designing, etc. 56 µPD75P4308 [MEMO] 57 µPD75P4308 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 58 µPD75P4308 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 59 µPD75P4308 MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard”, “Special”, and “Specific”. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program” for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5