DATA SHEET MOS INTEGRATED CIRCUIT µPD78217A,78218A 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µ PD78217A and 78218A are members of the 78K/II series of microcontrollers featuring a high-speed highperformance CPU. The µPD78217A and 78218A are based on the µPD78213 and 78214, and feature increased memory capacity and added functions, such as a timer/counter and macro servicing. Functions are described in detail in the following User’s Manuals, which should be read when carrying out design work. µPD78218A Subseries User’s Manual: Hardware (IEU-1313) 78K/II Series User’s Manual: Instruction (IEU-1311) FEATURES • Upper compatibility with µPD78214 subseries (pin-compatible) • • • • High-speed instruction execution (at 12 MHz): 333 ns (µPD78218A), 500 ns ( µPD78217A) On-chip high-performance interrupt controller On-chip A/D converter: 8 bits × 8 channels Number of I/O pins: 54 (µPD78218A), 36 (µ PD78217A) • Real-time output ports: 8 bits × 1 channel or 4 bits × 2 channels • Serial interface: 2 channels • Timer/counter: 16 bits × 1 channel and 8 bits × 3 channels APPLICATION FIELDS Printers, typewriters, OA equipment such as plain paper copiers (PPCs) and faxes, electronic music instruments, inverters, cameras, etc. ORDERING INFORMATION Part Number µPD78217ACW µPD78217AGC-AB8 µPD78218ACW-××× µPD78218AGC-×××-AB8 Remark Package 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic shrink DIP (750 mil) QFP (14 x 14 mm) shrink DIP (750 mil) QFP (14 x 14 mm) On-Chip ROM On-Chip RAM None None 32K 32K 1024 1024 1024 1024 ××× is the ROM code suffix. The information in this document is subject to change without notice. Document No. IC-2748E (O. D. No. IC-8131E) Date Published April 1995 P Printed in Japan The mark ★ shows revised points. © 1991 1992 µPD78217A, 78218A 78K/II Product Development On-Chip A/D and D/A Converters Additional PWM Output Function Improved Macro Service and Timer/Counter Comparator Deletion µPD78234 Subseries µPD78244 Subseries µPD78224 Subseries On-Chip D/A Converter Additional PWM Output Function Improved Macro Service and Timer/Counter Additional EEPROM Improved Macro Service and Timer/Counter On-Chip A/D Converter Improved Timer/Counter and Baud Rate Generator Function Comparator Deletion µPD78214 Subseries µPD78218A Subseries Expanded On-Chip Memory Capacity Improved Macro Service and Timer/Counter 2 µPD78218A(A) µPD78P218A µPD78218A µPD78217A µPD78217A, 78218A FUNCTION LIST Basic instructions (mnemonic) 65 Minimum instruction execution time 333 ns (at 12-MHz) Instruction set On-chip memory capacity 16-bit operation Multiply and divide (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulate BCD adjust, etc. ROM RAM Address space I/O pins Additional function pins Note µPD78218A µPD78217A Item None 32 Kbytes 1024 bytes Program memory: 64 Kbytes, data memory: 1 Mbytes Input 14 Output 12 Input/Output 10 28 Total 36 54 Pins with pull-up resistor 16 34 LED direct drive outputs — 16 Transistor direct drive outputs 8 ROM-less mode setting ROM-less version General registers 8 bits × 8 × 4 banks (memory mapping) Timer/counter 16-bit timer/counter Timer register × 1 Capture register × 1 Compare register × 2 Pulse output capability Toggle output, PWM/PPG × 2 One-shot pulse output 8-bit timer/counter 1 Timer register × 1 Capture/compare register × 1 Compare register × 1 Pulse output capability (Real-time outputs, 4 bits × 2) 8-bit timer/counter 2 Timer register × 1 Capture register × 1 Compare register × 2 Pulse output capability Toggle output PWM/PPG × 2 8-bit timer/counter 3 Timer register × 1 Compare register × 1 EA pin = low level Real-time output port Output port linked 8-bit timer/counter 1 4 bits × 2 channels Serial interface UART : 1 channel (on-chip dedicated baud rate generator) CSI (3-wire serial I/O, SBI) : 1 channel A/D converter 8-bit resolution × 8 channels Interrupt 19 sources (external 7, internal 12) + BRK instruction 2-level priority order (programmable) 2 servicing modes (vectored interrupt, macro service) Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 x 14 mm) Note Additional function pins are included in I/O pins. 3 µPD78217A, 78218A PIN CONFIGURATION (TOP VIEW) 64-pin plastic shrink DIP 1 64 P02 P04 2 63 P01 P05 3 62 P00 P06 4 61 P37/TO3 P07 5 60 P36/TO2 P67/REFRQ/AN7 6 59 P35/TO1 P66/WAIT/AN6 7 58 P34/TO0 P65/WR 8 57 P70/AN0 P64/RD 9 56 P71/AN1 P63/A19 10 55 P72/AN2 P62/A18 11 54 P73/AN3 P61/A17 12 53 P74/AN4 P60/A16 13 52 P75/AN5 RESET 14 51 AV REF X2 15 50 AV SS 49 V DD 48 EA 47 P33/SO/SB0 µPD78217ACW µPD78218ACW– × × × m P03 X1 16 V SS 17 P57/A15 18 P56/A14 19 46 P32/SCK P55/A13 20 45 P31/T X D P54/A12 21 44 P30/R X D P53/A11 22 43 P27/SI P52/A10 23 42 P26/INTP5 P51/A9 24 41 P25/INTP4/ASCK P50/A8 25 40 P24/INTP3 P47/AD7 26 39 P23/INTP2/CI P46/AD6 27 38 P22/INTP1 P45/AD5 28 37 P21/INTP0 P44/AD4 29 36 P20/NMI P43/AD3 30 35 ASTB P42/AD2 31 34 P40/AD0 V SS 32 33 P41/AD1 m 4 µPD78217A, 78218A P65/WR P66/WAIT/AN6 P67/REFRQ/AN7 P07 P06 P05 P04 P03 P02 P01 P00 P37/TO3 P36/TO2 P35/TO1 P34/TO0 P70/AN0 64-pin plastic QFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 P71/AN1 P63/A19 2 47 P72/AN2 P62/A18 3 46 P73/AN3 P61/A17 4 45 P74/AN4 P60/A16 5 44 P75/AN5 RESET 6 43 AV REF X2 7 42 AV SS X1 8 41 V DD V SS 9 40 EA 39 P33/SO/SB0 38 P32/SCK µPD78217AGC–AB8 µPD78218AGC– × × × –AB8 P64/RD 35 P27/SI P52/A10 15 34 P26/INTP5 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 32 P25/INTP4/ASCK P24/INTP3 16 17 P50/A8 P51/A9 P23/INTP2/CI 14 P22/INTP1 P53/A11 P21/INTP0 P30/R X D P20/NMI 36 ASTB 13 P40/AD0 P54/A12 P41/AD1 P31/T X D V SS 37 P42/AD2 12 P43/AD3 P55/A13 P44/AD4 11 P45/AD5 P56/A14 P46/AD6 10 P47/AD7 P57/A15 5 µPD78217A, 78218A PIN IDENTIFICATION 6 P00 to P07 P20 to P27 P30 to P37 : Port 0 : Port 2 : Port 3 P40 P50 P60 P70 : : : : Port Port Port Port TO0 to TO3 CI RXD TX D : : : : Timer Output Clock Input Receive Data Transmit Data SCK ASCK SB0 SI : : : : Serial Clock Asynchronous Serial Clock Serial Bus Serial Input SO NMI INTP0 to INTP5 AD0 to AD7 : : : : Serial Output Non-maskable Interrupt Interrupt From Peripherals Address/Data Bus A8 to A19 : Address Bus to to to to P47 P57 P67 P75 4 5 6 7 RD WR : Read Strobe : Write Strobe WAIT ASTB REFRQ RESET : : : : Wait Address Strobe Refresh Request Reset X1, X2 EA AN0 to AN7 AVREF : : : : Crystal External Access Analog Input Reference Voltage AVSS VDD VSS : Analog Ground : Power Supply : Ground µPD78217A, 78218A EXAMPLE OF SYSTEM CONFIGURATION (INVERTER AIR-CONDITIONER IN-DOOR UNIT) Quick Heater AC 100 V Outdoor Unit Varistor µPD78218A Remote Control Receive INTP0 P55,P56 2 Relay Driver P00-P03 4 Driver M Right/ Left Wind Direction P60-P63 4 Driver M Up-Down Wind Direction P04-P07 4 Driver M Right/ Left Wind Direction P50-P54 5 Driver M Indoor Fan Motor AN0 AN1 AN2 AN3 Room Temperature AN4 Special Sensor AN5 Humidity AN6 Heat Exchanger Temperature AN7 Stepping Motors Wind Direction Setting Wired Remote Control P32 T XD Serial Communication Display 8 Buzzer HA Control P40-P47 P34 2 R XD RESET RESET P35,P36 X1 X2 7 µPD78217A, 78218A INTERNAL BLOCK DIAGRAM A16-A19 (Expansion) A8-A15 ADDRESS BUS AD0-AD7 PC NMI PROGRAMMABLE INTERRUPT CONTROLLER INTP0-INTP5 BUS CONTROL RXD TXD UART ALU BAUD RATE GENERATOR ASCK SCK SO/SB0 ROM CLOCKED SERIAL INTERFACE SI INTP3 TO0 TO1 TIMER/COUNTER CHANNEL-2 (PS + 8 BITS) BOOLEAN PROCESSOR • RAM (256 Bytes) • GR • MACRO SERVICE CHANNEL BUS I/F TIMER/COUNTER CHANNEL-3 (PS + 8 BITS) REAL-TIME OUTPUT PORT (4 BITS × 2) P00-P03 P04-P07 • MICRO ROM • MICRO– SEQUENCER SP PSW SYSTEM CONTROL INTP1 INTP2 TO2 TO3 WAIT ASTB TEMPORARY REGISTERS DATA BUS (8) INTP0 TIMER/COUNTER CHANNEL-1 (PS + 8 BITS) WR REFRQ SFR ADDRESS/DATA BUS TIMER/COUNTER (16 BITS) RD DATA BUS X1 X2 RESET EA VDD VSS AN0-AN7 AVREF A/D CONVERTER AVSS INTP5 PORT Caution Note 8 P0 P2 P3 P4 P00 -P07 P20 -P27 P30 -P37 P40 -P47 RAM P5 Note P6 Note P50 -P57 P6 P7 Note P60 P64 -P63 -P67 P70 -P75 Inernal ROM/RAM capacity varies depending on the product. In case of the µPD78217A, P40 to P47, P50 to P57, P64 and P65 cannot be used as ports. µPD78217A, 78218A CONTENTS 1. DIFFERENCES BETWEEN µPD78218A AND µPD78214 SUBSERIES ..................................................10 2. PIN FUNCTIONS ........................................................................................................................................11 2.1 2.2 2.3 3. 4. PORTS .................................................................................................................................................................11 NON-PORT PINS ................................................................................................................................................12 PIN I/O CIRCUITS AND UNUSED PIN CONNECTION ...................................................................................13 INTERNAL BLOCK FUNCTIONS ..............................................................................................................15 3.1 3.2 3.3 3.4 MEMORY SPACE ...............................................................................................................................................15 PORTS .................................................................................................................................................................17 REAL-TIME OUTPUT PORT ..............................................................................................................................19 TIMER/COUNTER UNIT ....................................................................................................................................20 3.5 3.6 A/D CONVERTER ...............................................................................................................................................22 SERIAL INTERFACE ...........................................................................................................................................24 3.6.1 Asynchronous Serial Interface ........................................................................................................ 25 3.6.2 Clock Synchronous Serial Interface ................................................................................................26 INTERNAL/EXTERNAL CONTROL FUNCTION ......................................................................................27 4.1 INTERRUPTS ..................................................................................................................................................... 27 4.1.1 Interrupt Sources ..............................................................................................................................28 4.2 4.1.2 Vectored Interrupt .............................................................................................................................30 4.1.3 Macro Service ....................................................................................................................................30 4.1.4 Macro Service Application Examples .............................................................................................31 LOCAL BUS INTERFACE ...................................................................................................................................33 4.3 4.2.1 Memory Expansion ...........................................................................................................................33 4.2.2 Programmable Wait ..........................................................................................................................33 4.2.3 Pseudo-Static RAM Refresh Function ............................................................................................ 33 STANDBY ...........................................................................................................................................................34 4.4 RESET ..................................................................................................................................................................35 5. INSTRUCTION SET ...................................................................................................................................36 6. ELECTRICAL SPECIFICATIONS ................................................................................................................40 7. PACKAGE DRAWINGS .............................................................................................................................57 8. RECOMMENDED SOLDERING CONDITIONS ........................................................................................59 APPENDIX A. DEVELOPMENT TOOLS .........................................................................................................60 APPENDIX B. RELATED DOCUMENTS .........................................................................................................62 9 µPD78217A Part Number Minimum instruction execution time (at 12-MHz) PUSH PSW instruction execution time (number of clocks) 500 ns µPD78P218A 333 ns When stack area is an internal dual port RAM Other than above VDD=+5V±10% Power voltage range On-chip memory µPD78218A ROM ROM-less RAM I/O pins :6 :8 µPD78212 µPD78213 333 ns 500 ns 32 Kbytes (PROM) µPD78214 µPD78P214 333 ns When stack area is an internal dual port RAM Other than above : 5 or 7 : 7 or 9 VDD=+5V±10% VDD=+5V±0.3V 32 Kbytes (mask ROM) 8 Kbytes (mask ROM) 1024 bytes 36 16-bit timer/counter one-shot pulse output µPD78214 Subseries ROM-less 384 bytes 54 54 16 Kbytes (mask ROM) 16 Kbytes (PROM) 512 bytes 36 54 Available Not available Macro service counter bit width 8/16 bits select capability (except type A) Only 8 bits Macro service type C MPD, MPT increments 16-bit increment Only low-order 8 bits increment (high-order 8 bits are unchanged) Macro service execution time Macro service depends on mode. Compare with user’s manual of products. Restrictions when data is transferred from macro service type A memory to SFR Generated when transfer source buffer (memory) address is 0FED0H to 0FEDFH. Generated when transfer data is in D0H to DFH. A/D converter Only pins involved in A/D conversion Pins involved in A/D conversion and pins selected by ADM register bits ANI0 to ANI2 only: 0V to AVREF pin voltage Input voltage restrictions AVREF voltage restrictions 3.6 V to VDD 1. DIFFERENCES BETWEEN µPD78218A AND µPD78214 SUBSERIES 10 µPD78218A Subseries Series Name 3.4 V to VDD Dedicated counter 15 bits or NMI active pulse width + dedicated counter 16 bits NMI active pulse width + dedicated counter 16 bits Package • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 x 14 mm) • 64-pin ceramic shrink DIP (CERDIP, with window, 750 mil): µPD78P218A only • • • • • • 64-pin plastic shrink DIP (750 mil) 64-pin plastic QUIP: Except µPD78212 68-pin plastic QFJ: Except µPD78212 64-pin plastic QFP (14 x 14 mm) 74-pin plastic QFP (20 x 20 mm) 64-pin ceramic shrink DIP (CERDIP, with window, 750 mil): µPD78P214 only µPD78217A, 78218A Stabilization time for oscillation in STOP mode release µPD78217A, 78218A 2. PIN FUNCTIONS 2.1 PORTS Pin Name I/O P00 to P07 Output Alternate Function Function Port 0 (P0): Established as a real-time output port (4 bits × 2) Direct drive of transistors capability P20 Input NMI Port 2 (P2): P21 INTP0 P20 cannot be used as a general-purpose port. (Non-maskable interrupt) P22 INTP1 However, the input level can be confirmed in the interrupt routine. P23 INTP2/CI P24 INTP3 P25 INTP4/ASCK P26 INTP5 P27 SI Input/ output P30 The connection of the on-chip pull-up resistor can be specified as a 6-bit unit for P22 to P27 by software. RxD Port 3 (P3): TxD The input/output specifiable bit-wise. P32 SCK Input mode pins specifiable for on-chip pull-up resistor connection as a batch by P33 SO/SB0 P31 TO0 to TO3 P34 to P37 P40 to P47 Note software. Input/ output AD0 to AD7 Port 4 (P4): The input/output specifiable as an 8-bit batch. The connection of the on-chip pull-up resistor specifiable as an 8-bit batch by software. LED direct drive capability. P50 to P57 Note Input/ output A8 to A15 Port 5 (P5): The input/output specifiable bit-wise. Input mode pins specifiable for on-chip pull-up resistor connection as a batch by software. LED direct drive capability. P60 to P63 P64 P65 Note Note A16 to A19 Input/ output RD P64 to P67 enables to specify the input/output bit-wise. WR The connection of the on-chip pull-up resistor to input mode pins can be specified P66 WAIT/AN6 P67 REFRQ/AN7 P70 to P75 Note Port 6 (P6): Output Input AN0 to AN5 as a batch for P64 to P67 by software. Port 7 (P7) In case of the µPD78217A, these cannot be used as ports. 11 µPD78217A, 78218A 2.2 NON-PORT PINS Pin Name I/O Alternate Function TO0 to TO3 Output P34 to P37 Timer output CI Input P23 /INTP2 Count clock input to 8-bit timer/counter 2 RXD Input P30 Serial data input (UART) TXD Output P31 Serial data output (UART) Input P25/INTP4 Baud rate clock input (UART) Input/output P33/SO Serial data input/output (SBI) SI Input P27 SO Output P33/SB0 SCK Input/output P32 Serial clock input/output (SBI, 3-wire serial I/O) NMI Input P20 External interrupt request ASCK SB0 Serial data input (3-wire serial I/O) INTP0 P21 INTP1 P22 INTP2 P23/CI INTP3 P24 INTP4 P25/ASCK INTP5 P26 AD0 to AD7 Output A16 to A19 Output RD Output Output WR Time multiplexing address/data bus (external memory connection) Note Upper address bus (external memory connection) P50 to P57 P60 to P63 P64 P65 Serial data output (3-wire serial I/O) Note Input/output P40 to P47 A8 to A15 Function Upper address when extending address (external memory connection) Note Read strobe into external memory Note Write strobe into external memory P66/AN6 Wait insertion WAIT Input ASTB Output REFRQ Output RESET Input Chip reset X1 Input Crystal connection for system clock oscillation (external clock input to X1 Address (A0 to A7) latch timing output (during external memory access) P67/AN7 Refresh pulse output into external pseudo-static memory enabled) X2 EA ROM-less operating specification (external access of the same space as internal Input ROM). Used high for the µPD78218A and used low for the µPD78217A. AN0 to AN5 AN6, AN7 P70 to P75 Analog voltage input for A/D converter P66/WAIT, P67/REFRQ AVREF Reference voltage apply for A/D converter AVSS GND for A/D converter VDD Positive power supply VSS GND Note 12 Input In case of the µPD78217A, these cannot be used as ports. µPD78217A, 78218A 2.3 PIN I/O CIRCUITS AND UNUSED PIN CONNECTION The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, see Fig. 2-1. Table 2-1 Input/Output Circuit Type of Each Pin Pin Name Input/Output Circuit Type Unused Pin Connection I/O P00 to P07 4 Output P20/NMI 2 Input Leave open. Connected to VDD or VSS . P21/INTP0 P22/INTP1 Connected to VDD . 2-A P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK P26/INTP5 P27/SI P30/RXD 5-A Input/output P31/TXD P32/SCK 8-A P33/SB0/SO 10-A P34/TO0 to P37/TO3 5-A Input : Connected to VDD. Output : Leave open. P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD 4 Output 5-A Input/output P65/WR P66/WAIT/AN6 11 P67/REFRQ/AN7 P70/AN0 to P75/AN5 9 Input ASTB 4 Output RESET 2 Input EA 1 Leave open. Input : Connected to VDD. Output : Leave open. Input : Connected to VDD. Output : Leave open. Connected to VSS . Leave open. AVREF Connected to VSS or VDD . AVSS Connected to VSS . Note Note Note A voltage outside the range AVSS to AVREF should not be applied, as this may damage the µ PD78217A/78218A. Caution If the input/output mode is undefined for the input/output dual-function pins, connect these pins to VDD via a resistor of several ten kΩ. (Especially if the reset input pin exceeds the low-level input voltage at power-on or in case of input/ output switching by software.) Remark The type numbers are standardized for 78K series, therefore they are not always consecutive numbers for each product (some circuits are not incorporated). 13 µPD78217A, 78218A Fig. 2-1 Pin Input/Output Circuits Type 1 VDD Type 2-A VDD P pullup enable P IN N IN Schmitt-Triggered Input with Hysteresis Characteristic Type 2 Type 5-A IN VDD pullup enable Schmitt-Triggered Input with Hysteresis Characteristic P VDD Type 4 data VDD data P P IN / OUT output disable OUT N output disable input enable Push-pull output which enables output to be high-impedance (both P-ch and N-ch off). Type 8-A Type 9 VDD pullup enable P - P Vref (Threshold Voltage) IN / OUT output disable Comparator + P N IN VDD data N N input enable Type 10-A Type 11 VDD pullup enable pullup enable P open drain output disable data P output disable N IN / OUT P IN / OUT Comparator N + - Vref (Threshold Voltage) input enable 14 P VDD VDD data VDD P N µPD78217A, 78218A 3. INTERNAL BLOCK FUNCTIONS 3.1 MEMORY SPACE A memory space of 1 Mbytes can be accessed. Fig. 3-1 shows that memory space. The program memory mapping differs depending on the EA pin status. (1) µPD78217A (EA = L) The program memory is mapped onto external memory (64256 bytes: 00000H to 0FAFFH). This area can also be used as data memory. The data memory is mapped onto internal RAM (1024 bytes: 0FB00H to 0FEFFH). In the 1-Mbyte expansion mode, external memory (960 Kbytes: 10000H to FFFFFH) is mapped as expanded data memory. (2) µPD78218A (EA = H) The program memory is mapped onto internal ROM (32 Kbytes: 00000H to 07FFFH) and external memory (31488 bytes: 08000H to 0FAFFH). The external memory is accessed in the external memory expansion mode. The area mapped onto the external memory can also be used as data memory. The data memory is mapped onto internal RAM (1024 bytes: 0FB00H to 0FEFFH). In the 1-Mbyte expansion mode, external memory (960 Kbytes: 10000H to FFFFFH) is mapped as expanded data memory. 15 µPD78217A, 78218A Fig. 3-1 Memory Map EA = L (ROM-Less Mode) Note3 EA = H Data Memory 0FEFFH 10000H 0FFFFH 0FFDFH 0FFD0H 0FF00H Special Function Register (SFR) Note2 (256 bytes) Data Memory 0FEFFH 0FEE0H 0FEDFH 0FEC2H Internal RAM (1024 bytes) 0FB00H General Register (32 bytes) Macro Service Control Word (30 bytes) Data Area (1024 bytes) 0FB00H 0FAFFH 07FFFH Program Memory/ Data Memory Normal Address (64 Kbytes) Memory Space (1 Mbytes) Note1 External Memory Note1 (960 Kbytes) Program Area (28 Kbytes) External Memory Note2 (31488 bytes) External Memory (64256 bytes) 01000H 00FFFH CALLF Entry Area (2 Kbytes) 08000H 00800H 007FFH Program Memory/ Data Memory 07FFFH Internal ROM (32 Kbytes) 00000H 00080H 0007FH 00040H 0003FH 00000H Program Area (1920 bytes) CALLT Table Area (64 bytes) 00FFFH Vector Table Area (64 bytes) Notes 1. Accessed by 1-Mbyte expansion mode. Shaded areas denote internal memory. 2. Accessed by external memory expansion mode. 3. The µPD78217A applies only when EA = L. 16 Program Memory / Data Memory Extended Address FFFFFH µPD78217A, 78218A 3.2 PORTS The µPD78217A/78218A has the ports shown in Fig. 3-2 which allow various kinds of control. The functions of each port are shown in Table 3-1. For ports 2 to 6, on-chip pull-up resistor can be specified by software at input. Fig. 3-2 Port Configuration P00-P07 8 Port 0 8 P20-P27 Port 2 P30 Port 3 P37 8 P40-P47 Port 4 Note P50 Port 5 Note Port 6 Note P57 P60-63 4 P64 P67 P70-P75 Note 6 Port 7 In case of the µPD78217A, P40 to P47, P50 to P57, P64, and P65 cannot be used as ports. 17 µPD78217A, 78218A Table 3-1 Port Function Name P00 to P07 Port 0 Function Designation of Software Pull-Up Output or high-impedance specifiable as ––––– Pin Name an 8-bit batch. Can also operate as 4 bits real-time output (P00 to P03, P04 to P07). Transistor direct drive capability. Port 2 P20 to P27 Input port 6-bit batch (P22 to P27) Port 3 P30 to P37 Input or output specifiable bit-wise. Input mode pins specifiable as a batch Port 4 Note P40 to P47 Input or output specifiable as an 8-bit batch. 8-bit batch LED direct drive capability. Port 5 Port 6 Note Note P50 to P57 Input or output specifiable bit-wise. Input mode pins specifiable LED direct drive capability. as a batch P60 to P63 Output port P64 to P67 Input or output specifiable bit-wise. P70 to P75 Input port ––––– Input mode pins specifiable as a batch Port 7 Note 18 ––––– In case of the µPD78217A, P40 to P47, P50 to P57, P64, and P65 cannot be used as ports. µPD78217A, 78218A 3.3 REAL-TIME OUTPUT PORT The real-time output port outputs the data stored in the buffer in synchronization with timer match interrupts or external interrupts. A jitterless pulse output is obtained by means of this. Therefore, it is most suitable for applications which output any pattern at any interval time. (Stepping motor open loop control, etc.) Port 0 and the buffer register are the core elements of the configuration, as shown in Fig. 3-3. Fig. 3-3 Real-Time Output Port Block Diagram Internal Bus 8 Real-Time Output Port Control Register Buffer Register INTP0 (From Outside) INTC10 (From Timer) 4 4 P0H P0L 4 4 8 Output Trigger Control Circuit INTC11 (From Timer) Output Latch (P0) P07 P00 19 µPD78217A, 78218A 3.4 TIMER/COUNTER UNIT The µPD78217A/78218A has a 16-bit timer/counter unit for 1 channel and 8-bit timer/counter units for 3 channels. Table 3-2 Type and Function of Timer/Counter Unit 16-Bit Timer/ Counter 8-Bit Timer/ Counter 1 2 chs 2 chs External event counter ––– ––– ––– One-shot timer ––– ––– ––– 2 chs ––– Type & Function Type Interval timer Function Timer output 8-Bit Timer/ Counter 2 2 chs 2 chs 8-Bit Timer/ Counter 3 1 ch ––– Toggle output ––– ––– PWM/PPG output ––– ––– One-shot pulse output ––– Real-time output ––– ––– ––– ––– ––– Pulse amplitude measurement Number of interrupt requests Clock source of serial interface ––– 2 2 2 ––– ––– ––– 1 Since 7 interrupt requests are supported in total, it can also function as timer for 7 channels. Remark 20 The one-shot pulse output function activates the pulse output level by software, and inactivates it by hardware (interrupt request signal). This function is different from the one-shot timer function of 8-bit timer/counter 2. µPD78217A, 78218A Fig. 3-4 Timer/Counter Unit Block Diagram 16-bit timer/counter unit Software Trigger OVF Timer Register TM0 Match Compare Register CR00 Match Compare Register CR01 INTP3 Pulse Output Control fCLK/8 TO0 TO1 INTC00 Edge Detection Capture Register CR02 INTC01 INTP3 8-bit timer/counter unit 1 Prescaler fCLK/16 Timer Register TM1 OVF Match Compare Register CR10 INTC10 To Real-Time Output Port INTP0 Capture/Compare Register CR11 Edge Detection Match INTC11 INTP0 8-bit timer/counter unit 2 Prescaler fCLK/16 Event Input Edge Detection INTP2 INTP1 OVF Compare Register CR20 Match Compare Register CR21 Match TO2 TO3 INTC20 INTC21 Capture Register CR22 Edge Detection Pulse Output Control INTP2/CI Timer Register TM2 INTP1 8-bit timer/counter unit 3 fCLK/8 Prescaler Timer Register TM3 Clear UART Compare Register CR30 INTP4/ ASCK Edge Detection CSI Match INTP4/ INTC30 OVF: Overflow Flag 21 µPD78217A, 78218A 3.5 A/D CONVERTER The µPD78217A/78218A incorporate the analog/digital (A/D) converter with 8-channel multiplexed analog input (AN0 to AN7). The conversion method used is successive approximation. After the A/D conversion results are generated, they are held in the 8-bit A/D conversion result register (ADCR), which may allow high-speed and high-precision conversion (conversion time: Approx. 30 µs; at 12-MHz operation). The following two modes are available for starting A/D conversion: • • Hardware start : Starts conversion by trigger input (INTP5) Software start : Starts conversion by the A/D converter mode register (ADM) bit setting The following two modes of operation after starting are available: • Scan mode • Select mode : The analog input is fixed at one pin and a continuous conversion value is obtained. : Multiple analog input are selected sequentially and conversion data is obtained from all pins. The above modes and the conversion operation are all stopped by ADM. If the conversion result is transferred to the ADCR, an interrupt request INTAD is generated, (except in software start select mode). Therefore, the conversion value can be transferred to memory continuously using macro service (See section 4.1.3 “Macro Service”). Table 3-3 INTAD Generation Mode Scan Mode Select Mode Hardware start Software start 22 ––– µPD78217A, 78218A Fig. 3-5 A/D Converter Block Diagram AN0 Series Resistor String AN1 AN4 AN5 AV REF R/2 R Voltage Comparator Tap Selector AN3 Sample & Hold Circuit Input Selector AN2 AN6 AN7 Successive Approximation Register (SAR) INTP5 Conversion Trigger Edge Detector INTAD R/2 Controller AV SS INTP5 Trigger Enable 8 A/D Converter Mode Register (ADM) A/D Conversion Result Register (ADCR) 8 8 Selector Interrupt Request Internal Bus 23 µPD78217A, 78218A 3.6 SERIAL INTERFACE The µPD78217A/78218A has two independent serial interfaces. • • Asynchronous serial interface (UART) Clock synchronous serial interface (CSI) • 3-wire serial I/O • Serial bus interface (SBI) Therefore, communication with external devices and local communication inside the system can be performed simultaneously (See Fig. 3-6). Fig. 3-6 Serial Interface Example (a) UART + SBI µPD78218A (Master) VDD µ PD75402A (Slave) µ PD4711A [UART] RS-232-C Driver [SBI] RXD SB0 SB0 TXD SCK SCK Port µ PD75328 (Slave) SB0 SCK (b) UART + 3-wire serial I/O µPD78218A (Master) µ PD4711A [UART] RS-232-C Driver µ PD78C11A (Slave) [3-Wire Serial I/O] SO SI RXD SI SO TXD SCK SCK Note Port INTPm Port Port INT µ PD78C14 (Slave) SI SO SCK INTPn Port Note Port INT Note Handshake Line 24 LCD µPD78217A, 78218A 3.6.1 Asynchronous Serial Interface The µPD78217A/78218A incorporates UART (Universal Asynchronous Receiver Transmitter) as the asynchronous serial interface. UART is used to send/receive one byte of data following a start bit. The UART incorporates a dedicated baud rate generator which can generate a wide range of desired baud rates and also determine baud rates by scaling the ASCK pin input clocks or 8-bit timer/counter 3 output (TM3 output), allowing transmission/reception with a variety of baud rates. If the UART dedicated baud rate generator is used, the MIDI standard baud rate (31.25 kbps) can also be obtained. Fig. 3-7 Asynchronous Serial Interface (UART) Block Diagram Internal Bus Receive Buffer RXB Receive Shift Register RXD Transmit Shift Register TXS TXD INTSR Receive Control Parity Check INTSER Transmit Control Parity Addition 1/16 INTST 1/16 1/N2 TM3 Output 1/2 Selector ASCK 1/N1 Selector fCLK Selector UART Dedicated Baud Rate Generator fCLK: Internal system clock frequency (System Clock Frequency/2) 25 µPD78217A, 78218A 3.6.2 Clock Synchronous Serial Interface The master device starts transmission by activating the serial clock and transfers one-byte data in synchronization with this clock. Fig. 3-8 Clock Synchronous Serial Interface Block Diagram Internal Bus Set Clear SO/SB0 SIO Selector SI Shift Register Output Latch Busy/ Acknowledge Generator N-ch Open-drain output also possible (SB0: SBI) Bus Release Command/ Acknowledge Detector SCK Serial Clock Counter Interrupt Generator INTCSI Serial Clock Controller Selector TM3 Output/2 fCLK/8 fCLK/32 fCLK: Internal System Clock Frequency (System Clock Frequency/2) (1) 3-wire serial I/O This is an interface for communicating with devices incorporating a conventional clock synchronous serial interface. Basically, communication is performed with three lines, one serial clock line (SCK) and two serial data lines (SI, SO). When connecting to multiple devices, a handshake line is necessary. (2) SBI Communication with multiple devices is performed with one serial clock line (SCK) and one serial bus line (SB0). This is NEC's standard serial interface. The master device selects the slave device to be communicated with by outputting its “address” from the SB0 pin. Therefore, “commands” and “data” perform transfer and receive between the master and slave. 26 µPD78217A, 78218A 4. INTERNAL/EXTERNAL CONTROL FUNCTION 4.1 INTERRUPTS Two interrupt request servicing methods can be selected, as shown in the following table. Table 4-1 Interrupt Request Servicing Service Mode Servicing Subject Service PC, PSW Contents Vectored interrupt Software Branches to service routine, and executes (any process contents) With save and return Macro service Firmware Data transfer, etc., between memory and I/O (fixed process contents) Hold 27 µPD78217A, 78218A 4.1.1 Interrupt Sources There are 19 types of interrupt sources and a BRK instruction execution, as shown in Table 4-2. The priority of the interrupt servicing can be set to 2 levels (high and low priority levels). Therefore, the levels of nest control when the interrupt is in progress and when interrupt requests occur simultaneously (see Fig. 4-1, Fig. 4-2) can be separated. Nesting will always take place in the macro service (It won't be put on hold). The default priority is the priority level (fixed) to service the interrupt requests which occur at the same level simultaneously (see Fig. 4-2). Table 4-2 Interrupt Sources Type Default Priority Source Name Trigger Internal/ External Macro Service ––––– ––– Software BRK Instruction execution Nonmaskable NMI Pin input edge detection 0 (highest) INTP0 Pin input edge detection (TM1 capture trigger) 1 INTP1 Pin input edge detection (TM2 capture trigger) 2 INTP2 Pin input edge detection (TM2 event counter input) 3 INTP3 Pin input edge detection (TM0 capture trigger) 4 INTC00 TM0 to CR00 match signal generation 5 INTC01 TM0 to CR01 match signal generation 6 INTC10 TM1 to CR10 match signal generation 7 INTC11 TM1 to CR11 match signal generation 8 INTC21 TM2 to CR21 match signal generation 9 INTP4 Pin input edge detection External INTC30 TM3 to CR30 match signal generation Internal INTP5 Pin input edge detection External INTAD A/D converter conversion termination (transfer to ADCR) Internal 11 INTC20 TM2 to CR20 match signal generation 12 INTSER ASI receive error generation 13 INTSR ASI receive termination 14 INTST ASI transmit termination 15 (lowest) INTCSI CSI transfer termination Maskable 10 External Internal ––– TM0 : 16-bit timer TM1 to TM3 : 8-bit timer ASI : Asynchronous serial interface CSI : Clock synchronous serial interface 28 µPD78217A, 78218A Fig. 4-1 Servicing Example when an Interrupt Request Occurrence is Issued while an Interrupt is Serviced Main Routine [Nesting 1] [Nesting 2] [Nesting 3] Servicing of a Servicing of b Macro Service Request b → Vectored Interrupt Request a → (Low-Priority Level) Servicing of c Vectored Interrupt Request c → (High-Priority Level) Servicing of d Macro Service Request d → Servicing of e Servicing of f Macro Service Request f → Vectored Interrupt Request e → (High-Priority Level) Macro Service Request h → ← Vectored Interrupt Request g (Low-Priority Servicing Level: Pending) Servicing of h of g Fig. 4-2 Servicing Example of Simultaneous Interrupt Requests Main Routine [Nesting 1] [Nesting 2] Servicing of b • Vectored Interrupt Request a (Low-Priority Level) • Macro Service Request b (High-Priority Level) • Macro Service Request c (Low-Priority Level) • Vectored Interrupt Request d (High-Priority Level) Default Priority: a > b > c > d Servicing of d Servicing of c → Servicing of a 29 µPD78217A, 78218A 4.1.2 Vectored Interrupt The memory contents of the vector table address, which corresponds to the interrupt source, is branched into the service routine as a destination address. As the CPU executes the interrupt servicing, the following operations occur. • When branch : Saving the CPU status (PC, PSW contents) to the stack. • When return Returning the CPU status (PC, PSW contents) from the stack. : The RETI instruction executes returning to the main routine from the service routine. Table 4-3 Vector Table Address Interrupt Source Vector Table Address Vector Table Address Interrupt Source BRK 003EH INTC21 001CH NMI 0002H INTP4 000EH INTP0 0006H INTC30 INTP1 0008H INTP5 INTP2 000AH INTAD INTP3 000CH INTC20 0012H INTC00 0014H INTSER 0020H INTC01 0016H INTSR 0022H INTC10 0018H INTST 0024H INTC11 001AH INTCSI 0026H 0010H 4.1.3 Macro Service This is a function to transfer data between the memory and special function registers (SFR) without going through the CPU. The macro service controller accesses the memory and SFR, and transfers data directly without fetching it. High-speed data transfer is enabled because no data is saved, restored or fetched. Fig. 4-3 Macro Service Read CPU Memory Write Internal Bus 30 Macro Service Controller Write SFR Read µPD78217A, 78218A 4.1.4 Macro Service Application Examples (1) Transmit operation of serial interface Transmit Data Storage Buffer (Memory) Data n Data n–1 Data 2 Data 1 Internal Bus TXD Transmit Shift Register TXS (SFR) INTST Transmission Control Whenever the macro service request INTST is generated, the next transmit data is transferred to TXS from the memory. When the data n (last byte) is transferred to TXS (the transmit data storage buffer becomes empty), a vectored interrupt request INTST is generated. (2) Receive operation of serial interface Receive Data Storage Buffer (Memory) Data n Data n–1 Data 2 Data 1 Internal Bus Receive Buffer RXD RXB (SFR) Receive Shift Register Receive Control INTSR Whenever the macro service request INTSR is generated, the receive data is transferred to the memory from RXB. When the data n (last byte) is transferred to the memory (the receive data storage buffer becomes empty), the vectored interrupt request INTSR is generated. 31 µPD78217A, 78218A (3) Real-time output port The INTC10 and INTC11 become output triggers of the real-time output port. In the macro service for them, the next output pattern and interval can be set simultaneously. Therefore, the INTC10 and INTC11 can control 2 system stepping motor independently. Also, they can be applied to control a PWM or DC motor, etc. Output Pattern Profile (Memory) (SFR) Output Timing Profile (Memory) Pn Tn Pn-1 Tn-1 P2 T2 P1 T1 Internal Bus Internal Bus P0L Match CR10 (SFR) INTC10 Output Latch TM1 P00-P03 Whenever the macro service request INTC10 is generated, the pattern and timing are transferred to P0L and CR10, respectively. When the contents of the TM1 match with the contents of the CR10, the next INTC10 is generated and the contents of the P0L are sent to the output latch. If Tn (last byte) is sent to CR10, a vectored interrupt request INTC10 is generated. The same operation is available for INTC11 (differences: CR10 → CR11, P0L → P0H, P00-P03 → P04-P07). 32 µPD78217A, 78218A 4.2 LOCAL BUS INTERFACE The µPD78217A/78218A can be connected to an external memory and I/O (memory mapped I/O), and supports the 1M-byte memory space (see Fig.3-1). Fig. 4-4 Local Bus Interface Example A16-A19 Decoder µPD78218A RD Pseudo SRAM WR PROM µ PD27C256A REFRQ Data Bus AD0-AD7 ASTB Kanji-Character Generator µ PD24C1000 Latch Address Bus A8-A15 Gate Array I/O Expansion Centronics I/F, etc. 4.2.1 Memory Expansion The following modes have been prepared as a memory expansion function. • External memory expansion mode : Expands the program memory and data memory to 31488 bytes (64256 bytes for the µPD78217A) externally. However, this area can be used unconditionally under the ROM-less mode (EA = L). • 1-Mbyte expansion mode 4.2.2 : Expands the data memory by 960 Kbytes and become a 1-Mbyte memory space. Programmable Wait A wait can be independently inserted to the memory mapped on both a normal address (00000H to 0FFFFH) and an expanded address (10000H to FFFFFH). Therefore, the efficiency of the entire system is not decreased. 4.2.3 Pseudo-Static RAM Refresh Function The refresh operations are as follows. • Pulse refresh : Outputs the refresh pulse to REFRQ pin in synchronization with a bus cycle. • Power-down self refresh : Outputs a low-level to the REFRQ pin in the standby mode and holds the contents of the pseudo-static RAM. 33 µPD78217A, 78218A 4.3 STANDBY This is a function to reduce the power consumption of the chip. The following modes are available. • HALT mode : Stops the operation clock of the CPU. The average power consumption is reduced by switching from normal mode to HALT mode and vice-versa. • STOP mode : Stops the oscillator. This stops all operation in the chip and enables minute power consumption consisting only of leakage current. These modes are programmable. The macro service is started from the HALT mode. Fig. 4-5 Standby Status Flow Program Operation t Se STOP (Standby) I NM ut Inp Interrupt Request at Interrupt Disable RESET Input NMI Input Vectored Interrupt Request Note 2 R ut np TI E ES HALT Set OP ST Ma cro Se rvi y ce Da te T Re qu Te ta T rans es rm ra f t ina nsf er tio er n 1-B HALT (Standby) No te 4 t s ue Macro Service eq eR ic erv S r sfe ran er te 3 T o f yte ns N 1-B a Traation t Da rmin Te cro Ma Vectored Interrupt Request Note 1 Notes 1. In case a vectored interrupt request is a low-priority level (status to disable interrupt of a low-priority sequence under the HALT setting). 2. In case a vectored interrupt request is a high-priority level or in case of the status to enable interrupt of a low-priority sequence under the HALT setting. 3. In case a macro service is a high-priority level (status to disable interrupt of a low-priority sequence under the HALT setting). 4. In case a macro service is a high-priority level or in case of the status to enable interrupt of a low-priority sequence under the HALT setting. 34 µPD78217A, 78218A 4.4 RESET When a low level is input to the RESET pin, the internal hardware is initialized (reset state). When the RESET input changes from low level to high level, the following data is set in the program counter (PC). • Lower 8 bits of PC : Contents of 0000H address • Upper 8 bits of PC : Contents of 0001H address The contents of the PC set the destination address and the program starts to be executed from the address. Therefore, it can start from any address by reset start. Please set the program for the contents of each register as required. A noise eliminator has been incorporated in the RESET input circuit to prevent any error from noise. This noise eliminator is a sampling circuit based on analog delay. Fig. 4-6 Reset Acknowledge Delay Delay Delay PC Initialization Instruction Execution of Reset Start Address RESET (Input) Internal Reset Signal Reset Start Reset End Set the RESET signal active in the reset operation at power-on until the oscillation stabilization time (approx. 40 ms) elapses. Fig. 4-7 Reset Operation at Power-On Oscillation Stabilization Time Delay PC Initialization Instruction Execution of Reset Start Address V DD RESET (Input) Internal Reset Signal Reset End 35 µPD78217A, 78218A 5. INSTRUCTION SET (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP Table 5-1 Instructions Classified by 8-Bit Addressing Mode 2nd Operand #byte 1st Operand A r r saddr r’ saddr’ A sfr MOV XCH Note1 ADD mem &mem MOV MOV MOV MOV XCH XCH XCH XCH Note1 Note1 Note1 Note1 ADD ADD ADD ADD !addr16 &!addr16 MOV MOV r1 saddr MOV Note1 ADD MOV sfr MOV Note1 ADD MOV MOV XCH Note1 ADD 36 MOV MULU DIVUW INC DEC INC DBNZ DEC PUSH POP MOV mem1 &mem1 ROR4 ROL4 !addr16 MOV &!addr16 MOV PSW MOV STBC MOV 1. 2. Note2 None DBNZ mem & mem Notes n ROL ROLC ROR RORC SHR SHL MOV XCH Note1 ADD MOV PSW MOV ADDC, SUB, SUBC, AND, OR, XOR and CMP are the same as ADD. There is no 2nd operand, or the 2nd operand is not an operand address. PUSH POP µPD78217A, 78218A (2) 16-bit instructions MOVW, ADDW, SUBW, CMPW, INCW, DECW, SHRW, SHLW, PUSH, POP Table 5-2 Instructions Classified by 16-Bit Addressing Mode 2nd Operand rp #word AX AX ADDW SUBW CMPW ADDW SUBW CMPW rp MOVW saddrp MOVW MOVW sfrp MOVW MOVW mem1 &mem1 SP saddrp sfrp mem1 &mem1 MOVW ADDW SUBW CMPW MOVW ADDW SUBW CMPW MOVW SP n None SHLW SHRW INCW DECW PUSH POP rp’ 1st Operand MOVW MOVW MOVW MOVW MOVW MOVW INCW DECW 37 µPD78217A, 78218A (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Table 5-3 Instructions Classified by Bit Manipulation Instruction Addressing Mode 2nd Operand saddr. CY A.bit /A.bit X.bit 1st Operand MOV1 AND1 OR1 XOR1 CY A.bit X.bit saddr.bit sfr.bit PSW.bit AND1 OR1 MOV1 AND1 OR1 XOR1 /saddr. /X.bit AND1 OR1 /PSW. sfr.bit bit bit MOV1 AND1 OR1 XOR1 AND1 OR1 Note None bit MOV1 AND1 OR1 XOR1 AND1 OR1 MOV1 AND1 OR1 XOR1 AND1 OR1 SET1 CLR1 NOT1 MOV1 SET1 CLR1 NOT1 BT BF BTCLR MOV1 SET1 CLR1 NOT1 BT BF BTCLR MOV1 SET1 CLR1 NOT1 BT BF BTCLR MOV1 SET1 CLR1 NOT1 BT BF BTCLR MOV1 SET1 CLR1 NOT1 BT BF BTCLR Note There is no 2nd operand, or the 2nd operand is not an operand address. 38 /sfr.bit PSW.bit µPD78217A, 78218A (4) Call/branch instructions CALL, CALLF, CALLT, BR, BC, BT, BF, BTCLR, DBNZ, BL, BNC, BNL, BZ, BE, BNZ, BNE Table 5-4 Instructions Classified by Call/Branch Instruction Addressing Mode Operands of Instruction Address $addr16 !addr16 rp !addr11 [addr5] Basic instructions BR BCNote CALL BR CALL BR CALLF CALLT Compound instructions BT BF BTCLR DBNZ Note BL, BNC, BNL, BZ, BE, BNZ and BNE are the same as BC. (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, NOP, EI, DI, SEL 39 µPD78217A, 78218A 6. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) PARAMETER Supply voltage Input voltage SYMBOL RATING UNIT VDD –0.5 to +7.0 V AVREF –0.5 to VDD +0.5 V AVSS –0.5 to +0.5 V VI1 –0.5 to VDD +0.5 V –0.5 to AVREF +0.5 V –0.5 to VDD +0.5 V Per pin 15 mA All output pins 100 mA Per pin –10 mA All output pins –50 mA –40 to +85 °C –65 to +150 °C Note VI2 ★ Output voltage VO Output current, low IOL Output current, high IOH Operating ambient temperature TA Storage temperature Tstg Note TEST CONDITIONS P70/AN0 to P75/AN5, P66/WAIT/AN6, P67/REFRQ/AN7 pins are used as A/D converter input pins. However, VI1 absolute maximum ratings should also be satisfied. Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. OPERATING CONDITIONS ★ CLOCK FREQUENCY OPERATING AMBIENT TEMPERATURE (TA) SUPPLY VOLTAGE (VDD ) 4 MHz ≤ fXX ≤ 12 MHz –40 to +85 °C +5 V ± 10 % CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V) PARAMETER 40 SYMBOL Input capacitance CI Output capacitance CO I/O capacitance CIO TEST CONDITIONS f = 1 MHz unmeasured pins returned to 0 V. MIN. TYP. MAX. UNIT 20 pF 20 pF 20 pF µPD78217A, 78218A OSCILLATOR CHARACTERISTICS (TA= –40 to +85 °C, VDD = +5 V ±10 %, V SS = 0 V) RESONATOR Ceramic resonator or crystal resonator RECOMMENDED CIRCUIT VSS X1 MIN. MAX. UNIT Oscillator frequency (fXX) 4 12 MHz X1 input frequency (fX) 4 12 MHz X1 input rising/falling time (tXR , tXF ) 0 30 ns X1 input high/low level width (tWXH , tWXL) 30 130 ns X2 C1 C2 X2 X1 External clock HCMOS Inverter Caution PARAMETER When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. • Wiring should be as short as possible. • Wiring should not cross other signal lines. • Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS. Do not ground it to a ground pattern in which a high current flows. • Do not fetch a signal from the oscillator. 41 µPD78217A, 78218A RECOMMENDED OSCILLATOR CONSTANTS CERAMIC RESONATOR MANUFACTURER FREQUENCY [MHz] PART NUMBER CSA12.0MTZ Murata Mfg. EFOGC1205C4 12 ★ ★ TDK Co. Note 42 C1 [pF] C2 [pF] 30 30 12 CST12.0MTW Matsushita Electronics Parts RECOMMENDED CONSTANTS Capacitor on-chip type Note EFOEC1205C4 Capacitor on-chip type EFOEN1205C4 33 33 FCR12.0M2S 33 33 12 Production discontinued. FCR12.0MC Capacitor on-chip type µPD78217A, 78218A DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %, VSS = 0 V) PARAMETER SYMBOL Input voltage, low Input voltage, high TEST CONDITIONS VIL MIN. TYP. MAX. UNIT 0 0.8 V VIH1 Pins except for Note 1 and Note 2 2.2 VDD V VIH2 Pin of Note 1 2.2 AVREF V VIH3 Pin of Note 2 0.8 VDD VDD V VOL1 IOL = 2.0 mA 0.45 V 1.0 V Output voltage, low Output voltage, high Note3 VOL2 IOL = 8.0 mA VOH1 IOH = –1.0 mA VOH2 IOH = –100 µA Note4 VDD–1.0 V VDD–0.5 V 2.0 V VOH3 IOH = –5.0 mA X1 input current, low IIL 0 V ≤ VI ≤ VIL –100 µA X1 input current, high IIH VIH3 ≤ VI ≤ VDD 100 µA Input leakage current ILI 0 V ≤ VI ≤ VDD ±10 µA Output leakage current ILO 0 V ≤ VO ≤ VDD ±10 µA AVREF current AIREF Operating mode fXX = 12 MHz 1.5 5.0 mA IDD1 Operating mode fXX = 12 MHz 20 40 mA IDD2 HALT mode fXX = 12 MHz 7 20 mA 5.5 V VDD supply current Data retention voltage VDDDR Data retention current IDDDR Pull-up resistor RL STOP mode 2.5 STOP VDDDR = 2.5 V 2 20 µA mode VDDDR = 5 V ±10 % 5 50 µA 40 80 kΩ VI = 0 V 15 Notes 1. P70/AN0 to P75/AN5, P66/WAIT/AN6, P67/REFRQ/AN7 pins are used as A/D converter input pins. 2. X1, X2, RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK, P26/ INTP5, P27/SI, P32/SCK, P33/SO/SB0, EA pins 3. P40/AD0 to P47/AD7, P50/A8 to P57/A15 pins 4. P00 to P07 pins 43 µPD78217A, 78218A AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %, VSS = 0 V) READ/WRITE OPERATION (1/2) PARAMETER SYMBOL MIN. MAX. UNIT tCYX 82 250 ns tSAST • 52 ns Address hold time (from ASTB↓) tHSTA 25 ns Address hold time (from RD↑) tHRA 30 ns Address hold time (from WR↑) tHWA 30 ns RD↓ delay time from address tDAR • 129 ns Address float time (from RD↓) tFAR • 11 ns Data input time from address tDAID • No. of waits = 0 228 ns Data input time from ASTB↓ tDSTID • No. of waits = 0 181 ns Data input time from RD↓ tDRID • No. of waits = 0 100 ns RD↓ delay time from ASTB↓ tDSTR • 52 ns Data hold time (from RD↑) tHRID 0 ns Address active time from RD↑ tDRA • 124 ns ASTB↑ delay time from RD↑ tDRST • 124 ns RD low-level width tWRL • 124 ns ASTB high-level width tWSTH • 52 ns WR↓ delay time from address tDAW • 129 ns Data output time from ASTB↓ tDSTOD • 142 ns tDWOD 60 ns X1 input clock cycle time Address setup time (to ASTB↓) Note Data output time from WR↓ TEST CONDITIONS No. of waits = 0 tDSTW1 • Refreshing disabled 52 ns tDSTW2 • Refreshing enabled 129 ns tSODWR • No. of waits = 0 146 ns tSODWF • Refreshing enabled 22 ns WR↓ delay time from ASTB↓ Data setup time (to WR↑) Data setup time (to WR↓) Note Data hold time (from WR↑) tHWOD 20 ns ASTB↑ delay time from WR↑ tDWST • 42 ns tWWL1 • Refreshing disabled No. of waits = 0 196 ns tWWL2 • Refreshing enabled No. of waits = 0 114 ns WR low-level width WAIT↓ input time from address tDAWT • 146 ns WAIT↓ input time from ASTB↓ tDSTWT • 84 ns Note The hold time includes the time to hold the VOH and VOL under the load conditions of CL = 100 pF and RL = 2 kΩ. Remarks 1. The values in the above table are based on "fXX = 12 MHz and CL = 100 pF". 2. For a parameter with a dot (•) in the SYMBOL column, refer to "tCYX DEPENDENT BUS TIMING DEFINITION" as well. 44 µPD78217A, 78218A READ/WRITE OPERATION (2/2) PARAMETER SYMBOL TEST CONDITIONS MIN. 174 MAX. UNIT WAIT hold time from ASTB↓ tHSTWT • No. of external waits = 1 ns WAIT↑ delay time from ASTB↓ tDSTWTH • No. of external waits = 1 WAIT↓ input time from RD↓ tDRWTL • WAIT hold time from RD↓ tHRWT • No. of external waits = 1 WAIT↑ delay time from RD↓ tDRWTH • No. of external waits = 1 Data input time from WAIT↑ tDWTID • WR↑ delay time from WAIT↑ tDWTW • 154 ns RD↑ delay time from WAIT↑ tDWTR • 72 ns WAIT input time from WR↓ (At refresh disabled) tDWWTL • WAIT hold time Refresh disabled tHWWT1 • No. of external waits = 1 87 ns from WR↓ Refresh enabled tHWWT2 • No. of external waits = 1 5 ns WAIT↑ delay Refresh disabled tDWWTH1 • No. of external waits = 1 186 ns time from WR↓ Refresh enabled tDWWTH2 • No. of external waits = 1 104 ns 273 ns 22 ns 87 ns 186 ns 62 ns 22 ns REFRQ↓ delay time from RD↑ tDRRFQ • 154 ns REFRQ↓ delay time from WR↑ tDWRFQ • 72 ns REFRQ low-level width tWRFQL • 120 ns ASTB↑ delay time from REFRQ↑ tDRFQST • 280 ns Remarks 1. 2. The values in the above table are based on "fXX = 12 MHz and CL = 100 pF". For a parameter with a dot (•) in the SYMBOL column, refer to "tCYX DEPENDENT BUS TIMING DEFINITION" as well. 45 µPD78217A, 78218A SERIAL OPERATION PARAMETER SYMBOL TEST CONDITIONS Input Serial clock cycle time tCYSK MIN. MAX. External clock 1.0 µs Internal divided by 16 1.3 µs Internal divided by 64 5.3 µs External clock 420 ns Internal divided by 16 556 ns Internal divided by 64 2.5 µs External clock 420 ns Internal divided by 16 556 ns Internal divided by 64 2.5 µs Output Input Serial clock low-level width tWSKL Output Input Serial clock high-level width tWSKH Output UNIT SI, SB0 setup time (to SCK↑) tSSSK 150 ns SI, SB0 hold time (from SCK↑) tHSSK 400 ns tDSBSK1 SO/SB0 output delay time CMOS push-pull output 0 300 ns 0 800 ns (3-wire serial I/O mode) (from SCK↓) Open-drain output (SBI mode), tDSBSK2 RL = 1 kΩ SB0 high hold time (from SCK↑) tHSBSK 4 tCYX SBI mode SB0 low setup time (to SCK↓) tSSBSK 4 tCYX SB0 low-level width tWSBL 4 tCYX SB0 high-level width tWSBH 4 tCYX Remark 46 The values in the above table are based on "fXX = 12 MHz and CL = 100 pF". µPD78217A, 78218A OTHER OPERATIONS PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT NMI low-level width tWNIL 10 µs NMI high-level width tWNIH 10 µs INTP0 to INTP5 low-level width tWITL 24 tCYX INTP0 to INTP5 high-level width tWITH 24 tCYX RESET low-level width tWRSL 10 µs RESET high-level width tWRSH 10 µs EXTERNAL CLOCK TIMING PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT X1 input low-level width tWXL 30 130 ns X1 input high-level width tWXH 30 130 ns X1 input rise time tXR 0 30 ns X1 input fall time tXF 0 30 ns X1 input clock cycle time tCYX 82 250 ns A/D CONVERTER CHRACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %, VSS = AVSS = 0 V) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. 8 Resolution Overall error Note1 Conversion time Sampling time tCONV tSAMP Analog input voltage VIAN Analog input impedance RAN Reference voltage AVREF AVREF current AIREF 2. UNIT bit 4.0 V ≤ AVREF ≤ VDD TA = –10 to +70°C 0.4 % 3.6 V ≤ AVREF ≤ VDD TA = –10 to +70°C 0.8 % 4.0 V ≤ AVREF ≤ VDD 0.8 % ±1/2 LSB Quantization error Notes 1. MAX. 82 ns ≤ tCYX < 125 ns (The FR bit of ADM is to be "0") 360 tCYX 125 ns ≤ tCYX < 250 ns (The FR bit of ADM is to be "1") 240 tCYX 82 ns ≤ tCYX < 125 ns (The FR bit of ADM is to be "0") 72 tCYX 125 ns ≤ tCYX < 250 ns (The FR bit of ADM is to be "1") 48 tCYX AVREF +0.3 –0.3 1000 3.6 V MΩ VDD V fXX = 12 MHz 1.5 5.0 mA Note 2 0.2 1.5 mA ★ Quantization error is not included. Represented by the ratio to full-scale value. When ADM register's CS bit = 0, in STOP mode. 47 µPD78217A, 78218A tCYX DEPENDENT BUS TIMING DEFINITION (1/2) PARAMETER SYMBOL FORMULA MIN./MAX. 12 MHz UNIT MIN. 82 ns X1 input clock cycle time tCYX Address setup time (to ASTB↓) tSAST tCYX – 30 MIN. 52 ns RD↓ delay time from address tDAR 2tCYX – 35 MIN. 129 ns Address float time (from RD↓) tFAR tCYX/2 – 30 MIN. 11 ns Data input time from address Data input time from ASTB↓ tDAID tDSTID (4 + 2n) tCYX – 100 (3 + 2n) tCYX – 65 MAX. MAX. 228 181 100 Note Note Note ns ns Data input time from RD↓ tDRID (2 + 2n) tCYX – 64 MAX. RD↓ delay time from ASTB↓ tDSTR tCYX – 30 MIN. 52 ns Address active time from RD↑ tDRA 2tCYX – 40 MIN. 124 ns ASTB↑ delay time from RD↑ tDRST 2tCYX – 40 MIN. 124 ns RD low-level width tWRL (2 + 2n) tCYX – 40 MIN. ASTB high-level width tWSTH tCYX – 30 MIN. 52 ns WR↓ delay time from address tDAW 2tCYX – 35 MIN. 129 ns Data output time from ASTB↓ tDSTOD tCYX + 60 MAX. 142 ns MIN. 52 ns MIN. 129 ns tDSTW1 tCYX – 30 124 Note ns ns (Refreshing disabled) WR↓ delay time from ASTB↓ tDSTW2 2tCYX – 35 (Refreshing enabled) Data setup time (to WR↑) tSODWR Data setup time (to WR↓) tSODWF (3 + 2n) tCYX – 100 MIN. 146 Note ns tCYX – 60 MIN. 22 ns MIN. 42 ns (Refreshing enabled) ASTB↑ delay time from WR↑ tDWST tWWL1 tCYX – 40 (3 + 2n) tCYX – 50 MIN. 196 MIN. 114 Note ns (Refreshing disabled) WR low-level width tWWL2 (2 + 2n) tCYX – 50 Note ns (Refreshing enabled) WAIT↓ input time from address tDAWT 3tCYX – 100 MAX. 146 ns WAIT↓ input time from ASTB↓ tDSTWT 2tCYX – 80 MAX. 84 ns Remark Note 48 "n" indicates the number of waits. When n = 0 µPD78217A, 78218A tCYX DEPENDENT BUS TIMING DEFINITION (2/2) PARAMETER WAIT hold time from ASTB↓ SYMBOL tHSTWT FORMULA 2XtCYX + 10 MIN./MAX. MIN. WAIT↑ delay time from ASTB↓ tDSTWTH 2(1 + X)tCYX – 55 MAX. WAIT↓ input time from RD↓ tDRWTL tCYX – 60 MAX. WAIT hold time from RD↓ tHRWT (2X – 1)tCYX + 5 MIN. 12 MHz 174 273 Note Note 22 Note 87 ns ns ns ns WAIT↑ delay time from RD↓ tDRWTH (2X + 1)tCYX – 60 MAX. Data input time from WAIT↑ tDWTID tCYX – 20 MAX. 62 ns WR↑ delay time from WAIT↑ tDWTW 2tCYX – 10 MIN. 154 ns RD↑ delay time from WAIT↑ tDWTR tCYX – 10 MIN. 72 ns WAIT input time from WR↓ (At refresh disabled) tDWWTL tCYX – 60 MAX. 22 ns WAIT hold time Refresh disabled tHWWT1 (2X – 1)tCYX + 5 MIN. from WR↓ Refresh enabled WAIT↑ delay Refresh disabled time from WR↓ Refresh enabled tHWWT2 tDWWTH1 tDWWTH2 2(X – 1)tCYX + 5 (2X + 1)tCYX – 60 MIN. MAX. 2XtCYX – 60 MAX. 186 Note UNIT Note 87 5 Note 186 104 Note Note ns ns ns ns ns REFRQ↓ delay time from RD↑ tDRRFQ 2tCYX – 10 MIN. 154 ns REFRQ↓ delay time from WR↑ tDWRFQ tCYX – 10 MIN. 72 ns REFRQ low-level width tWRFQL 2tCYX – 44 MIN. 120 ns ASTB↑ delay time from REFRQ↑ tDRFQST 4tCYX – 48 MIN. 280 ns Remarks 1. 2. 3. Note X: The number of the external waits (1, 2, ...) tCYX ≅ 82 ns (fXX = 12 MHz) "n" indicates the number of waits. When X = 1 49 µPD78217A, 78218A DATA RETENTION CHARACTERISTICS (TA= –40 to +85 °C) PARAMETER SYMBOL Data retention voltage VDDDR Data retention current IDDDR TEST CONDITIONS STOP mode MIN. TYP. 2.5 MAX. UNIT 5.5 V VDDDR = 2.5 V 2 20 µA VDDDR = 5 V ±10 % 5 50 µA VDD rise time tRVD 200 µs VDD fall time tFVD 200 µs tHVD 0 ms tDREL 0 ms Crystal resonator 30 ms Ceramic resonator 5 ms VDD hold time (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time Low-level input voltage High-level input voltage Note tWAIT VIL Specified pin Note VIH 0 0.1 VDDDR V 0.9 VDDDR VDDDR V RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK, P26/INTP5, P27/SI, P32/SCK, P33/SO/SB0 and EA pins. AC Timing Test Point V DD-1 V 0.8 V DD or 2.2 V 0.8 V DD or 2.2 V Test Points 0.8 V 0.45 V 50 0.8 V µPD78217A, 78218A Timing Waveform Read operation tCYX X1 A8-A15 P60-P63 tDAID tDAR tHRA AD0-AD7 tSAST tHSTA tHRID tFAR tDRA tDSTID ASTB tWSTH tDSTR tDRST tDRID tWRL RD Write operation tCYX X1 A8-A15 P60-P63 tHWA tDAW AD0-AD7 tSAST tHSTA tHWOD tDSTOD tDWOD tSODWF tSODWR ASTB tWSTH tDWST tWWL1 tWWL2 WR tDSTW1 tDSTW2 51 µPD78217A, 78218A External WAIT Signal Input Timing Read operation A8-A15 P60-P63 AD0-AD7 tDWTID ASTB tDSTWTH tHSTWT tDRWTH tHRWT RD tDSTWT tDWTR tDRWTL tDAWT WAIT Write operation A8-A15 P60-P63 AD0-AD7 tDWWTH1 tHWWT1 ASTB tDSTWTH tHSTWT tDWWTH2 tHWWT2 WR tDAWT tDSTWT WAIT tDWWTL 52 tDWTW µPD78217A, 78218A Refresh Timing Waveform Refresh after read ASTB RD tDRRFQ tDRFQST REFRQ tWRFQL Refresh after write ASTB WR tDWRFQ tDRFQST REFRQ tWRFQL 53 µPD78217A, 78218A Serial Operation 3-wire serial I/O mode tWSKL tWSKH SCK tSSSK tCYSK tHSSK Input Data SI tDSBSK1 Output Data SO SBI Mode Bus release signal transfer SCK tHSBSK tWSBL tWSBH tSSBSK SB0 Command signal transfer tWSKL tWSKH SCK tHSBSK SB0 54 tSSBSK tCYSK tDSBSK2 tSSSK tHSSK I/O Data µPD78217A, 78218A Interrupt Input Timing tWNIH tWNIL 0.8 VDD 0.8 V NMI tWITH tWITL 0.8 VDD 0.8 V INTP0-INTP5 Reset Input Timing tWRSH RESET tWRSL 0.8 VDD 0.8 V 55 µPD78217A, 78218A External Clock Timing tWXH 0.8 VDD 0.8 V X1 tXF tXR tWXL tCYX Data Retention Characteristics STOP Mode Setting VDDDR VDD tDREL tHVD tWAIT tFVD RESET tRVD 0.8 VDD 0.8 V NMI 0.8 VDD (Release by Falling Edge) 0.8 V 0.8 VDD NMI (Release by Rising Edge) 56 0.8 V µPD78217A, 78218A 7. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE B C M R ITEM MILLIMETERS INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 Remark ES versions have the same package drawings and use the same materials as mass-produced versions. 57 µPD78217A, 78218A 64 PIN PLASTIC QFP ( 14) A B 48 49 33 32 F Q 5°±5° S D C detail of lead end 64 1 G 17 16 H I M J M P K N L P64GC-80-AB8-3 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. Remark 58 ITEM MILLIMETERS INCHES A 17.6 ± 0.4 0.693 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 1.0 0.039 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.55 0.100 Q 0.1 ± 0.1 0.004 ± 0.004 S 2.85 MAX. 0.112 MAX. ES versions have the same package drawings and use the same materials as mass-produced versions. µPD78217A, 78218A ★ 8. RECOMMENDED SOLDERING CONDITIONS The µPD78217A/78218A should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting Technology Manual” (IEI-1207). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 8-1 Surface Mounting Type Soldering Conditions µPD78217AGC-AB8/78218AGC-×××-AB8 : 64-pin plastic QFP (14 x 14 mm) Soldering Method Infrared ray reflow Soldering Conditions Package peak temperature: 235 °C, Reflow time: 30 seconds or less (at 210 °C or higher), Maximum number of reflow processes: 2 times <Cautions> (1) After the first reflow process, cool the package down to room temperature , then start the second reflow process. Symbol IR35-00-2 (2) After the first reflow process, do not use water to remove residual flux. VPS Package peak temperature: 215 °C, Reflow time: 40 seconds or less (at 200 °C or higher), Maximum number of reflow processes: 2 times <Cautions> (1) After the first reflow process, cool the package down to room temperature , then start the second reflow process. (2) After the first reflow process, do not use water to remove residual flux. Partial heating Pin temperature: 300 °C or below, Heat time: 3 seconds or less (per each side of the device) Caution VP15-00-2 ––– Apply only one kind of soldering method to a device, except for partial heating method. Table 8-2 Insertion Type Soldering Conditions µPD78217ACW/78218ACW-××× : 64-pin plastic shrink DIP (750 mil) Soldering Method Soldering Conditions Wave soldering (pin only) Solder temperature: 260 °C or below, Flow time: 10 seconds or less Partial heating Pin temperature: 300 °C or below, Heat time: 3 seconds or less (per pin) Caution The wave soldering process must be applied only to pins, and make sure that the package body does not get jet soldered. 59 µPD78217A, 78218A APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µ PD78217A/78218A. Language Processing Software RA78K/II Notes1, 2, 3 78K/II series common assembler package CC78K/II Notes1, 2, 3 78K/II series common C compiler package CC78K/II-L Notes1, 2, 3 78K/II series common C compiler library source file PROM Writing Tools PG-1500 PROM programmer PA-78P214CW PA-78P214GC Programmer adapters connected to PG-1500 PG-1500 controller Notes1, 2 PG-1500 control program Debugging Tools IE-78240-R-A IE-78240-R Note4 µPD78218A subseries common in-circuit emulators IE-78200-R-BK 78K/II series common break board IE-78240-R-EM IE-78200-R-EM Note4 µPD78218A subseries evaluation emulation boards EP-78210CW Note4 EP-78240CW-R EP-78210GC Note4 EP-78240GC-R µPD78218A subseries common emulation probes EV-9200GC-64 Socket to be mounted on a user system board made for 64-pin plastic QFP SD78K/II Notes1, 2 IE-78240-R-A screen debugger DF78210 Notes1, 2 µPD78218A subseries device file Fuzzy Inference Development Support System 60 FE9000 Note1, FE9200 Note5 Fuzzy knowledge data creation tool FT9080 Note1, FT9085 Note2 Translator FI78K/II Notes1, 2 Fuzzy inference module FD78K/II Notes1, 2 Fuzzy inference debugger µPD78217A, 78218A Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM (PC DOSTM) based 3. HP9000 series 300TM (HP-UXTM) based, SPARCstationTM (Sun OSTM) based, EWS-4800 series (EWS-UX/ V) based 4. No longer manufactured and not available for purchase 5. IBM PC/AT (PC DOS + WindowsTM) based Remark For third-party development tools, see the 78K/II Series Development Tool Selection Guide (EF-231). 61 µPD78217A, 78218A APPENDIX B. RELATED DOCUMENTS Device Related Documents Document No. (Japanese) Document No. (English) µPD78218A Subseries User's Manual: Hardware IEU-755 IEU-1313 78K/II Series User's Manual: Instruction IEU-754 IEU-1311 78K/II Series Application Note Fundamentals IEA-607 IEA-1220 Application IEA-700 IEA-1282 Floating Point Operation Program IEA-686 IEA-1273 78K/II Series Selection Guide IF-304 IF-1160 78K/II Series Instruction Table IEM-5101 78K/II Series Instruction Set IEM-5102 µPD78218A Series Special Function Register Table IEM-5532 Document Name Development Tool Related Documents (User‘s Manuals) Document No. (Japanese) Document No. (English) Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 EEU-817 EEU-1402 Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Document Name RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler CC78K Series Library Source File EEU-777 PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller EEU-704 EEU-1291 IE-78240-R-A In-Circuit Emulator EEU-796 EEU-1395 Hardware EEU-705 EEU-1322 Software EEU-706 EEU-1331 Introduction EEU-841 Reference EEU-813 IE-78240-R In-Circuit Emulator SD78K/II Screen Debugger SD78K/II Screen Debugger MS-DOS Based PC DOS Based Introduction Reference 78K/II Series Development Tool Selection Guide Caution 62 EEU-956 EEU-1447 EF-231 The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. µPD78217A, 78218A Embedded Software Related Documents (User’s Manuals) Document Name RX78K/II Real-Time OS Document No. (Japanese) Basic EEU-910 Installation EEU-884 Debugger EEU-895 Technical EEU-885 Fuzzy Knowledge Data Creation Tool Document No. (English) EEU-829 EEU-1438 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator EEU-862 EEU-1444 78K/II Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU-860 EEU-1440 EEU-917 EEU-1459 78K/II Series Fuzzy Inference Debugger Other Related Documents Document Name Document No. (Japanese) Document No. (English) QTOP Microcomputer Pamphlet IB-5040 Semiconductor Device Package Manual IEI-635 IEI-1213 Semiconductor Device Mounting Technology Manual IEI-616 IEI-1207 Quality Grades on NEC Semiconductor Devices IEI-620 IEI-1209 NEC Semiconductor Device Reliability & Quality Control System IEM-5068 Electrostatic Discharge (ESD) Test MEM-539 Guide to Quality Assurance for Semiconductor Devices MEI-603 Microcomputer-Related Products Guide – Third Party Products MEI-604 Caution MEI-1202 The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 63 µPD78217A, 78218A [MEMO] 64 µPD78217A, 78218A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 65 µPD78217A, 78218A The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: µPD78217ACW, 78217AGC-AB8 The customer must judge the need for license: µPD78218ACW-xxx, 78218AGC-xxx-AB8 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. SPARCstation is a trademark of SPARC International, Inc. Sun OS is a trademark of Sun Microsystems, Inc. HP9000 series 300 and HP-UX are trademarks of Hewlett-Packard Company.