DATA SHEET MOS INTEGRATED CIRCUIT µPD784915B, 784916B 16-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The µPD784915B, 784916B are members of the NEC 78K/IV Series of microcontrollers equipped with a highspeed 16-bit CPU and are versions with improved electrical characteristics of the µPD784915A, 784916A of the µPD784915 Subseries. This series contains many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer unit) suitable for software servo control and VCR analog circuits. A one-time PROM version of the µPD784916B, the µPD78P4916, is also available. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD784915 Subseries User’s Manual - Hardware: U10444E 78K/IV Series User’s Manual - Instruction: U10905E FEATURES • High instruction execution speed realized by 16-bit CPU core • Minimum instruction execution time: 250 ns (with 8-MHz internal clock) • High internal memory capacity Part Number ROM µPD784915B 49152 bytes µPD784916B 63488 bytes RAM 1280 bytes • VCR analog circuits conforming to VHS Standard • CTL amplifier • RECCTL driver (rewritable) • CFG amplifier • DFG amplifier • DPG comparator • DPFG separation circuit (ternary separation circuit) • Reel FG comparator (2 channels) • CSYNC comparator • Timer unit (super timer unit) for servo control • Serial interface: 2 channels (3-wire serial I/O) • A/D converter: 12 channels (conversion time: 10 µs) • Low-frequency oscillation mode: main system clock frequency = internal clock frequency • Low-power dissipation mode: CPU can operate with a subsystem clock. • Supply voltage range: VDD = 2.7 to 5.5 V • Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current APPLICATIONS Control system/servo/timer of VCR Unless mentioned otherwise, the µPD784916B is described as the representative product. The information in this document is subject to change without notice Document No. U13118EJ1V0DS00 (1st edition) Date Published January 1998 N CP(K) Printed in Japan © 1996 1998 µPD784915B, 784916B ORDERING INFORMATION Part Number Package µPD784915BGF-xxx-3BA 100-pin plastic QFP (14 x 20 mm) µPD784916BGF-xxx-3BA 100-pin plastic QFP (14 x 20 mm) Remark xxx indicates ROM code suffix. Product Development of 78K/IV Series : Under mass production : Under development I2C bus supported Multimaster I2C bus supported µPD784038Y µPD784225Y µPD784038 Standard Internal memory capacity was enhanced Pin compatible with µPD784026 µPD784026 Enhanced A/D, 16-bit timer, and power management 80-pin, ROM correction was enhanced Multimaster I2C bus supported Multimaster I2C bus supported µPD784216Y µPD784218Y µPD784216 100-pin I/O and internal memory capacity was enhanced µPD784054 µPD784046 ASSP On-chip 10-bit A/D µ PD784955 DC inverter control µPD784908 On-chip IEBusTM Controller µPD78F4943 For CD-ROM, 56 Kbytes of flash memory µPD784915 On-chip software servo control VCR analog circuit, enhanced timer 2 µPD784225 Multimaster I2C bus supported µPD784928Y µPD784928 Function of the µPD784915 was enhanced µPD784218 Internal memory capacity was enhanced ROM correction was added µPD784915B, 784916B Function List (1/2) µPD784915B Item µPD784916B Internal ROM capacity 49152 bytes Internal RAM capacity 1280 bytes Operating clock 16 MHz (internal clock: 8 MHz) Low frequency oscillation mode: 8 MHz (internal clock: 8 MHz) Low power dissipation mode: 32.768 kHz (subsystem clock) Minimum instruction execution time 250 ns (with 8-MHz internal system clock) I/O ports 54 Real-time output port Super timer unit 63488 bytes input : 8 I/O : 46 11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation) Timer/counter Timer/counter TM0 (16 bits) TM1 (16 bits) FRC (22 bits) TM3 (16 bits) UDC (5 bits) EC (8 bits) EDV (8 bits) Compare register 3 3 2 1 4 1 Capture register Input signal CFG DFG HSW VSYNC CTL TREEL SREEL Number of bits 22 22 16 22 16 22 22 VCR special circuit General-purpose timer PWM output • • • • Capture register Remark 1 6 1 For HSW signal generation For CFG signal division Measurable cycle 125 ns to 524 ms 125 ns to 524 ms 1 µs to 65.5 ms 125 ns to 524 ms 1 µs to 65.5 ms 125 ns to 524 ms 125 ns to 524 ms Operating edge ↑ ↓ ↑ ↑ ↓ ↑ ↑ ↓ ↑ ↓ ↑ ↓ VSYNC separation circuit, HSYNC separation circuit VISS detection, wide aspect detection circuits Field identification circuit Head amplifier switch/chroma rotation output circuit Timer TM2 (16 bits) TM4 (16 bits) TM5 (16 bits) • 16-bit accuracy • 8-bit accuracy Compare register 1 1 (capture/compare) 1 Capture register — 1 — : 3 channels (carrier frequency: 62.5 kHz) : 3 channels (carrier frequency: 62.5 kHz) Serial interface 3-wire serial I/O: 2 channels • BUSY/STRB control (1 channel only) A/D converter 8-bit resolution × 12 channels, conversion time: 10 µs 3 µPD784915B, 784916B Function List (2/2) µPD784915B Item µPD784916B Analog circuit • • • • • • CTL amplifier RECCTL driver (rewritable) DFG amplifier, DPG comparator, CFG amplifier DPFG separation circuit (ternary separation circuit) Reel FG comparator (2 channels) CSYNC comparator Interrupt 4 levels (programmable), vector interrupt, macro service, context switching External 9 (including NMI) Internal 19 (including software interrupt) Standby function HALT/STOP mode/low power dissipation mode/low power dissipation HALT mode STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or INTP1/INTP2/KEY0-KEY4 pins Watch function 4 0.5-second measurement, low-voltage operation (VDD = 2.7 V) Supply voltage VDD = 2.7 to 5.5 V Package 100-pin plastic QFP (14 × 20 mm) µPD784915B, 784916B PIN CONFIGURATION (Top View) • 100-pin plastic QFP (14 x 20 mm) µPD784915BGF-xxx-3BA CSYNCIN REEL0IN/INTP3 REEL1IN DFGIN DPGIN CFGCPIN CFGAMPO CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECCTLRECTTL+ CTLDLY AVSS2 ANI11 ANI10 µPD784916BGF-xxx-3BA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ANI9 ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVDD2 P96 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV NMI INTP0 INTP1 INTP2 P00 P01 P02 P03 P04 P05 P06 P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07 P64 P65/HWIN P66/PWM4 P67/PWM5 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 PWM0 PWM1 SCK2 SO2 SI2/BUSY VDD XT1 XT2 VSS X2 X1 RESET IC PTO02 PTO01 PTO00 P87/PTO11 P86/PTO10 P85/PWM3 P84/PWM2 P83/ROTC P82/HASW Caution Directly connect the IC (Internally Connected) pin to VSS. 5 µPD784915B, 784916B ANI0-ANI11 : Analog Input P00-P07 : Port0 AVDD1, AVDD2 : Analog Power Supply P40-P47 : Port4 AVSS1, AVSS2 : Analog Ground P50-P57 : Port5 AVREF : Analog Reference Voltage P60-P67 : Port6 BUSY : Serial Busy P70-P77 : Port7 BUZ : Buzzer Output P80, P82-P87 : Port8 CFGAMPO : Capstan FG Amplifier Output P90-P96 : Port9 CFGCPIN : Capstan FG Capacitor Input PTO00-PTO02 : Programmable Timer Output CFGIN : Analog Unit Input PTO10, PTO11 CLO : Clock Output PWM0-PWM5 CSYNCIN : Analog Unit Input RECCTL+, RECCTL– : RECCTL Output/PBCLT Input CTLDLY : Control Delay Input REEL0IN, REEL1IN : Analog Unit Input CTLIN : CTL Amplifier Input Capacitor RESET : Reset CTLOUT1, CTLOUT2 : CTL Amplifier Output ROTC : Chrominance Rotate Output DFGIN : Analog Unit Input SCK1, SCK2 : Serial Clock DPGIN : Analog Unit Input SI1, SI2 : Serial Input ENV : Envelope Input SO1, SO2 : Serial Output HASW : Head Amplifier Switch Output STRB : Serial Strobe : Pulse Width Modulation Output HWIN : Hardware Timer External Input VDD : Power Supply IC : Internally Connected VREFC : Reference Amplifier Capacitor INTP0-INTP3 : Interrupt From Peripherals VSS : Ground KEY0-KEY4 : Key Return X1, X2 : Crystal (Main System Clock) NMI : Nonmaskable Interrupt XT1, XT2 : Crystal (Subsystem Clock) 6 µPD784915B, 784916B INTERNAL BLOCK DIAGRAM NMI INTP0 to INTP3 INTERRUPT CONTROL SYSTEM CONTROL PWM0 to PWM5 PTO00 to PTO02 SUPER TIMER UNIT PTO10, PTO11 VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTLCTLDLY AVDD1, AVDD2 AVSS1, AVSS2 AVREF ANI0 to ANI1 VDD VSS X1 X2 XT1 XT2 RESET CLOCK OUTPUT CLO BUZZER OUTPUT BUZ KEY INPUT KEY0 to KEY4 P00 to P07 78K/IV 16-bit CPU CORE (RAM: 512 bytes) ANALOG UNIT & A/D CONVERTER SI1 SO1 SCK1 SERIAL INTERFACE 1 SI2/BUSY SO2 SCK2 STRB SERIAL INTERFACE 2 RAM 768 bytes ROM REAL-TIME OUTPUT PORT P80, P82, P83 PORT0 P00 to P07 PORT4 P40 to P47 PORT5 P50 to P57 PORT6 P60 to P67 PORT7 P70 to P77 PORT8 P80, P82 to P87 PORT9 P90 to P96 Remark Internal ROM capacity depends on the product. 7 µPD784915B, 784916B SYSTEM CONFIGURATION EXAMPLE • Camera-contained VCR µ PD784916B DFG DPG Drum motor M Driver M Driver Key matrix DPGIN PORT PWM0 CFG Capstan motor PORT DFGIN PORT SCK1 SI1 SO1 INTP0 CFGIN INTP0 SCK Cameracontrolling SO microcontroller SI µ PD784036 PORT PWM1 Camera block RECCTL+ PORT SCK2 SO2 BUSY CTL head RECCTL- Loading motor M Driver CS CLK DATA BUSY LCD C/D µ PD7225 PWM2 LCD display panel PORT Audio/video signal processing circuit Remote controller signal Remote controller reception signal µ PC2800A STRB PORT INTP2 X1 X2 16 MHz 8 PORT Composite sync signal CSYNCIN Video head switch PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 XT1 XT2 32.768 kHz CS CLK DATA BUSY STB OSD µ PD6461 Mechanical block µPD784915B, 784916B • Stationary VCR µ PD784916B DFG DPG Drum motor M Driver DFGIN PORT SCK1 SI1 SO1 DPGIN PWM0 CFG STB CLK FIPTM C/D DOUT µ PD16311 DIN CFGIN FIP Capstan motor M Driver Key matrix PWM1 PORT SCK2 SO2 CS CLK DATA OSD µ PD6464 RECCTL+ CTL head RECCTL- Loading motor M Driver Reel FG0 M Driver PWM2 PORT Composite sync signal Audio/video signal CSYNCIN Video head switch processing circuit PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 REEL0IN Driver Reel FG1 Tuner PORT Mechanical block PWM3 Reel motor M PWM5 PORT PWM4 INTP2 REEL1IN Low frequency oscillation mode X1 X2 XT1 8 MHz Remote controller reception signal Remote controller signal µ PC2800A XT2 32.768 kHz 9 µPD784915B, 784916B CONTENTS 1. DIFFERENCES AMONG µPD784915 SUBSERIES PRODUCTS .................................................. 11 2. PIN FUNCTIONS .............................................................................................................................. 12 2.1 2.2 2.3 Port Pins ................................................................................................................................................ Non-Port Pins ........................................................................................................................................ I/O Circuits and Connection of Unused Pins ...................................................................................... 12 13 15 3. INTERNAL BLOCK FUNCTIONS .................................................................................................... 19 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 4. CPU Registers ....................................................................................................................................... 3.1.1 General-purpose registers ......................................................................................................... 3.1.2 Other CPU registers .................................................................................................................... Memory Space ....................................................................................................................................... Special Function Registers (SFRs) ..................................................................................................... Ports ....................................................................................................................................................... Real-time Output Port ........................................................................................................................... Super Timer Unit ................................................................................................................................... Serial Interface ...................................................................................................................................... A/D Converter ........................................................................................................................................ VCR Analog Circuits ............................................................................................................................. Watch Function ..................................................................................................................................... Clock Output Function ......................................................................................................................... 19 19 20 20 23 28 29 33 38 40 41 47 48 INTERNAL/EXTERNAL CONTROL FUNCTION ............................................................................ 49 4.1 4.2 4.3 4.4 Interrupt Function ................................................................................................................................. 4.1.1 Vector interrupt ........................................................................................................................... 4.1.2 Context switching ....................................................................................................................... 4.1.3 Macro service .............................................................................................................................. 4.1.4 Application example of macro service ..................................................................................... Standby Function .................................................................................................................................. Clock Generator Circuit ........................................................................................................................ Reset Function ...................................................................................................................................... 49 51 51 52 54 57 59 60 5. INSTRUCTION SETS ....................................................................................................................... 61 6. ELECTRICAL CHARACTERISTICS ............................................................................................... 65 7. PACKAGE DRAWING ..................................................................................................................... 77 8. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 78 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 79 APPENDIX B. RELATED DOCUMENTS ............................................................................................... 81 10 µPD784915B, 784916B 1. DIFFERENCES AMONG µPD784915 SUBSERIES PRODUCTS The µPD784915 Subseries consists of the six products listed in Table 1-1. The µPD784915A is a low-cost processshrinked version of the µPD784915. The µPD784916A expands the internal ROM capacity of the µPD784915 to 62 Kbytes. The µPD784915B and 784916B feature improved electrical characteristics compared to the µPD784915A and 784916A. The µPD78P4916 features writable one-time PROM instead of the mask ROM of the µPD784915, 784915A, 784916A, 784915B, and 784916B. Except for this substitution of PROM for ROM and the fact that PROM capacity differs from the ROM capacities offered in the other products, the µPD78P4916 has the same functions as those products. In switching from the PROM product, used for debugging and testing application systems, to the mask ROM products for mass production, be careful to check the differences among these products. For details on the CPU functions and the internal hardware, refer to µPD784915 Subseries User’s Manual — Hardware (U10444E). Table 1-1. Differences among µPD784915 Subseries Products Item Internal ROM µPD784915, 784915A µPD784916A µPD784915B µPD784916B µPD78P4916 Mask ROM 49152 bytes 63488 bytes 49152 bytes 63488 bytes 63232 bytes Note Internal RAM 1280 bytes 2048 bytesNote Internal memory capacity selection register (IMS) Not provided Provided Electrical characteristics The electrical characteristics of the µPD784915A/784916A, the µPD784915B/784916B, and the µPD78P4916 differ with respect to the items listed below. • P40 to P47, P50 to P57: Low-level input voltage • VDD supply current • Data hold current • CTL amplifier: Phase signal elimination ratio • CFG amplifier: CFGAMPO low-level output current For details, refer to the data sheet of each product. • µPD784915A/784916A Data Sheet (U11022J) • µPD784915B/784916B Data Sheet (This document) • µPD78P4916 Data Sheet (U11045J) Pin connections In the µPD78P4916, pin function for PROM read/write has been added. Note The internal PROM and internal RAM capacities can be changed using the internal memory selection register (IMS). Caution The PROM version and mask ROM version differ in noise immunity and noise radiation, etc. When considering replacing a PROM version with a mask ROM version when switching from preproduction to volume production, perform sufficient evaluation using a CS version (not ES version) of the mask ROM version. 11 µPD784915B, 784916B 2. PIN FUNCTIONS 2.1 Port Pins Pin Name P00 to P07 I/O I/O Alternate Function Function Real-time 8-bit I/O port (port 0). output port • Can be set in input or output mode in 1-bit units. • Can be connected with software pull-up resistors. P40 to P47 I/O - 8-bit I/O port (port 4). • Can be set in input or output mode in 1-bit units. • Can be connected with software pull-up resistors. P50 to P57 I/O - 8-bit I/O port (port 5). • Can be set in input or output mode in 1-bit units. • Can be connected with software pull-up resistors. P60 I/O STRB/CLO 8-bit I/O port (port 6). P61 SCK1/BUZ • Can be set in input or output mode in 1-bit units. P62 SO1 • Can be connected with software pull-up resistors. P63 SI1 P64 - P65 HWIN P66 PWM4 P67 PWM5 P70 to P77 P80 Input I/O P82 ANI0 to ANI7 8-bit input port (port 7) Real-time Pseudo VSYNC output 7-bit I/O port (port 8). output port HASW output • Can be set in input or output mode in 1-bit units. P83 ROTC output • Can be connected with software pullup resistors. P84 PWM2 P85 PWM3 P86 PTO10 P87 PTO11 P90 P91 to P95 P96 12 I/O ENV 7-bit I/O port (port 9). KEY0 to KEY4 • Can be set in input or output mode in 1-bit units. - • Can be connected with software pull-up resistors. µPD784915B, 784916B 2.2 Non-Port Pins (1/2) Pin Name REEL0IN I/O Input Alternate Function INTP3 REEL1IN - Function Reel FG input DFGIN - Drum FG, PFG input (ternary) DPGIN - Drum PG input CFGIN - Capstan FG input CSYNCIN - Composite SYNC input CFGCPIN - CFG comparator input CFGAMPO Output - CFG amplifier output PTO00 Output - Programmable timer output of super timer unit PTO01 - PTO02 - PTO10 P86 PTO11 PWM0 P87 - Output PWM1 PWM output of super timer unit - PWM2 P84 PWM3 P85 PWM4 P66 PWM5 P67 HASW Output P82 Head amplifier switch signal output ROTC Output P83 Chroma rotation signal output ENV Input P90 Envelope signal input SI1 Input P63 Serial data input (serial interface channel 1) SO1 Output SCK1 I/O SI2 Input SO2 Output SCK2 I/O BUSY Input STRB ANI0 to ANI7 Output Analog input ANI8 to ANI11 CTLIN P62 Serial data output (serial interface channel 1) P61/BUZ Serial clock I/O (serial interface channel 1) BUSY Serial data input (serial interface channel 2) - Serial data output (serial interface channel 2) - Serial clock I/O (serial interface channel 2) SI2 Serial busy signal input (serial interface channel 2) P60/CLO Serial strobe signal output (serial interface channel 2) P70 to P77 Analog signal input of A/D converter - - CTL amplifier input capacitor connection CTLOUT1 Output - CTL amplifier output CTLOUT2 I/O - Logic signal input/CTL amplifier output RECCTL+, RECCTL– I/O - RECCTL signal output/PBCTL signal input CTLDLY - - External time constant connection (for RECCTL rewriting) VREFC - - VREF amplifier AC connection NMI Input - Non-maskable interrupt request input INTP0 to INTP2 Input - External interrupt request input INTP3 Input REEL0IN KEY0 to KEY4 Input P91 to P95 CLO Output P60/STRB Clock output BUZ Output P61/SCK1 Buzzer output Key input signal input 13 µPD784915B, 784916B 2.2 Non-Port Pins (2/2) Pin Name I/O Alternate Function P65 Function HWIN Input RESET Input - Reset input External input of hardware watch counter X1 Input - Crystal connection for main system clock oscillation X2 - Crystal connection for subsystem clock oscillation. XT1 Input XT2 - AVDD1, AVDD2 - - Positive power supply to analog circuits AVSS1, AVSS2 - - GND of analog circuits AVREF - - Reference voltage input to A/D converter VDD - - Positive power supply to digital circuits VSS - - GND of digital circuits IC - - Internally connected. Directly connect to VSS. 14 Crystal connection for watch clock oscillation µPD784915B, 784916B 2.3 I/O Circuits and Connection of Unused Pins Table 2-1 shows the I/O circuit type of each pin and the recommended connection of unused pins. For the configuration of each type of I/O circuit, refer to Figure 2-1. Table 2-1. I/O Circuit Type of each Pin and Recommended Connection of Unused Pins (1/2) Pin P00 to P07 I/O Circuit Type I/O 5-A I/O P40 to P47 Recommended Connection of Unused Pins Input: Connect to VDD Output: Leave open P50 to P57 P60/STRB/CLO P61/SCK1/BUZ 8-A P62/SO1 5-A P63/SI1 8-A P64 5-A P65/HWIN 8-A P66/PWM4 5-A P67/PWM5 P70/ANI0 to P77/ANI7 P80 9 Input 5-A I/O P82/HASW Connect to VSS Input: Connect to VDD Output: Leave open P83/ROTC P84/PWM2 P85/PWM3 P86/PTO10 P87/PTO11 P90/ENV P91/KEY0 to P95/KEY4 8-A P96 5-A SI2/BUSY 2-A Input 4 Output 8-A I/O ANI8 to ANI11 7 Input RECCTL+, RECCTL– — I/O SO2 SCK2 Connect to VDD Hi-Z: Connect to VSS via a pull-down resistor Others: Leave open Input: Connect to VDD Output: Leave open Connect to VSS When ENCTL = 0 and ENREC = 0: Connect to VSS Remark ENCTL : bit 1 of amplifier control register (AMPC) ENREC: bit 7 of amplifier mode register 0 (AMPM0) 15 µPD784915B, 784916B Table 2-1. I/O Circuit Type of each Pin and Recommended Connection of Unused Pins (2/2) Pin DFGIN I/O Circuit Type I/O — Input Recommended Connection of Unused Pins When ENDRUM = 0: Connect to VSS DPGIN When ENDRUM = 0 or ENDRUM = 1 and SELPGSEPA = 0: Connect to VSS CFGIN, CFGCPIN When ENCAP = 0: Connect to VSS CSYNCIN When ENCSYN = 0: Connect to VSS REEL0IN/INTP3, REEL1IN When ENREEL = 0: Connect to VSS CTLOUT1 — Output CTLOUT2 — I/O CFGAMPO — Output CTLIN — — Leave open When ENCTL = 0 and ENCOMP = 0: Connect to VSS When ENCTL = 1: Leave open Leave open When ENCTL = 0: Leave open VREFC When ENCTL = 0 and ENCAP = 0 and ENCOMP = 0: Leave open CTLDLY Leave open PWM0, PWM1 3 Output 2 Input Leave open PTO00 to PTO02 NMI INTP0 Connect to VDD Connect to VDD or VSS INTP1, INTP2 2-A Input Connect to VDD AVDD1, AVDD2 — — Connect to VDD AVREF, AVSS1, AVSS2 Connect to VSS RESET 2 — XT1 — — — Connect to VSS XT2 Leave open IC Directly connect to VSS Remark ENDRUM : bit 2 of amplifier control register (AMPC) SELPGSEPA : bit 2 of amplifier mode register 0 (AMPM0) 16 ENCAP : bit 3 of amplifier control register (AMPC) ENCSYN : bit 5 of amplifier control register (AMPC) ENREEL : bit 6 of amplifier control register (AMPC) ENCTL : bit 1 of amplifier control register (AMPC) ENCOMP : bit 4 of amplifier control register (AMPC) µPD784915B, 784916B Figure 2-1. I/O Circuits of Pins (1/2) Type 2 Type 5-A IN VDD Schmitt trigger input with hysteresis characteristics pullup enable P-ch VDD Type 2-A data P-ch IN/ OUT VDD output disable pullup enable P-ch N-ch input enable IN Schmitt trigger input with hysteresis characteristics Type 3 Type 7 VDD P-ch data IN OUT P-ch N-ch + Comparator - N-ch VREF (threshold voltage) Type 4 Type 8-A VDD pullup enable VDD data VDD P-ch OUT output disable P-ch data P-ch IN/ OUT N-ch output disable N-ch Push-pull output that can make output high impedance (both P-ch and N-ch are off) 17 µPD784915B, 784916B Figure 2-1. I/O Circuits of Pins (2/2) Type 9 IN P-ch N-ch + Comparator - VREF (threshold voltage) input enable 18 µPD784915B, 784916B 3. INTERNAL BLOCK FUNCTIONS 3.1 CPU Registers 3.1.1 General-purpose registers The µPD784916B has eight banks of general-purpose registers. One bank consists of sixteen 8-bit generalpurpose registers. Two of these 8-bit registers can be used in pairs as a 16-bit register. Four of the 16-bit generalpurpose registers can be used to specify a 24-bit address in combination with an 8-bit address expansion register. These eight banks of general-purpose registers can be selected by software or context switching function. The general-purpose registers, except for the address expansion registers V, U, T, and W, are mapped to the internal RAM. Figure 3-1. Configuration of General-Purpose Registers A (R1) X (R0) B (R3) AX (RP0) C (R2) BC (RP1) R5 R4 RP2 R7 R6 RP3 V R9 R8 VP (RP4) VVP (RG4) U R11 R10 UP (RP5) UUP (RG5) T D (R13) E (R12) DE (RP6) TDE (RG6) W H (R15) L (R14) HL (RP7) WHL (RG7) ( Caution 8 banks ): absolute name Although R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of PSW to 1, do not use this function. The function of the RSS bit is planned to be deleted from the future models in the 78K/IV Series. 19 µPD784915B, 784916B 3.1.2 Other CPU registers (1) Program counter The program counter of the µPD784916B is 20 bits wide. The value of the program counter is automatically updated as the program is executed. 19 0 PC (2) Program status word This is a register that holds the various statuses of the CPU. Its contents are automatically updated as the program is executed. 15 14 13 12 UF RBS2 RBS1 RBS0 PSWH PSW 7 S PSWL Note 6 Z 5 Note RSS 4 AC 11 10 9 8 3 IE 2 P/V 1 0 0 CY The RSS flag is provided to maintain compatibility with the microcontrollers in the 78K/III Series. Always set this flag to 0 except when the software of the 78K/III Series is used. (3) Stack pointer This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the high-order 4 bits. SP 23 0 0 0 20 0 0 3.2 Memory Space The µPD784916B can access a 64 Kbyte memory space. Table 3-1 shows the addresses of the internal ROM and internal data areas. Table 3-1. Memory Space Part Number Caution Internal ROM Area µ PD784915B 0000H-BFFFH µ PD784916B 0000H-F7FFH Internal Data Area FA00H-FFFFH Some products in the 78K/IV Series can access up to 1 Mbyte of memory space in an address expansion mode which is set by the LOCATION instruction. However, the memory space of the µPD784916B is 64 Kbytes (0000H to FFFFH). Therefore, be sure to execute the LOCATION 0 instruction immediately after reset to set the memory space to 64 Kbytes (the LOCATION instruction cannot be used more than twice). 20 µPD784915B, 784916B Figure 3-2. Memory Map of µPD784915B FEFFH General-purpose registers (128 bytes) FE80H FE7FH Memory space (64 Kbytes) Data memory FFFFH FF00H FEFFH Special function register (SFR) (256 bytes) FE3BH Macro service control FE06H word area (54 bytes) FD00H FCFFH Internal RAM (1280 bytes) Data area (512 bytes) Program/data area (768 bytes) FA00H FA00H F9FFH BFFFH Cannot be used Program/data area (49152 bytes) 1000H 0FFFH Program memory/ data memory C000H BFFFH 0800H 07FFH Internal ROM (49152 bytes) 0000H 0080H 007FH 0040H 003FH 0000H CALLF entry area (2048 bytes) CALLT table area (64 bytes) Vector table area (64 bytes) 21 µPD784915B, 784916B Figure 3-3. Memory Map of µPD784916B FEFFH General-purpose registers (128 bytes) FE80H FE7FH FF00H FEFFH Special function register (SFR) (256 bytes) FE3BH Macro service control FE06H word area (54 bytes) FD00H FCFFH Internal RAM (1280 bytes) Program/data area (768 bytes) Cannot be used F800H F7FFH F7FFH Program/data area (63488 bytes) 1000H 0FFFH Internal ROM (63488 bytes) 0800H 07FFH 0080H 007FH 0040H 003FH 0000H 22 Data area (512 bytes) FA00H FA00H F9FFH Program memory/ data memory Memory space (64 Kbytes) Data memory FFFFH 0000H CALLF entry area (2048 bytes) CALLT table area (64 bytes) Vector table area (64 bytes) µPD784915B, 784916B 3.3 Special Function Registers (SFRs) Special function registers are assigned special functions and mapped to a 256-byte space from addresses FF00H through FFFFH. These registers include mode registers and control registers that control the internal peripheral hardware units. Caution Do not access an address to which no SFR is assigned. If such an address is accessed by mistake, the µPD784916B may be deadlocked. This deadlock can be cleared only by reset input. Table 3-2 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: • Abbreviation ............................ Abbreviation of an SFR. This abbreviation is reserved for NEC’s assembler (RA78K4). With a C compiler (CC78K4), the abbreviation can be used as an sfr variable by the #pragma sfr instruction. • R/W ......................................... Indicates whether the SFR in question can be read or written. R/W : Read/write R : Read only W : Write only • Bit length ................................. Indicates the bit length (word length) of the SFR. • Bit units for manipulation ....... Indicates bit units in which the SFR in question can be manipulated. An SFR that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. Specify an even address to manipulate this SFR. An SFR that can be manipulated in 1-bit units can be described for a bit manipulation instruction. • After reset ............................... Indicates the status of each register after the RESET signal has been input. 23 µPD784915B, 784916B Table 3-2. Special Function Registers (1/4) Bit Address Special Function Register (SFR) Name Symbol R/W Length Bit Units for After Manipulation Releasing 1 bit 8 bits 16 bits Reset Undefined FF00H Port 0 P0 8 √ √ - FF04H Port 4 P4 8 √ √ - FF05H Port 5 P5 8 √ √ - FF06H Port 6 P6 8 √ √ - FF07H Port 7 P7 R 8 √ √ - FF08H Port 8 P8 R/W 8 √ √ - R/W FF09H Port 9 P9 8 √ √ - FF0EH Port 0 buffer register L P0L 8 √ √ - FF0FH Port 0 buffer register H P0H 8 √ √ - FF10H Timer 0 compare register 0 CR00 16 - - √ FF11H Event counter compare register 0 ECC0 W 8 - √ - FF12H Timer 0 compare register 1 CR01 R/W 16 - - √ FF13H Event counter compare register 1 ECC1 W 8 - √ - FF14H Timer 0 compare register 2 CR02 R/W 16 - - √ FF15H Event counter compare register 2 ECC2 W 8 - √ - FF16H Timer 1 compare register 0 CR10 R/W 16 - - √ FF17H Event counter compare register 3 ECC3 W 8 - √ - FF18H Timer 1 compare register 1 CR11 R/W 16 - - √ FF1AH Timer 1 compare register 2 CR12 R 16 - - √ R/W FF1CH Timer 1 compare register 3 CR13 FF1EH Timer 2 compare register 0 CR20 16 - - √ 16 - - √ Cleared to 0 FF20H Port 0 mode register PM0 8 - √ - FF24H Port 4 mode register PM4 8 - √ - FF25H Port 5 mode register PM5 8 - √ - FF26H Port 6 mode register PM6 8 - √ - FF28H Port 8 mode register PM8 8 - √ - FDH FF29H Port 9 mode register PM9 8 - √ - 7FH FF2EH Real-time output port 0 control register FF30H Timer register 0 FF31H FF32H FF34H Free running counter (bits 0 to 15) FF35H Free running counter (bits 16 to 21) FF36H Timer register 2 TM2 FF38H Timer control register 0 TMC0 FF39H Timer control register 1 TMC1 FF3AH Timer control register 2 TMC2 FF3BH Timer control register 3 TMC3 W FFH RTPC R/W 8 √ √ - 00H TM0 R 16 - - √ Cleared to 0 Event counter EC R/W 8 - √ - Timer register 1 TM1 R 16 - - √ FRCL 16 - - √ 0000H FRCH 8 - √ - 00H 16 - - √ Cleared to 0 8 √ √ - 00H 8 √ √ - 8 √ √ - 8 √ √ - R/W 00×00000 Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the contents before initialization are undefined). 24 µPD784915B, 784916B Table 3-2. Special Function Registers (2/4) Bit Address Special Function Register (SFR) Name Symbol R/W Length Bit Units for After Manipulation Releasing 1 bit 8 bits 16 bits Reset TM3 R 16 - - √ Cleared to 0 TMC4 R/W 8 √ √ - ××000000 TM4 R 16 - - √ Cleared to 0 PMC8 R/W 8 √ √ - 00H √ √ - √ √ - √ √ - √ √ - 8 - √ - Undefined 8 - √ - Cleared to 0 √ √ - 00H - - √ Cleared to 0 - - √ 8 - √ - ××000000 8 - √ - 00H FF3CH Timer register 3 FF3DH Timer control register 4 FF3EH Timer register 4 FF48H Port 8 mode control register FF4DH Trigger source select register TRGS0 8 FF4EH Pull-up resistor option register L PUOL 8 FF4FH Pull-up resistor option register H PUOH 8 FF50H Input control register ICR 8 FF51H Up/down counter count register UDC FF52H Event divider counter EDV R CPTM R/W 8 TM5 R 16 16 10H FF53H Capture mode register FF54H Timer register 5 FF56H Timer 3 capture register 0 CPT30 FF58H Timer 0 output mode register TOM0 FF59H Timer 0 output control register TOC0 FF5AH Timer 1 output mode register TOM1Note 1 R/W 8 - √ - 80H FF5BH Timer 1 output control register TOC1 W 8 - √ - 00H R/W 16 - - √ Cleared to 0 16 - - √ W FF5CH Timer 3 compare register 0 CR30 FF5EH Timer 3 compare register 1 CR31 FF60H Port 8 buffer register L FF63H Up/down counter compare register UDCC W R/W P8L 8 √ √ - 000×0×0× 8 - √ - Undefined 00H FF65H Trigger source select register 1 TRGS1 8 √ √ - FF66H Port 6 mode control register PMC6 8 √ √ - FF68H A/D converter mode register ADM 16 - - √ ADMLNote 2 8 √ √ - 0000H FF6AH A/D conversion result register ADCR R 8 - √ - Undefined FF6CH Hardware watch counter 0 HW0 R/W 16 - - √ Not affected FF6EH Hardware watch counter 1 HW1 R 16 - - √ by reset FF6FH Watch mode register WM R/W 8 √ √ - 00××0×00 R/W FF70H PWM control register 0 PWMC0 8 √ √ - 05H FF71H PWM control register 1 PWMC1 8 √ √ - 15H FF72H PWM0 modulo register PWM0 16 - - √ 0000H FF73H PWM2 modulo register PWM2 8 - √ - 00H FF74H PWM1 modulo register PWM1 16 - - √ 0000H FF75H PWM3 modulo register PWM3 8 - √ - 00H Notes 1. When the timer 1 output mode register (TOM1) is read, the write sequence of the REC driver is read (bits 0 and 1). 2. ADML is the low-order 8 bits of the A/D converter mode register (ADM) and can be manipulated in 1or 8-bit units. Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the contents before initialization are undefined). 25 µPD784915B, 784916B Table 3-2. Special Function Registers (3/4) Bit Address Special Function Register (SFR) Name Symbol R/W Length R/W Bit Units for After Manipulation Releasing 1 bit 8 bits 16 bits Reset 16 - 8 - - √ 0000H √ - 00H FF76H PWM5 modulo register PWM5 FF77H PWM4 modulo register PWM4 FF78H Event divider control register EDVC W 8 - √ - 00H FF79H Clock output mode register CLOM R/W 8 √ √ - 00H FF7AH Timer 4 capture/compare register 0 CR40 16 - - √ Cleared to 0 FF7BH Clock control register CC 8 √ √ - 00H FF7CH Timer 4 capture register 1 CR41 R 16 - - √ Cleared to 0 FF7DH Capture/compare control register CRC W 8 - √ - 00H FF7EH Timer 5 compare register CR50 R/W 16 - - √ Cleared to 0 FF84H Serial mode register 1 CSIM1 8 √ √ - 00H FF85H Serial shift register 1 FF88H Serial mode register 2 FF89H Serial shift register 2 SIO1 8 - √ - Undefined CSIM2 8 √ √ - 00H SIO2 8 - √ - Undefined 00H FF8AH Serial control register 2 CSIC2 8 - √ - FF91H Head amplifier switch output control register HAPC 8 √ √ - FF94H Amplifier control register AMPC 8 √ √ - FF95H Amplifier mode register 0 AMPM0 8 √ √ - FF96H Amplifier mode register 1 AMPM1 8 √ √ - FF97H Gain control register CTLM 8 √ √ - FFA0H External interrupt mode register INTM0 8 √ √ - 000000×0 FFA1H External capture mode register 1 INTM1 8 √ √ - 00H FFA2H External capture mode register 2 INTM2 8 √ √ - FFA6H Key interrupt control register KEYC 8 √ √ - 70H FFA8H In-service priority register ISPR R 8 √ √ - 00H IMC R/W 8 √ √ - 80H √ FFH FFAAH Interrupt mode control register FFACH Interrupt mask flag register MK0L FFADH MK0H FFAEH MK1L FFAFH MK1H MK0 MK1 8 √ √ 8 √ √ 8 √ √ 8 √ √ √ FFB0H FRC capture register 0L CPT0L 16 - - √ FFB1H FRC capture register 0H CPT0H 8 - √ - R FFB2H FRC capture register 1L CPT1L 16 - - √ FFB3H FRC capture register 1H CPT1H 8 - √ - FFB4H FRC capture register 2L CPT2L 16 - - √ FFB5H FRC capture register 2H CPT2H 8 - √ - FFB6H FRC capture register 3L CPT3L 16 - - √ FFB7H FRC capture register 3H CPT3H 8 - √ - FFB8H FRC capture register 4L CPT4L 16 - - √ Cleared to 0 Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the contents before initialization are undefined). 26 µPD784915B, 784916B Table 3-2. Special Function Registers (4/4) Bit Address Special Function Register (SFR) Name Symbol R/W Length 1 bit FRC capture register 4H CPT4H FFBAH FRC capture register 5L FFB9H CPT5L FFBBH FRC capture register 5H CPT5H FFC0H Standby control register FFC4H Execution speed select register FFCEH CPU clock status register R Bit Units for After Manipulation Releasing 8 bits 16 bits Reset Cleared to 0 8 - √ - 16 - - √ 8 - √ - STBC R/W 8 - √ - 0000×000 MM W 8 - √ - 20H PCS R 8 √ √ - 00H FFCFH Oscillation stabilization time specification register OSTS W 8 - √ - FFE0H Interrupt control register (INTP0) PIC0 R/W 8 √ √ - FFE1H Interrupt control register (INTCPT3) CPTIC3 8 √ √ - FFE2H Interrupt control register (INTCPT2) CPTIC2 8 √ √ - FFE3H Interrupt control register (INTCR12) CRIC12 8 √ √ - FFE4H Interrupt control register (INTCR00) CRIC00 8 √ √ - FFE5H Interrupt control register (INTCLR1) CLRIC1 8 √ √ - FFE6H Interrupt control register (INTCR10) CRIC10 8 √ √ - FFE7H Interrupt control register (INTCR01) CRIC01 8 √ √ - FFE8H Interrupt control register (INTCR02) CRIC02 8 √ √ - FFE9H Interrupt control register (INTCR11) CRIC11 8 √ √ - FFEAH Interrupt control register (INTCPT1) CPTIC1 8 √ √ - FFEBH Interrupt control register (INTCR20) CRIC20 8 √ √ - FFEDH Interrupt control register (INTTB) TBIC 8 √ √ - FFEEH Interrupt control register (INTAD) ADIC 8 √ √ - PIC2 8 √ √ - FFEFH Interrupt control register (INTP2)Note Interrupt control register (INTCR40)Note CRIC40 FFF0H Interrupt control register (INTUDC) UDCIC 8 √ √ - FFF1H Interrupt control register (INTCR30) CRIC30 8 √ √ - FFF2H Interrupt control register (INTCR50) CRIC50 8 √ √ - FFF3H Interrupt control register (INTCR13) CRIC13 8 √ √ - FFF4H Interrupt control register (INTCSI1) CSIIC1 8 √ √ - FFF5H Interrupt control register (INTW) WIC 8 √ √ - FFF7H Interrupt control register (INTP1) PIC1 8 √ √ - FFF8H Interrupt control register (INTP3) PIC3 8 √ √ - FFFAH Interrupt control register (INTCSI2) CSIIC2 8 √ √ - Note 43H PIC2 and CRIC40 are at the same address (register). Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the contents before initialization are undefined). 27 µPD784915B, 784916B 3.4 PORTS The µPD784916B is provided with the ports shown in Figure 3-4. Table 3-3 shows the function of each port. Figure 3-4. Port Configuration P00 P60 Port 0 Port 6 P07 P67 P40 P70-P77 Port 4 8 Port 7 P80 P82 P47 Port 8 P50 P87 Port 5 P90 P57 Port 9 P96 Table 3-3. Port Function Name 28 Pin Name Port 0 P00 to P07 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P60 to P67 Port 7 Function Specification of Pull-up Resistor Can be set in input or output mode in 1bit units. Pull-up resistors are connected to all pins in input mode. P70 to P77 Input port Pull-up resistor is not provided. Port 8 P80, P82 to P87 Port 9 P90 to P96 Can be set in input or output mode in 1bit units. Pull-up resistors are connected to all pins in input mode. µPD784915B, 784916B 3.5 Real-time Output Port A real-time output port consists of a port output latch and a buffer register (refer to Figure 3-5). The function to transfer the data prepared in advance in the buffer register to the output latch when a trigger such as a timer interrupt occurs, and output the data to an external device is called a real-time output function. A port used in this way is called a real-time output port (RTP). Table 3-4 shows the real-time output ports of the µPD784916B. Table 3-5 shows the trigger sources of RTPs. Figure 3-5. Configuration of RTP Buffer register Output trigger Port output latch Port Table 3-4. Bit Configuration of RTP Number of Bits of Real-Time Output Data Number of Bits That Can Be Specified as RTP RTP Alternate Function RTP0 Port 0 4 bits × 2 channels or 8 bits × 1 channel 4-bit units — RTP8 Port 8 1 bit × 1 channel and 2 bits × 1 channel 1-bit units Pseudo VSYNC output : 1 channel (RTP80) Head amplifier switch : 1 channel (RTP82) Chrominance rotation signal output: 1 channel (RTP83) Remark Table 3-5. Trigger Sources of RTP Trigger Source INTCR00 INTCR01 INTCR02 INTCR13 INTCR50 INTP0 Remark RTP RTP0 RTP8 √ High-order 4 bits Low-order 4 bits √ √ All 8 bits √ √ √ Bit 0 Bits 2 and 3 √ √ √ √ Note 1 Note 2 Notes 1. Select one of the four trigger sources. 2. When the real-time output port mode is set by the port mode control register 8 (PMC8), the HASW and ROT-C signals that are set by the head amplifier switch output control register (HAPC) are directly output. The HASW and ROT-C signals are synchronized with HSW output (TM0-CR00 coincidence signal). However, the set signal is output immediately when the HAPC register is rewritten. 29 µPD784915B, 784916B Figures 3-6 and 3-7 show the block diagrams of RTP0 and RTP8. Figure 3-8 shows the types of RTP output trigger sources. Figure 3-6. Block Diagram of RTP0 Internal bus 8 4 Buffer register P0H P0L Real-time output port 0 control register INTP0 INTCR01 INTCR02 4 4 Output trigger 8 4 Control circuit Output latch (P0) P07 P00 Remark INTCR01: TM0-CR01 coincidence signal INTCR02: TM0-CR02 coincidence signal Figure 3-7. Block Diagram of RPT8 Internal bus 8 8 Head amplifier output control register (HAPC) SEL SEL SEL PB PB PB 0 0 ROTC HASW ENV MOD2 MOD1 MOD0 Port 8 buffer register L (P8L) SEL 0 0 0 P8L4 P8L2 0 P8L0 MD80 TRGP80 HASW, ROT-C TM0-CR00 control circuit coincidence signal Pseudo VSYNC output control circuit PMC80 0 PMC82 PMC83 PMC8 Output latch (P8) HSYNC superimposition circuit P83 P82 30 P80 8 µPD784915B, 784916B Figure 3-8. Types of RTP Output Trigger Sources Real-time output port 0 control register (RTPC) INTP0 TM0 Selector Trigger of P0H Trigger of P0L CR00 CR01 Interrupt and timer output Trigger of P82 and P83 CR02 Selector Trigger of P80 TM1 CR10 Interrupt and timer output Trigger source select register 0 (TRGS0) CR11 Capture CR12 Interrupt CR13 TM5 CR50 Interrupt 31 µPD784915B, 784916B RTP80 can output low-level, high-level, and high-impedance values real-time. Because RTP80 can superimpose a horizontal sync signal, it can be used to create a pseudo vertical sync signal. When RTP80 is set in the pseudo VSYNC output mode, it repeatedly outputs a specific pattern when an output trigger occurs. Figure 3-9 shows the operation timing of RTP80. Figure 3-9. Example of Operation Timing of RTP80 (a) When HSYNC signal is superimposed High level P80 High impedance Low level Trigger signal (b) Pseudo VSYNC output mode High level P80 High impedance Low level Trigger signal 32 µPD784915B, 784916B 3.6 Super Timer Unit The µPD784916B is provided with a super timer unit that consists of the timers shown in Table 3-6. Table 3-6. Configuration of Super Timer Unit Unit Name Timer 0 Timer/Counter Resolution 1 µs TM0 Maximum Count Time 65.5 ms (16-bit timer) EC - - (8-bit counter) Free running FRC counter Remark Register CR00 Controls delay of video head switching signal CR01 Controls delay of audio head switching signal CR02 Controls pseudo VSYNC output timing ECC0, ECC1, Creates internal head switching signal ECC2, ECC3 125 ns 524 ms (22-bit counter) CPT0 Detects reference phase (to control drum phase) CPT1 Detects phase of drum motor (to control drum phase) CPT2 Detects speed of drum motor (to control drum speed) CPT3 Detects speed of capstan motor (to control speed of capstan motor) Timer 1 1 µs TM1 65.5 ms CPT4, CPT5 Detects remaining tape for reel FG CR10 Playback: Creates internal reference signal Recording: Buffer oscillator in case VSYNC is (16-bit timer) missing CR11 Controls RECCTL output timing CR12 Detects phase of capstan motor (to control capstan phase) CR13 Controls VSYNC mask as noise prevention measures 1 µs or 1.1 µs 65.5 ms or TM3 Controls duty detection timing of PBCTL signal 71.5 ms (16-bit timer) EDV CR30, CR31 CPT30 Measures cycle of PBCTL signal - - EDVC Divides CFG signal frequency 1 µs 65.5 ms CR20 Can be used as interval timer (to control sys- (8-bit counter) Timer 2 TM2 tem) (16-bit timer) Timer 4 2 µs TM4 131 ms CR40 Detects duty of remote controller signal (to decode remote controller signal) (16-bit timer) CR41 Measures cycle of remote controller signal (to decode remote controller signal) Timer 5 2 µs TM5 131 ms CR50 tem) (16-bit timer) Up/down UDC counter (5-bit counter) PWM output unit - Can be used as interval timer (to control sys- Creates linear tape counter - - UDCC - - PWM0, PWM1, 16-bit resolution (carrier frequency: 62.5 kHz) PWM5 PWM2, PWM3, 8-bit resolution (carrier frequency: 62.5 kHz) PWM4 33 µPD784915B, 784916B (1) Timer 0 unit Timer 0 unit creates head switching signal and pseudo VSYNC output timing from the PG and FG signals of the drum motor. This unit consists of an event counter (EC: 8 bits), four compare registers (ECC0 to ECC3), a timer (TM0: 16 bits), and three compare registers (CR00 to CR02). A signal indicating coincidence between the value of timer 0 and the value of a compare register can be used as the output trigger of the real-time output port. (2) Free running counter unit The free running counter unit detects the speed and phase of the drum motor, and the speed and reel speed of the capstan motor. This unit consists of a free running counter (FRC), six capture registers (CPT0 to CPT5), a VSYNC separation circuit, and a HSYNC separation circuit. (3) Timer 1 unit Timer 1 unit is a reference timer unit synchronized with the frame cycle and creates the RECCTL signal, detects the phase of the capstan motor, and detects the duty factor of the PBCTL signal. This unit consists of the following three groups. • Timer 1 (TM1), compare registers (CR10, CR11, and CR13), and capture register (CR12) • Timer 3 (TM3), compare registers (CR30 and CR31), and capture register (CPT30) • Event divider counter (EDV) and compare register (EDVC) The TM1-CR13 coincidence signal can be used for automatic unmasking of VSYNC or as the output trigger of the real-time output port. 34 PBCTL PTO10 PTO11 CFGIN REEL1IN REEL0IN CSYNCIN Selector Selector F/F F/F CTL F/F Mask Selector Clear TM3 EDVC Clear EDV Mask Selector CR30 CR31 Capture CPT30 VSYNC separation circuit ECC3 ECC2 ECC1 ECC0 Clear EC Selector Selector Selector Selector DFGIN Writes 00H to EC Capture Capture Capture Capture Capture Capture FFLVL Capture Selector Divider CR10 CR11 CR12 CR13 Clear TM1 CPT0 CPT1 CPT2 CPT3 CPT4 CPT5 FRC HSYNC separation circuit CR00 CR01 CR02 Clear TM0 RTP, A/D RTP INTCR02 INTCR01 INTCR00 Output control circuit Output control circuit PTO11 PTO10 PTO02 PTO01 PTO00 INTCR30 To PBCTL signal input block INTCR11 INTCR12 INTCR13 INTCR10 INTP3 INTCPT1 INTCPT2 INTCPT3 INTCLR1 To P80 RTP, A/D (Superimposition) Output control circuit Output control circuit Output control circuit (Superimposition) Selector DPGIN Selector Selector Selector Selector Selector Selector Analog circuit Figure 3-10. Block Diagram of Super Timer Unit (TM0, FRC, TM1) µPD784915B, 784916B 35 µPD784915B, 784916B (4) Timer 2 unit Timer 2 unit is a general-purpose 16-bit timer unit. This unit consists of a timer 2 (TM2) and a compare register (CR20). The timer is cleared when the TM2-CR20 coincidence signal occurs, and at the same time, an interrupt request is generated. Figure 3-11. Block Diagram of Timer 2 Unit Clear TM2 INTCR20 CR20 (5) Timer 4 unit Timer 4 unit is a general-purpose 16-bit timer unit. This unit consists of a timer 4 (TM4), a capture/compare register (CR40), and a capture register (CR41). The value of the timer is captured to CR40/CR41 when the INTP2 signal is input. This timer can be used to decode a remote controller signal. Figure 3-12. Block Diagram of Timer 4 Unit Mask Clear INTP2 Selector TM4 INTCR40 CR40 CR41 (6) Timer 5 unit Timer 5 unit is a general-purpose 16-bit timer unit. This unit consists of a timer 5 (TM5) and a compare register (CR50). The timer is cleared by the TM5-CR50 coincidence signal, and at the same time, an interrupt request is generated. Figure 3-13. Block Diagram of Timer 5 Unit Clear TM5 CR50 INTCR50 RTP, A/D 36 µPD784915B, 784916B (7) Up/down counter unit The up/down counter unit is a counter that realizes a linear time counter. This unit consists of an up/down counter (UDC) and a compare register (UDCC). The up/down counter counts up the rising edges of PBCTL and counts down the falling edges of PBCTL. When the value of the up/down counter coincides with the value of the compare register, or when the counter underflows, an interrupt request is generated. Figure 3-14. Block Diagram of Up/Down Counter Unit Selector EDVC output Selector PBCTL P77 UP/DOWN Selector PTO10 PTO11 Selector SELUD UDC UDCC INTUDC (8) PWM output unit The PWM output unit has three 16-bit accuracy output lines (PWM0, PWM1, and PWM5) and 8-bit accuracy output lines (PWM2 to PWM4). The carrier frequency of all the output lines is 62.5 kHz (fCLK = 8 MHz). PWM0 and PWM1 can be used to control the drum motor and capstan motor. Figure 3-15. Block Diagram of 16-Bit PWM Output Unit (n = 0, 1, 5) Internal bus 16 PWMn 15 8 7 8 0 PWMC0 8 Reload 16 MHz 8 8-bit down counter 1/256 To selector Reload PWM pulse generation circuit Reload control PWMn Output control circuit 8-bit counter RESET 37 µPD784915B, 784916B Figure 3-16. Block Diagram of 8-Bit PWM Output Unit Internal bus PWM2 PWM3 PWM4 8-bit comparator 8-bit comparator 8-bit comparator 16 MHz PWM counter PWMC1 Output control circuit PWM4 Output control circuit PWM3 Output control circuit PWM2 3.7 Serial Interface The µPD784916B is provided with the serial interfaces shown in Table 3-7. Data can be automatically transmitted or received through these serial interfaces, when the macro service is used. Table 3-7. Types of Serial Interfaces Name Function Serial interface channel 1 • Clocked serial interface (3-wire) • Bit length: 8 bits • Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) • MSB first/LSB first selectable Serial interface channel 2 • Clocked serial interface (3-wire) • Bit length: 8 bits • Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) • MSB first/LSB first selectable • BUSY/STRB control function 38 µPD784915B, 784916B Figure 3-17. Block Diagram of Serial Interface Channel n (n = 1 or 2) SIn /BUSY Selector Internal bus SIOn register CSIMn register SOn Serial clock counter INTCSIn Busy detection circuit STRB Selector SCKn fCLK/8 fCLK/16 fCLK/32 fCLK/64 fCLK/128 fCLK/256 Strobe generation circuit CSIC2 register Internal bus Remark The circuits enclosed in the broken line are provided for serial interface channel 2 only. 39 µPD784915B, 784916B 3.8 A/D Converter The µPD784916B has an analog-to-digital (A/D) converter with 12 multiplexed analog inputs (ANI0 to ANI11). This A/D converter is of successive approximation type, and the conversion result is held by an 8-bit A/D conversion result register (ADCR) (conversion time: 10 µs at fCLK = 8 MHz). A/D conversion can be started in the following two modes: • Hardware start : Conversion is started by a hardware triggerNote. • Software start : Conversion is started by setting the A/D conversion mode register (ADM). After conversion has been started, the A/D converter operates in the following modes: • Scan mode : Sequentially selects more than one analog input to obtain data to be converted from all the pins. • Select mode: Use only one pin for analog input to obtain successive data. When the conversion result is transferred to ADCR, interrupt request INTAD is generated. By processing this interrupt with the macro service, the conversion result can be successively transferred to memory. A mode in which starting A/D conversion of the next pin is kept pending until the value of ADCR is read is also available. When this mode is used, reading the conversion result by mistake when timing is shifted because an interrupt is disabled can be prevented. Note A hardware trigger can be one of the following coincidence signals, one of which is selected by the trigger source select register 1 (TRGS1): • TM0-CR01 coincidence signal • TM0-CR02 coincidence signal • TM1-CR13 coincidence signal • TM5-CR50 coincidence signal 40 µPD784915B, 784916B Figure 3-18. Block Diagram of A/D Converter ANI0 ANI3 . . . . . . AVREF Voltage comparator ANI11 Successive approximation register (SAR) TM0-CR02 coincidence TM1-CR13 coincidence AVSS2 Control circuit TM5-CR50 coincidence Trigger enable Trigger source select register 1 (TRGS1) A/D converter mode register (ADM) R R/2 Conversion trigger Selector TM0-CR01 coincidence R/2 Tap selector ANI2 Series resistor string Sample & hold circuit Input selector ANI1 8 Delay detection circuit INTAD A/D conversion end interrupt A/D conversion result register (ADCR) 8 16 Internal bus 3.9 VCR Analog Circuits The µPD784916B is provided with the following VCR analog circuits: • CTL amplifier • RECCTL driver (rewritable) • DPG comparator • DFG amplifier • DPFG separation circuit (ternary separation circuit) • CFG amplifier • Reel FG comparator (2 channels) • CSYNC comparator 41 µPD784915B, 784916B (1) CTL amplifier/RECCTL driver The CTL amplifier is used to amplify the playback control (PBCTL) signal that is reproduced from the CTL signal recorded on a VCR tape. The gain of the CTL amplifier is set by the gain control register (CTLM). Thirty-two types of gains can be set in increments of about 1.78 dB. The µPD784195 is also provided with a gain control signal generation circuit that monitors the status of the amplifier output to perform optimum gain control by program. The gain control signal generation circuit generates a CTL detection flag that identifies the amplitude status of the CTL amplifier output. By using this CTL detection flag, the gain of the CTL amplifier can be optimized. The RECCTL driver writes a control signal onto a VCR tape. This driver operates in two modes: REC mode that is used for recording, and rewrite mode used to rewrite the VISS signal. The output status of the RECCTL± pin is changed by hardware, by using the timer output from the super timer unit as a trigger. Figure 3-19. Block Diagram of CTL Amplifier and RECCTL Driver ANI11 CTLDLY RECCTL+ RECCTL driver RECCTL- CTL head Selector TOM1.4-TOM1.6 TM1-CR11 coincidence signal TM1-CR13 coincidence signal TM3-CR30 coincidence signal VREF AMPC. 1 + - AMPC. 1 CTLIN + - Gain control signal generation circuit CTL detection flag L (AMPM0. 1) CTL detection flag S (AMPM0. 3) CTL detection flag clear (1 write to AMPM0. 6) CTLOUT1 CTLM. 0-CTLM. 4 CTLOUT2 42 Waveform shaping circuit PBCTL signal (to timer unit) µPD784915B, 784916B (2) DPG comparator, DFG amplifier, and DPFG separation circuit The DPG comparator converts the drum PG (DPG) signal that indicates the phase information of the drum motor into a logic signal. The DFG amplifier amplifies the drum FG (DFG) signal that indicates the speed information of the drum motor. The DPFG separation circuit (ternary separation circuit) separates a drum PFG (DPFG) signal having speed and phase information into a DFG and DPG signals. Figure 3-20. Block Diagram of DPG Comparator, DFG Amplifier, and DPFG Separation Circuit VREF AMPC.2 AMPM0.2 AMPC.2 Drum PG signal DPGIN DPG comparator 0 1 0 Selector 1 Selector AMPM0.0 DPG signal (to timer unit) VREF AMPC.2 AMPM0.0 + DFG amplifier DFGIN AMPM0.2 AMPM0.2 1 AMPC.2 AMPC.2 DPFG separation circuit (ternary separation circuit) 1 0 AMPM0.2 1 Selector 0 Selector Drum FG signal or drum PFG signal DFG signal (to timer unit) 0 43 µPD784915B, 784916B (3) CFG amplifier The CFG amplifier amplifies the capstan FG (CFG) signal that indicates the speed information of the capstan motor. This amplifier consists of an operational amplifier and a comparator. The gain of the operational amplifier is set by using an external resistor. When the gain of the operational amplifier is set to 50 dB, the output duty accuracy of the CFG signal can be improved to 50.0 ± 0.3%. Figure 3-21. Block Diagram of CFG Amplifier VREF AMPC.3 + CFG amplifier - Capstan FG signal CFGIN AMPM0.0 VREF AMPC.3 - CFGCPIN CFG comparator AMPC.3 1 + 0 44 Selector CFGAMPO CFG signal (to timer unit) µPD784915B, 784916B (4) Reel FG comparators The reel FG comparator converts a reel FG signal that indicates the speed information of the reel motor into a logic signal. Two comparators, one for take-up and the other for supply, are provided. Figure 3-22. Block Diagram of Reel FG Comparators VREF AMPC.6 AMPM0.0 Selector 1 Supply reel signal REEL0IN Reel FG comparator 0 Reel FG0 signal (to timer unit) VREF AMPC.6 AMPC.6 AMPM0.0 Selector 1 Take-up reel signal REEL1IN Reel FG comparator 0 Reel FG1 signal (to timer unit) (5) CSYNC comparator The CSYNC comparator converts the COMPSYNC signal into a logic signal. Figure 3-23. Block Diagram of COMPSYNC Comparator VREF AMPM1.7 AMPC.5 AMPC.5 AMPM0.0 CSYNCIN CSYNC comparator 0 Selector 1 COMPSYNC signal CSYNC signal (to timer unit) 45 µPD784915B, 784916B (6) Reference amplifier The reference amplifier generates a reference voltage (VREF) to be supplied to the internal amplifiers and comparators of the µPD784916B. Figure 3-24. Block Diagram of Reference Amplifier ENCAP (AMPC.3) AVDD1 VREFC + AVSS1 VREF (CFG amplifier) + VREF (CFG amplifier) ENCTL (AMPC.1) + VREF (CTL amplifier) ENDRUM (AMPC.2) ENREEL (AMPC.6) ENCSYN (AMPC.5) + VREF DFG amplifier, DPG comparator, reel FG comparator, and CSYNC comparator) Remark Multiple reference amplifiers are provided to assure the accuracy of the amplifiers and comparators. 46 µPD784915B, 784916B 3.10 Watch Function The µPD784916B has a watch function that counts the overflow signals of the watch timer by hardware. As the clock, the subsystem clock (32.768 kHz) is used. Because this watch function is independent from the CPU, it can be used even while the CPU is in the standby mode (STOP mode) or is reset. In addition, this function can be used at a low voltage of VDD = 2.7 V (MIN.). Therefore, by using only the watch function with the CPU set in the standby mode or reset, a watch operation can be performed at a low voltage and low current dissipation. In addition, the watch function can also be used while the CPU is in the normal operation mode, because a dedicated counter is provided. The watch function can be used to count up to about 17 years of data. The hardware watch counters (HW0 and HW1) are shared with external input counters. These counters execute counting at the falling edge of input to the P65 pin, and can be used to count the HSYNC signals. Figure 3-25. Block Diagram of Watch Counter PM65 PMC65 P65 Edge detection P65 Pin level read 0 Watch timer Normal 1 Fast forward 1 0 0 15 HW0 0 13 HW1 WM.2 Selector 13 Selector 0 WM.1 Selector fXT (32.768 kHz) WM.2 (enables/disables operation) Selector WM.2 (enables/disables operation) BUZ signal To NMI generation block WM.6 INTW WM.7 WM.5 WM.4 47 µPD784915B, 784916B 3.11 Clock Output Function The µPD784916A can output a square wave (with a duty factor of 50%) to the P60/CLO pin as the operating clock for the peripheral devices or other microccontrollers. To enable or disable the clock output, and to set the frequency of the clock, the clock output mode register (CLOM) is used. When setting the frequency, the division ratio can be set to fCLK/n (where n = 2, 4, 8, or 16) (fCLK = fOSC/2: fOSC is the oscillation frequency of the oscillator). Figure 3-26 shows the configuration of the clock output circuit. The clock output (CLO) pin is shared with P60. Figure 3-26. Block Diagram of Clock Output Circuit Selector fCLK fCLK/2 fCLK/4 fCLK/8 0 0 Output control circuit CLOM 0 ENCLO 0 0 SELFRQ1 SELFRQ0 1/2 P60/CLO P60 RESET Remark fCLK: internal system clock Caution Do not use the clock output function in the STOP mode. Clear ENCLO (CLOM.4) to 0 in the STOP mode. Figure 3-27 Application Example of Clock Output Function µ PD784916B µ PD75356 LCD 24 CLO SCK1 SI1 SO1 48 System clock CL1 SCK SO SI µPD784915B, 784916B 4. INTERNAL/EXTERNAL CONTROL FUNCTION 4.1 Interrupt Function The µPD784916B has as many as 30 interrupt sources, including internal and external sources. For 26 sources, a high-speed interrupt processing mode such as context switching or macro service can be specified by software. Table 4-1 lists the interrupt sources. Table 4-1. Interrupt Sources Interrupt Request Interrupt Request Source Priority Name Trigger Macro Service Vector Macro Context Control Word Table Control RegService Switching Address Address ister Name 0000H No No 0002H Interrupt Type Reset - Non- - RESET RESET pin input NMI NMI pin input edge 0 1 INTCPT3 EDVC output signal (CPT3 capture) CPTIC3 2 INTCPT2 DFGIN pin input edge (CPT2 capture) CPTIC2 FE0AH 000AH 3 CRIC12 FE0CH 000CH 4 INTCR12 PBCTL signal input edge/EDVC output signal (CR12 capture) INTCR00 TM0-CR00 coincidence signal INTCLR1 CSYNCIN pin input edge INTCR10 TM1-CR10 coincidence signal CRIC00 CLRIC1 FE0EH FE10H 000EH 5 6 CRIC10 FE12H 0010H 0012H 7 INTCR01 TM0-CR01 coincidence signal INTCR02 TM0-CR02 coincidence signal CRIC01 FE14H 0014H CRIC02 FE16H 0016H INTCR11 TM1-CR11 coincidence signal INTCPT1 Pin input edge/EC output signal (CPT1 capture) CRIC11 CPTIC1 FE18H FE1AH 001AH INTCR20 TM2-CR20 coincidence signal INTTB Time base from FRC CRIC20 FE1CH 001CH TBIC FE20H 0020H ADIC FE22H 0022H INTP2 pin input edge INTCR40 TM4-CR40 coincidence signal INTUDC UDC-UDCC coincidence/UDC underflow PIC2 CRIC40 FE24H 0024H UDCIC FE26H 0026H INTCR30 TM3-CR30 coincidence signal INTCR50 TM5-CR50 coincidence signal CRIC30 FE28H 0028H CRIC50 FE2AH 002AH INTCR13 TM1-CR13 coincidence signal INTCSI1 End of serial transfer (channel 1) INTW Overflow of watch timer CRIC13 FE2CH 002CH CSIIC1 WIC FE2EH FE30H 002EH PIC1 FE34H maskable Maskable 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Operand - error Software - INTP0 INTAD INTP0 pin input edge A/D converter conversion end INTP2 INTP1 INTP1 pin input edge INTP3 INTP3 pin input edge INTCSI2 End of serial transfer (channel 2) Illegal operand of MOV STBC, #byte or LOCATION instruction - Execution of BRK instruction Execution of BRKCS instruction PIC0 Yes Yes FE06H FE08H 0006H 0008H 0018H 0030H 0034H PIC3 FE36H 0036H CSIIC2 FE3AH 003AH - 003CH - 003EH - - No No - Yes - 49 µPD784915B, 784916B Figure 4-1. Differences in Operation Depending on Interrupt Processing Mode Macro service Main routine Macro service processing Main routine Interrupt processing Context Note 1 switching Main routine Note 2 Vector Note 2 interrupt Main routine Note 4 SEL RBn Vector interrupt Main routine Note 4 Saving general register Note 3 Main routine Interrupt processing Restoring PC and PSW Initializing general register Interrupt processing Main routine Restoring general register Restoring PC and PSW Main routine Interrupt request generated Notes 1. When the register bank switching function is used and when initial values are set in advance to the registers 2. Selecting a register bank and saving PC and PSW by context switching 3. Restoring register bank, PC, and PSW by context switching 4. Saves PC and PSW to stack and loads vector address to PC 50 µPD784915B, 784916B 4.1.1 Vector interrupt When an interrupt request is acknowledged, an interrupt processing program is executed according to the data stored in the vector table area (the first address of the interrupt processing program created by the user). Four levels of priorities can be specified by software for the vector interrupts of the µPD784916B. 4.1.2 Context switching When an interrupt request is generated or when the BRKCS instruction is executed, a specific register bank is selected by hardware, and execution branches to a vector address set in advance in the register bank. At the same time, the current contents of the program counter (PC) and program status word (PSW) are saved to the registers in the register bank. Because the contents of PC and PSW are not saved to the stack area, execution can be branched to an interrupt processing routine more quickly than the vector interrupt. Figure 4-2. Context Switching Operation When Interrupt Request Is Generated Register bank (0-7) <7> 0H Register bank n (n = 0-7) PC19-16 PC15-0 A <6> Exchange <2> Save Bits 8-11 of temporary register B C R5 R4 R7 <5> Save Temporary register <1> Save X V R6 VP U UP T D E W H L <3> Switching register bank (RBS0 – RBS2 ← n) <4> RSS ← 0 IE ← 0 PSW 51 µPD784915B, 784916B 4.1.3 Macro service The macro service is a function to transfer data between the memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR and directly transfers the data. Because the status of the CPU is not saved or restored, data can be transferred more quickly than context switching. The processing that can be executed with the macro service is described below. Figure 4-3. Macro Service CPU Read Write Memory Macro service controller Write Read SFR Internal bus (1) Counter mode In this mode, the value of the macro service counter (MSC) is decremented when an interrupt request occurs. This mode can be used to execute the division operation of an interrupt or count the number of times an interrupt has occurred. When the value of the macro service counter has been decremented to 0, a vector interrupt occurs. MSC -1 (2) Compound data transfer mode When an interrupt request occurs, data are simultaneously transferred from an 8-bit SFR to memory, a 16-bit SFR to memory (word), memory (byte) to an 8-bit SFR, and memory (word) to a 16-bit SFR (3 points MAX. for each transfer). This mode can also be used to exchange data, instead of transferring data. This mode can be used for automatic transfer/reception by the serial interface or automatic updating of data/timing by the serial output port. When the value of the macro service counter reaches to 0, a vector interrupt request occurs. Memory SFR<4>-1 SFR<4>-2 SFR<4>-3 SFR<3>-1 SFR<3>-2 SFR<3>-3 SFR<1>-2 SFR<1>-3 Internal bus SFR<2>-1 SFR<2>-2 SFR<2>-3 SFR<1>-1 Internal bus 52 .. . µPD784915B, 784916B (3) Macro service type A When an interrupt request occurs, data is transferred from an 8-/16-bit SFR to memory (byte/word) or from memory (byte/word) to an 8-/16-bit SFR. Data is transferred the number of times set in advance by the macro service counter. This mode can be used to store the result of A/D conversion or for automatic transfer (or reception) by the serial interface. Because transfer data is stored at an address FE00H to FEFFH, if only a small quantity of data is to be transferred, the data can be transferred at high speeds. When the value of the macro service counter is decremented to 0, a vector interrupt request occurs. Data storage buffer (memory) Data storage buffer (memory) Data n Data n Data n - 1 Data n - 1 Data 2 Data 2 Data 1 Data 1 Internal bus Internal bus SFR SFR (4) Data pattern identification mode (VISS detection mode) This mode of macro service is for detection of the VISS signal and is used in combination with a pulse width detection circuit. When an interrupt request occurs, the content of bit 7 of an SFR (usually, TMC3) specified by SFR pointer 1 is shifted into the buffer area. At the same time, the data in the buffer area is compared with the data in the compare area. If the two data coincide, an interrupt request is generated. When the value of the macro service counter is decremented to 0, a vector interrupt request occurs. It can be specified by option that the value of an SFR (usually, CPT30) specified by SFR pointer 2 be multiplied by a coefficient and the result of this multiplication be stored to an SFR (usually, CR30) specified by SFR pointer 3 (this operation is to automatically update an identification threshold value when the tape speed fluctuates). Buffer area (memory) Coefficient (memory) Compare area (memory) CPT30 Multiplier TM3 Coincidence CR30 CTL F/F (bit 7 of TMC3) Vector interrupt 53 µPD784915B, 784916B 4.1.4 Application example of macro service (1) Automatic transfer/reception of serial interface Automatic transfer/reception of 3-byte data by serial interface channel 1 Setting of macro service register: compound data transfer mode (exchange mode) 7 0 FE50H Higher address Mode register (= 10110011B) FE2EH Lower address Macro service counter (MSC = 2) Memory pointer H (= FD) Macro service channel Memory pointer L (= 50) ddccbbaa (= 01000100B) SFR pointer <2> (SFRP2 = 85H) SFR pointer <4> (SFRP4 = 85H) Channel pointer (= 50H) Macro service control word (Before transfer) (Exchange 2) Transmit data 3 FD52H SI1 SIO1 (FF85H) <3> SO1 Transmit data 2 FD51H <2> (Exchange 1) (Transmit data 1) FD50H <1> Transfer is started by writing transmit data 1 to SIO1 by software. (After transfer) Receive data 2 FD51H Receive data 1 FD50H (Receive data 3 is the data of SIO1.) 54 µPD784915B, 784916B (2) Reception operation of serial interface Transfer of receive data by serial interface channel 1 (16 bytes) Setting of macro service mode register: macro service type A (1-byte transfer from SFR to memory) Internal RAM FE7FH MSC 0FH SFR pointer 85H Setting of number of transfers Low-order 8 bits of address of SIO1 register Channel pointer (= 7FH) FE2EH Mode register (= 00010001B) Starts macro service when INTCSI1 occurs SI1 SIO1 (FF85H) 55 µPD784915B, 784916B (3) VISS detection operation Setting of macro service mode register: data pattern identification mode (with multiplication, 8-byte comparison) CPT30 Higher address TM3 FE50H Macro service counter (MSC = FFH) SFR pointer 2 (SFRP2 = 56H) Multiplier Coefficient (6EH: 43%) CR30 SFR pointer 3 (SFRP3 = 5CH) Bit 7 SFR pointer 1 (SFRP1 = 3BH) Buffer size specification register (64 bits: 8H) 0 TMC3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 8 bytes Compare area pointer (high): 10H Compare area pointer (low): 50H Coincidence (vector interrupt) Channel pointer (= 50H) FE0CH Mode register (= 00010100B) (CTL signal input edge detection interrupt) Lower address 56 1050H 8 bytes µPD784915B, 784916B 4.2 Standby Function The standby function serves to reduce the power dissipation of the chip and is used in the following modes: Mode Function HALT mode Stops operating clock of CPU. Reduces average power dissipation when used in combination with normal mode for intermittent operation STOP mode Stops oscillator. Stops all internal operations of chip to minimize current dissipation to leakage current only Low power dissipation mode Stops main system clock with subsystem clock used as system clock. CPU can operate with subsystem clock to reduce power dissipation Low power dissipation HALT mode Standby function in low power dissipation mode. Stops operating clock of CPU. Reduces power dissipation of overall system These modes are programmable. The macro service can be started in the HALT mode. Figure 4-4. Status Transition of Standby Mode ce Macro service st ue ss ing req ce ce rvi pro ne se cro Ma fo TO P T in SE RE sS ode Tm wp s lo En Set st ng rvi 2 owe r dis sipa tion HAL pt rru inte put st ue req 1 t Note pu se Note P2 ue ssi est I in req ce T 1 t Low power dissipation HALT mode (standby) ro ce pro HAL INT Sets put requ te pu No I in W, ac rupt Waits for stabilization of oscillation rvi ne fm ET in NM d perio se fo do Inter End iliz stab En RES tion ci la of os ation do do Restores normal operation cro En Normal operation NM INT Ma Sets low power dissipation mode Set Low power dissipation mode (subsystem clock operation) STOP mode (standby) HALT mode (standby) Unmasked interrupt request Notes 1. NMI input means starting NMI by NMI pin input, watch interrupt, or key interrupt input. 2. Unmasked interrupt request 57 µPD784915B, 784916B Figure 4-5. Relations among NMI, Watch Interrupt, and Key Interrupt When STOP Mode Is Released INTM0.0 NMI Selector Standby control block Latch Interrupt control block Clear INTP1 INTP2 KEY0 KEY1 KEY2 S Q KEY3 KEYC.7 R KEY4 Cleared when "0" is written to KEYC.7 Mask KEYC.6 Mask KEYC.5 Mask KEYC.4 S Q KEYC.0 R Selector WM.6 Cleared when "0" is written to KEYC.0 Mask WM.3 58 Watch timer INTW (OVF) Divides INTW by 128 (HW0L.7) 1/2 1/2 fXX/8 (fXX/4)Note 1 fXX/4 (fXX/2)Note 1 Oscillation stop From standby control block XT1 XT2 32.768 kHz Subsystem clock oscillator circuit fXT Watch timer STBC.6 fXX/16 (fXX/8)Note 1 fXX/2 (fXX)Note 1 Selector 1/2 1/2 STBC.4, 5 Selector Normal mode Selector X2 16 MHz or 8 MHz Main system fXX clock oscillation circuit Oscillation Stabilization Timer fCLK CPU Peripheral hardware operation clockNote 2 Hardware watch function Watch interrupt Oscillation stop STBC.7 Notes 1. Oscillation frequency, values in parentheses indicate the low frequency oscillation mode. 2. The peripheral hardware units that can operate with the subsystem clock have some restrictions. For details, refer to 14.6 Low Power Dissipation Mode in µPD784915 Subseries User’s Manual. 4.3 Clock Generator Circuit X1 Low-frequency oscillation mode µPD784915B, 784916B 59 The clock generator circuit generates and controls the internal system clock (CLK) to be supplied to the CPU and CC.7 µ PD784916B peripheral circuits. Figure 4-6 shows the configuration of this circuit. Figure 4-6. Block Diagram of Clock Generator Circuit µPD784915B, 784916B 4.4 Reset Function When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset status). During the reset period, oscillation of the system clock is unconditionally stopped, so that the current dissipation of the overall system can be reduced. When the RESET pin goes high, the reset status is cleared. After the count time of the oscillation stabilization timer (32.8 ms at 16 MHz or 65.6 ms at 8 MHz) has elapsed, the contents of the reset vector table are set to the program counter (PC), and execution branches to the address set to the PC, and the program is executed starting from the branch destination address. Therefore, execution can be reset and started from any address. Figure 4-7. Oscillation of Main System Clock during Reset Period Main system clock oscillation circuit During reset, oscillation is unconditionally stopped. fCLT RESET input Oscillation stabilization timer count time The RESET pin is provided with an analog delay noise elimination circuit to prevent malfunctioning due to noise. Figure 4-8. Accepting Reset Signal Analog delay RESET input Internal reset signal Internal clock 60 Analog delay Oscillation Analog stabilization delay time µPD784915B, 784916B 5. INSTRUCTION SETS (1) 8-bit instructions (( ): combination realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA 2nd Operand # byte A r r' saddr saddr' sfr !addr16 mem r3 [WHL+] [WHL–] !!addr24 [saddrp] PSWL 1st Operand A None Note 2 [%saddrg] PSWH (MOV) ADDNote 1 (MOV) (XCH) MOV (MOV)Note 6 MOV (MOV) MOV MOV (MOV) (MOV) XCH (XCH)Note 6 (XCH) (XCH) XCH (XCH) (XCH) (ADD)Note 1 (ADD)Note 1 (ADD)Notes 1,6 (ADD)Note 1 ADDNote 1 ADDNote 1 r n MOV ADDNote 1 (MOV) (XCH) MOV XCH MOV XCH (ADD)Note 1 ADDNote 1 ADDNote 1 MOV XCH (ADD)Note 1 (ADD)Note 1 RORNote 3 MULU DIVUW MOV XCH ADDNote 1 INC DEC saddr MOV (MOV)Note 6 MOV ADDNote 1 (ADD)Note 1 ADDNote 1 XCH MOV INC DEC ADDNote 1 sfr MOV MOV ADDNote 1 (ADD)Note 1 ADDNote 1 DBNZ PUSH MOV POP CHKL CHKLA !addr16 MOV (MOV) !!addr24 mem ADDNote 1 [saddrp] ADDNote 1 MOV MOV [%saddrg] mem3 ROR4 ROL4 r3 PSWL MOV MOV PSWH B, C DBNZ STBC, WDM MOV [TDE+] (MOV) MOVBKNote 5 (ADD)Note 1 MOVMNote 4 [TDE–] (MOV) (ADD)Note 1 MOVBKNote 5 MOVMNote 4 Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. Either the second operand is not used, or the second operation is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short. 61 µPD784915B, 784916B (2) 16-bit instructions (( ): combination realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW 2nd Operand # word AX rp saddrp rp' saddrp' sfrp !addr16 mem !!addr24 [saddrp] [%saddrg] 1st Operand AX (MOVW) ADDWNote 1 (MOVW) (MOVW) (MOVW)Note 3 MOVW (XCHW) (XCHW) (XCHW)Note 3 (XCHW) [WHL+] (MOVW) MOVW (MOVW) XCHW (XCHW) XCHW byte n None Note 2 SHRW MULWNote 4 SHLW INCW DECW (ADDW)Note 1 (ADDW)Note 1 (ADDW)Notes 1, 3 (ADDW)Note 1 rp saddrp MOVW (MOVW) MOVW MOVW MOVW ADDWNote 1 (XCHW) XCHW ADDWNote 1 XCHW ADDWNote 1 MOVW XCHW (ADDW)Note 1 ADDWNote 1 (MOVW)Note 3 MOVW ADDWNote 1 (ADDW)Note 1 ADDWNote 1 MOVW MOVW INCW XCHW DECW ADDWNote 1 sfrp MOVW !addr16 ADDWNote 1 (ADDW)Note 1 ADDWNote 1 MOVW (MOVW) MOVW MOVW MOVW PUSH POP MOVTBLW !!addr24 mem MOVW [saddrp] [%saddrg] PSW SP PUSH POP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] (MOVW) SACW byte MACW MACSW Notes 1. SUBW and CMPW are the same as ADDW. 2. Either the second operand is not used, or the second operation is not an operand address. 3. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short. 4. MULUW and DIVUX are the same as MULW. 62 µPD784915B, 784916B (3) 24-bit instructions (( ): combination realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP 2nd Operand # imm24 rg WHL rg' !!addr24 mem1 [%saddrg] SP NoneNote saddrg 1st Operand WHL (MOVG) (MOVG) (MOVG) (MOVG) (ADDG) (SUBG) (ADDG) (ADDG) (SUBG) ADDG SUBG MOVG (MOVG) (ADDG) MOVG MOVG ADDG ADDG DECG SUBG (SUBG) SUBG PUSH POP saddrg !!addr24 (MOVG) MOVG MOVG mem1 MOVG MOVG rg (MOVG) [%saddrg] SP MOVG Note (SUBG) (MOVG) MOVG MOVG MOVG MOVG INCG MOVG INCG DECG Either the second operand is not used, or the second operation is not an operand address. (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET 2nd Operand CY 1st Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit Note MOV1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit iaddr16.bit !addr24.bit /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit MOV1 AND1 OR1 XOR1 AND1 OR1 NoneNote NOT1 SET1 CLR1 NOT1 SET1 CLR1 BF BT BTCLR BFSET Either the second operand is not used, or the second operation is not an operand address. 63 µPD784915B, 784916B (5) Call/return and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Operand of $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None instruction address Basic BCNote CALL CALL CALL CALL CALL CALL CALL instruction BR BR BR BR BR BR BR Compound BF instruction BT BR CALLF CALLT BRKCS BRK RET RETCS RETI RETCSB RETB BTCLR BFSET DBNZ Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS 64 µPD784915B, 784916B 6. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol VDD AVDD1 | VDD – AVDD1 | ≤ 0.5 V | VDD – AVDD2 | ≤ 0.5 V Unit –0.5 to +7.0 V –0.5 to +7.0 V V AVSS1 –0.5 to +0.5 V AVSS2 –0.5 to +0.5 V | AVDD1 – AVDD2 | ≤ 0.5 V –0.5 to VDD + 0.5 V VDD ≥ AVDD2 –0.5 to AVDD2 + 0.5 V VDD < AVDD2 –0.5 to VDD + 0.5 V VI Analog input voltage Ratings –0.5 to +7.0 AVDD2 Input voltage Condition VIAN (ANI0 to ANI11) Output voltage VO Low-level output current IOL –0.5 to VDD + 0.5 V Pin 1 15 mA Total of all pins 100 mA Pin 1 –10 mA High-level output current IOH –50 mA Operating ambient temperature TA –10 to +70 °C Storage temperature Tstg –65 to +150 °C Total of all pins Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings therefore specify the values exceeding which the product may be physically damaged. Never exceed these values when using the product. Operating Conditions Clock Frequency 4 MHz ≤ fXX ≤ 16 MHz 32 kHz ≤ fXT ≤ 35 kHz Operating Temperature (TA) –10 to +70°C Operating Conditions Supply Voltage (VDD) All functions +4.5 to +5.5 V CPU function only +4.0 to +5.5 V Subclock operation (CPU, watch, and port functions only) +2.7 to +5.5 V 65 µPD784915B, 784916B Oscillator Characteristics (main clock) (TA = –10 to +70°C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V) Oscillator Recommended Circuit Crystal oscillator Parameter Oscillation frequency (fXX) X1 X2 C1 MIN. MAX. Unit 4 16 MHz VSS C2 Oscillator Characteristics (subclock) (TA = –10 to +70°C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) Oscillator Recommended Circuit Crystal oscillator XT1 C1 Caution Parameter Oscillation frequency (fXT) XT2 MIN. MAX. Unit 32 35 kHz VSS C2 When using the main system clock and subsystem clock oscillation circuits, wire the portion enclosed by the broken line in the above figures as follows to avoid the adverse influence of wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. Do not route the wiring in the neighborhood of a signal line through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit to the same potential as VSS. Do not ground the capacitor to a ground pattern to which a high current flows. • Do not extract signals from the oscillation circuit. Exercise particular care in using the subsystem clock oscillation circuit because the amplification factor of this circuit is kept low to reduce the power dissipation. 66 µPD784915B, 784916B DC Characteristics (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Symbol Conditions TYP. MAX. Unit VIL1 Pins other than those listed in Note 1 below 0 0.3 VDD V VIL2 Pins listed in Note 1 below 0 0.2 VDD V 0 0.4 V 0.7 VDD VDD V 0.8 V DD V DD V V DD – 0.5 V DD V VIL3 X1, X2 VIH1 Pins other than those listed in Note 1 below VIH2 Pins listed in Note 1 below V IH3 X1, X2 V OL1 I OL = 5.0 mA (pins in Note 2) 0.6 V V OL2 I OL = 2.0 mA 0.45 V V OL3 I OL = 100 µ A V OH1 I OH = –1.0 mA V DD – 1.0 V OH2 I OH = –100 µ A V DD – 0.4 I LI 0 ≤ V I ≤ V DD Output leakage current I LO 0 ≤ V O ≤ V DD V DD supply current I DD1 Operation Input leakage current MIN. mode 0.25 V ±10 f XX = 16 MHz V V µA ±10 µA 30 50 mA 50 80 µA 10 25 mA 25 50 µA 18 50 µA 2.5 10 µA 0.2 7.0 µA 55 110 kΩ fXX = 8 MHz (low-frequency oscillation mode) Internally, 8-MHz main system clock operation f XT = 32.768 kHz Subclock operation (CPU, watch, port) VDD = 2.7 V I DD2 HALT mode f XX = 16 MHz fXX = 8 MHz (low-frequency oscillation mode) Internally, 8-MHz main clock operation f XT = 32.768 MHz Subclock operation (CPU, watch, port) VDD = 2.7 V Data hold voltage V DDDR STOP mode Data hold current Note 3 I DDDR STOP mode Subclock oscillates 2.5 V VDDDR = 5.0 V STOP mode Subclock oscillates VDDDR = 2.7 V STOP mode Subclock stops VDDDR = 2.5 V Pull-up resistor RL VI = 0 V 25 Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0P95/KEY4 2. P46, P47 3. In the STOP mode in which the subclock oscillation is stopped, disconnect the feedback resistor, and connect the XT1 pin to VDD. 67 µPD784915B, 784916B AC Characteristics CPU and peripheral circuit operation clock (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter CPU operation clock cycle time Symbol tCLK Condition fXX = 16 MHz VDD = AVDD = 4.0 to 5.5 V TYP. Unit 125 ns 125 ns MAX. Unit CPU Function only fXX = 16 MHz fXX = 8 MHz low-frequency oscillation mode (Bit 7 of CC = 1) Peripheral operation clock cycle time tCLK1 fXX = 16 MHz fXX = 8MHz low-frequency oscillation mode (Bit 7 of CC = 1) Serial interface (1) SIOn: n = 1 or 2 (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Serial clock cycle time Serial clock high- and low-level widths Symbol tCYSK Condition MIN. Input External clock 1.0 µs Output fCLK1/8 1.0 µs fCLK1/16 2.0 µs fCLK1/32 4.0 µs fCLK1/64 8.0 µs fCLK1/128 16 µs fCLK1/256 32 µs tWSKH Input External clock 420 ns tWSKL Output Internal clock tCYSK/2 – 50 ns SIn setup time (to SCKn ↑) tSSSK 100 ns SIn hold time (from SCKn ↑ ) tHSSK 400 ns SOn output delay time (to SCKn ↓ ) tDSSK 0 300 ns MIN. MAX. Unit Remarks 1. fCLK1: operating clock of peripheral circuit (8 MHz) 2. n = 1 or 2 (2) SIO2 only (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Condition SCK2(8) ↑→STRB ↑ tDSTRB tWSKH tCYSK Strobe high-level width tWSTRB tCYSK – 30 tCYSK + 30 BUSY setup time t SBUSY 100 ns t HBUSY 100 ns ns (to BUSY detection timing) BUSY hold time (to BUSY detection timing) BUSY inactive →SCK2(1) ↓ tLBUSY tCYSK + tWSKH Remarks 1. The value in parentheses following SCK2 indicates the number of SCK2. 2. BUSY is detected after the time (n+2) x tCYSK (n = 0, 1, and so on) has elapsed relative to SCK2 (8) ↑. 3. BUSY inactive →SCK2 (1) ↓ is the value when data write to SIO2 has been completed. 68 µPD784915B, 784916B Other operations (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Timer input signal low-level width Symbol tWCTL Condition When DFGIN, CFGIN, DPGIN, REEL0IN, MIN. MAX. Unit tCLK1 ns tCLK1 ns or REEL1IN logic level is input Timer input signal high-level width tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input Timer input signal valid edge input cycle tPERIN When DFGIN, CFGIN, or DPGIN is input 2 µs CSYNCIN low-level width tWCR1L When digital noise elimination circuit is not used 8tCLK1 ns When digital noise elimination circuit is used 108tCLK1 ns 180tCLK1 ns When digital noise elimination circuit is not used 8tCLK1 ns When digital noise elimination circuit is used 108tCLK1 ns 180tCLK1 ns (Bit 4 of INTM2 = 0) When digital noise elimination circuit is used (Bit 4 of INTM2 = 1) CSYNCIN high-level width tWCR1H (Bit 4 of INTM2 = 0) When digital noise elimination circuit is used (Bit 4 of INTM2 = 1) Digital noise Eliminated pulse width tWSEP elimination circuit Passed pulse width Bit 4 of INTM2 = 0 104tCLK1 ns Bit 4 of INTM2 = 1 176tCLK1 ns Bit 4 of INTM2 = 0 108tCLK1 ns Bit 4 of INTM2 = 1 180tCLK1 ns NMI low-level width tWNIL VDD = AVDD = 2.7 to 5.5 V 10 µs NMI high-level width tWNIH VDD = AVDD = 2.7 to 5.5 V 10 µs INTP0, INTP3 low-level widths tWIPL0 2tCLK1 ns INTP0, INTP3 high-level widths tWIPH0 2tCLK1 ns INTP1, KEY0 to KEY4 low-level widths tWIPL1 2tCLK1 ns 10 µs 2tCLK1 ns 10 µs Mode other than STOP mode In STOP mode, for releasing STOP mode INTP1, KEY0 to KEY4 high-level widths tWIPH1 Mode other than STOP mode In STOP mode, for releasing STOP mode INTP2 low-level width tWIPL2 In normal mode, Sampling = fCLK 2tCLK1 ns with main clock Sampling = fCLK/128 32Note µs Normal mode, Sampling = fCLK with subclock Sampling = fCLK/128 tWIPH2 10 µs 2tCLK1 ns with main clock Sampling = fCLK/128 32Note µs Normal mode, Sampling = fCLK with subclock Sampling = fCLK/128 In normal mode, In STOP mode, for releasing STOP mode RESET low-level width Note µs ms Sampling = fCLK In STOP mode, for releasing STOP mode INTP2 high-level width 61 7.9Note tWRSL 61 µs 7.9Note ms 10 µs 10 µs If a high or low level is successively input two times during the sampling period, a high or low level is detected. Remark tCKL1: operating clock cycle time of peripheral circuit (125 ns) 69 µPD784915B, 784916B Clock output operation (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter CLO cycle time Symbol Condition tCYCL MIN. MAX. Unit 250 2000 ns CLO low-level width tCLL tCYCL/2 ± 50 75 1050 ns CLO high-level width tCLH tCYCL/2 ± 50 75 1050 ns CLO rise time tCLR 50 ns CLO fall time tCLF 50 ns Data hold characteristics (TA = –10 to +70°C, VDD = AVDD = 2.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Low-level input voltage VIL High-level input voltage VIH Note Condition Special pins (pins in Note) MIN. MAX. Unit 0 TYP. 0.1 VDDDR V 0.9 VDDDR VDDDR V RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/ KEY4 Watch function (TA = –10 to +70°C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. MAX. Unit Subclock oscillation hold voltage VDDXT 2.7 V Hardware watch function operating voltage VDDW 2.7 V Subclock oscillation stop detection flag (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Oscillation stop detection width Symbol Condition MIN. MAX. µs 45 tOSCF Unit A/D converter characteristics (TA = –10 to +70°C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Condition Resolution MIN. TYP. MAX. 8 Total error bit AVREF = VDD Quantization error Conversion time tCONV Sampling time t SAMP Analog input voltage V IAN Analog input impedance AV REF current Unit 2.0 % ±1/2 LSB Bit 4 of ADM = 0 160t CLK1 µs Bit 4 of ADM = 1 80t CLK1 µs Bit 4 of ADM = 0 32t CLK1 µs Bit 4 of ADM = 1 16t CLK1 µs 0 AV REF V Z AN 1000 AI REF 0.4 1.2 MΩ mA MIN. TYP. MAX. Unit 2.35 2.50 2.65 V VREF amplifier (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Reference voltage VREF Charge current ICHG Condition Sets AMPM0.0 to 1 300 (pins in Note) Note 70 RECCTL+, RECCTL–, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN µA µPD784915B, 784916B CTL amplifier (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit CTL+, – input resistance RICTL 2 5 10 kΩ Feedback resistance RFCTL 20 50 100 kΩ RBCTL 20 50 100 kΩ Minimum voltage gain GCTLMIN 17 20 22 dB Maximum voltage gain GCTLMAX 71 Bias resistance Gain selecting step SGAIN In-phase elimination ratio CMR DC, voltage gain: 20 dB 75 dB 1.77 dB 50 dB High comparator set voltage of waveform shaping VPBCTLHS VREF + 0.47 VREF + 0.50 VREF + 0.53 V High comparator reset voltage of waveform shaping VPBCTLHR VREF + 0.27 VREF + 0.30 VREF + 0.33 V Low comparator set voltage of waveform shaping VPBCTLLS VREF – 0.53 VREF – 0.50 VREF – 0.47 V Low comparator reset voltage of waveform shaping VPBCTLLR VREF – 0.33 VREF – 0.30 VREF – 0.27 150 200 250 V Waveform shaping comparator Schmit width VPBSH mV High comparator voltage of CTL flag S VFSH VREF + 1.00 VREF + 1.05 VREF + 1.10 V Low comparator voltage of CLT flag S VFSL VREF – 1.10 VREF – 1.05 VREF – 1.00 V High comparator voltage of CTL flag L VFLH VREF + 1.40 VREF + 1.45 VREF + 1.50 V Low comparator voltage of CTL flag L VFLL VREF – 1.50 VREF – 1.45 VREF – 1.40 V CFG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Voltage gain 1 Condition MIN. TYP. MAX. fi = 2 kHz, open loop Voltage gain 2 GCFG2 fi = 30 kHz, open loop 34 dB CFGAMPO High-level output current IOHCFG DC –1 mA CFGAMPO Low-level output current IOLCFG DC 0.1 mA High comparator voltage VCFGH Low comparator voltage VCFGL Duty accuracy PDUTY Note 50 Unit GCFG1 dB VREF + 0.09 VREF + 0.12 VREF + 0.15 VREF – 0.15 VREF – 0.12 VREF – 0.09 Note 49.7 50.0 50.3 V V % The conditions include the following circuit and input signal. Input signal : Sine wave input (5 mVp-p) µ PD784916B fi = 1 kHz Voltage gain: 50 dB 1 kΩ – + 22 µ F 330 kΩ CFGIN CFGAMPO 0.01 µ F CFGCPIN 71 µPD784915B, 784916B DFG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Voltage gain GDFG Feedback resistance R FDFG Condition MIN. f i = 900 Hz, open loop TYP. MAX. Unit 400 640 kΩ 50 160 dB Input protection resistance R IDFG 150 Ω High comparator voltage V DFGH VREF + 0.07 VREF + 0.10 VREF + 0.14 V Low comparator voltage VDFGL VREF – 0.14 VREF – 0.10 VREF – 0.07 V Caution Set the input resistance connected to the DFGIN pin to 16 kΩ or below. Connecting a resistor exceeding that value may cause the DFG amp to oscillate. DPG comparator (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance ZIDPG High comparator voltage VDPGH VREF + 0.02 VREF + 0.05 VREF + 0.08 V Low comparator voltage VDPGL VREF – 0.08 VREF – 0.05 VREF – 0.02 V Ternary separation circuit (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Input impedance ZIPFG High comparator voltage VPFGH Low comparator voltage VPFGL Condition MIN. TYP. MAX. Unit 20 50 100 kΩ VREF + 0.5 VREF + 0.7 VREF + 0.9 V VREF – 1.4 VREF – 1.2 VREF – 1.0 V CSYNC comparator (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance ZICSYN High comparator voltage VCSYNH VREF + 0.07 VREF + 0.10 VREF + 0.13 V Low comparator voltage VCSYNL VREF – 0.13 VREF – 0.10 VREF – 0.07 V Reel FG comparator (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 20 50 100 kΩ Input impedance ZIRLFG High comparator voltage VRLFGH VREF + 0.02 VREF + 0.05 VREF + 0.08 V Low comparator voltage VRLFGL VREF – 0.08 VREF – 0.05 VREF – 0.02 V RECCTL driver (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V) Parameter Symbol Condition RECCTL+, – high-level output voltage VOHREC IOH = –4 mA RECCTL+, – low-level output voltage VOLREC CTLDLY internal resistance RCTL CTLDLY charge current I OHCTL CTLDLY discharge current I OLCTL 72 MIN. TYP. 40 Unit V IOL = 4 mA Use of internal resistor MAX. VDD – 0.8 70 0.8 V 140 kΩ –3 mA –3 mA µPD784915B, 784916B Timing waveform AC timing test point 0.8 VDD or 2.2 V 0.8 VDD or 2.2 V Test points 0.8 V 0.8 V Serial transfer timing (SIOn: n = 1 or 2) tWSKL tWSKH SCKn tCYSK tSSSK tHSSK Input data SIn tDSSK SOn Output data 73 µPD784915B, 784916B Serial transfer timing (SIO2 only) No busy processing tWSKL SCK2 tWSKH 7 8 9 10 1 2 10 10+n tCYSK BUSY Active high Busy invalid tDSTRB tWSTRB STRB Continuation of busy processing tWSKL SCK2 tWSKH 7 8 9 tCYSK BUSY tSBUSY tHBUSY Active high tDSTRB tWSTRB STRB End of busy processing tWSKL SCK2 tWSKH 7 8 tCYSK BUSY Caution 10+n tHBUSY 11+n 1 tLBUSY Active high When an external clock is selected as the serial clock, do not use the busy control or strobe control. 74 9 µPD784915B, 784916B Super timer unit input timing tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input tWCTL 0.8 VDD 0.8 V tWCR1H When CSYNCIN logic level is input tWCR1L 0.8 VDD 0.8 V Interrupt input timing tWNIH NMI tWNIL 0.8 VDD 0.8 V tWIPH0 INTP0, INTP3 tWIPL0 0.8 VDD 0.8 V tWIPH1 INTP1, KEY0-KEY4 tWIPL1 0.8 VDD 0.8 V tWIPH2 tWIPL2 0.8 VDD INTP2 0.8 V Reset input timing tWRSL RESET 0.8 V 75 µPD784915B, 784916B Clock output timing tCLH CLO 0.8 VDD 0.8 V tCLR tCLF tCLL tCYCL 76 µPD784915B, 784916B 7. PACKAGE DRAWING 100 PIN PLASTIC QFP (14 × 20) A B Q F G H I M 5°±5° 31 30 S 100 1 detail of lead end D 51 50 C 80 81 J M P K N L P100GF-65-3BA1-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. Remark External Dimensions of the ES version are the same as those of the mass-produced version. ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795 +0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 0.8 0.031 G 0.6 0.024 H 0.30 ± 0.10 0.012+0.004 –0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.8 ± 0.2 0.071+0.008 –0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. 77 µPD784915B, 784916B 8. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the µ PD784915B and 784916B. For details of the recommended soldering conditions, refer to the NEC document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 18-1. Soldering Conditions for Surface-Mount Type µ PD784915BGF-×××-3BA : 100-pin plastic QFP (14 × 20 mm) µ PD784916BGF-×××-3BA : 100-pin plastic QFP (14 × 20 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Duration: 30 sec. max. Recommended Condition Symbol IR35-00-3 (at 210°C or above), Number of times: 3 times max. VPS Wave soldering Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above), Number of times: 3 times max. VP15-00-3 Solder bath temperature: 260°C max. Duration: 10 sec. max. WS60-00-1 Number of times: Once Preliminary heat temperature: 120°C max. (Package surface temperature) Partial heating Caution 78 Pin temperature: 300°C max., Duration: 3 sec. max. (per pin row) – Using more than one soldering method should be avoided (except in the case of partial heating). µPD784915B, 784916B APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD784916B. Also refer to (5) Cautions on Using Development Tools. (1) Language Processing Software RA78K4 Assembler package common to 78K/IV Series CC78K/4 C compiler package common to 78K/IV Series DF784915 Device file for µPD784915 Subseries CC78K/4-L C compiler library source file common to 78K/IV Series (2) PROM Programming Tools PG-1500 PROM programmer PA-78P4916GF Program adapter connected to PG-1500. PG-1500 controller Control program for PG-1500 (3) Debugging Tools IE-784000-R In-circuit emulator common to 78K/IV Series IE-784000-R-EM Emulation board common to 78K/IV Series IE-70000-98-IF-B Interface adapter required when using PC-9800 series (except notebook PCs) as IE-70000-98-IF-CNote host machine IE-70000-98N-IF-B Interface adapter and cable required when using PC-9800 series (except notebook PCs) as host machine. IE-70000-PC-IF-B Interface adapter required when using IBM PC/AT or compatible as host machine. IE-70000-PC-IF-CNote IE-78000-R-SV3 Interface adapter and cable required when using EWS as host machine. IE-784915-R-EM1 Emulation board for emulating µPD784915 Subseries EP-784915GF-R Emulation probe for µPD784915 Subseries EV-9200GF-100 Socket to be mounted on target system board manufactured for 100-pin plastic QFP (GF-3BA type). Used for LCC packages. NQPACK100RB Socket to be mounted on target system board manufactured for 100-pin plastic ID78K4 Integrated debugger for IE-784000-R. SM78K4 System simulator common to 78K/IV Series DF784915 Device file for µPD784915 Subseries QFP (GF-3BA type). Used for QFP packages. Note Under development 79 µPD784915B, 784916B (4) Real-Time OS RX78K/IV Real-time OS for 78K/IV Series MX78K4 OS for 78/IV Series (5) Cautions on Using Development Tools • Use the ID78K4, SM78K4 in combination with the DF784915. • Use the CC78K4, RX78K/IV in combination with the RA78K4 and DF784915. • The NQPACK100RB is a product made by TOKYO ELETECH CORPORATION. Tokyo Electronic Components Division (TEL(03)3820-7112) Osaka Electronic Components Division (TEL(06)244-6672) • The host machines and OS supported by each software product are as follows. Host Machine PC EWS PC-9800 series [WindowsTM] HP9000 series 700TM [HP-UXTM] IBM PC/AT and Compatibles SPARCstationTM [SunOSTM] Software [Japanese/English Windows] NEWSTM (RISC) [NEWS-OSTM] RA78K4 √Note √ CC78K4 √Note √ PG-1500 controller √ – [OS] Note ID78K4 √ √ SM78K4 √ – RX78K/IV √Note √ MX78K4 √ √ Note DOS-based software 80 Note µPD784915B, 784916B APPENDIX B. RELATED DOCUMENTS Documents related to devices Document Number Document Name Japanese English µPD784915 Subseries User’s manual — Hardware U10444J U10444E µPD784915 Data Sheet U11044J U11044E µPD784915A, 784916A Data Sheet U11022E U11022J µPD784915B, 784916B Data Sheet U13118J This document µPD78P4916 Data Sheet U11045J U11045E µPD784915 Subseries Appllication Note U11361J U11361E µPD784915 Subseries Special function register table U10976J 78K/IV Series User’s manual — Instruction U10905J 78K/IV Series Instruction table U10594J — 78K/IV Series Instruction set U10595J — 78K/IV Series Application note — Software basics U10095J — U10905E U10095E Documents related to development tools (user’s manual) Document Number Document Name Japanese RA78K4 Series Assembler package U11162J U11162E Operation U11334J U11334E U11743J U11743E Language U11571J U11571E Operation U11572J U11572E RA78K4 Series Structured assembler preprocessor CC78K4 C compiler English Language CC78K Series Library source file U12322J — PG-1500 PROM Programmer U11940J EEU-1335 PG-1500 Controller PC-9800 series (MS-DOSTM) based EEU-704 EEU-1291 PG-1500 Controller IBM PC series (PC DOSTM) based EEU-5008 U10540E IE-784000-R U12903J EEU-1534 IE-784915-R-EMI, EP-784915-GF-R U10931J U10931E SM78K4 System Simulator Windows based Reference U10093J U10093E SM78K Series System Simulator External parts user open interface specifications U10092J U10092E ID78K4 Integrated debugger - Windows based Reference U10440J U10440E ID78K4 Integrated debugger - HP-UX, SunOS, NEWS-OS based Reference U11960J U11960E Caution The above related documents are subject to change without notice. Be sure to read the latest version of documents before designing. 81 µPD784915B, 784916B Documents related to embedded software (user’s manual) Document Number Document Name Japanese RX78K/IV Real-time OS 78K/IV Series OS MX78K4 English Basics U10603J U10603E Installation U10604J U10604E Debugger U10364J — Fundamental U11779J — Other related documents Document Number Document Name Japanese English IC package manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to prevent damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Guide to Quality Assurance for Semiconductor Devices MEI-1202 Microcomputer Product Series Guide Caution U11416J — The above related documents are subject to change without notice. Be sure to read the latest version of documents before designing. 82 — µPD784915B, 784916B [MEMO] 83 µPD784915B, 784916B NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 84 µPD784915B, 784916B Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J97. 8 85 µPD784915B, 784916B The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. FIP is a registered trademark of NEC Corporation. MS-DOS and Windows are either trademarks or registered trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT, and PC-DOS are trademarks of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS ia a trademark of Sun Microsystems, Inc. NEWS and NEW-OS are trademarks of Sony Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-in's. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 84