DATA SHEET MOS INTEGRATED CIRCUIT mPD78042F, 78043F, 78044F, 78045F 8-BIT SINGLE-CHIP MICROCOMPUTER The mPD78042F, mPD78043F, mPD78044F, and m PD78045F are 8-bit single-chip microcomputers that incorporate many hardware peripherals such as an FIP® controller/driver, 8-bit resolution A/D converter, timer, serial interface, and interrupt controller. The one-time PROM and EPROM models that can operate in the same voltage range as that of masked ROM models, and various development tools are provided. The functions of these microcomputers are described in detail in the following User’s Manual. Be sure to read this manual when you design a system using any of these microcomputers. mPD78044F Sub-Series User’s Manual : U10908E 78K/0 Series User's Manual, Instruction: IEU-1372 FEATURES • High-capacity ROM and RAM Item Product name Program memory (ROM) mPD78042F 16K bytes mPD78043F 24K bytes mPD78044F 32K bytes mPD78045F 40K bytes Data memory Internal high-speed RAM 512 bytes Buffer RAM 64 bytes FIP display RAM 48 bytes 1024 bytes • Wide range of instruction execution time - from high-speed (0.4 ms) to ultra low-speed (122 ms) • I/O ports: 68 • FIP controller/driver: total display outputs: 34 • • • • 8-bit resolution A/D converter: 8 channels Serial interface: 2 channels Timer: 6 channels Power supply voltage: VDD = 2.7 to 5.5 V ★ APPLICATIONS CD players, cassete tape recorders, tuners, minicomponent stereos, VCRs, microwave ovens, ECRs, etc. ORDERING INFORMATION Part number Package mPD78042FGF-¥¥¥-3B9 80-pin plastic QFP (14 ¥ 20 mm) mPD78043FGF-¥¥¥-3B9 80-pin plastic QFP (14 ¥ 20 mm) mPD78044FGF-¥¥¥-3B9 80-pin plastic QFP (14 ¥ 20 mm) mPD78045FGF-¥¥¥-3B9 80-pin plastic QFP (14 ¥ 20 mm) Remark ¥¥¥ indicates ROM code number. The information in this document is subject to change without notice. Document No. U10700EJ1V0DS00 (1st edition) Date Published July 1996 P Printed in Japan The mark ★ shows major revised points. © 1996 1990 mPD78042F, 78043F, 78044F, 78045F ★ 78K/0 SERIES PRODUCT DEVELOPMENT The 78K/0 series products were developed as shown below. The sub-series names are indicated in frames. Products under mass production Products under development 2 The Y Subseries is compatible with the I C bus. For control 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin µPD78078 µ PD78070A µ PD78058F µ PD78054 µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 µPD78078Y µPD78070AY µPD78058FY µPD78054Y µPD78018FY µPD78014Y µPD78002Y For FIP driving 78K/0 series 100-pin 80-pin 64-pin A timer added to the µPD78054 and external interface functions enhanced. ROM-less product of the µ PD78078 Counter-measure against EMI noise added to the µPD78054 An UART and D/A converter added to the µPD78014 and I/O function enhanced. Low-voltage (1.8 V) versions of the µPD78014. ROM and RAM variations enhanced. An A/D converter and 16-bit timer added to the µ PD78002. An A/D converter added to the µPD78002 Basic subseries for control These products include an UART and can operate at a low voltage (1.8 V). The I/O and FIP C/D of the µ PD78044F enhanced. Total indication output pins: 53 A 6-bit U/D counter added to the µPD78024. Total indication output pins: 34 Basic subseries for FIP driving. Total indication output pins: 26 µPD780208 µ PD78044F µPD78024 For LCD driving 100-pin 100-pin 100-pin µ PD780308 µPD780308Y SIO of the µPD78064 enhanced and ROM/RAM expanded. µ PD78064B µPD78064 µ PD78064Y Counter-measure against EMI noise added to the µ PD78064. Basic subseries for LCD driving. These products include an UART. Compatible with IEBusTM 80-pin µ PD78098 An IEBus controller added to the µPD78054. For LV 100-pin 2 µ PD78P0914 PWM output, LV digital code decoder, built-in Hsync counter. mPD78042F, 78043F, 78044F, 78045F The table below shows the main differences between subseries. Function Subseries name For control mPD78078 Timer 8-bit 8-bit Serial 8-bit 16-bit Watch WDT A/D D/A interface 4ch 8ch 2ch 3ch (UART : 1ch) ROM capacity 32K-60K 1ch 1ch 1ch I/O 88 pins 1.8 V 61 pins 2.7 V mPD78070A – mPD78058F 48K-60K mPD78054 16K-60K mPD78018F 8K-60K mPD78014 8K-32K mPD780001 8K mPD78002 8K-16K 1ch – mPD78083 8K-16K – 8ch For FIP mPD780208 32K-60K driving mPD78044F 16K-40K 68 pins mPD78024 24K-32K 54 pins For LCD mPD780308 48K-60K driving mPD78064B 32K mPD78064 16K-32K mPD78098 32K-60K 2ch 1ch 1ch 1ch 8ch 2ch mPD78P0914 32K 6ch – – 1ch 8ch – Compatible 2ch VDD Min. External value expansion ★ 69 pins 2.0 V – 2ch 53 pins 1.8 V 2.7 V – 2ch 2ch 1ch 1ch – 1ch 1ch 1ch 1ch 1ch 8ch 8ch 39 pins – 53 pins – – 1ch (UART : 1ch) 33 pins 1.8 V – 2ch 74 pins 2.7 V – 1.8 V – 3ch (UART : 1ch) 57 pins 2ch (UART : 1ch) ★ 2.0 V 3ch (UART : 1ch) 69 pins 2.7 V 2ch 54 pins 4.5 V with IEBus For LV ★ 3 mPD78042F, 78043F, 78044F, 78045F FUNCTIONAL OUTLINE Product name Item Internal memory mPD78043F mPD78042F ROM 16K bytes Internal high-speed RAM 512 bytes Buffer RAM 64 bytes FIP display RAM 48 bytes mPD78044F 32K bytes 24K bytes mPD78045F 40K bytes 1024 bytes General registers 8 bits ¥ 32 registers (8 bits ¥ 8 registers ¥ 4 banks) Instruction cycle Variable instruction execution time For main system clock 0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (at 5.0 MHz) For subsystem clock 122 ms (at 32.768 kHz) • Multiplication/division (8 bits ¥ 8 bits, 16 bits ÷ 8 bits) Instruction set • Bit (set, reset, test, Boolean algebra) I/O ports (including those Total : 68 lines multiplexed with FIP pins) • CMOS input : • CMOS I/O : 27 lines • N-ch open-drain : • P-ch open-drain I/O : 16 lines • P-ch open-drain output : 18 lines FIP controller/driver Total 2 lines 5 lines : 34 lines • Segments : 9 to 24 lines • Digits : 2 to 16 lines • 8-bit resolution ¥ 8 channels A/D converter ★ • Power supply voltage: AVDD = 4.0 to 5.5 V Serial interface • 3-wire serial I/O/SBI/2-wire serial I/O selectable modes: 1 channel • 3-wire serial I/O mode (with automatic transmission/ reception function of up to 64 bytes) Timer : 1 channel • 16-bit timer/event counter : 1 channel • 8-bit timer/event counter : 2 channels • Watch timer : 1 channel • Watchdog timer : 1 channel • 6 bit up/down counter : 1 channel Timer output 3 lines (one for 14-bit PWM output) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz (Main system clock: at 5.0 MHz) 32.768 kHz (Subsystem clock: at 32.768 kHz) Buzzer output Vectored interrupt ★ 1.2 kHz, 2.4 kHz, 4.9 kHz (Main system clock: at 5.0 MHz) Maskable interrupt Internal 10 lines, external 4 lines Non-maskable interrupt Internal 1 line Software interrupt 1 line Text input Internal 1 line Power supply voltage VDD = 2.7 to 5.5 V Package 80-pin plastic QFP (14 ¥ 20 mm) 4 mPD78042F, 78043F, 78044F, 78045F CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 6 2. BLOCK DIAGRAM ..................................................................................................................... 8 3. PINS FUNCTIONS ..................................................................................................................... 9 3.1 PORT PINS ...................................................................................................................................... 9 3.2 PINS OTHER THAN PORT PINS ................................................................................................... 11 3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ........................................................ 13 4. MEMORY SPACE ...................................................................................................................... 16 5. PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 17 6. 5.1 PORTS ............................................................................................................................................. 17 5.2 CLOCK GENERATOR CIRCUIT .................................................................................................... 18 5.3 TIMER/EVENT COUNTER .............................................................................................................. 18 5.4 CLOCK OUTPUT CONTROL CIRCUIT ......................................................................................... 21 5.5 BUZZER OUTPUT CONTROL CIRCUIT ....................................................................................... 21 5.6 A/D CONVERTER ........................................................................................................................... 22 5.7 SERIAL INTERFACE ...................................................................................................................... 22 5.8 FIP CONTROLLER/DRIVER .......................................................................................................... 24 INTERRUPT FUNCTION AND TEST FUNCTION .................................................................... 26 6.1 INTERRUPT FUNCTION................................................................................................................. 26 6.2 TEST FUNCTION ............................................................................................................................ 29 7. STANDBY FUNCTION ............................................................................................................... 30 8. RESET FUNCTION .................................................................................................................... 30 9. INSTRUCTION SET ................................................................................................................... 31 10. ELECTRICAL SPECIFICATIONS ............................................................................................. 34 ★ 11. CHARACTERISTIC CURVE (REFERENCE VALUE) .............................................................. 58 ★ 12. PACKAGE DRAWING ............................................................................................................... 63 13. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 64 APPENDIX A DEVELOPMENT TOOLS ......................................................................................... 65 APPENDIX B RELATED DOCUMENTS ......................................................................................... 67 5 ★ mPD78042F, 78043F, 78044F, 78045F 1. PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 ¥ 20 mm) mPD78042FGF-¥¥¥-3B9, mPD78043FGF-¥¥¥-3B9 P112/FIP20 P113/FIP21 P111/FIP19 P110/FIP18 P107/FIP17 P106/FIP16 VLOAD P105/FIP15 P104/FIP14 P103/FIP13 P102/FIP12 P101/FIP11 P100/FIP10 P97/FIP9 P96/FIP8 P95/FIP7 mPD78044FGF-¥¥¥-3B9, mPD78045FGF-¥¥¥-3B9 P94/FIP6 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 P114/FIP22 P93/FIP5 2 63 P115/FIP23 P92/FIP4 3 62 P116/FIP24 P91/FIP3 4 61 P117/FIP25 P90/FIP2 5 60 P120/FIP26 P81/FIP1 6 59 P121/FIP27 P80/FIP0 7 58 P122/FIP28 VDD 8 57 P123/FIP29 P27/SCK0 9 56 P124/FIP30 P26/SO0/SB1 10 55 P125/FIP31 P25/SI0/SB0 11 54 P126/FIP32 P24/BUSY 12 53 P127/FIP33 P23/STB 13 52 VDD P22/SCK1 14 51 P70 P21/SO1 15 50 P71 P03/INTP3/CI0 P16/ANI6 22 43 P30/TO0 P15/ANI5 23 42 P31/TO1 P14/ANI4 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P32/TO2 P33/TI1 44 P34/TI2 21 P35/PCL P02/INTP2 P17/ANI7 P36/BUZ 45 X2 20 P37 P01/INTP1 AVSS X1 46 VSS 19 XT2 P00/INTP0/TI0 P73 P04/XT1 47 AVREF IC 18 AVDD 48 P74 P10/ANI0 17 P11/ANI1 49 RESET P12/ANI2 16 P72 P13/ANI3 P20/SI1 Cautions 1. Connect the IC (Internally Connected) pins directly to the VSS. 2. Connect the AVDD pin to the VDD pin. 3. Connect the AVSS pin to the VSS pin. 6 mPD78042F, 78043F, 78044F, 78045F P00-P04 : Port 0 SCK0, SCK1 : Serial clock P10-P17 : Port 1 PCL : Programmable clock P20-P27 : Port 2 BUZ : Buzzer clock P30-P37 : Port 3 STB : Strobe P70-P74 : Port 7 BUSY : Busy P80, P81 : Port 8 FIP0-FIP33 : Fluorescent indicator panel P90-P97 : Port 9 VLOAD P100-P107 : Port 10 X1, X2 : Crystal (main system clock) P110-P117 : Port 11 XT1, XT2 : Crystal (subsystem clock) P120-P127 : Port 12 : Negative power supply RESET : Reset INTP0-INTP3 : Interrupt from peripherals ANI0-ANI7 : Analog input TI0-TI2 : Timer input AVDD : Analog power supply TO0-TO2 : Timer output AVSS : Analog ground CI0 : Counter input AVREF : Analog reference voltage SB0, SB1 : Serial bus VDD : Power supply SI0, SI1 : Serial input VSS : Ground SO0, SO1 : Serial output IC : Internally connected 7 mPD78042F, 78043F, 78044F, 78045F 2. BLOCK DIAGRAM TO0/P30 TI0/INTP0/P00 16-bit timer/ event counter Port 0 P00 P01-P03 P04 TO1/P31 TI1/P33 8-bit timer/ event counter 1 Port 1 P10-P17 TO2/P32 TI2/P34 8-bit timer/ event counter 2 Port 2 P20-P27 Watchdog timer Port 3 P30-P37 Watch timer Port 7 P70-P74 CI0/INTP3/P03 6-bit up/down counter Port 8 P80, P81 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 Serial interface 0 Port 9 P90-P97 Port 10 P100-P107 Port 11 P110-P117 Port 12 P120-P127 78K/0 CPU core ROM SI1/P20 SO1/P21 SCK1/P22 Serial interface 1 STB/P23 BUSY/P24 ANI0/P10ANI7/P17 AVDD AVSS AVREF A/D converter RAM FIP controller/driver FIP0-FIP33 VLOAD INTP0/TI0/P00INTP3/CI0/P03 BUZ/P36 PCL/P35 Interrupt control Buzzer output Clock output control System control VDD VSS IC Remark The capacities of the internal ROM and RAM differ depending on the product. 8 RESET X1 X2 XT1/P04 XT2 mPD78042F, 78043F, 78044F, 78045F 3. PINS FUNCTIONS 3.1 PORT PINS (1/2) Pin name I/O Function On reset Shared by: P00 Input Port 0 Input only Input INTP0/TI0 P01 I/O 5-bit I/O port Can be specified for input or output in 1-bit Input INTP1 P02 units. When used as an input port pin, a built-in INTP2 P03 pull-up resistor can be used by software. INTP3/CI0 P04Note 1 Input P10-P17 I/O Input only Port 1 Input XT1 Input ANI0-ANI7 Input SI1 8-bit I/O port Can be specified for input or output in 1-bit units. When used as an input port pin, a built-in pull-up resistor can be used by software.Note 2 P20 I/O Port 2 P21 8-bit I/O port SO1 P22 Can be specified for input or output in 1-bit units. SCK1 P23 When used as an input port pin, a built-in pull-up resistor can be STB P24 used by software. BUSY P25 SI0/SB0 P26 SO0/SB1 P27 SCK0 P30 I/O Port 3 Input TO0 P31 8-bit I/O port TO1 P32 Can be specified for input or output in 1-bit units. TO2 P33 Can directly drive LEDs. TI1 P34 When used as an input port pin, a built-in pull-up resistor can be TI2 P35 used by software. PCL P36 A pull-down resistor can be connected in 1-bit units by the mask BUZ P37 option. — Notes 1. When the P04/XT1 pins is used as an input port pin, bit 6 (FRC) of the processor clock control register (PCC) must be set to 1. At this time, do not use the feedback resistor of the subsystem clock oscillator circuit. 2. When the P10/ANI0 through P17/ANI7 pins are used as the analog input lines of the A/D converter, be sure to place the port 1 in the input mode. In this case, the built-in pull-up resistors are automatically unused. 9 mPD78042F, 78043F, 78044F, 78045F 3.1 PORT PINS (2/2) Pin name P70-P74 I/O I/O Function Port 7 5-bit N-ch open-drain I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-up resistor can be connected in 1-bit units by the mask On reset Input Shared by: — option. P80, P81 Output Port 8 2-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be Output FIP0, FIP1 Output FIP2-FIP9 specified in bit units). P90-P97 Output Port 9 8-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). P100-P107 Output Port 10 8-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Output FIP10-FIP17 P110-P117 I/O Port 11 8-bit P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Input FIP18-FIP25 P120-P127 I/O Port 12 8-bit P-ch open-drain high-voltage I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or V SS is connected can be specified in 4-bit units). Input FIP26-FIP33 10 mPD78042F, 78043F, 78044F, 78045F 3.2 PINS OTHER THAN PORT PINS (1/2) Pin name INTP0 I/O Input Function Valid edge (rising, falling, or both rising and falling edges) can On reset Input Shared by: P00/TI0 INTP1 be specified. P01 INTP2 External interrupt input P02 INTP3 Falling edge-active external interrupt input Input P03/CI0 Serial data input lines of serial interface Input P25/SB0 SI0 Input SI1 SO0 P20 Output Serial data output lines of serial interface Input SO1 SB0 P21 I/O Serial data I/O lines of serial interface Input SB1 SCK0 P26/SB1 P25/SI0 P26/SO0 I/O Serial clock I/O lines of serial interface Input SCK1 P27 P22 STB Output Automatic transmission/reception strobe output line of serial interface Input P23 BUSY Input Automatic transmission/reception busy input line of serial interface Input P24 TI0 Input External count clock input to 16-bit timer (TM0) Input P00/INTP0 TI1 External count clock input to 8-bit timer (TM1) P33 TI2 External count clock input to 8-bit timer (TM2) P34 TO0 Output TO1 16-bit timer output (multiplexed with 14-bit PWM output) Input 8-bit timer output P30 P31 TO2 P32 CI0 Input Clock input to 6-bit up/down counter Input P03/INTP3 PCL Output Clock output (for trimming main system clock and subsystem clock) Input P35 BUZ Output Buzzer output Input P36 FIP0, FIP1 Output High-voltage, high-current digit/segment output of FIP Output P80, P81 FIP2-FIP9 controller/driver P90-P97 FIP10-FIP15 Output High-voltage, high-current digit/segment output of FIP controller/driver Output P100-P105 FIP16, FIP17 Output High-voltage segment output of FIP controller/driver Output P106, P107 Input P110-P117 FIP18-FIP25 FIP26-FIP33 VLOAD P120-P127 — Connects pull-down resistor to FIP controller/driver — — 11 mPD78042F, 78043F, 78044F, 78045F 3.2 PINS OTHER THAN PORT PINS (2/2) Pin name I/O Function On reset Input Shared by: ANI0-ANI7 Input A/D converter analog input lines P10-P17 AVREF Input A/D converter reference voltage input line — — AVDD — Analog power supply to A/D converter. Connected to the VDD pin. — — AVSS — A/D converter ground line. Connected to the VSS pin. — — RESET Input System reset input — — X1 Input Connect crystal for main system clock oscillation — — X2 — — — XT1 Input XT2 — VDD — VSS IC 12 Connect crystal for subsystem clock oscillation Input P04 — — Positive power supply — — — Ground potential — — — Internal connection. Connected directly to the VSS pin. — — mPD78042F, 78043F, 78044F, 78045F 3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS Table 3-1 shows the I/O circuit type of each pin and the processing of unused pins. For the configuration of the I/O circuit of each type, refer to Fig. 3-1. Table 3-1 Pin name P00/INTP0/TI0 I/O Circuit Type I/O Circuit type Recommended connections when unused Input Connected to VSS . 8-A I/O Individually connected to V SS with a resistor. P04/XT1 16 Input Connected to VDD or VSS . P10/ANI0-P17/ANI7 11 I/O Individually connected to V DD or VSS with a resistor. P20/SI1 8-A P21/SO1 5-A P22/SCK1 8-A P23/STB 5-A P24/BUSY 8-A P25/SI0/SB0 10-A P01/INTP1 2 I/O P02/INTP2 P03/INTP3/CI0 P26/SO0/SB1 P27/SCK0 P30/TO0 5-C P31/TO1 P32/TO2 P33/TI1 8-B P34/TI2 P35/PCL 5-C P36/BUZ P37 P70-P74 13-B P80/FIP0, P81/FIP1 14-A Output Open 15-C I/O Individually connected to V DD or VSS with a resistor. P90/FIP2-P97/FIP9 P100/FIP10-P107/FIP17 P110/FIP18-P117/FIP25 P120/FIP26-P127/FIP33 RESET 2 XT2 16 AV REF — Input — — Open Connected to VSS . AV DD Connected to V DD. AV SS Connected to VSS . VLOAD IC Connected directly to VSS. 13 mPD78042F, 78043F, 78044F, 78045F Fig. 3-1 Pin I/O Circuits (1/2) Type 2 Type 8-A V DD Pull-up enable P-ch V DD IN Data P-ch IN/OUT Schmitt trigger input with hysteresis characteristics Type 5-A N-ch Type 8-B V DD Pull-up enable Output disable V DD Pull-up enable P-ch P-ch V DD V DD Data P-ch Data IN/OUT Output disable P-ch IN/OUT N-ch Output disable N-ch (Mask option) Input enable Type 5-C Type 10-A V DD V DD Pull-up enable Pull-up enable P-ch V DD Data P-ch V DD Data P-ch P-ch IN/OUT Output disable Input enable 14 N-ch (Mask option) IN/OUT Open-drain Output disable N-ch mPD78042F, 78043F, 78044F, 78045F Fig. 3-1 Pin I/O Circuits (2/2) V DD Type 11 Pull-up enable Type 15-C P-ch P-ch IN/OUT Data P-ch IN/OUT Output disable V DD P-ch V DD Data VDD N-ch N-ch P-ch Comparator (Mask option) + – N-ch RD N-ch VREF (Threshold voltage) VLOAD (Mask option) Input enable Type 13-B Type 16 V DD (Mask option) Feedback cut-off IN/OUT P-ch Data Output disable N-ch V DD RD P-ch Input buffer with intermediate withstand voltage XT1 XT2 Type 14-A V DD P-ch V DD P-ch OUT Data N-ch (Mask option) VLOAD (Mask option) 15 mPD78042F, 78043F, 78044F, 78045F 4. MEMORY SPACE Fig. 4-1 shows the memory map for mPD78042F, mPD78043F, m PD78044F, and mPD78045F. Fig. 4-1 Memory Map FFFFH Special function register (SFR) 256 × 8 bits FF00H FEFFH FEE0H FEDFH General register 32 × 8 bits Internal high-speed RAM Note Data memory space mmmmH mmmmH – 1 FB00H FAFFH FAC0H FABFH nnnnH Program area Inhibited 1000H 0FFFH Buffer RAM 64 × 8 bits CALLF entry area Inhibited FA80H FA7FH FA50H FA4FH 0800H 07FFH FIP display RAM 48 × 8 bits Program area 0080H 007FH Inhibited CALLT table area nnnnH + 1 nnnnH Program memory space 0040H 003FH Internal ROM Note Vector table area 0000H 0000H Note The internal ROM and internal high-speed RAM capacities vary depending on the product. (See the table below.) Product name 16 Last Address of Internal ROM First address of internal high-speed RAM nnnnH mmmmH mPD78042F 3FFFH FD00H mPD78043F 5FFFH mPD78044F 7FFFH mPD78045F 9FFFH FB00H mPD78042F, 78043F, 78044F, 78045F 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports are classified into the following five types: • CMOS input (P00, P04) :2 • CMOS input/output (P01 - P03, ports 1 - 3) : 27 • N-ch open-drain input/output (port 7) :5 • P-ch open-drain output (ports 8 - 10) : 18 • P-ch open-drain input/output (ports 11 and 12) : 16 Total : 68 Table 5-1 Product Port 0 Pin Port Function Function P00, P04 Input-only port P01-P03 I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. Port 1 P10-P17 I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. Port 2 P20-P27 I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. Port 3 P30-P37 I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. Pull-down resistor can be connected in 1-bit units by the mask option. Can directly drive LED. Port 7 P70-P74 N-ch open-drain I/O port. Can be specified for input or output in 1-bit units. Pull-up resistor can be connected in 1-bit units by the mask option. Can directly drive LED. Port 8 P80, P81 P-ch open-drain output port with high withstand voltage. Pull-down resistor can be connected in 2-bit units by the mask option (connection to VLOAD or VSS can be specified in 2-bit units). Can directly drive LED. Port 9 P90-P97 P-ch open-drain output port with high withstand voltage. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. Port 10 P100-P107 P-ch open-drain output port with high withstand voltage. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. Port 11 P110-P117 P-ch open-drain I/O port with high withstand voltage. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. Port 12 P120-P127 P-ch open-drain I/O port with high withstand voltage. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. 17 mPD78042F, 78043F, 78044F, 78045F 5.2 CLOCK GENERATOR CIRCUIT The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock. The instruction time can be changed. • 0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (with main system clock: 5.0 MHz) • 122 ms (with subsystem clock: 32.768 kHz) Fig. 5-1 Subsystem clock oscillator XT2 f XT Clock output circuit Selector XT1/P04 Clock Generator Circuit Block Diagram Noise eliminator Watch timer Selector fX 8 fX 16 Prescaler 1 Main system clock oscillator Prescaler 2 Clock to hardware peripherals fX X2 fX 22 fX 2 fX 23 f XT 2 fX 24 Selector X1 STOP Standby control circuit CPU clock (f CPU) To INTP0 sampling clock 5.3 TIMER/EVENT COUNTER Six channels of timer/event counters are provided. • 16-bit timer/event counter : 1 channel • 8-bit timer/event counter : 2 channels • Watch timer : 1 channel • Watchdog timer : 1 channel • 6-bit up/down counter : 1 channel Table 5-2 Timer/Event Counter Groups and Configurations Function Group 16-bit timer/ event counter Watch timer 6-bit up/ down counter 1 channel 2 channels External event counter 1 channel 2 channels — — Timer output 1 output 2 outputs — — — PWM output 1 output — — — — Pulse width measurement 1 input — — — — Square wave output 1 output 2 outputs — — — Interrupt Request 1 2 — 1 channel Watchdog timer Interval timer Test input 18 8-bit timer/ event counter 1 — 1 input 1 channel 1 — 1 channel 1 — — mPD78042F, 78043F, 78044F, 78045F Fig. 5-2 16-Bit Timer/Event Counter Block Diagram Internal bus 16-bit compare register (CR00) INTTM0 PWM pulse output control circuit Match fX Selector f X/2 f X/22 f X/23 TI0/P00/INTP0 16-bit timer/event counter output control circuit TO0/P30 16-bit timer register (TM0) Edge detector Selector Clear INTP0 16-bit capture register (CR01) Internal bus Fig. 5-3 8-Bit Timer/Event Counter Block Diagram Internal bus INTTM1 8-bit compare register (CR10) Selector 8-bit compare register (CR20) Match Match 8-bit timer register 1 (TM1) TI1/P33 f X/2 -fX/210 f X/212 Selector Clear Selector f X/212 TO2/P32 INTTM2 Selector f X/2 -fX/210 Output control circuit Selector TI2/P34 8-bit timer register 2 (TM2) Clear Output control circuit TO1/P31 Internal bus 19 mPD78042F, 78043F, 78044F, 78045F f XT fW Prescaler fW 25 fW 26 fW 27 fW 28 Fig. 5-5 fX 23 f WDT INTTM3 Watchdog Timer Block Diagram Prescaler f WDT 22 f WDT 23 f WDT 24 f WDT 25 f WDT 26 f WDT 28 Selector f WDT 2 Control circuit Selector fX 24 INTWT fW 213 fW 29 Selector fW 24 fW 214 5-bit counter Selector Selector f X/28 Watch Timer Block Diagram Selector Fig. 5-4 8-bit counter INTWDT Maskable interrupt request RESET INTWDT Nonmaskable interrupt request Fig. 5-6 6-Bit Up/Down Counter Block Diagram Selector INTP3/INTUD Clear CI0/P03/INTP3 6-bit up/down counter (UDC) Edge detector Load Match Underflow 6-bit up/down counter compare register (UDCC) Internal bus Caution When using the 6-bit up/down counter, set the CI0/P03/INTP3 pin in the input mode (set bit 3 of port mode register 0 (PM03) to 1). 20 mPD78042F, 78043F, 78044F, 78045F 5.4 CLOCK OUTPUT CONTROL CIRCUIT Clocks of the following frequencies can be output to the clock: • 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz (with main system clock: 5.0 MHz) • 32.768 kHz (with subsystem clock: 32.768 kHz) Fig. 5-7 Clock Output Control Circuit Block Diagram f X /2 3 f X /2 4 5 5.5 f X /2 7 f X /2 f XT 8 Selector f X /2 f X /2 6 Sync circuit Output control circuit PCL/P35 BUZZER OUTPUT CONTROL CIRCUIT Clocks of the following frequencies can be output to the buzzer: • 1.2 kHz/2.4 kHz/4.9 kHz (with main system clock: 5.0 MHz) f X /2 10 f X /2 11 f X /2 12 Selector Fig. 5-8 Buzzer Output Control Circuit Block Diagram Output control circuit BUZ/P36 21 mPD78042F, 78043F, 78044F, 78045F 5.6 A/D CONVERTER An 8-bit resolution 8-channel A/D converter is provided. This A/D converter can be started in the following two modes: • Hardware start • Software start Fig. 5-9 A/D Converter Block Diagram Series resistor string AVDD ANI0/P10 AVREF ANI2/P12 Voltage comparator Selector ANI3/P13 ANI4/P14 Tap selector Sample & hold circuit ANI1/P11 ANI5/P15 ANI6/P16 AVSS Successive approximation register (SAR) ANI7/P17 INTP3/P03 Falling edge detector Control circuit INTAD INTP3 A/D conversion result register (ADCR) Internal bus 5.7 SERIAL INTERFACE Two channels of clocked serial interfaces are provided. • Serial interface channel 0 • Serial interface channel 1 Table 5-3 Function Serial Interface Groups and Functions Serial interface channel 0 Serial interface channel 1 3-wire serial I/O mode • (MSB/LSB first selectable) SBI (serial bus interface) mode • (MSB first) — 2-wire serial I/O mode • (MSB first) — 3-wire serial I/O mode with automatic transmission/ reception function 22 — • (MSB/LSB first selectable) • (MSB/LSB first selectable) mPD78042F, 78043F, 78044F, 78045F Fig. 5-10 Serial Interface Channel 0 Block Diagram Selector SO0/SB1/P26 Serial I/O shift register 0 (SIO0) Output latch Busy/acknowledge output circuit Bus release/ command/acknowledge detector Interrupt request signal generator Serial clock counter SCK0/P27 Serial clock control circuit Fig. 5-11 INTCSI0 f X/22 -fX/29 Selector SI0/SB0/P25 Selector Internal bus TO2 Serial Interface Channel 1 Block Diagram Internal bus Automatic data transmission/reception address pointer (ADTP) Serial I/O shift register 1 (SIO1) SI1/P20 Automatic data transmission/ reception interval specification register (ADTI) Buffer RAM Match SO1/P21 5-bit counter STB/P23 BUSY/P24 SCK1/P22 Handshake control circuit Serial clock counter Interrupt request signal generator INTCSI1 fX/22-fX/29 Serial clock control circuit Selector TO2 23 mPD78042F, 78043F, 78044F, 78045F 5.8 FIP CONTROLLER/DRIVER An FIP controller/driver having the following features is provided: (a) Automatic output of segment signals (DMA operation) and digit signals by automatically reading display data (b) Display mode registers (DSPM0 and DSPM1) that can control an FIP of 9 to 24 segments and 2 to 16 digits (c) Port pins not used for FIP display can be used as output port or I/O port pins. (d) Display mode register (DSPM1) can adjust luminance in eight steps. (e) Hardware suitable for key scan application using segment pins (f) High-voltage output buffer (FIP driver) that can directly drive an FIP (g) Display output pins can be connected to a pull-down resistor by the mask option. Fig. 5-12 Selecting Display Modes Selecting number of digits 0 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9 10 11 12 Selecting number of segments 13 14 15 16 17 18 19 20 21 22 23 24 Caution If the total number of digits and segments exceeds 34, the specified number of digits takes precedence. 24 mPD78042F, 78043F, 78044F, 78045F Fig. 5-13 FIP Controller/Driver Block Diagram Internal bus Display data memory Digit signal generator Segment data latch Port output latch Buffer with high withstand voltage FIP0/P80 FIP1/P81 FIP33/P127 25 mPD78042F, 78043F, 78044F, 78045F 6. INTERRUPT FUNCTION AND TEST FUNCTION 6.1 INTERRUPT FUNCTION The following three types of interrupt functions are available: • Non-maskable interrupt : 1 • Maskable interrupt : 13 • Software interrupt : 1 Table 6-1 Interrupt Source List Note 2 Interrupt source Note 1 Interrupt type Default priority Non-maskable — INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow Name Internal/ external Vector table address Internal 0004H Trigger Basic configuration type (A) (B) (with interval timer mode selected) Software 1 INTP0 2 Pin input edge detection External 0006H (C) INTP1 0008H (D) 3 INTP2 000AH 4 INTP3 000CH INTUD 6-bit up/down counter match signal generation Internal 5 INTCSI0 End of serial interface channel 0 transfer 000EH 6 INTCSI1 End of serial interface channel 1 transfer 0010H 7 INTTM3 Reference time interval signal from watch timer 0012H 8 INTTM0 16-bit timer/event counter match signal generation 0014H 9 INTTM1 8-bit timer/event counter 1 match signal generation 0016H 10 INTTM2 8-bit timer/event counter 2 match signal generation 0018H 11 INTAD End of A/D converter conversion 001AH 12 INTKS Key scan timing from FIP controller/driver 001CH — BRK Execution of BRK instruction — (B) 003EH (E) Notes 1. Default priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest order and the 12 is the lowest order. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Fig. 6-1. 26 mPD78042F, 78043F, 78044F, 78045F Fig. 6-1 Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt request Vector table address generator Priority control circuit Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Vector table address generator Priority control circuit IF Standby release signal (C) External maskable interrupt (INTP0) Internal bus Sampling clock select register (SCS) Interrupt request Sampling clock External interrupt mode register (INTM0) Edge detector MK IF IE PR Priority control circuit ISP Vector table address generator Standby release signal 27 mPD78042F, 78043F, 78044F, 78045F Fig. 6-1 Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) Internal bus External interrupt mode register (INTM0) Interrupt request Edge detector MK IE PR Priority control circuit IF ISP Vector table address generator Standby release signal (E) Software interrupt Internal bus Interrupt request IF : Interrupt request flag IE : Interrupt enable flag ISP : In-service priority flag 28 MK : Interrupt mask flag PR : Priority specification flag Priority control circuit Vector table address generator mPD78042F, 78043F, 78044F, 78045F 6.2 TEST FUNCTION The following test function is available. Test input source Name INTWT Internal/external Trigger Overflow of watch timer Fig. 6-2 Internal Basic Configuration of Test Function Internal bus MK Test input source (INTWT) IF IF Standby release signal : Test request flag MK : Test mask flag 29 mPD78042F, 78043F, 78044F, 78045F 7. STANDBY FUNCTION The standby function is to reduce the current dissipation of the system and can be effected in the following two modes: • HALT mode : In this mode, the operating clock of the CPU is stopped. By using this mode in combination with the normal operation mode, the system can be operated intermittently, so that the average current dissipation can be reduced. • STOP mode : Oscillation of the main system clock is stopped. All the operations on the main system clock are stopped, and therefore, the current dissipation of the system can be minimized with only the subsystem clock oscillating. Fig. 7-1 Main system clock operation STOP instruction Interrupt request STOP mode (Oscillation of main system clock stopped) Standby Function CSS = 1 CSS = 0 Subsystem clock operationNote HALT instruction Interrupt request HALT instruction Interrupt request HALT mode (Clock supply to CPU stopped. Oscillation continues) HALT modeNote (Clock supply to CPU stopped. Oscillation continues) Note By stopping the main system clock, the current dissipation can be reduced. When the CPU operates on the subsystem clock, stop the main system clock by setting bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction cannot be used. Caution When the main system clock is stopped and the subsystem clock is operating, to switch again from the subsystem clock to the main system clock, allow sufficient time for the oscillation to settle before switching, by coding the program accordingly. 8. RESET FUNCTION The system can be reset in the following two modes: • External reset by RESET pin • Internal reset by watchdog timer that detects hang up 30 mPD78042F, 78043F, 78044F, 78045F 9. INSTRUCTION SET (1) 8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second operand #byte A r Note sfr saddr !addr16 MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP First operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV B, C 1 None ROR ROL RORC ROLC INC DEC ★ DBNZ !addr16 PSW MOV $addr16 DBNZ INC DEC MOV MOV MOV [DE] MOV [HL] MOV [HL + byte] [HL + B] [HL + C] MOV PUSH POP ROR4 ROL4 X MULU C DIVUW Note Except for r = A 31 mPD78042F, 78043F, 78044F, 78045F (2) 16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second operand #word Note AX rp sfrp saddrp !addr16 SP None First operand AX ADDW SUBW CMPW rp MOVW MOVW sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW XCHW MOVW MOVW MOVW MOVW Note INCW DECW PUSH POP MOVW SP MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 First operand CY 32 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 mPD78042F, 78043F, 78044F, 78045F (4) Call/Branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second operand AX !addr16 !addr11 [addr5] $addr16 CALL BR CALLF CALLT First operand Basic operation BR Compound operation BR BC BNC BZ BNZ BT BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 33 mPD78042F, 78043F, 78044F, 78045F ★ 10. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Power supply voltage Input voltage Output voltage Symbol Conditions Rating –0.3 to +7.0 V VLOAD VDD – 40 to VDD + 0.3 V AVDD –0.3 to VDD + 0.3 V AVREF –0.3 to VDD + 0.3 V AVSS –0.3 to +0.3 V VDD VI1 P00-P04, P10-P17 (except when used as analog input pins), P20-P27, P30-P37, X1, X2, XT2, RESET –0.3 to VDD + 0.3 V VI2 P70-P74 N-ch open drain –0.3 to +16Note 1 V VI3 P110-P117, P120-P127 P-ch open drain VDD – 40 to VDD + 0.3 V VO1 P01-P03, P10-P17, P20-P27, P30-P37 –0.3 to VDD + 0.3 V +16Note 1 V –0.3 to VO2 P70-P74 VO3 P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 Analog input voltage VAN ANI0-ANI7 Output current, high IOH Output current, low IOL VDD – 40 to VDD + 0.3 V AVSS – 0.3 to AVREF + 0.3 V P01-P03, P10-P17, P20-P27, P30-P37 per pin –10 mA P01-P03, P10-P17, P20-P27, P30-P37 total –30 mA P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 per pin –30 mA P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 total –120 mA 30 mA Analog input pin P01-P03, P10-P17, P20-P27, P30-P37, Peak value P70-P74 per pin rms value 15Note 2 mA P70-P74 total Peak value 100 mA rms value 60Note 2 mA Peak value 50 mA rms value 20Note 2 mA TA = –40 to +60 °C 800 mW TA = +85 °C 600 mW P01-P03, P10-P17, P20-P27, P30-P37 total Total power Unit PTNote 3 dissipation Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. Notes 1. For pins to which pull-up resistors are connected by the mask option, the rating is –0.3 to VDD + 0.3. 2. To obtain the rms value, calculate [rms value] = [peak value] ¥ √duty. 34 mPD78042F, 78043F, 78044F, 78045F Notes 3. Permissible total power loss differs depending on the temperature (see the following figure). Total power loss PT [mW] 800 600 400 200 –40 0 +40 +80 Temperature [°C] How to calculate total power loss The following three power consumption are available for the mPD78042F. The sum of the three power consumption should be less than the total power loss PT (80 % or less of ratings is recommended). 1 CPU power consumption: calculate VDD (MAX.) ¥ IDD1 (MAX.). 2 Output pin power consumption: Normal output and display output are available. Power consumption when maximum current flows into each output pin. 3 Pull-down resistor power consumption: Power consumption by pull-down resistor connected to display output pin by the mask option. 35 mPD78042F, 78043F, 78044F, 78045F The following total power consumption calculation example assumes the case where the characters shown in the figure on the next page are displayed. Example: The operating conditions are as follows: VDD = 5 V ±10 %, operating at 5.0 MHz Supply current (I DD) = 21.6 mA Display outputs: 11 grids ¥ 10 segments (cut width is 1/16) It is assumed that up to 15 mA flows to each grid pin, and that up to 3 mA flows to each segment pin. It is also assumed that all display outputs are turned off at key scan timings. VO3 = VDD – 2 V (Voltage drop of 2 V is assumed.) Display output voltage: grid segment VO3 = VDD – 0.4 V (Voltage drop of 0.4 V is assumed.) Voltage applied to fluorescent indication panel (V LOAD) = –30 V Mask-option pull-down resistor = 25 kΩ The total power loss is calculated by determining power consumption 1 to 3 under the above conditions. 1 Power consumption of CPU: 5.5 V ¥ 21.6 mA = 118.8 mW 2 Power consumption at output pins: total current for all grids Grid: (VDD – VO3) ¥ number of grids + 1 ¥ digit width (1 – cut width) = 15 mA ¥ 11 grids 2V ¥ ¥ (1 – 1/16) = 25.8 mW 11 grids + 1 total segment current for all dots to be lit Segment: (V DD – VO3 ) ¥ number of grids + 1 = 3 mA ¥ 31 dots 0.4 V ¥ 3 = 3.1 mW 11 grids + 1 Power consumption at pull-down resistors: Grid: Segment: (VO3 – VLOAD) 2 number of grids ¥ ¥ digit width = pull-down resistance number of grids + 1 (5.5 V – 2 V – (–30 V))2 11 grids ¥ ¥ (1 – 1/16) = 38.6 mW 25 kΩ 11 grids + 1 (VO3 – VLOAD) 2 ¥ number of dots to be lit = pull-down resistance number of grids + 1 31 dots (5.5 V – 0.4 V – (–30 V))2 ¥ = 127.3 mW 25 kΩ 11 grids + 1 Total power consumption = 1 + 2 + 3 = 118.8 + 25.8 + 3.1 + 38.6 + 127.3 = 313.6 mW In this example, the total power consumption does not exceed the rated value for the permissible total power loss shown in the graph on the previous page. Therefore, the calculation result in this example (313.6 mW) satisfies the requirement. If the total power consumption exceed the rated value for the permissible total power loss, the power consumption must be reduced, by reducing the number of built-in pull-down resistors. 36 a b c d e f g h i j S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 0 AM i PM j i 1 SUN 2 MON 3 4 5 6 7 SAT 8 9 g b a f FRI e d c 10 h THU j WED T0 j TUE T1 Bit 6 0 0 0 0 0 0 0 1 0 0 0 T2 Bit 7 0 0 0 0 0 0 0 0 1 0 1 T3 Bit 0 0 0 0 0 1 0 0 0 0 0 0 T4 Bit 1 1 1 1 0 0 1 1 0 0 0 0 T5 Bit 2 1 0 0 0 0 1 1 0 0 0 0 T6 Bit 3 1 1 0 0 0 0 0 0 0 0 0 T7 Bit 4 0 1 1 0 0 1 0 0 0 0 0 T8 Bit 5 1 0 1 1 0 1 1 0 1 1 0 T9 Bit 6 0 0 1 1 0 0 1 0 1 1 0 T10 Bit 7 0 0 1 0 0 1 0 0 0 0 0 FA7AH FA79H FA78H FA77H FA76H FA75H FA74H FA73H FA72H FA71H FA70H FA6AH FA69H FA68H FA67H FA66H FA65H FA64H FA63H FA62H FA61H FA60H Display data memory 10-Segment/11-Digit Display Example FA6 × H FA7 × H mPD78042F, 78043F, 78044F, 78045F 37 mPD78042F, 78043F, 78044F, 78045F MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Resonator Ceramic resonator Recommended circuit VSS X1 X2 C1 Crystal VSS X1 C2 X2 C1 External clock X1 C2 X2 µ PD74HCU04 Parameter Conditions Oscillation frequency (fX)Note 1 MIN. TYP. 1 Oscillation settling timeNote 2 Oscillation frequency (fX)Note 1 Oscillation settling timeNote 2 1 VDD = 4.5 to 5.5 V X1 input frequency (fX)Note 1 X1 input high, low-level width (tXH, tXL) 4.19 MAX. Unit 5 MHz 4 ms 5 MHz 10 ms 30 1 5 MHz 100 500 ns Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Characteristics. 2. Time required until oscillation becomes stable after V DD is applied or the STOP mode is disabled. Cautions 1. If the main system clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance: • Make wiring as short as possible. • Do not cross other signal lines. • Do not get close to lines with fluctuating large current. • Make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as VSS. • Do not connect the oscillator to a ground pattern that conducts a large current. • Do not take out signal from the oscillator. 2. When switching to the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to set the program to provide enough time for the oscillation to stabilize. 38 mPD78042F, 78043F, 78044F, 78045F SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Resonator Crystal Recommended circuit XT1 XT2 VSS Parameter Conditions Oscillation frequency (fXT)Note 1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s R C3 C4 Oscillation settling timeNote 2 VDD = 4.5 to 5.5 V 10 External XT1 XT2 XT1 input frequency (fXT)Note 1 32 100 kHz XT1 input high, lowlevel width (tXTH , tXTL) 5 15 ms Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Characteristics. 2. Time required until oscillation becomes stable after V DD reaching MIN. of oscillation voltage range. Cautions 1. If the subsystem clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance: • Make wiring as short as possible. • Do not cross other signal lines. • Do not get close to lines with fluctuating large current. • Make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as VSS. • Do not connect the oscillator to a ground pattern that conducts a large current. • Do not take out signal from the oscillator. 2. The subsystem clock oscillator is more likely to have malfunctions due to noise than the main system clock oscillator because gain for the subsystem clock oscillator is made lower to reduce current consumption. When using the subsystem clock, be careful about how to connect wires. 39 mPD78042F, 78043F, 78044F, 78045F RECOMMENDED OSCILLATOR CONSTANT MAIN SYSTEM CLOCK: CERAMIC RESONATOR (TA = –40 to +85 °C) Manufacturer Murata Mfg. Co., Ltd. Product name Frequency (MHz) Recommended circuit constant Oscillator voltage range C1 (pF) C2 (pF) MIN. (V) MAX. (V) Remark Rd = 4.7 kΩNote CSB1000J 1.00 100 100 2.7 5.5 CSA2.00MG040 2.00 100 100 2.7 5.5 CST2.00MG040 2.00 — — 2.7 5.5 CSA4.00MG 4.00 30 30 2.7 5.5 CST4.00MGW 4.00 — — 2.7 5.5 CSA5.00MG 5.00 30 30 2.7 5.5 CST5.00MGW 5.00 — — 2.7 5.5 Built-in capacitor CCR1000K2 1.00 150 150 2.7 5.5 Surface-mount type CCR2.0MC3 2.00 — — 2.7 5.5 Built-in capacitor, surface-mount type CCR4.0MC3 4.00 — — 2.7 5.5 Built-in capacitor, surface-mount type FCR4.0MC5 4.00 — — 2.7 5.5 Built-in capacitor CCR5.0MC3 5.00 — — 2.7 5.5 Built-in capacitor, surface-mount type FCR5.0MC5 5.00 — — 2.7 5.5 Built-in capacitor Matsushita Electronics EFOEC2004A4 2.00 33 33 2.7 5.5 Built-in capacitor Components Co., Ltd. EFOS2004B5 2.00 33 33 2.7 5.5 Built-in capacitor, surface-mount type EFOEC3584A4 3.58 33 33 2.7 5.5 Built-in capacitor EFOS3584B5 3.58 33 33 2.7 5.5 Built-in capacitor, surface-mount type EFOEC4004A4 4.00 33 33 2.7 5.5 Built-in capacitor EFOS4004B5 4.00 33 33 2.7 5.5 Built-in capacitor, surface-mount type EFOEC5004A4 5.00 33 33 2.7 5.5 Built-in capacitor EFOS5004B5 5.00 33 33 2.7 5.5 Built-in capacitor, surface-mount type TDK Corp. Built-in capacitor Built-in capacitor Note When the CSB1000J (1.00 MHz) manufactured by Murata Mfg. is used, a limiting resistor (4.7 kΩ) is necessary (see the figure in the next page). When one of other resonators is used, no limiting resistor is required. Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator that being used. 40 mPD78042F, 78043F, 78044F, 78045F Recommended sample circuit for the main system clock when the CSB1000J manufactured by Murata Mfg. is used VSS X1 X2 CSB1000J C1 Rd C2 VDD 41 mPD78042F, 78043F, 78044F, 78045F CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz Unmeasured pins returned to 0 V 15 pF Output capacitance COUT f = 1 MHz Unmeasured pins returned to 0 V 35 pF Input/output C IO f = 1 MHz Unmeasured pins returned to 0 V P01-P03, P10-P17, P20-P27, P30-P37 15 pF P70-P74 20 pF P110-P117, P120-P127 35 pF capacitance Remark Unless otherwise specified, the characteristics of the shared pin are the same as the characteristics of the port pin. POWER SUPPLY VOLTAGE (TA = –40 to +85 °C) Parameter MAX. Unit 2.7Note 2 5.5 V Display controller/driver 4.5 5.5 V PWM mode of 16-bit timer/event counter (TM0) 4.5 5.5 V A/D converter 4.0 5.5 V Other hardware 2.7 5.5 V CPUNote 1 Conditions MIN. TYP. Notes 1. Except for system clock oscillator, display controller/driver, and PWM. 2. Operating power supply voltage differs depending on the cycle time. See the AC Characteristics. 42 mPD78042F, 78043F, 78044F, 78045F DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter High-level input voltage Symbol TYP. MAX. Unit VIH1 P21, P23 0.7VDD VDD V VIH2 P00-P03, P20, P22, P24-P27, P33, P34, RESET 0.8VDD VDD V VIH3 P70-P74 0.7VDD 15Note 1 V VIH4 X1, X2Note 2 VDD – 0.5 VDD V VIH5 XT1/P04, XT2Note 2 VDD – 0.5 VDD V VDD – 0.3 VDD V 0.65V DD VDD V 0.7VDD VDD V 0.7VDD VDD V VDD – 0.5 VDD V VIH6 VIH7 Low-level input voltage MIN. Conditions P10-P17, P30-P32, P35-P37 P110-P117, P120-P127 N-ch open drain VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VIL1 P21, P23 0 0.3V DD V VIL2 P00-P03, P20, P22, P24-P27, P33, P34, RESET 0 0.2V DD V VIL3 P70-P74 0 0.3V DD V 0 0.2V DD V 0 0.4 V 0 0.4 V 0 0.3 V 0 0.3V DD V VDD – 35 0.3V DD V VIL4 X1, X2Note 2 VIL5 XT1/P04, XT2Note 2 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VIL6 P10-P17, P30-P32, P35-P37 VIL7 P110-P117, P120-P127 High-level output voltage VOH P01-P03, P10-P17, P20-P27, P30-P37, P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 VDD = 4.5 to 5.5 V IOH = –1 mA VDD – 1.0 V IOH = –100 mA VDD – 0.5 V Low-level output voltage VOL1 P30-P37, P70-P74 VDD = 4.5 to 5.5 V, IOL = 15 mA P01-P03, P10-P17, P20-P27 VDD = 4.5 to 5.5 V, IOL = 1.6 mA SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, With open-drain and pull-up (R = 1 kW) VOL2 VOL3 P01-P03, P10-P17, P20-P27, P30-P37, P70-P74 IOL = 400 mA 0.4 2.0 V 0.4 V 0.2V DD V 0.5 V Notes 1. Pins to which pull-up resistors are connected by the mask option become VDD. 2. If the X1 pin is used for high-level voltage input, the X2 pin is used for low-level voltage input, or vice versa. This is also true for the XT1/P04 pin and XT2 pin. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. 43 mPD78042F, 78043F, 78044F, 78045F DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter High-level input leakage current Low-level input leakage current Symbol ILIH1 MAX. Unit P00-P03, P10-P17, P20-P27, P30-P37, RESET 3 mA X1, X2, XT1/P04, XT2 20 mA 20 mA 3Note 1 mA 3Note 2 mA Conditions VIN = VDD ILIH2 MIN. TYP. ILIH3 VIN = 15 V P70-P74 ILIH4 P110-P117, P120-P127, VIN = VDD VDD = 4.5 to 5.5 V VIN = 0 V P00-P03, P10-P17, P20-P27, P30-P37, RESET –3 mA X1, X2, XT1/P04, XT2 –20 mA –3Note 3 mA –10 mA ILIL1 ILIL2 ILIL3 P70-P74 ILIL4 P110-P117, P120-P127 High-level output leakage current Note 4 ILOH1 VOUT = VDD P01-P03, P10-P17, P20-P27, P30-P37, P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 3 mA ILOH2 VOUT = 15 V P70-74, N-ch open drain 20 mA Low-level output leakage current Note 4 ILOL1 VOUT = 0 V P01-P03, P10-P17, P20-P27, P30-P37, P70-P74 –3 mA ILOL2 VOUT = VLOAD = VDD – 35 V P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 –10 mA Display output current IOD VDD = 4.5 to 5.5 V, VO3 = V DD – 2 V –15 –25 Mask option R1 VIN = 0 V, P70-P74 20 40 90 kΩ R2 VIN = 0 V, P01-P03, P10-P17, P20-P27, P30-P37 VDD = 4.5 to 5.5 V 15 40 90 kΩ 500 kΩ P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 VO3 – V LOAD = 35 V 25 65 135 kΩ VO3 – V SS = 5 V 15 40 90 kΩ 40 80 150 kΩ mA pull-up resistor Software pullup resistor Mask option pull-down resistor R3 R4 P30-P37, VIN = VDD 20 Notes 1. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 150 mA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out port 11 or 12 (P11 or P12) or port mode register 11 or 12 (PM11 or PM12). Outside the 1.5 clocks after a read instruction, the current is 3 mA (MAX.). 2. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 90 mA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out P11, P12, PM11, or PM12. Outside the 1.5 clocks after a read instruction, the current is 3 m A (MAX.). 3. When P70 to P74 do not contain the pull-down resistors (according to the specification of the mask option), a low-level input leakage current of –150 mA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out port 7 (P7) or port mode register 7 (PM7). Outside the 1.5 clocks after a read out instruction, the current is –3 m A (MAX.). 4. Current which flows in the built-in pull-up or pull-down resistor is not included. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. 44 mPD78042F, 78043F, 78044F, 78045F DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter Symbol Power supply current Note 1 IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Conditions TYP. MAX. Unit %Note 2 MIN. 7.2 21.6 mA 5.0 MHz crystal oscillation Operating mode VDD = 5.0 V ±10 VDD = 3.0 V ±10 %Note 3 0.9 2.7 mA 5.0 MHz crystal oscillation HALT mode VDD = 5.0 V ±10 % 1.3 3.9 mA VDD = 3.0 V ±10 % 550 1650 mA 32.768 kHz crystal oscillation Operating modeNote 4 VDD = 5.0 V ±10 % 60 120 mA VDD = 3.0 V ±10 % 35 70 mA VDD = 5.0 V ±10 % 25 50 mA VDD = 3.0 V ±10 % 5 10 mA XT1 = 0 V VDD = 5.0 V ±10 % 1 20 mA STOP mode Feedback resistor connected VDD = 3.0 V ±10 % 0.5 10 mA VDD = 5.0 V ±10 % 0.1 20 mA VDD = 3.0 V ±10 % 0.05 10 mA 32.768 kHz crystal oscillation HALT modeNote 4 XT1 = 0 V STOP mode Feedback resistor not connected Notes 1. This current excludes the AV REF current, port current, and current which flows in the built-in pull-down resistor (mask option). 2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H) 3. When operating at low-speed mode (when the PCC is set to 04H) 4. When the main system clock is stopped 45 mPD78042F, 78043F, 78044F, 78045F AC CHARACTERISTICS (1) Basic operation (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter Symbol Cycle time (minimum instruction execution time) TCY TI1, 2 input frequency fTI MIN. Conditions Operated with main system clock VDD = 4.5 to 5.5 V TYP. MAX. Unit 32 ms 32 ms 125 ms 0 2 MHz 0 138 kHz 0.4 0.8 40Note 1 Operated with subsystem clock tTIH TI1, 2 input high, low-level tTIL width VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V Interrupt input high, low-level width tINTH INTP0 tINTL INTP1-INTP3 RESET lowlevel width tRSL 122 250 ns 3.6 ms 8/fsamNote 2 ms 10 ms 10 ms Notes 1. Value when external clock input is used as subsystem clock. When crystal is used, the value becomes 114 ms. 2. Selection of fsam = fX/2N+1, fX/64, fX/128 is available (N = 0 to 4) by bits 0 and 1 (SCS0, SCS1) of sampling clock select register (SCS). TCY vs. VDD (with main system clock operated) 60 Cycle time TCY [ µ s] 30 Operation guarantee range 10 2.0 1.0 0.5 0.4 0 1 2 3 4 5 Power supply voltage VDD [V] 46 6 mPD78042F, 78043F, 78044F, 78045F (2) Serial interface (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) (a) Serial interface channel 0 (i) Three-wire serial I/O mode (SCK0: Internal clock output) Parameter SCK0 cycle time Symbol TYP. MAX. Unit ns 3200 ns tKCY1/2 – 50 ns tKL1 tKCY1 /2 – 150 ns SI0 setup time to SCK0↑ tSIK1 100 ns SI0 hold time from SCK0↑ tKSI1 400 ns SCK0ØÆ SO0 output delay time tKH1 tKSO1 VDD = 4.5 to 5.5 V MIN. 800 SCK0 high, low-level width tKCY1 Conditions VDD = 4.5 to 5.5 V C = 100 pFNote VDD = 4.5 to 5.5 V 300 ns 1000 ns MAX. Unit Note C is a load capacitance of the SCK0 or SO0 output line. (ii) Three-wire serial I/O mode (SCK0: External clock input) Parameter SCK0 cycle time SCK0 high, low-level width Symbol tKCY2 tKH2 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKL2 SI0 setup time to SCK0↑ tSIK2 SI0 hold time from SCK0↑ tKSI2 SCK0ØÆ SO0 output delay time tKSO2 SCK0 rise time and fall time VDD = 4.5 to 5.5 V C = 100 pFNote tR2 VDD = 4.5 to 5.5 V MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns 100 ns 400 ns 300 ns 1000 ns 160 ns tF2 Note C is a load capacitance of the SO0 output line. 47 mPD78042F, 78043F, 78044F, 78045F (iii) SBI mode (SCK0: Internal clock output) Parameter SCK0 cycle time SCK0 high, low-level width Symbol tKCY3 tKH3 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKL3 SB0, SB1 setup time to SCK0↑ tSIK3 VDD = 4.5 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3200 ns tKCY3/2 – 50 ns tKCY3 /2 – 150 ns 100 ns 300 ns tKCY3 /2 ns SB0, SB1 hold time from SCK0↑ tKSI3 SCK0ØÆSB0, SB1 output delay time tKSO3 SCK0↑ÆSB0, SB1Ø tKSB tKCY3 ns SB0, SB1ØÆ SCK0Ø tSBK tKCY3 ns SB0, SB1 high-level width t SBH tKCY3 ns SB0, SB1 low-level width tSBL tKCY3 ns R = 1 kW, C = 100 pFNote VDD = 4.5 to 5.5 V 0 250 ns 0 1000 ns Note R is a load resistance of the SCK0, SB0, or SB1 output line, and C is its load capacitance. (iv) SBI mode (SCK0: External clock input) Parameter SCK0 cycle time SCK0 high, low-level width Symbol tKCY4 tKH4 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKL4 SB0, SB1 setup time to SCK0↑ tSIK4 VDD = 4.5 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 300 ns tKCY4 /2 ns SB0, SB1 hold time from SCK0↑ tKSI4 SCK0ØÆSB0, SB1 output delay time tKSO4 SCK0↑ÆSB0, SB1Ø tKSB tKCY4 ns SB0, SB1ØÆSCK0Ø tSBK tKCY4 ns SB0, SB1 high-level witdh tSBH tKCY4 ns SB0, SB1 low-level width tSBL tKCY4 ns SCK0 rise time and fall time tR4 tF4 R = 1 kW, C = 100 pFNote VDD = 4.5 to 5.5 V 0 300 ns 0 1000 ns Note R is a load resistance of the SB0 or SB1 output line, and C is its load capacitance. 48 160 ns mPD78042F, 78043F, 78044F, 78045F (v) Two-wire serial I/O mode (SCK0: Internal clock output) Parameter SCK0 cycle time Symbol tKCY5 Conditions R = 1 kW, C = 100 pFNote VDD = 4.5 to 5.5 V MIN. TYP. MAX. Unit 1600 ns 3800 ns SCK0 high-level width tKH5 tKCY5/2 – 160 ns SCK0 low-level width tKL5 tKCY5/2 – 50 ns SB0, SB1 setup time to SCK0↑ tSIK5 300 ns SB0, SB1 hold time from tKSI5 600 ns SCK0↑ SCK0ØÆ SB0, SB1 output delay time tKSO5 VDD = 4.5 to 5.5 V 0 250 ns 0 1000 ns Note R is a load resistance of the SCK0, SB0, or SB1 output line, and C is its load capacitance. (vi) Two-wire serial I/O mode (SCK0: External clock input) Parameter SCK0 cycle time Symbol tKCY6 Conditions VDD = 4.5 to 5.5 V MIN. TYP. MAX. Unit 1600 ns 3800 ns SCK0 high-level width tKH6 650 ns SCK0 low-level width tKL6 800 ns SB0, SB1 setup time to SCK0↑ tSIK6 100 ns SB0, SB1 hold time from SCK0↑ tKSI6 tKCY6 /2 ns SCK0ØÆ SB0, SB1 output delay time tKSO6 SCK0 rise time and fall time tR6 tF6 R = 1 kW, C = 100 pFNote VDD = 4.5 to 5.5 V 0 300 ns 0 1000 ns 160 ns Note R is a load resistance of the SB0 or SB1 output line, and C is its load capacitance. 49 mPD78042F, 78043F, 78044F, 78045F (b) Serial interface channel 1 (i) Three-wire serial I/O mode (SCK1: Internal clock output) Parameter SCK1 cycle time Symbol TYP. MAX. Unit ns 3200 ns tKCY7/2 – 50 ns tKL7 tKCY7 /2 – 150 ns SI1 setup time to SCK1↑ tSIK7 100 ns SI1 hold time from SCK1↑ tKSI7 400 ns SCK1ØÆ SO1 output delay time tKH7 tKSO7 VDD = 4.5 to 5.5 V MIN. 800 SCK1 high, low-level width tKCY7 Conditions VDD = 4.5 to 5.5 V C = 100 pFNote VDD = 4.5 to 5.5 V 300 ns 1000 ns MAX. Unit Note C is a load capacitance of the SCK1 or SO1 output line. (ii) Three-wire serial I/O mode (SCK1: External clock input) Parameter SCK1 cycle time SCK1 high, low-level width Symbol tKCY8 tKH8 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKL8 SI1 setup time to SCK1↑ tSIK8 SI1 hold time from SCK1↑ tKSI8 SCK1ØÆ SO1 output delay time tKSO8 SCK1 rise time and fall time tR8 tF8 VDD = 4.5 to 5.5 V C = 100 pFNote Note C is a load capacitance of the SO1 output line. 50 VDD = 4.5 to 5.5 V MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns 100 ns 400 ns 300 ns 1000 ns 160 ns mPD78042F, 78043F, 78044F, 78045F (iii) 3-wire serial I/O mode with automatic transmission/reception function (SCK1: internal clock output) Parameter SCK1 cycle time Symbol TYP. MAX. Unit ns 3200 ns tKCY9/2 – 50 ns tKL9 tKCY9 /2 – 150 ns SI1 setup time to SCK1↑ tSIK9 100 ns SI1 hold time from SCK1↑ tKSI9 400 ns SCK1ØÆSO1 output delay time tKSO9 tKH9 VDD = 4.5 to 5.5 V MIN. 800 SCK1 high, low-level width tKCY9 Conditions VDD = 4.5 to 5.5 V C = 100 pFNote VDD = 4.5 to 5.5 V 300 ns 1000 ns SCK1↑ÆSTB• tSBD tKCY9 /2 – 100 tKCY9/2 + 100 ns Strobe signal high level width tSBW tKCY9 – 30 tKCY9 + 30 ns Busy signal setup time (to busy tBYS 100 ns 100 ns signal detection timing) Busy signal hold time (to busy signal detection timing) tBYH Busy inactive Æ SCK1Ø tSPS 2tKCY9 ns Note C is a load capacitance of the SCK1 or SO1 output line. (iv) 3-wire serial I/O mode with automatic transmission/reception function (SCK1: external clock input) Parameter SCK1 cycle time Symbol TYP. MAX. Unit ns 3200 ns 400 ns tKL10 1600 ns SI1 setup time to SCK1↑ tSIK10 100 ns SI1 hold time from SCK1↑ tKSI10 400 ns SCK1ØÆ SO1 output delay time tKSO10 SCK1 rise time and fall time tR10 tF10 tKH10 VDD = 4.5 to 5.5 V MIN. 800 SCK1 high, low-level width tKCY10 Conditions VDD = 4.5 to 5.5 V C = 100 pFNote VDD = 4.5 to 5.5 V 300 ns 1000 ns 160 ns Note C is a load capacitance of the SO1 output line. 51 mPD78042F, 78043F, 78044F, 78045F AC timing test points (except X1, XT1 input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock timing 1/fX tXH tXL VDD – 0.5 V X1 input 0.4 V 1/fXT tXTH tXTL VDD – 0.5 V XT1 input 0.4 V TI timing 1/fTI tTIL TI1, TI2 52 tTIH mPD78042F, 78043F, 78044F, 78045F Serial transfer timing 3-wire serial I/O mode: tKCY1, 2, 7, 8 tKL1, 2, 7, 8 tKH1, 2, 7, 8 tR2, 8 tF2, 8 SCK0, SCK1 tSIK1, 2, 7, 8 tKSI1, 2, 7, 8 Input data SI0, SI1 tKSO1, 2, 7, 8 SO0, SO1 Output data SBI mode (bus release signal transfer): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBL tSBH tSIK3, 4 tSBK tKSI3, 4 SB0, SB1 tKSO3, 4 SBI mode (command signal transfer): tKCY3, 4 tKL3, 4 tKH3, 4 SCK0 tKSB tSIK3, 4 tSBK tKSI3, 4 SB0, SB1 tKSO3, 4 53 mPD78042F, 78043F, 78044F, 78045F 2-wire serial I/O mode: tKCY5, 6 tKH5, 6 tKL5, 6 tR6 tF6 SCK0 tSIK5, 6 tKSO5, 6 tKSI5, 6 SB0, SB1 3-wire serial I/O mode with automatic transmission/reception function: SO1 SI1 D2 D2 D1 D1 D0 D7 D0 D7 tKSI9, 10 tKH9, 10 tSIK9, 10 tKSO9, 10 tF10 SCK1 tR10 tKL9, 10 tKCY9, 10 tSBD tSBW STB 3-wire serial I/O mode with automatic transmission/reception function (busy processing): SCK1 7 8 9Note 10Note tBYS 10 + nNote tBYH 1 tSPS BUSY (Active high) Note SCK does not become low actually at this point, but is indicated so to conform to the timing specification. 54 mPD78042F, 78043F, 78044F, 78045F A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions Resolution MIN. TYP. MAX. Unit 8 8 8 bit 0.8 % 19.1 200 ms Total errorNote 1 Conversion timeNote 2 tCONV 1 MHz - f X - 5.0 MHz Sampling timeNote 3 tSAMP 2.86 30 ms Analog signal input voltage VIAN AVSS AVREF V Reference voltage AVREF 4.0 AVDD V AVREF resistor RAVREF 4 AVDD current AIDD kΩ 14 200 400 mA Notes 1. Quantization error (±1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale value. 2. Set the A/D conversion time to 19.1 ms or more. 3. Sampling time depends on the conversion time. 55 mPD78042F, 78043F, 78044F, 78045F DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85 °C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal set time tSREL Oscillation stabilization wait time tWAIT Conditions MIN. TYP. 2.0 VDDDR = 2.0 V Subsystem clock stopped Feedback resistor not connected 0.1 MAX. Unit 5.5 V 10 mA ms 0 Release by RESET 217/fX ms Release by interrupt Note ms Note Selection of 212/fX, 214/fX to 217/fX is available by bits 0 to 2 (OSTS0 to OSTS2) of oscillation settling time select register (OSTS). Data retention timing (STOP mode release by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data retention timing (standby release signal: STOP mode release by interrupt signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 56 mPD78042F, 78043F, 78044F, 78045F Interrupt input timing tINTH tINTL INTP0-INTP2 tINTL INTP3 RESET input timing tRSL RESET 57 mPD78042F, 78043F, 78044F, 78045F 11. CHARACTERISTIC CURVE (REFERENCE VALUE) IDD vs. VDD (Main system clock: 5.0 MHz) (TA = 25 °C) 10.0 PCC = 00H 5.0 PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 and XT1 oscillate) 1.0 0.5 Supply current IDD [mA] ★ fX = 5.0 MHz fXT = 32.768 kHz 0.1 PCC = B0H 0.05 HALT (X1 stops but XT1 oscillates) STOP (X1 stops but XT1 oscillates) 0.01 0.005 0.001 0 2 3 4 5 Supply voltage VDD [V] 58 6 7 8 mPD78042F, 78043F, 78044F, 78045F IDD vs. fX (VDD = 3 V, TA = 25 °C) 4 PCC = 00H Supply current IDD [mA] 3 2 PCC = 01H PCC = 02H 1 0 PCC = 03H PCC = 04H HALT (X1 oscillates) 0 1 2 3 4 5 6 Clock oscillation frequency fX [MHz] IDD vs. fX (VDD = 5 V, TA = 25 °C) 7 6 PCC = 00H Supply current IDD [mA] 5 4 PCC = 01H 3 PCC = 02H 2 PCC = 03H PCC = 04H HALT (X1 oscillates) 1 0 0 1 2 3 4 5 6 Clock oscillation frequency fX [MHz] 59 mPD78042F, 78043F, 78044F, 78045F VOL vs. IOL (Port 1) (TA = 25 °C) VDD = 6 V 30 VDD = 5 V Low-level output currnt IOL [mA] VDD = 4 V VDD = 3 V 20 10 0 0 0.5 1.0 1.5 Low-level output voltage VOL [V] VOL vs. IOL (Ports 0, 2, and 3) (TA = 25 °C) VDD = 6 V VDD = 5 V 30 Low-level output current IOL [mA] VDD = 4 V VDD = 3 V 20 10 0 0 0.5 1.0 Low-level output voltage VOL [V] 60 1.5 mPD78042F, 78043F, 78044F, 78045F VOL vs. IOL (Port 7) (TA = 25 °C) VDD = 6 V Low-level output current IOL [mA] 30 VDD = 5 V VDD = 4 V VDD = 3 V 20 10 0 0 0.5 1.0 1.5 Low-level output voltage VOL [V] 61 mPD78042F, 78043F, 78044F, 78045F VDD – VOH vs. IOH (Port 0 - Port 3) High-level output current IOH [mA] (TA = 25 °C) VDD = 5 V VDD = 6 V VDD = 4 V –10 VDD = 3 V –5 0 0 0.5 1.0 1.5 High-level output voltage VDD – VOH [V] VDD – VOH vs. IOH (Port 8 - Port 12) (TA = 25 °C) VDD = 6 V VDD = 5 V High-level output current IOH [mA] –30 VDD = 4 V VDD = 3 V –20 –10 0 0 1.0 2.0 High-level output voltage VDD – VOH [V] 62 3.0 mPD78042F, 78043F, 78044F, 78045F 12. PACKAGE DRAWING ★ 80 PIN PLASTIC QFP (14 20) A B 41 40 64 65 detail of lead end S C D Q R 25 24 80 1 F G J H I M K P M N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 23.6±0.4 0.929±0.016 B 20.0±0.2 0.795 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.6±0.4 0.693±0.016 F 1.0 0.039 G 0.8 0.031 H 0.35±0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1±0.1 0.004±0.004 R S 5°±5° 5°±5° 3.0 MAX. 0.119 MAX. P80GF-80-3B9-3 Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product. 63 mPD78042F, 78043F, 78044F, 78045F ★ 13. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the m PD78042F, m PD78043F, m PD78044F, or mPD78045F. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 13-1 Soldering Conditions for Surface-Mount Devices ¥¥¥ ¥¥¥-3B9: 80-pin plastic QFP (14 ¥ 20 mm) mPD78042FGF-¥¥¥ ¥¥¥-3B9: 80-pin plastic QFP (14 ¥ 20 mm) mPD78043FGF-¥¥¥ ¥¥¥ ¥¥¥ ¥¥¥-3B9: 80-pin plastic QFP (14 ¥ 20 mm) mPD78044FGF-¥¥¥ ¥¥¥-3B9: 80-pin plastic QFP (14 ¥ 20 mm) ¥¥¥ mPD78045FGF-¥¥¥ Soldering process Soldering conditions Recommended conditions Infrared ray reflow Peak package's surface temperature: 235 °C Reflow time: 30 seconds or less (210 °C or more) Maximum allowable number of reflow processes: 3 IR35-00-3 VPS Peak package's surface temperature: 215 °C Reflow time: 40 seconds or less (200 °C or more) Maximum allowable number of reflow processes: 3 VP15-00-3 Wave soldering Solder temperature: 260 °C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature : 120 °C max. (measured on the package surface) WS60-00-1 Partial heating method Terminal temperature: 300 °C or less Heat time: 3 seconds or less (for one side of a device) — Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). 64 mPD78042F, 78043F, 78044F, 78045F APPENDIX A DEVELOPMENT TOOLS The following tools are available for development of systems using the mPD78042F, mPD78043F, m PD78044F, or mPD78045F. Language processing software RA78K/0Notes 1, 2, 3, 4 Assembler package common to 78K/0 series CC78K/0Notes 1, 2, 3, 4 C compiler package common to 78K/0 series DF78044Notes 1, 2, 3, 4 Device file for mPD78044A subseries CC78K/0-LNotes 1, 2, 3, 4 C compiler library source file common to 78K/0 series PROM writing tools PG-1500 PROM programmer PA-78P048GF PA-78P048KL-S Programmer adapter connected to PG-1500 PG-1500 controllerNotes 1, 2 Control program for PG-1500 Debugging tools IE-78000-R In-circuit emulator common to 78K/0 series IE-78000-R-ANote 8 In-circuit emulator common to 78K/0 series (for integrated debugger) IE-78000-R-BK Break board common to 78K/0 series IE-78044-R-EM Emulation board for evaluating mPD78044A subseries EP-78130GF-R Emulation probe common to mPD78134 EV-9200G-80 Socket mounted on target system created for 80-pin plastic QFP SM78K0Notes 5, 6, 7 System simulator common to 78K/0 series ID78K0Notes 4, 5, 6, 7, 8 Integrated debugger for IE-78000-R-A SD78K/0Notes 1, 2 Screen debugger for IE-78000-R DF78044Notes 1, 2, 5, 6, 7 Device file common to mPD78044A subseries ★ ★ Real-time OS RX78K/0Notes 1, 2, 3, 4 Real-time OS for 78K/0 series MX78K0Notes 1, 2, 3, 4 OS for 78K/0 series Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 series 300TM (HP-UXTM) based 4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWSUX/V) based 5. PC-9800 series (MS-DOS + Windows TM) based 6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based ★ 8. Under development 65 mPD78042F, 78043F, 78044F, 78045F Fuzzy inference development support system FE9000Note 1/FE9200Note 3 Fuzzy knowledge data creation tool FT9080Note 1/FT9085 Note 2 Translator FI78K0Notes 1, 2 Fuzzy inference module FD78K0Notes 1, 2 Fuzzy inference debugger Notes 1. PC-9800 series (MS-DOS) based 2. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS) based 3. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools. 2. RA78K/0, CC78K/0, SM78K/0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78044. 66 mPD78042F, 78043F, 78044F, 78045F APPENDIX B RELATED DOCUMENTS • Documents Related to Devices Document No. Document name Japanese English mPD78044F Sub-Series User’s Manual U10908J U10908E mPD78042F, 78043F, 78044F, 78045F Data Sheet U10700J This manual mPD78P048A Data Sheet U10611J U10611E mPD78044A, 78044F Sub-Series Special Function Registers U10701J 78K/0 Series User’s Manual, Instruction IEU-849 78K/0 Series Instruction Summary Sheet U10903J — 78K/0 Series Instruction Set U10904J — — IEU-1372 • Documents Related to Development Tools (User’s Manual) Document No. Document name Japanese RA78K Series Assembler Package Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 EEU-817 EEU-1402 Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Programming Know-How EEA-618 EEA-1208 RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler CC78K/0 Compiler Application Note English CC78K Series Library Source File EEU-777 — PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller PC-9800 Series (MS-DOS) Base EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC DOS) Base EEU-5008 U10540E IE-78000-R EEU-810 U11376E IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-78044-R-EM EEU-833 EEU-1424 EP-78130GF-R EEU-943 EEU-1470 SM78K0 System Simulator Reference EEU-5002 U10181E SM78K Series System Simulator External Parts User Open Interface Specifications U10092J U10092E ID78K0 Integrated Debugger Reference U11151J SD78K/0 Screen Debugger Tutorial EEU-852 PC-9800 Series (MS-DOS) Base Reference EEU-816 SD78K/0 Screen Debugger Tutorial EEU-5024 EEU-1414 IBM PC/AT (PC DOS) Base Reference U11279J EEU-1413 ★ ★ — U10539E — Caution The above documents may be revised without notice. Use the latest versions when you design an application system. 67 mPD78042F, 78043F, 78044F, 78045F • Documents Related to Software to Be Incorporated into the Product (User’s Manual) Document No. Document name Japanese 78K/0 Series Real-Time OS OS for 78K/0 Series MX78K0 English Basic EEU-912 — Installation EEU-911 — Technical EEU-913 — Basic EEU-5010 — Tool for Creating Fuzzy Knowledge Data EEU-829 EEU-1438 78K/0, 78K/II, and 87AD Series Fuzzy Inference Development EEU-829 EEU-1444 78K/0 Series Fuzzy Inference Development Support System, Fuzzy Inference Module EEU-858 EEU-1441 78K/0 Series Fuzzy Inference Development Support System, EEU-921 EEU-1458 Support System, Translator Fuzzy Inference Debugger • Other Documents Document No. Document name Japanese ★ English IC PACKAGE MANUAL C10943X SMD Surface Mount Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device IEI-620 IEI-1209 NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 Guide to Quality Assurance for Semiconductor Device MEI-603 Guide for Products Related to Micro-Computer: Other Companies MEI-604 — MEI-1202 — Caution The above documents may be revised without notice. Use the latest versions when you design an application system. 68 mPD78042F, 78043F, 78044F, 78045F [MEMO] 69 mPD78042F, 78043F, 78044F, 78045F Cautions on CMOS Devices Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first. FIP is a trademark of NEC Corporation. IEBus is trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. 70 mPD78042F, 78043F, 78044F, 78045F Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 3 71 mPD78042F, 78043F, 78044F, 78045F Note that “preliminary” is not indicated in this document, even though the related documents may be preliminary versions. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94. 11 72