DATA SHEET MOS INTEGRATED CIRCUIT µPD78044H, 78045H, 78046H 8-BIT SINGLE-CHIP MICROCOMPUTER The µPD78044H, µ PD78045H, and µPD78046H are µ PD78044H sub-series products in the 78K/0 series. These microcomputers are advanced models of the µPD78044A sub-series, featuring the added N-ch open-drain I/O ports. In addition, the µ PD78P048B (one-time PROM or EPROM model) that can operate in the same voltage range as that of the mask ROM models, and various development tools are provided. The functions of these microcomputers are described in detail in the following User’s Manual. Be sure to read this manual when you design a system using any of these microcomputers. µPD78044H Sub-Series User’s Manual : To be created 78K/0 Series User's Manual, Instruction: IEU-1372 FEATURES • I/O ports: 68 (N-ch open-drain I/O: 13) • High-capacity ROM and RAM Item Data memory Product name Program memory (ROM) Internal high-speed RAM FIP display RAM µPD78044H 32K bytes 1024 bytes 48 bytes µPD78045H 40K bytes µPD78046H 48K bytes • Wide range of instruction execution time: • Serial interface: 1 channel From high-speed (0.4 µs) to ultra low-speed (122 µs) • FIP controller/driver: total display outputs: 34 • Timer: 5 channels • Power supply voltage: VDD = 2.7 to 5.5 V • 8-bit resolution A/D converter: 8 channels APPLICATIONS VCRs, audio systems, etc. ORDERING INFORMATION Part number Package µPD78044HGF-×××-3B9 80-pin plastic QFP (14 × 20 mm) µPD78045HGF-×××-3B9 80-pin plastic QFP (14 × 20 mm) µPD78046HGF-×××-3B9 80-pin plastic QFP (14 × 20 mm) Remark ××× indicates ROM code number. The information in this document is subject to change without notice. Document No. U10865EJ1V0DS00 (1st edition) Date Published August 1996 P Printed in Japan The mark ★ shows major revised points. © 1990 1996 µPD78044H, 78045H, 78046H 78K/0 SERIES PRODUCT DEVELOPMENT The 78K/0 series products were developed as shown below. The sub-series names are indicated in frames. Products being mass-produced Products under development Y sub-series products are compatible with the I2C bus. Used for control 100-pin µ PD78078 µ PD78078Y 100-pin µ PD78070A µ PD78070AY 100-pin µ PD780018 µ PD780018Y 80-pin µ PD78058F µ PD78058FY 80-pin µ PD78054 µ PD78054Y 64-pin µ PD78018F µ PD78018FY 64-pin µ PD78014 µ PD78014Y 64-pin µ PD780001 64-pin µ PD78002 42-/44-pin µ PD78083 A timer has been added to the µ PD78054 to enhance external interface functions. ROM-less versions of the µ PD78078 The serial I/O of the µPD78078 has been enhanced. The functions have been limited. EMI noise-reduced version of the µPD78054 An UART and D/A converter have been added to the µPD78014 to enhance I/O. Low-voltage (1.8 V) versions of the µ PD78014. ROM and RAM variations have been enhanced. An A/D converter and 16-bit timer have been added to the µ PD78002. An A/D converter has been added to the µPD78002. µ PD78002Y Basic sub-series for control These products include an UART and can operate at a low voltage (1.8 V). For FIP driving 78K/0 series 100-pin µ PD780208 80-pin µ PD78044F 80-pin µ PD78044H 64-pin µ PD78024 The I/O and FIP C/D of the µ PD78044F have been enhanced. Total indication output pins: 53 A 6-bit U/D counter has been added to the µ PD78024. Total indication output pins: 34 N-ch open-drain I/O ports have been added to the µPD78044F. Total indication output pins: 34 Basic sub-series for FIP driving. Total indication output pins: 26 For LCD driving 100-pin µ PD780308 100-pin µ PD78064B 100-pin µ PD78064 µ PD780308Y The SIO of the µPD78064 has been enhanced. ROM and RAM have been expanded. EMI noise-reduced version of the µ PD78064 µ PD78064Y Sub-series for LCD driving. These products include an UART. Compatible with IEBusTM 80-pin µ PD78098 An IEBus controller has been added to the µPD78054. For LV 64-pin 2 µ PD78P0914 A PWM output, LV digital code decoder, and Hsync counter are incorporated. µPD78044H, 78045H, 78046H The table below shows the main differences between sub-series. Function Sub-series name µPD78078 ROM capacity 32K-60K For control µPD78070A Timer 8-bit 16-bit Watch WDT 4ch 1ch For FIP driving For LCD driving 1ch 8ch 8-bit D/A 2ch Serial interface I/O 3ch (UART:1ch) 88 pins 1.8 V 61 pins 2.7 V — µPD780018 48K-60K µPD78058F 48K-60K µPD78054 16K-60K µPD78018F 8K-60K µPD78014 8K-32K µPD780001 8K µPD78002 8K-16K — 2ch 2ch 2ch 88 pins 3ch (UART:1ch) 69 pins — External expansion 2ch 53 pins 1.8 V 2.7 V — — 1ch — 1ch 39 pins 1ch (UART:1ch) 33 pins 1.8 V — 2ch 74 pins 2.7 V — 1.8 V — µPD780208 32K-60K µPD78044F 16K-40K µPD78044H 32K-48K 1ch µPD78024 24K-32K 2ch 54 pins µPD780308 48K-60K 3ch (UART:1ch) 57 pins µPD78064B 32K µPD78064 16K-32K µPD78098 32K-60K 2ch 1ch 1ch 1ch 8ch — 53 pins 8ch — For LV µPD78P0914 32K Minimum VDD 2.0 V µPD78083 Compatible with IEBus 1ch 8-bit A/D — 68 pins 2ch 1ch 1ch 1ch 8ch — 2.0 V 2ch (UART:1ch) 2ch 1ch 1ch 1ch 8ch 6ch — — 1ch 8ch 2ch — 3ch (UART:1ch) 69 pins 2.7 V 2ch 54 pins 4.5 V 3 µPD78044H, 78045H, 78046H FUNCTIONAL OUTLINE Product name µPD78044H Item Internal memory ROM 32K bytes Internal high-speed RAM 1024 bytes FIP display RAM 48 bytes General registers µPD78045H 40K bytes µPD78046H 48K bytes 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Variable instruction execution time Instruction cycle For main system clock For subsystem clock 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 5.0 MHz) 122 µs (at 32.768 kHz) • Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Instruction set • Bit (set, reset, test, Boolean algebra) I/O ports (including those multiplexed with FIP pins) FIP controller/driver Total : 68 lines • CMOS input : • CMOS I/O : 19 lines 2 lines • N-ch open-drain : 13 lines • P-ch open-drain I/O : 16 lines • P-ch open-drain output : 18 lines Total : 34 lines • Segments : 9 to 24 lines • Digits : 2 to 16 lines • 8-bit resolution × 8 channels A/D converter • Power supply voltage: AVDD = 4.0 to 5.5 V Serial interface • 3-wire serial I/O mode : 1 channel Timer • 16-bit timer/event counter : 1 channel • 8-bit timer/event counter : 2 channels Timer output • Watch timer : 1 channel • Watchdog timer : 1 channel 3 lines (one for 14-bit PWM output) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz (main system clock: when operating at 5.0 MHz) 32.768 kHz (subsystem clock: when operating at 32.768 kHz) Buzzer output Vectored interrupt 1.2 kHz, 2.4 kHz, 4.9 kHz (main system clock: when operating at 5.0 MHz) Maskable interrupt Internal 8 lines, external 4 lines Non-maskable interrupt Internal 1 line Software interrupt 1 line Text input Internal 1 line Power supply voltage VDD = 2.7 to 5.5 V Package 80-pin plastic QFP (14 × 20 mm) 4 µPD78044H, 78045H, 78046H CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 6 2. BLOCK DIAGRAM ...................................................................................................................... 8 3. PIN FUNCTIONS ......................................................................................................................... 9 3.1 PORT PINS .......................................................................................................................................... 9 3.2 PINS OTHER THAN PORT PINS ....................................................................................................... 11 3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ........................................................... 12 4. MEMORY SPACE ....................................................................................................................... 15 5. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 16 5.1 PORTS ............................................................................................................................................. 16 5.2 CLOCK GENERATOR CIRCUIT .................................................................................................... 17 5.3 TIMER/EVENT COUNTER .............................................................................................................. 17 5.4 CLOCK OUTPUT CONTROL CIRCUIT ......................................................................................... 20 5.5 BUZZER OUTPUT CONTROL CIRCUIT ....................................................................................... 20 5.6 A/D CONVERTER ........................................................................................................................... 21 5.7 SERIAL INTERFACE ...................................................................................................................... 22 5.8 FIP CONTROLLER/DRIVER .......................................................................................................... 23 INTERRUPT FUNCTION AND TEST FUNCTION ..................................................................... 25 6.1 INTERRUPT FUNCTION ................................................................................................................. 25 6.2 TEST FUNCTION ............................................................................................................................ 28 7. STANDBY FUNCTION ................................................................................................................ 29 8. RESET FUNCTION ..................................................................................................................... 29 9. INSTRUCTION SET .................................................................................................................... 30 10. ELECTRICAL SPECIFICATIONS .............................................................................................. 33 11. PACKAGE DRAWING ................................................................................................................ 50 12. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 51 APPENDIX A DEVELOPMENT TOOLS ......................................................................................... 52 APPENDIX B RELATED DOCUMENTS......................................................................................... 54 6. 5 µPD78044H, 78045H, 78046H 1. PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 × 20 mm) P112/FIP20 P113/FIP21 P111/FIP19 P110/FIP18 P107/FIP17 P106/FIP16 VLOAD P105/FIP15 P104/FIP14 P103/FIP13 P102/FIP12 P101/FIP11 P100/FIP10 P97/FIP9 P96/FIP8 P95/FIP7 µPD78044HGF-×××-3B9, µPD78045HGF-×××-3B9, µ PD78046HGF-×××-3B9 59 P121/FIP27 P80/FIP0 7 58 P122/FIP28 VDD 8 57 P123/FIP29 P27 9 56 P124/FIP30 P26 10 55 P125/FIP31 P25 11 54 P126/FIP32 P24 12 53 P127/FIP33 P23 13 52 VDD P22/SCK1 14 51 P70 P21/SO1 15 50 P71 P20/SI1 16 49 P72 RESET 17 48 IC P74 18 47 P00/INTP0/TI0 P73 19 46 P01/INTP1 AVSS 20 45 P02/INTP2 P17/ANI7 21 44 P03/INTP3 P16/ANI6 22 43 P30/TO0 P15/ANI5 23 42 P31/TO1 P14/ANI4 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P32/TO2 P33 6 P34 P120/FIP26 P81/FIP1 P35/PCL P117/FIP25 60 P36/BUZ 61 5 P37 4 P90/FIP2 X2 P91/FIP3 X1 P116/FIP24 VSS 62 XT2 3 P04/XT1 P115/FIP23 P92/FIP4 AVREF 63 AVDD 2 P10/ANI0 P114/FIP22 P93/FIP5 P11/ANI1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 P12/ANI2 1 P13/ANI3 P94/FIP6 Cautions 1. Connect the IC (Internally Connected) pins directly to the VSS. 2. Connect the AVDD pin to the VDD pin. 3. Connect the AVSS pin to the VSS pin. 6 µPD78044H, 78045H, 78046H P00-P04 : Port 0 SCK1 : Serial clock P10-P17 : Port 1 PCL : Programmable clock P20-P27 : Port 2 BUZ : Buzzer clock P30-P37 : Port 3 FIP0-FIP33 : Fluorescent indicator panel P70-P74 : Port 7 VLOAD : Negative power supply P80, P81 : Port 8 X1, X2 : Crystal (main system clock) P90-P97 : Port 9 XT1, XT2 : Crystal (subsystem clock) P100-P107 : Port 10 RESET : Reset P110-P117 : Port 11 ANI0-ANI7 : Analog input P120-P127 : Port 12 AVDD : Analog power supply INTP0-INTP3 : Interrupt from peripherals AVSS : Analog ground TI0 : Timer input AVREF : Analog reference voltage TO0-TO2 : Timer output VDD : Power supply SI1 : Serial input VSS : Ground SO1 : Serial output IC : Internally connected 7 µPD78044H, 78045H, 78046H 2. BLOCK DIAGRAM 16-bit timer/ event counter Port 0 P00 P01-P03 P04 TO1/P31 P33 8-bit timer/ event counter 1 Port 1 P10-P17 TO2/P32 P34 8-bit timer/ event counter 2 Port 2 P20-P27 Watchdog timer Port 3 P30-P37 Watch timer Port 7 P70-P74 Serial interface 1 Port 8 P80, P81 Port 9 P90-P97 Port 10 P100-P107 Port 11 P110-P117 Port 12 P120-P127 TO0/P30 TI0/INTP0/P00 SI1/P20 SO1/P21 SCK1/P22 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/TI0/P00INTP3/P03 BUZ/P36 PCL/P35 78K/0 CPU core ROM A/D converter Interrupt control Buzzer output Clock output control RAM 1024 bytes FIP0-FIP33 FIP controller/driver VLOAD System control VDD VSS IC Remark The capacity of the internal ROM differs depending on the product. 8 RESET X1 X2 XT1/P04 XT2 µPD78044H, 78045H, 78046H 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Function I/O P00 Input P01 I/O Port 0 5-bit I/O port On reset Input only Input INTP0/TI0 Can be specified for input or output in 1- Input INTP1 bit units. When used as an input port P02 Shared by: INTP2 pin, a built-in pull-up resistor can be P03 INTP3 connected through software. P04Note 1 Input P10-P17 I/O Input only Port 1 Input XT1 Input ANI0-ANI7 Input SI1 8-bit I/O port Can be specified for input or output in 1-bit units. When used as an input port pin, a built-in pull-up resistor can be connected through software.Note 2 P20 I/O Port 2 8-bit I/O port P21 SO1 Can be specified for input or output in 1-bit units. P22 SCK1 When used as an input port pin, a built-in pull-up resistor can be connected through software. P23 — P24 — P25 — P26 — P27 — P30 I/O Port 3 Input TO0 N-ch open-drain 8-bit I/O port P31 Can be specified for input or output in 1-bit units. P32 Can directly drive LEDs. TO1 TO2 A built-in pull-up resistor can be connected in 1-bit units by the P33 — mask option. P34 — P35 PCL P36 BUZ P37 — Notes 1. When the P04/XT1 pin is used as an input port pin, bit 6 (FRC) of the processor clock control register (PCC) must be set to 1. At this time, do not use the feedback resistor of the subsystem clock oscillator circuit. 2. When the P10/ANI0 through P17/ANI7 pins are used as the analog input lines of the A/D converter, be sure to place the port 1 in the input mode. In this case, the built-in pull-up resistors are automatically unused. 9 µPD78044H, 78045H, 78046H 3.1 PORT PINS (2/2) Pin P70-P74 I/O I/O Function Port 7 On reset Input Shared by: — 5-bit N-ch open-drain I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-up resistor can be connected in 1-bit units by the mask option. P80, P81 Output Port 8 2-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 2-bit units). Output FIP0, FIP1 P90-P97 Output Port 9 8-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be Output FIP2-FIP9 specified in 4-bit units). P100-P107 Output Port 10 8-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Output FIP10-FIP17 P110-P117 I/O Port 11 8-bit P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Can directly drive LEDs A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Input FIP18-FIP25 P120-P127 I/O Port 12 Input FIP26-FIP33 8-bit P-ch open-drain high-voltage I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). 10 µPD78044H, 78045H, 78046H 3.2 PINS OTHER THAN PORT PINS Pin INTP0 I/O Input Function Valid edge (rising, falling, or both rising and falling edges) can On reset Input Shared by: P00/TI0 INTP1 be specified. P01 INTP2 External interrupt input P02 INTP3 Falling edge-active external interrupt input Input P03 SI1 Input Serial data input lines of serial interface Input P20 SO1 Output Serial data output lines of serial interface Input P21 SCK1 I/O Serial clock I/O lines of serial interface Input P22 TI0 Input External count clock input to 16-bit timer (TM0) Input P00/INTP0 TO0 Output 16-bit timer output (multiplexed with 14-bit PWM output) Input P30 TO1 8-bit timer (TM1) output P31 TO2 8-bit timer (TM2) output P32 PCL Output Clock output (for trimming main system clock and subsystem Input P35 P36 clock) BUZ Output Buzzer output Input FIP0, FIP1 Output High-voltage, high-current digit/segment output of FIP Output FIP2-FIP9 FIP10-FIP15 controller/driver Output High-voltage, high-current digit/segment output of FIP P80, P81 P90-P97 Output P100-P105 Output P106, P107 Input P110-P117 controller/driver FIP16, FIP17 Output High-voltage segment output of FIP controller/driver FIP18-FIP25 FIP26-FIP33 VLOAD P120-P127 — Connects pull-down resistor to FIP controller/driver ANI0-ANI7 Input A/D converter analog input lines AV REF Input A/D converter reference voltage input line — — Input P10-P17 — — AV DD — Analog power supply to A/D converter. Connected to the V DD pin. — — AV SS — A/D converter ground line. Connected to the VSS pin. — — RESET Input System reset input — — X1 Input Connect crystal for main system clock oscillation — — X2 — — — XT1 Input XT2 — VDD — VSS IC Connect crystal for subsystem clock oscillation Input P04 — — Positive power supply — — — Ground potential — — — Internal connection. Connected directly to the VSS pin. — — 11 µPD78044H, 78045H, 78046H 3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS Table 3-1 shows the I/O circuit type of each pin and the processing of unused pins. For the configuration of the I/O circuit of each type, see Fig. 3-1. Table 3-1 Pin P00/INTP0/TI0 I/O circuit type I/O Recommended connections when unused Input Connected to VSS . 8-A I/O Individually connected to VSS with a resistor. P04/XT1 16 Input Connected to VDD or VSS . P10/ANI0-P17/ANI7 11 I/O Individually connected to VDD or VSS with a resistor. P20/SI1 8-A P21/SO1 5-A P22/SCK1 8-A P23 5-A P24 8-A P25 10-A 14-A Output Open 15-C I/O Individually connected to VDD or VSS with a resistor. P01/INTP1 2 I/O Circuit Type P02/INTP2 P03/INTP3 P26 P27 P30/TO0 13-B P31/TO1 P32/TO2 P33 22-A P34 P35/PCL 13-B P36/BUZ P37 P70-P74 P80/FIP0, P81/FIP1 P90/FIP2-P97/FIP9 P100/FIP10-P107/FIP17 P110/FIP18-P117/FIP25 P120/FIP26-P127/FIP33 RESET 2 Input XT2 16 — AVREF — — Open Connected to VSS. AVDD Connected to VDD. AVSS Connected to VSS. VLOAD IC 12 Connected directly to VSS. µPD78044H, 78045H, 78046H Fig. 3-1 Pin I/O Circuits (1/2) Type 2 Type 10-A VDD Pull-up enable P-ch VDD IN Data P-ch IN/OUT Open-drain Output disable N-ch Schmitt trigger input with hysteresis characteristics Type 5-A Type 11 VDD Pull-up enable VDD Pull-up enable P-ch Data VDD Data P-ch IN/OUT P-ch IN/OUT Output disable P-ch VDD Output disable N-ch P-ch N-ch Comparator + – N-ch VREF (Threshold voltage) Input enable Input enable Type 8-A Type 13-B VDD VDD Pull-up enable (Mask option) P-ch Data Output disable VDD Data IN/OUT N-ch P-ch VDD IN/OUT Output disable N-ch RD P-ch Input buffer with intermediate withstand voltage 13 µPD78044H, 78045H, 78046H Fig. 3-1 Pin I/O Circuits (2/2) Type 14-A Type 16 VDD Feedback cut-off VDD P-ch P-ch P-ch OUT Data (Mask option) N-ch VLOAD (Mask option) XT1 XT2 Type 22-A Type 15-C VDD VDD VDD P-ch (Mask option) P-ch IN/OUT Data IN/OUT Data Output disable N-ch N-ch VDD RD N-ch P-ch VLOAD (Mask option) 14 RD (Mask option) Input buffer with intermediate withstand voltage µPD78044H, 78045H, 78046H 4. MEMORY SPACE Fig. 4-1 shows the memory map for µ PD78044H, µPD78045H, and µPD78046H. Fig. 4-1 Memory Map FFFFH Special function register (SFR) 256 × 8 bits FF00H FEFFH FEE0H FEDFH General-purpose register 32 × 8 bits Internal high-speed RAM 1024 × 8 bits nnnnH Program area FB00H FAFFH Data memory space 1000H 0FFFH CALLF entry area Inhibited FA80H FA7FH FA50H FA4FH 0800H 07FFH FIP display RAM 48 × 8 bits Inhibited 0080H 007FH CALLT table area nnnnH+1 nnnnH Program memory space Program area 0040H 003FH Internal ROM Note Vector table area 0000H 0000H Note The internal ROM capacity varies depending on the product. (See the table below.) Product name Last address of internal ROM nnnnH µPD78044H 7FFFH µPD78045H 9FFFH µPD78046H BFFFH 15 µPD78044H, 78045H, 78046H 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports are classified into the following 5 kinds: • CMOS input (P00, P04) :2 • CMOS input/output (P01 - P03, ports 1 and 2) : 19 • N-ch open-drain input/output (ports 3 and 7) : 13 • P-ch open-drain output (ports 8 - 10) : 18 • P-ch open-drain input/output (ports 11 and 12) : 16 Total : 68 Table 5-1 Product Port 0 Port 1 Pin Port Function Function P00, P04 Input port P01-P03 I/O port. Can be specified for input or output in 1-bit units. When used as input port, built-in pull-up resistor can be connected through software. P10-P17 I/O port. Can be specified for input or output in 1-bit units. When used as input port, built-in pull-up resistor can be connected through software. Port 2 P20-P27 I/O port. Can be specified for input or output in 1-bit units. When used as input port, built-in pull-up resistor can be connected through software. Port 3 P30-P37 N-ch open-drain I/O port. Can be specified for input or output in 1-bit units. Built-in pull-up resistor can be connected in 1-bit units by the mask option. Can directly drive LED. Port 7 P70-P74 N-ch open-drain I/O port. Can be specified for input or output in 1-bit units. Built-in pull-up resistor can be connected in 1-bit units by the mask option. Can directly drive LED. Port 8 P80, P81 P-ch open-drain high-voltage output port. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 2-bit units). Can directly drive LED. Port 9 P90-P97 P-ch open-drain high-voltage output port. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. Port 10 P100-P107 P-ch open-drain high-voltage output port. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. Port 11 P110-P117 P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. Port 12 P120-P127 P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. 16 µPD78044H, 78045H, 78046H 5.2 CLOCK GENERATOR CIRCUIT The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock. The instruction time can be changed. • 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (with main system clock: 5.0 MHz) • 122 µs (with subsystem clock: 32.768 kHz) Fig. 5-1 XT2 f XT Clock output circuit Selector Subsystem clock generator circuit XT1/P04 Clock Generator Circuit Block Diagram Noise eliminator Selector fX 8 Watch timer fX 16 Pre-scaler X2 Main system clock generator circuit 1 Pre-scaler 2 Clock to hardware peripherals fX fX 2 fX 22 fX 23 f XT 2 fX 24 Selector X1 STOP Standby control circuit CPU clock (fCPU) To INTP0 sampling clock 5.3 TIMER/EVENT COUNTER Five channels of timer/event counters are provided. • 16-bit timer/event counter : 1 channel • 8-bit timer/event counter : 2 channels • Watch timer : 1 channel • Watchdog timer : 1 channel Table 5-2 Timer/Event Counter Groups and Configurations Function Group 16-bit timer/ event counter 8-bit timer/ event counter Interval timer 1 channel 2 channels External event counter 1 channel — Timer output 1 output PWM output 1 output Pulse width measurement 1 input Square wave output 1 output 2 outputs Interrupt request 1 2 Test input Watch timer 1 channel 1 channel — — — — — — — — — — — — 2 outputs — Watchdog timer 1 — 1 input 1 — 17 µPD78044H, 78045H, 78046H Fig. 5-2 16-Bit Timer/Event Counter Block Diagram Internal bus 16-bit compare register (CR00) INTTM0 PWM pulse output control circuit Match fX Selector f X/2 f X/22 f X/23 TI0/P00/INTP0 16-bit timer/event counter output control circuit TO0/P30 16-bit timer register (TM0) Edge detector circuit Selector Clear INTP0 16-bit capture register (CR01) Internal bus Fig. 5-3 8-Bit Timer/Event Counter Block Diagram Internal bus INTTM1 8-bit compare register (CR10) Selector 8-bit compare register (CR20) Match Match Output control circuit TO2/P32 8-bit timer register 1 (TM1) Clear Selector f X/212 Selector INTTM2 f X/2 -fX/210 8-bit timer register 2 (TM2) f X/2 -fX/210 f X/212 Selector Clear Selector Output control circuit Internal bus 18 TO1/P31 µPD78044H, 78045H, 78046H f XT fW Pre-scaler fW 25 fW 26 fW 27 fW 28 f WDT Watchdog Timer Block Diagram Pre-scaler f WDT 2 f WDT 22 f WDT 23 f WDT 24 f WDT 25 f WDT 26 f WDT 28 8-bit counter Control circuit fX 23 INTTM3 Selector fX 24 Selector Fig. 5-5 INTWT fW 213 fW 29 Selector fW 24 fW 214 5-bit counter Selector Selector f X/28 Watch Timer Block Diagram Selector Fig. 5-4 INTWDT Maskable interrupt request RESET INTWDT Nonmaskable interrupt request 19 µPD78044H, 78045H, 78046H 5.4 CLOCK OUTPUT CONTROL CIRCUIT Clocks of the following frequencies can be output to the clock: • 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz (with main system clock: 5.0 MHz) • 32.768 kHz (with subsystem clock: 32.768 kHz) Fig. 5-6 Clock Output Control Circuit Block Diagram f X /2 3 f X /2 4 Selector f X /2 5 f X /2 6 f X /2 7 PCL/P35 Output control circuit Sync circuit f X /2 8 f XT 5.5 BUZZER OUTPUT CONTROL CIRCUIT Clocks of the following frequencies can be output to the buzzer: • 1.2 kHz/2.4 kHz/4.9 kHz (with main system clock: 5.0 MHz) f X /2 10 f X /2 11 f X /2 12 20 Selector Fig. 5-7 Buzzer Output Control Circuit Block Diagram Output control circuit BUZ/P36 µPD78044H, 78045H, 78046H 5.6 A/D CONVERTER An 8-bit resolution 8-channel A/D converter is provided. This A/D converter can be started in the following two modes: • Hardware start • Software start Fig. 5-8 A/D Converter Block Diagram Series resistor string AVDD ANI0/P10 AVREF ANI2/P12 ANI4/P14 Voltage comparator Selector ANI3/P13 Tap selector Sample-and-hold circuit ANI1/P11 ANI5/P15 ANI6/P16 AVSS Successive approximation register (SAR) ANI7/P17 INTP3/P03 Falling edge detector circuit Control circuit INTAD INTP3 A/D conversion result register (ADCR) Internal bus 21 µPD78044H, 78045H, 78046H 5.7 SERIAL INTERFACE One channel of clocked serial interfaces is provided. Serial interface channel 1 can be operated in the 3-wire serial I/O mode, where the MSB or LSB is selectable as the first bit. Fig. 5-9 Serial Interface Channel 1 Block Diagram Internal bus SI1/P20 Serial I/O shift register 1 (SIO1) SO1/P21 SCK1/P22 Serial clock counter Interrupt request signal generator INTCSI1 fX/22-fX/29 Serial clock control circuit 22 Selector TO2 µPD78044H, 78045H, 78046H 5.8 FIP CONTROLLER/DRIVER An FIP controller/driver having the following features is provided: (a) Automatic output of segment signals (DMA operation) and digit signals by automatically reading display data (b) Display mode registers (DSPM0 and DSPM1) that can control an FIP of 9 to 24 segments and 2 to 16 digits (c) Port pins not used for FIP display can be used as output port or I/O port pins. (d) Display mode register (DSPM1) can adjust luminance in eight steps. (e) Hardware suitable for key scan application using segment pins (f) High-voltage output buffer (FIP driver) that can directly drive an FIP (g) Display output pins can be connected to a pull-down resistor by the mask option. Fig. 5-10 Selecting Display Modes Selecting number of digits 0 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9 10 11 12 Selecting number of segments 13 14 15 16 17 18 19 20 21 22 23 24 Caution If the total number of digits and segments exceeds 34, the specified number of digits takes precedence. 23 µPD78044H, 78045H, 78046H Fig. 5-11 FIP Controller/Driver Block Diagram Internal bus Display data memory Digit signal generator circuit Segment data latch Port output latch High-voltage buffer FIP0/P80 FIP1/P81 24 FIP33/P127 µPD78044H, 78045H, 78046H 6. INTERRUPT FUNCTION AND TEST FUNCTION 6.1 INTERRUPT FUNCTION The following three types of interrupt functions are available: • Non-maskable interrupt : 1 • Maskable interrupt : 12 • Software interrupt : 1 Table 6-1 Default priority Internal/ external Name Trigger Non-maskable — INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (with interval timer mode selected) 1 INTP0 Pin input edge detection 2 Software Note 2 Interrupt source Note 1 Interrupt type Interrupt Source List Internal Vector table address 0004H Basic configuration type (A) (B) 0006H (C) INTP1 0008H (D) 3 INTP2 000AH 4 INTP3 000CH 5 INTCSI1 End of serial interface channel 1 transfer 6 INTTM3 Reference time interval signal from watch timer 0012H 7 INTTM0 16-bit timer/event counter match signal generation 0014H 8 INTTM1 8-bit timer/event counter 1 match signal generation 0016H 9 INTTM2 8-bit timer/event counter 2 match signal generation 0018H 10 INTAD End of A/D converter conversion 001AH 11 INTKS Key scan timing from FIP controller/driver 001CH — BRK Execution of BRK instruction External Internal — 0010H 003EH (B) (E) Notes 1. Default priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest order and the 11 is the lowest order. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Fig. 6-1. 25 µPD78044H, 78045H, 78046H Fig. 6-1 Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt request Vector table address generator circuit Priority control circuit Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Vector table address generator circuit Priority control circuit IF Standby release signal (C) External maskable interrupt (INTP0) Internal bus Sampling clock select register (SCS) Interrupt request Sampling clock External interrupt mode register (INTM0) Edge detector circuit MK IF IE PR Priority control circuit ISP Vector table address generator circuit Standby release signal 26 µPD78044H, 78045H, 78046H Fig. 6-1 Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) Internal bus External interrupt mode register (INTM0) Edge detector circuit Interrupt request MK IE PR Priority control circuit IF ISP Vector table address generator circuit Standby release signal (E) Software interrupt Internal bus Interrupt request Priority control circuit Vector table address generator circuit IF : Interrupt request flag IE : Interrupt enable flag ISP: In-service priority flag MK : Interrupt mask flag PR : Priority specification flag 27 µPD78044H, 78045H, 78046H 6.2 TEST FUNCTION The following test function is available. Test input source Internal/external Name INTWT Fig. 6-2 Trigger Overflow of watch timer Internal Basic Configuration of Test Function Internal bus MK Test input source (INTWT) IF : Test request flag MK: Test mask flag 28 IF Standby release signal µPD78044H, 78045H, 78046H 7. STANDBY FUNCTION The standby function is to reduce the current dissipation of the system and can be effected in the following two modes: • HALT mode : In this mode, the operating clock of the CPU is stopped. By using this mode in combination with the normal operation mode, the system can be operated intermittently, so that the average current dissipation can be reduced. • STOP mode : Oscillation of the main system clock is stopped. All the operations on the main system clock are stopped, and therefore, the current dissipation of the system can be minimized with only the subsystem clock oscillating. Fig. 7-1 CSS=1 Main system clock operation Interrupt request STOP instruction Standby Function CSS=0 Interrupt request STOP mode (Oscillation of main system clock stopped) Subsystem clock operationNote HALT instruction Interrupt request HALT mode (Clock supply to CPU stopped. Oscillation continues) HALT instruction HALT modeNote (Clock supply to CPU stopped. Oscillation continues) Note By stopping the main system clock, the current dissipation can be reduced. When the CPU operates on the subsystem clock, stop the main system clock by setting bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction cannot be used. Caution When the main system clock is stopped and the subsystem clock is operating, to switch again from the subsystem clock to the main system clock, allow sufficient time for the oscillation to settle before switching, by coding the program accordingly. 8. RESET FUNCTION The system can be reset in the following two modes: • External reset by RESET pin • Internal reset by watchdog timer that detects hang up 29 µPD78044H, 78045H, 78046H 9. INSTRUCTION SET (1) 8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second operand #byte A r Note sfr saddr MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP First operand A ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH 1 None ROR ROL RORC ROLC MOV ADD ADDC SUB SUBC AND OR XOR CMP B, C INC DEC DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV !addr16 PSW MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP $addr16 DBNZ INC DEC MOV MOV MOV [DE] MOV [HL] MOV [HL + byte] [HL + B] [HL + C] MOV PUSH POP ROR4 ROL4 X MULU C DIVUW Note Except for r = A 30 µPD78044H, 78045H, 78046H (2) 16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second operand #word AX Note rp sfrp saddrp !addr16 SP None First operand AX ADDW SUBW CMPW MOVW XCHW rp MOVW MOVW sfrp MOVW MOVW saddrp MOVW MOVW MOVW MOVW MOVW MOVW Note !addr16 INCW DECW PUSH POP MOVW SP MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 First operand CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 31 µPD78044H, 78045H, 78046H (4) Call/branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second operand AX !addr16 !addr11 [addr5] $addr16 CALL BR CALLF CALLT First operand Basic operation BR Compound operation BR BC BNC BZ BNZ BT BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 32 µPD78044H, 78045H, 78046H 10. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Power supply voltage Input voltage Output voltage Symbol Conditions Rating –0.3 to +7.0 V VLOAD VDD – 40 to VDD + 0.3 V AVDD –0.3 to VDD + 0.3 V AVREF –0.3 to VDD + 0.3 V AVSS –0.3 to +0.3 V VDD VI1 P00-P04, P10-P17 (except when used as analog input pins), P20-P27, X1, X2, XT2, RESET –0.3 to VDD + 0.3 V VI2 P30-P37, P70-P74 N-ch open drain –0.3 to +16Note 1 V VI3 P110-P117, P120-P127 P-ch open drain VDD – 40 to VDD + 0.3 V VO1 P01-P03, P10-P17, P20-P27 –0.3 to VDD + 0.3 V +16Note 1 V –0.3 to VO2 P30-P37, P70-P74 VO3 P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 Analog input voltage VAN ANI0-ANI7 Output current, high IOH Output current, low IOL VDD – 40 to VDD + 0.3 V AVSS – 0.3 to AV REF + 0.3 V P01-P03, P10-P17, P20-P27 per pin –10 mA P01-P03, P10-P17, P20-P27 total –30 mA P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 per pin –30 mA P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 total –120 mA 30 mA 15Note 2 mA 100 mA 60Note 2 mA 100 mA 60Note 2 mA TA = –40 to +60 °C 800 mW TA = +85 °C 600 mW Analog input pin P01-P03, P10-P17, P20-P27, P30-P37, Peak value P70-P74 per pin rms value P70-P74 total Peak value rms value P01-P03, P10-P17, P20-P27, P30-P37 total Peak value rms value Total power Unit PTNote 3 dissipation Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of the corresponding port pin. Notes 1. For pins to which pull-up resistors are connected by the mask option, the rating is –0.3 to VDD + 0.3. 2. To obtain the rms value, calculate [rms value] = [peak value] × √duty. 33 µPD78044H, 78045H, 78046H Notes 3. Permissible total power loss differs depending on the temperature (see the following figure). Total power loss PT [mW] 800 600 400 200 –40 0 +40 +80 Temperature [°C] How to calculate total power loss The power consumption of the µPD78044H, µPD78045H, and µPD78046H can be classified into the three categories shown below. The sum of the three categories should be less than the total power loss PT (80 % or less of ratings is recommended). 1 CPU power consumption: calculate VDD (MAX.) × IDD1 (MAX.). 2 Output pin power consumption: Normal output and display output are available. Power consumption when maximum current flows into each output pin. 3 Pull-down resistor power consumption: Power consumption by pull-down resistor connected to display output pin by the mask option. 34 µPD78044H, 78045H, 78046H The following total power consumption calculation example assumes the case where the characters shown in the figure on the next page are displayed. Example: The operating conditions are as follows: VDD = 5 V ±10 %, operating at 5.0 MHz Supply current (IDD) = 21.6 mA Display outputs: 11 grids × 10 segments (cut width is 1/16) It is assumed that up to 15 mA flows to each grid pin, and that up to 3 mA flows to each segment pin. It is also assumed that all display outputs are turned off at key scan timings. VO3 = VDD – 2 V (Voltage drop of 2 V is assumed.) Display output voltage: grid segment VO3 = VDD – 0.4 V (Voltage drop of 0.4 V is assumed.) Voltage applied to fluorescent indication panel (V LOAD) = –30 V Mask-option pull-down resistor = 25 kΩ The total power loss is calculated by determining power consumption 1 to 3 under the above conditions. 1 Power consumption of CPU: 5.5 V × 21.6 mA = 118.8 mW 2 Power consumption at output pins: Grid: total current for all grids (V DD – V O3) × number of grids + 1 2V × Segment: (V DD – V O3 ) × 0.4 V × 3 15 mA × 11 grids 11 grids + 1 × digit width (1 – cut width) = × (1 – 1/16) = 25.8 mW total segment current for all dots to be lit number of grids + 1 3 mA × 31 dots = = 3.1 mW 11 grids + 1 Power consumption at pull-down resistors: Grid: Segment: (VO3 – VLOAD )2 number of grids × × digit width = pull-down resistance number of grids + 1 (5.5 V – 2 V – (–30 V))2 11 grids × × (1 – 1/16) = 38.6 mW 25 kΩ 11 grids + 1 (VO3 – VLOAD )2 × number of dots to be lit = pull-down resistance number of grids + 1 31 dots (5.5 V – 0.4 V – (–30 V))2 × = 127.3 mW 25 kΩ 11 grids + 1 Total power consumption = 1 + 2 + 3 = 118.8 + 25.8 + 3.1 + 38.6 + 127.3 = 313.6 mW In this example, the total power consumption does not exceed the rated value for the permissible total power loss shown in the graph on the previous page. Therefore, the calculation result in this example (313.6 mW) satisfies the requirement. If the total power consumption exceeds the rated value for the permissible total power loss, the power consumption must be reduced, by reducing the number of built-in pull-down resistors. 35 36 a b c d e f g h i j S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 0 AM i PM j i 1 SUN 2 MON 3 4 5 6 7 SAT 8 9 g b a e d c 10 h FRI j THU f WED T0 j TUE T1 Bit 6 0 0 0 0 0 0 0 1 0 0 0 T2 Bit 7 0 0 0 0 0 0 0 0 1 0 1 T3 Bit 0 0 0 0 0 1 0 0 0 0 0 0 T4 Bit 1 1 1 1 0 0 1 1 0 0 0 0 T5 Bit 2 1 0 0 0 0 1 1 0 0 0 0 T6 Bit 3 1 1 0 0 0 0 0 0 0 0 0 T7 Bit 4 0 1 1 0 0 1 0 0 0 0 0 T8 Bit 5 1 0 1 1 0 1 1 0 1 1 0 T9 Bit 6 0 0 1 1 0 0 1 0 1 1 0 T10 Bit 7 0 0 1 0 0 1 0 0 0 0 0 FA7AH FA79H FA78H FA77H FA76H FA75H FA74H FA73H FA72H FA71H FA70H FA6AH FA69H FA68H FA67H FA66H FA65H FA64H FA63H FA62H FA61H FA60H Display data memory 10-Segment/11-Digit Display Example FA6 × H FA7 × H µPD78044H, 78045H, 78046H µPD78044H, 78045H, 78046H MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Resonator Ceramic resonator Recommended circuit VSS X1 X2 C1 Crystal VSS X1 C2 X2 C1 External clock X1 C2 X2 µ PD74HCU04 Parameter Conditions Oscillation frequency (fX)Note 1 MIN. TYP. 1 Oscillation settling timeNote 2 Oscillation frequency (fX)Note 1 Oscillation settling timeNote 2 1 VDD = 4.5 to 5.5 V X1 input frequency (fX)Note 1 X1 input high, low-level width (tXH, t XL) 4.19 MAX. Unit 5 MHz 4 ms 5 MHz 10 ms 30 1 5 MHz 100 500 ns Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Characteristics. 2. Time required until oscillation becomes stable after VDD is applied or the STOP mode is disabled. Cautions 1. If the main system clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance: • Make wiring as short as possible. • Do not cross other signal lines. • Do not get close to lines with fluctuating large current. • Make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as V SS. • Do not connect the oscillator to a ground pattern that conducts a large current. • Do not take out signal from the oscillator. 2. When switching to the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to set the program to provide enough time for the oscillation to stabilize. 37 µPD78044H, 78045H, 78046H SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Resonator Crystal Recommended circuit XT1 XT2 VSS Parameter Conditions Oscillation frequency (fXT)Note 1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s R C3 C4 Oscillation settling timeNote 2 VDD = 4.5 to 5.5 V 10 External XT1 XT2 XT1 input frequency (fXT)Note 1 32 100 kHz XT1 input high, lowlevel width (tXTH, tXTL) 5 15 µs Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Characteristics. 2. Time required until oscillation becomes stable after VDD reaching MIN. of oscillation voltage range. Cautions 1. If the subsystem clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance: • Make wiring as short as possible. • Do not cross other signal lines. • Do not get close to lines with fluctuating large current. • Make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as V SS. • Do not connect the oscillator to a ground pattern that conducts a large current. • Do not take out signal from the oscillator. 2. The subsystem clock oscillator is more likely to have malfunctions due to noise than the main system clock oscillator because gain for the subsystem clock oscillator is made lower to reduce current consumption. When using the subsystem clock, be careful about how to connect wires. 38 µPD78044H, 78045H, 78046H RECOMMENDED OSCILLATOR CONSTANT MAIN SYSTEM CLOCK: CERAMIC RESONATOR (TA = –40 to +85 °C) Manufacturer Murata Mfg. Co., Ltd. TDK Corp. Product name Frequency (MHz) Recommended circuit constant Oscillator voltage range C1 (pF) C2 (pF) MIN. (V) MAX. (V) Remark Rd = 4.7 kΩNote CSB1000J 1.00 100 100 2.7 5.5 CSA2.00MG040 2.00 100 100 2.7 5.5 CST2.00MG040 2.00 — — 2.7 5.5 CSA4.00MG 4.00 30 30 2.7 5.5 CST4.00MGW 4.00 — — 2.7 5.5 CSA5.00MG 5.00 30 30 2.7 5.5 CST5.00MGW 5.00 — — 2.7 5.5 Built-in capacitor CCR1000K2 1.00 150 150 2.7 5.5 Surface-mount type CCR2.0MC3 2.00 — — 2.7 5.5 Built-in capacitor Built-in capacitor Built-in capacitor, surface-mount type CCR4.0MC3 4.00 — — 2.7 5.5 Built-in capacitor, surface-mount type FCR4.0MC5 4.00 — — 2.7 5.5 Built-in capacitor CCR5.0MC3 5.00 — — 2.7 5.5 Built-in capacitor, surface-mount type FCR5.0MC5 5.00 — — 2.7 5.5 Built-in capacitor Matsushita Electronics EFOEC2004A4 2.00 33 33 2.7 5.5 Built-in capacitor Components Co., Ltd. EFOS2004B5 2.00 33 33 2.7 5.5 Built-in capacitor, surface-mount type EFOEC3584A4 3.58 33 33 2.7 5.5 Built-in capacitor EFOS3584B5 3.58 33 33 2.7 5.5 Built-in capacitor, surface-mount type EFOEC4004A4 4.00 33 33 2.7 5.5 Built-in capacitor EFOS4004B5 4.00 33 33 2.7 5.5 Built-in capacitor, surface-mount type EFOEC5004A4 5.00 33 33 2.7 5.5 Built-in capacitor EFOS5004B5 5.00 33 33 2.7 5.5 Built-in capacitor, surface-mount type Note When the CSB1000J (1.00 MHz) manufactured by Murata Mfg. is used, a limiting resistor (4.7 kΩ) is necessary (see the figure in the next page). When one of other resonators is used, no limiting resistor is required. Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator that being used. 39 µPD78044H, 78045H, 78046H Recommended sample circuit for the main system clock when the CSB1000J manufactured by Murata Mfg. is used VSS X1 X2 CSB1000J C1 Rd C2 VDD CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz Unmeasured pins returned to 0 V 15 pF Output capacitance COUT f = 1 MHz Unmeasured pins returned to 0 V 35 pF Input/output capacitance CIO f = 1 MHz Unmeasured pins returned to 0 V P01-P03, P10-P17, P20-P27 15 pF P30-P37, P70-P74 20 pF P110-P117, P120-P127 35 pF Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of the corresponding port pin. POWER SUPPLY VOLTAGE (TA = –40 to +85 °C) Parameter MAX. Unit 2.7Note 2 5.5 V Display controller/driver 4.5 5.5 V PWM mode of 16-bit timer/event counter (TM0) 4.5 5.5 V A/D converter 4.0 5.5 V Other hardware 2.7 5.5 V CPUNote 1 Conditions MIN. TYP. Notes 1. Except for system clock oscillator, display controller/driver, and PWM. 2. Operating power supply voltage differs depending on the cycle time. See the AC Characteristics. 40 µPD78044H, 78045H, 78046H DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter High-level input voltage Symbol TYP. MAX. Unit VIH1 P21, P23 0.7VDD VDD V VIH2 P00-P03, P20, P22, P24-P27, RESET 0.8VDD VDD V 0.7VDD 15Note 1 V VDD – 0.5 VDD V VDD – 0.5 VDD V VDD – 0.3 VDD V 0.65V DD VDD V 0.7VDD VDD V 0.7VDD VDD V VDD – 0.5 VDD V VIH3 P30-P37, P70-P74 VIH4 X1, X2Note 2 VIH5 XT1/P04, XT2Note 2 VIH6 VIH7 Low-level input voltage MIN. Conditions P10-P17 N-ch open drain VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V P110-P117, P120-P127 VDD = 4.5 to 5.5 V VIL1 P21, P23 0 0.3V DD V VIL2 P00-P03, P20, P22, P24-P27, RESET 0 0.2V DD V VIL3 P30-P37, P70-P74 0 0.3V DD V 0 0.2V DD V 0 0.4 V 0 0.4 V 0 0.3 V 0 0.3V DD V VDD – 35 0.3V DD V VIL4 VIL5 X1, VDD = 4.5 to 5.5 V X2Note 2 XT1/P04, XT2Note 2 VDD = 4.5 to 5.5 V VIL6 P10-P17 VIL7 P110-P117, P120-P127 High-level output voltage VOH P01-P03, P10-P17, P20-P27, P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 VDD = 4.5 to 5.5 V IOH = –1 mA VDD – 1.0 V IOH = –100 µA VDD – 0.5 V Low-level output voltage VOL1 P30-P37, P70-P74 VDD = 4.5 to 5.5 V, IOL = 15 mA P01-P03, P10-P17, P20-P27 VDD = 4.5 to 5.5 V, IOL = 1.6 mA VOL2 IOL = 400 µA 0.4 2.0 V 0.4 V 0.5 V Notes 1. Pins to which pull-up resistors are connected by the mask option become VDD. 2. If the X1 pin is used for high-level voltage input, the X2 pin is used for low-level voltage input, or vice versa. This is also true for the XT1/P04 pin and XT2 pin. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of the corresponding port pin. 41 µPD78044H, 78045H, 78046H DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter High-level input leakage current Low-level input leakage current Symbol ILIH1 VIN = VDD ILIH2 TYP. MAX. Unit P00-P03, P10-P17, P20-P27, RESET 3 µA X1, X2, XT1/P04, XT2 20 µA Conditions MIN. ILIH3 VIN = 15 V P30-P37, P70-P74 20 µA ILIH4 P110-P117, P120-P127, VIN = VDD VDD = 4.5 to 5.5 V 3Note 1 µA 3Note 2 µA VIN = 0 V P00-P03, P10-P17, P20-P27, RESET –3 µA ILIL2 X1, X2, XT1/P04, XT2 –20 µA ILIL3 P30-P37, P70-P74 –3Note 3 µA ILIL4 P110-P117, P120-P127 –10 µA ILIL1 High-level output leakage current Note 4 ILOH1 VOUT = VDD P01-P03, P10-P17, P20-P27, P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 3 µA ILOH2 VOUT = 15 V P30-P37, P70-P74 20 µA Low-level output leakage currentNote 4 ILOL1 VOUT = 0 V P01-P03, P10-P17, P20-P27, P30-P37, P70-P74 –3 µA ILOL2 VOUT = VLOAD = VDD – 35 V P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 –10 µA Display output current IOD VDD = 4.5 to 5.5 V, VO3 = VDD – 2 V –15 –25 Mask option pull-up resistor R1 VIN = 0 V, P30-P37, P70-P74 20 40 90 kΩ Software pullup resistor R2 VIN = 0 V, P01-P03, P10-P17, P20-P27 VDD = 4.5 to 5.5 V 15 40 90 kΩ 500 kΩ P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 VO3 – VLOAD = 35 V 25 65 135 kΩ VO3 – VSS = 5 V 15 40 90 kΩ VIN = VDD 40 80 150 kΩ Mask option pull-down resistor R3 R4 20 mA Notes 1. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 150 µA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out port 11 or 12 (P11 or P12) or port mode register 11 or 12 (PM11 or PM12). Outside the 1.5 clocks after a read instruction, the current is 3 µA (MAX.). 2. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 90 µA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out P11, P12, PM11, or PM12. Outside the 1.5 clocks after a read instruction, the current is 3 µA (MAX.). 3. When P30 to P37 and P70 to P74 do not contain the pull-down resistors (according to the specification of the mask option), a low-level input leakage current of –150 µA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out port 3 or 7 (P3 or P7) or port mode register 3 or 7 (PM3 or PM7). Outside the 1.5 clocks after a read out instruction, the current is –3 µA (MAX.). 4. Current which flows in the built-in pull-up or pull-down resistor is not included. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. 42 µPD78044H, 78045H, 78046H DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter Symbol Power supply currentNote 1 IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Conditions TYP. MAX. Unit VDD = 5.0 V ±10 %Note 2 7.2 21.6 mA VDD = 3.0 V ±10 %Note 3 0.9 2.7 mA VDD = 5.0 V ±10 % 1.3 3.9 mA VDD = 3.0 V ±10 % 550 1650 µA VDD = 5.0 V ±10 % 60 120 µA VDD = 3.0 V ±10 % 35 70 µA VDD = 5.0 V ±10 % 25 50 µA VDD = 3.0 V ±10 % 5 10 µA XT1 = 0 V STOP mode Feedback resistor connected VDD = 5.0 V ±10 % 1 20 µA VDD = 3.0 V ±10 % 0.5 10 µA XT1 = 0 V STOP mode Feedback resistor not connected VDD = 5.0 V ±10 % 0.1 20 µA VDD = 3.0 V ±10 % 0.05 10 µA 5.0 MHz crystal oscillation Operating mode 5.0 MHz crystal oscillation HALT mode 32.768 kHz crystal oscillation Operating modeNote 4 32.768 kHz crystal oscillation HALT modeNote 4 MIN. Notes 1. This current excludes the AVREF current, port current, and current which flows in the built-in pull-down resistor (mask option). 2. When operating in high-speed mode (when the processor clock control register (PCC) is set to 00H) 3. When operating in low-speed mode (when the PCC is set to 04H) 4. When the main system clock is stopped 43 µPD78044H, 78045H, 78046H AC CHARACTERISTICS (1) Basic operation (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter Symbol Cycle time (minimum instruction execution time) TCY Interrupt input high, low-level width RESET lowlevel width tRSL MIN. Conditions Operated with main system clock VDD = 4.5 to 5.5 V TYP. MAX. Unit 0.4 32 µs 0.8 32 µs 125 µs Operated with subsystem clock 40Note 1 tINTH INTP0 8/fsam Note 2 µs tINTL INTP1-INTP3 10 µs 10 µs 122 Notes 1. Value when external clock input is used as subsystem clock. When a crystal is used, the value becomes 114 µs. 2. Selection of fsam = fX/2 N+1, fX/64, or fX/128 is available (N = 0 to 4) by bits 0 and 1 (SCS0, SCS1) of the sampling clock select register (SCS). TCY vs. VDD (with main system clock operated) 60 Cycle time TCY [ µ s] 30 Operation guarantee range 10 2.0 1.0 0.5 0.4 0 1 2 3 4 5 Power supply voltage VDD [V] 44 6 µPD78044H, 78045H, 78046H (2) Serial interface channel 1 (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) (a) Three-wire serial I/O mode (SCK1: Internal clock output) Parameter SCK1 cycle time Symbol TYP. MAX. Unit ns 3200 ns tKCY1/2 – 50 ns tKL1 t KCY1/2 – 150 ns SI1 setup time to SCK1↑ tSIK1 100 ns SI1 hold time from SCK1↑ tKSI1 400 ns SCK1↓→ SO1 output delay time tKSO1 tKH1 VDD = 4.5 to 5.5 V MIN. 800 SCK1 high, low-level width tKCY1 Conditions VDD = 4.5 to 5.5 V C = 100 pFNote VDD = 4.5 to 5.5 V 300 ns 1000 ns MAX. Unit Note C is a load capacitance of the SCK1 or SO1 output line. (b) Three-wire serial I/O mode (SCK1: External clock input) Parameter SCK1 cycle time SCK1 high, low-level width Symbol tKCY2 tKH2 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKL2 SI1 setup time to SCK1↑ tSIK2 SI1 hold time from SCK1↑ tKSI2 SCK1↓→ SO1 output delay time tKSO2 SCK1 rise time and fall time tR2 tF2 VDD = 4.5 to 5.5 V C = 100 pFNote VDD = 4.5 to 5.5 V MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns 100 ns 400 ns 300 ns 1000 ns 160 ns Note C is a load capacitance of the SO1 output line. 45 µPD78044H, 78045H, 78046H AC timing test points (except X1, XT1 input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock timing 1/fX tXH tXL VIH4 (Min.) X1 input VIL4 (Max.) 1/fXT tXTH tXTL VIH5 (Min.) XT1 input VIL5 (Max.) Serial transfer timing 3-wire serial I/O mode: tKCY1, 2 tKH1, 2 tKL1, 2 tR2 tF2 SCK1 tSIK1, 2 tKSI1, 2 Input data SI1 tKSO1, 2 SO1 46 Output data µPD78044H, 78045H, 78046H A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions Resolution MIN. TYP. MAX. Unit 8 8 8 bit 0.8 % 19.1 200 µs Total errorNote 1 Conversion timeNote 2 tCONV 1 MHz ≤ fX ≤ 5.0 MHz Sampling timeNote 3 tSAMP 2.86 30 µs Analog signal input voltage VIAN AVSS AVREF V Reference voltage AVREF 4.0 AVDD V AVREF resistor RAVREF 4 AVDD current AIDD 14 200 kΩ 400 µA Notes 1. Quantization error (±1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale value. 2. Set the A/D conversion time to 19.1 µs or more. 3. Sampling time depends on the conversion time. 47 µPD78044H, 78045H, 78046H DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85 °C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal set time tSREL Oscillation settling time tWAIT Conditions MIN. TYP. MAX. Unit 5.5 V 10 µA 2.0 VDDDR = 2.0 V Subsystem clock stopped Feedback resistor not connected 0.1 µs 0 Release by RESET 217/fX ms Release by interrupt Note ms Note Selection of 212/fX, 214 /fX to 217/fX is available by bits 0 to 2 (OSTS0 to OSTS2) of the oscillation settling time select register (OSTS). Data retention timing (STOP mode release by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data retention timing (standby release signal: STOP mode release by interrupt signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 48 µPD78044H, 78045H, 78046H Interrupt input timing tINTL tINTH INTP0-INTP2 tINTL INTP3 RESET input timing tRSL RESET 49 µPD78044H, 78045H, 78046H 11. PACKAGE DRAWING 80 PIN PLASTIC QFP (14 20) A B 41 40 64 65 detail of lead end S C D Q R 25 24 80 1 F G J H I M K P M N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 23.6±0.4 0.929±0.016 B 20.0±0.2 0.795 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.6±0.4 0.693±0.016 F 1.0 0.039 G 0.8 0.031 H 0.35±0.10 0.014 +0.004 –0.005 0.006 I 0.15 J 0.8 (T.P.) 0.031 (T.P.) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1±0.1 0.004±0.004 R S 5°±5° 5°±5° 3.0 MAX. 0.119 MAX. P80GF-80-3B9-3 Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product. 50 µPD78044H, 78045H, 78046H 12. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the µ PD78044H, µ PD78045H, or µPD78046H. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 12-1 Soldering Conditions for Surface-Mount Devices µPD78044HGF-×××-3B9: 80-pin plastic QFP (14 × 20 mm) µPD78045HGF-×××-3B9: 80-pin plastic QFP (14 × 20 mm) µPD78046HGF-×××-3B9: 80-pin plastic QFP (14 × 20 mm) Soldering process Soldering conditions Recommended conditions Infrared ray reflow Peak package's surface temperature: 235 °C Reflow time: 30 seconds or less (210 °C or more) Maximum allowable number of reflow processes: 3 IR35-00-3 VPS Peak package's surface temperature: 215 °C Reflow time: 40 seconds or less (200 °C or more) Maximum allowable number of reflow processes: 3 VP15-00-3 Wave soldering Solder temperature: 260 °C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature : 120 °C max. (measured on the package surface) WS60-00-1 Partial heating method Terminal temperature: 300 °C or less Heat time: 3 seconds or less (for one side of a device) — Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). 51 µPD78044H, 78045H, 78046H APPENDIX A DEVELOPMENT TOOLS The following tools are available for development of systems using the µPD78044H, µ PD78045H, or µ PD78046H. Language processing software RA78K/0Notes 1, 2, 3, 4 Assembler package common to 78K/0 series CC78K/0Notes 1, 2, 3, 4 C compiler package common to 78K/0 series DF78044Notes 1, 2, 3, 4 Device file used in common with µPD78044A subseries CC78K/0-LNotes 1, 2, 3, 4 C compiler library source file common to 78K/0 series PROM writing tools PG-1500 PROM programmer PA-78P048GF PA-78P048KL-S Programmer adapter connected to PG-1500 PG-1500 controllerNotes 1, 2 Control program for PG-1500 Debugging tools IE-78000-R In-circuit emulator common to 78K/0 series IE-78000-R-ANote 8 In-circuit emulator common to 78K/0 series (for integrated debugger) IE-78000-R-BK Break board common to 78K/0 series IE-78044-R-EM Emulation board used in common with µPD78044A subseries EP-78130GF-R Emulation probe used in common with µPD78134 EV-9200G-80 Socket mounted on target system created for 80-pin plastic QFP SM78K0Notes 5, 6, 7 System simulator common to 78K/0 series ID78K0Notes 4, 5, 6, 7, 8 Integrated debugger for IE-78000-R-A SD78K/0Notes 1, 2 Screen debugger for IE-78000-R DF78044Notes 1, 2, 5, 6, 7 Device file used in common with µPD78044A subseries Real-time OS RX78K/0Notes 1, 2, 3, 4 Real-time OS for 78K/0 series MX78K0Notes 1, 2, 3, 4 OS for 78K/0 series Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 series 300TM (HP-UXTM) based 4. HP9000 series 700 TM (HP-UX) based, SPARCstation TM (SunOSTM) based, EWS4800 series (EWS-UX/V) based 5. PC-9800 series (MS-DOS + WindowsTM) based 6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based 8. Under development 52 µPD78044H, 78045H, 78046H Fuzzy inference development support system FE9000Note 1/FE9200 Note 3 Fuzzy knowledge data creation tool FT9080Note 1/FT9085Note 2 Translator FI78K0Notes 1, 2 Fuzzy inference module FD78K0Notes 1, 2 Fuzzy inference debugger Notes 1. PC-9800 series (MS-DOS) based 2. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS) based 3. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools. 2. RA78K/0, CC78K/0, SM78K/0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78044. 53 µPD78044H, 78045H, 78046H APPENDIX B RELATED DOCUMENTS • Documents Related to Devices Document No. Document name Japanese English µPD78044H Sub-Series User’s Manual To be prepared To be prepared µPD78044H, 78045H, 78046H Data Sheet U10865J This manual µPD78P048B Product Information To be prepared To be prepared 78K/0 Series User’s Manual, Instruction IEU-849 IEU-1372 78K/0 Series Instruction Summary Sheet U10903J — 78K/0 Series Instruction Set U10904J — • Documents Related to Development Tools (User’s Manual) Document No. Document name Japanese RA78K Series Assembler Package Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 EEU-817 EEU-1402 Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Programming Know-How EEA-618 EEA-1208 RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler CC78K/0 Compiler Application Note English CC78K Series Library Source File EEU-777 — PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller PC-9800 Series (MS-DOS) Base EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC DOS) Base EEU-5008 U10540E IE-78000-R EEU-810 U11376E IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-78044-R-EM EEU-833 EEU-1424 EP-78130GF-R EEU-943 EEU-1470 SM78K0 System Simulator Reference EEU-5002 U10181E SM78K Series System Simulator External Parts User Open Interface Specifications U10092J U10092E ID78K0 Integrated Debugger Reference U11151J SD78K/0 Screen Debugger Tutorial EEU-852 PC-9800 Series (MS-DOS) Base Reference U10952J SD78K/0 Screen Debugger Tutorial EEU-5024 EEU-1414 IBM PC/AT (PC DOS) Base Reference U11279J EEU-1413 — U10539E — Caution The above documents may be revised without notice. Use the latest versions when you design an application system. 54 µPD78044H, 78045H, 78046H • Documents Related to Software to Be Incorporated into the Product (User’s Manual) Document No. Document name Japanese 78K/0 Series Real-Time OS OS for 78K/0 Series MX78K0 English Basic EEU-912 — Installation EEU-911 — Technical EEU-913 — Basic EEU-5010 — Tool for Creating Fuzzy Knowledge Data EEU-829 EEU-1438 78K/0, 78K/II, and 87AD Series Fuzzy Inference Development EEU-862 EEU-1444 78K/0 Series Fuzzy Inference Development Support System, Fuzzy Inference Module EEU-858 EEU-1441 78K/0 Series Fuzzy Inference Development Support System, Fuzzy Inference Debugger EEU-921 EEU-1458 Support System, Translator • Other Documents Document No. Document name Japanese English IC PACKAGE MANUAL C10943X SMD Surface Mount Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device IEI-620 IEI-1209 NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 Guide to Quality Assurance for Semiconductor Device MEI-603 Guide for Products Related to Micro-Computer: Other Companies MEI-604 — MEI-1202 — Caution The above documents may be revised without notice. Use the latest versions when you design an application system. 55 µPD78044H, 78045H, 78046H Cautions on CMOS Devices 1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. 2 CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. 3 Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first. FIP is a trademark of NEC Corporation. IEBus is trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. 56 µPD78044H, 78045H, 78046H Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 3 57 µPD78044H, 78045H, 78046H Note that “preliminary” is not indicated in this document, even though the related documents may be preliminary versions. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5