NEC UPD78P368A

DATA SHEET
MOS INTEGRATED CIRCUIT
mPD78P368A
16/8 BIT SINGLE-CHIP MICROCOMPUTER
The m PD78P368A is produced by replacing the internal mask ROM of the m PD78366A with a one-time PROM
or EPROM. One-time PROM products, in which data can be written once are effective for manufacture of small
quantities of multiple products and early stage start-up of application. EPROM products, to which programs can
be re-written after previously written programs have been erased, are suited for system evaluation.
The following user's manual describes the details of functions. Be sure to read it before design.
mPD78366A User's Manual, Hardware: U10205E
mPD78356 User's Manual, Instructions: IEU-1395
FEATURES
• Compatible with the mPD78366A
• Can be replaced with the mPD78366A containing mask ROM on a full-production basis.
• Internal PROM: 48K bytes
• Data can be written once (one-time PROM product without an erasure window)
• Written data can be erased by exposure to ultraviolet light and re-written electrically (EPROM product with an
erasure window)
• PROM programming characteristics: Compatible with the mPD27C1001A
• QTOPTM microcomputer
Remark The QTOP microcomputer is a single-chip microcomputer with a built-in one-time PROM that is totally
supported by NEC. The support includes writing application programs, marking, screening, and
verification.
ORDERING INFORMATION
Part number
mPD78P368AGF-3B9
mPD78P368AKL-S Note
Note
Package
Internal ROM
80-pin plastic QFP (14 ¥ 20 mm)
80-pin ceramic WQFN
One-time PROM
EPROM
Under development
In this manual, the description of the PROM is for both a one-time PROM and EPROM.
The information in this document is subject to change without notice.
Document No. U11373EJ1V0DS00 (1st edition)
(Previous No. IP-3680)
Date Published June 1996 P
Printed in Japan
The mark H shows major revised points.
©
1996
1990
mPD78P368A
PIN CONFIGURATION (TOP VIEW)
(1) Normal operation mode (MODE0 = L, MODE1 = L)
• 80-pin plastic QFP (14 ¥ 20 mm)
mPD78P368AGF-3B9
• 80-pin ceramic WQFN
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P90/RD
P91/WR
P92
P93
ASTB
P80/TO00
P81/TO01
P82/TO02
P83/TO03
P84/TO04
P85/TO05
mPD78P368AKL-S
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VSS
1
64
P52/A10
P00/RTP0
2
63
P51/A9
P01/RTP1
3
62
P50/A8
P02/RTP2
4
61
P47/AD7
P03/RTP3
5
60
P46/AD6
P04/PWM0
6
59
P45/AD5
P05/ TCUD/PWM1
7
58
P44/AD4
P06/ TIUD/TO40
8
57
P43/AD3
P07/ TCLRUD
9
56
P42/AD2
WDTO
10
55
P41/AD1
IC
11
54
P40/AD0
VDD
12
53
VSS
VSS
13
52
VDD
X1
14
51
AVDD
X2
15
50
AVREF
MODE1
16
49
P77/ANI7
RESET
17
48
P76/ANI6
P30/ TXD0
18
47
P75/ANI5
P31/RXD0
19
46
P74/ANI4
P32/SO/SB0
20
45
P73/ANI3
P33/SI/SBI
21
44
P72/ANI2
P34/SCK
22
43
P71/ANI1
P35/ TXD1
23
42
P70/ANI0
P36/RXD1
24
41
AVSS
Caution Directly connect the IC pin to VSS.
Remark Pin compatible with the mPD78366AGF
2
P25/INTP4
P24/INTP3/TI
P23/INTP2
P22/INTP1
P21/INTP0
MODE0
P20/NMI
VSS
P17
P16
P15
P14
P12
P13
P11
P10
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
mPD78P368A
P00-P07:
Port 0
SI:
Serial input
P10-P17:
Port 1
SO:
Serial output
P20-P25:
Port 2
SB0, SB1:
Serial bus
P30-P36:
Port 3
SCK:
Serial clock
P40-P47:
Port 4
PWM0, PWM1:
Pulse width modulation output
P50-P57:
Port 5
WDTO:
Watchdog timer output
P70-P77:
Port 7
MODE0, MODE1:
Mode
P80-P85:
Port 8
AD0-AD7:
Address/data bus
P90-P93:
Port 9
A8-A15:
Address bus
RTP0-RTP3:
Real-time port
ASTB:
Address strobe
NMI:
Nonmaskable interrupt
RD:
Read strobe
INTP0-INTP4:
Interrupt from peripherals
WR:
Write strobe
TO00-TO05, TO40: Timer output
RESET:
Reset
TI:
Timer input
X1, X2:
Crystal
TIUD:
Timer input for up/down
AVDD:
Analog VDD
counter
AVSS:
Analog VSS
TCUD:
Timer control for up/down
AVREF:
Analog reference voltage
counter
VDD:
Power supply
TCLRUD:
Timer clear for up/down
VSS:
Ground
counter
IC:
Internally connected
ANI0-ANI7:
Analog input
TxD0, TxD1:
Transmit data
RxD0, RxD1:
Receive data
3
mPD78P368A
(2) PROM programming mode (MODE0/VPP = H, MODE1 = L)
• 80-pin plastic QFP (14 ¥ 20 mm)
mPD78P368AGF-3B9
• 80-pin ceramic WQFN
(L)
OE
CE
(L)
PGM
A10
A11
A12
A13
A14
A15
mPD78P368AKL-S
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VSS
1
64
A0
2
63
A1
3
62
A2
4
61
D7
A3
5
60
D6
A4
6
59
D5
A5
7
58
D4
A6
8
57
D3
A7
9
56
D2
(Open)
10
55
D1
(G)
11
54
D0
VDD
12
53
VSS
VSS
13
52
VDD
(G)
14
51
VDD
(Open)
15
50
MODE1
16
49
(G)
17
48
A16
18
47
19
46
20
45
21
44
22
43
23
42
24
41
(L)
(L)
(G)
(G)
A8
A9
MODE0/VPP
(L)
VSS
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Caution Symbols in parentheses denote how the pins not used in the PROM programming mode should
be treated.
L:
Connect these pins to the VSS pins through separate resistors.
G:
Connect these pins to the VSS pins.
Open: Do not connect these pins to anything.
4
mPD78P368A
A0-A16: Address bus
MODE0, MODE1:
Programming mode set
D0-D7:
Data bus
VPP:
Programming power supply
CE:
Chip enable
VDD:
Power supply
OE:
Output enable
VSS:
Ground
PGM:
Programming mode
5
6
4
Real-time output
port
Serial
interface
(SBI)
(UART)
Timer/counter unit
(Real-time pulse unit)
A/D
converter
Micro ROM
Micro
sequence
control
General
registers
128 × 8
&
Data
memory
128 × 8
Main RAM
PWM
Watchdog
timer
PROM
48K × 8
&
Peripheral RAM
1792 × 8
System
control
&
Bus
control
&
Prefetch
control
8
17
8
8
Port
OE
PGM
CE
D0-D7
A0-A16
AD0-AD7
A8-A15
Note
MODE0/ VPPNote
MODE1
WR
RD
ASTB
RESET
X2
X1
8
P1
6
P2
7
P3
8
P4
8
P5
8
P7
6
P8
4
P9
2
4
2
8
VDD
VSS
WDTO
PWM
AVDD
AVREF
AVSS
INTP2
ANI
Note Shading indicates the pins used in the PROM programming mode.
ALU
BCU
P0
4
2
2
7
5
5
Programmable
interrupt
controller
PROM/RAM
8
RTP
RxD
TxD
SI/SB1
SO/SB0
SCK
TCLRUD
TCUD
TIUD
TI
TO
INTP
NMI
EXU
mPD78P368A
BLOCK DIAGRAM
mPD78P368A
CONTENTS
1.
PIN FUNCTIONS ........................................................................................................................
8
1.1
8
NORMAL OPERATION MODE (MODE0 = L, MODE1 = L) .........................................................
1.2
PROM PROGRAMMING MODE (MODE0/VPP = H, MODE1 = L) ................................................
10
1.3
INPUT/OUTPUT CIRCUIT TYPE FOR EACH PIN AND HANDLING OF UNUSED PINS ..........
11
2.
MEMORY CONFIGURATION ...................................................................................................
13
3.
DIFFERENCES BETWEEN THE mPD78P368A AND mPD78366A .........................................
14
4.
PROM PROGRAMMING ............................................................................................................
15
4.1
OPERATION MODE ........................................................................................................................
15
4.2
PROCEDURE FOR WRITING ON PROM (PAGE PROGRAM MODE) ...............................
16
4.3
PROCEDURE FOR WRITING ON PROM (BYTE PROGRAM MODE) ................................
18
4.4
PROCEDURE FOR READING FROM PROM ...........................................................................
21
5.
ERASURE CHARACTERISTICS (mPD78P368AKL-S ONLY) ................................................
22
6.
PROTECTIVE FILM COVERING THE ERASURE WINDOW (mPD78P368AKL-S ONLY) ........
22
7.
SCREENING ONE-TIME PROM PRODUCTS ..........................................................................
22
8.
ELECTRICAL SPECIFICATIONS .............................................................................................
23
9.
PACKAGE DRAWINGS .............................................................................................................
39
10. RECOMMENDED SOLDERING CONDITIONS ......................................................................
41
APPENDIX A TOOLS ......................................................................................................................
42
A.1
DEVELOPMENT TOOLS ................................................................................................................
42
A.2
EMBEDDED SOFTWARE ...............................................................................................................
47
APPENDIX B DIMENSIONS OF THE CONVERSION SOCKET AND RECOMMENDED
PATTERN ON BOARDS.........................................................................................
49
7
H
H
mPD78P368A
1. PIN FUNCTIONS
1.1 NORMAL OPERATION MODE (MODE0 = L, MODE1 = L)
(1) Port pins
Pin name
I/O
P00-P03
I/O
P04
Port 0.
8-bit I/O port.
Can be specified as input or output bit by bit.
Dual-function pin
RTP0-RTP3
PWM0
P05
TCUD/PWM1
P06
TIUD/TO40
P07
TCLRUD
P10-P17
I/O
P20
I
P21
Port 1.
8-bit I/O port.
Can be specified as input or output bit by bit.
Port 2.
Port used only for 6-bit input.
–
NMI
INTP0
P22
INTP1
P23
INTP2
P24
INTP3/TI
P25
INTP4
P30
I/O
P31
Port 3.
7-bit I/O port.
Can be specified as input or output bit by bit.
TxD0
RxD0
P32
SO/SB0
P33
SI/SB1
P34
SCK
P35
TxD1
P36
RxD1
AD0-AD7
P40-P47
I/O
Port 4.
8-bit I/O port.
Can be specified as input or output in units of 8 bits.
P50-P57
I/O
Port 5.
8-bit I/O port.
Can be specified as input or output bit by bit.
P70-P77
I
P80-P85
I/O
Port 8.
6-bit I/O port.
Can be specified as input or output bit by bit.
TO00 - TO05
P90
I/O
Port 9.
4-bit I/O port.
Can be specified as input or output bit by bit.
RD
P91
P92
P93
8
Function
Port 7.
Port used only for 8-bit input.
A8-A15
ANI0-ANI7
WR
–
–
mPD78P368A
(2) Non-port pins (1/2)
Pin name
I/O
Function
Dual-function pin
RTP0-RTP3
O
Outputs a pulse in real time as triggered by a trigger signal sent from the
real-time pulse unit.
P00-P03
NMI
I
Nonmaskable interrupt request input
P20
External interrupt request input
P21
INTP0
INTP1
P22
INTP2
P23
INTP3
P24/TI
INTP4
P25
External count clock input to timer 1
P24/INTP3
TCUD
Input for the control signal to determine whether the up/down counter (timer
4) counts up or down.
P05/PWM1
TIUD
External count clock input to the up/down counter (timer 4)
P06/TO40
TI
I
TCLRUD
TO00-TO05
Clear signal input to the up/down counter (timer 4)
O
Pulse output from the real-time pulse unit
TO40
P80-P85
P06/TIUD
ANI0-ANI7
I
Analog input to the A/D converter
TxD0
O
Serial data output from the asynchronous serial interface
P70-P77
P30
P35
TxD1
RxD0
P07
I
Serial data input to the asynchronous serial interface
P31
P36
RxD1
Serial clock I/O for the clock synchronous serial interface
SCK
I/O
SI
I
Serial data input to the clock synchronous serial interface in the 3-wire mode
P33/SB1
SO
O
Serial data output from the clock synchronous serial interface in the 3-wire
mode
P32/SB0
SB0
I/O
Serial data I/O for the clock synchronous serial interface in the SBI mode
P32/SO
P33/SI
SB1
PWM0
P34
O
PWM signal output
P04
P05/TCUD
PWM1
WDTO
O
Output for the signal which indicates the watchdog timer overflowed. (A
nonmaskable interrupt is generated.)
–
AD0-AD7
I/O
Multiplexed address/data bus used when external memory is expanded
P40-P47
Address bus used when external memory is expanded
P50-P57
A8-A15
ASTB
O
Output for the timing signal used in externally latching address information
output from the AD0 to AD7 and A8 to A15 pins, in order to access the
external memory
–
RD
Read strobe signal output to the external memory
P90
WR
Write strobe signal output to the external memory
P91
9
mPD78P368A
(2) Non-port pins (2/2)
Pin name
I/O
Function
Dual-function pin
MODE0
I
Input for the control signal which sets the operation mode. Normally, both
MODE0 and MODE1 are directly connected to the VSS pin.
–
RESET
I
System reset input
–
X1
I
–
X2
–
Crystal input pin for the system clock. A clock signal provided externally is
input to the X1 pin. The reversed signal of the clock signal is input to the
X2 pin.
AVREF
I
A/D converter reference voltage input
–
AVDD
–
Analog power supply for the A/D converter
–
AVSS
–
Ground for the A/D converter
–
VDD
–
Positive power supply
–
VSS
–
Ground
–
IC
–
Internally connected. Directly connect the IC pin to VSS .
–
MODE1
1.2 PROM PROGRAMMING MODE (MODE0/VPP = H, MODE1 = L)
Pin name
10
Function
I/O
MODE0/VPP
I
PROM programming mode set/programming supply voltage
MODE1
I
PROM programming mode set
A0-A16
I
Address bus
D0-D7
I/O
Data bus
PGM
I
Program input
CE
I
Enable PROM
OE
I
Read strobe to PROM
VDD
Positive power supply
VSS
GND
mPD78P368A
1.3 INPUT/OUTPUT CIRCUIT TYPE FOR EACH PIN AND HANDLING OF UNUSED PINS
Table 1-1 lists the input and output circuit type for each pin and how to handle it when it is not used. Fig. 1-1 shows
the circuits.
Table 1-1
Input/Output Circuit Type for Each Pin and Recommended Connection Methods for Unused
Pins
Pin
P00/RTP0-P03/RTP3
I/O circuit type
5-A
Recommended connection method
Input state:
P04/PWM0
Output state:
Each pin is connected to the V DD or
VSS pin via a separate resistor.
Open
P05/TCUD/PWM1
P06/TIUD/TO40
P07/TCLRUD
P10-P17
P20/NMI
P21/INTP0
2
Connected to the VSS pin.
2-A
P22/INTP1
P23/INTP2
P24/INTP3/TI
P25/INTP4
P30/TxD0
5-A
Input state:
P31/RxD0
Output state:
P32/SO/SB0
Each pin is connected to the V DD or
VSS pin via a separate resistor.
Open
8-A
P33/SI/SB1
P34/SCK
P35/TxD1
5-A
P36/RxD1
P40/AD0-P47/AD7
P50/A8-P57/A15
P70/ANI0-P77/ANI7
9
P80/TO00-P85/TO05
5-A
Connected to the VSS pin.
Input state:
P90/RD
Output state:
Each pin is connected to the V DD or
VSS pin via a separate resistor.
Open
P91/WR
P92, P93
ASTB
5
WDTO
19
Connected to the VSS pin.
MODE0, MODE1
1
–
RESET
2
AVREF, AVSS
–
AVDD
Connected to the VSS pin.
Connected to the VDD pin.
11
mPD78P368A
Fig. 1-1 Input/Output Circuits of Each Pin
Type 1
VDD
Type 5-A
VDD
Pull-up
enable
P-ch
P-ch
IN
VDD
P-ch
Data
IN/OUT
Output
disable
N-ch
N-ch
Input
enable
Type 2
Type 8-A
VDD
Pull-up
enable
IN
P-ch
VDD
P-ch
Data
IN/OUT
Output
disable
N-ch
Schmitt trigger input with hysteresis characteristics
Type 2-A
Type 9
Comparator
VDD
P-ch
IN
Pull-up
enable
P-ch
+
N-ch
–
Vref
(Threshold voltage)
IN
Input
enable
Schmitt trigger input with hysterisis characteristics
Type 5
Data
Output
disable
Input
enable
12
Type 19
VDD
P-ch
N-ch
IN/OUT
OUT
N-ch
mPD78P368A
2.
MEMORY CONFIGURATION
The mPD78P368A can access memory of up to 64K bytes. Fig. 2-1 shows the memory map.
Fig. 2-1 Memory Map
MODE 0, 1 = LL
FFFFH
FF00H
FEFFH
Special function
register (SFR)
(256 × 8)
FE80H
Main RAM
(256 × 8)
Data memory
FEFFH
FE25H
FE06H
FE00H
FDFFH
Peripheral RAM
(1792 × 8)
General register
(128 × 8)
Macro service control
(32 × 8)
Data area
(2048 × 8)
F700H
F700H
F6FFH
BFFFH
Memory
space
(64K × 8)
Program area
External memoryNote
(14080 × 8)
Program
memory
Data
memory
1000H
0FFFH
0800H
07FFH
C000H
CALLF instruction
entry area
(2048 × 8)
Program area
BFFFH
0080H
007FH
Internal PROM
(49152 × 8)
CALLT instruction
table area
(64 × 8)
0040H
003FH
Vector table area
(64 × 8)
0000H
0000H
Note Access in the external memory expansion mode.
Caution When word access (including the stack operation) to the main RAM space (FE00H to FEFFH) is
executed, the addresses specified in the operand must be even numbers.
13
mPD78P368A
3. DIFFERENCES BETWEEN THE mPD78P368A AND mPD78366A
The m PD78P368A is produced by replacing the internal mask ROM of the mPD78366A with a 48K-byte PROM.
Both have the same functions except some differences in ROM specifications, such as write and verify modes. Table
3-1 shows the differences.
In this manual, the functions specific to the m PD78P368A are explained. For details of the other functions, refer
to the mPD78366A document.
Table 3-1 Differences between the mPD78P368A and mPD78366A
Part number
mPD78P368A
Item
mPD78366A
ROM
48K bytes
32K bytes
Internal program memory
(Electrical write)
One-time PROM
(Data can be written once)
PROM programming pin
Provided
Not provided
Setting of MODE0 and
MODE1
• Normal operation mode
MODE0, 1 = LL
• PROM programming mode
MODE0, 1 = HL
• Normal operation mode
MODE0, 1 = LL
• ROM-less mode
MODE0, 1 = HH
Package
80-pin plastic QFP
Electrical characteristics
They differ in supply current and other factors.
Others
Since each product has a different circuit scale and mask layout, the noise immunity and
noise radiation of each product differ.
EPROM (Data can be
written multiple times)
80-pin ceramic WQFN
Mask ROM
80-pin plastic QFP
Cautions 1. The PROM and mask ROM products differ in noise immunity and noise radiation. Use not ES
products but CS products (mask ROM products) to evaluate them thoroughly when considering
the change from the PROM products to the mask ROM products during processes from
preproduction to volume production.
2. Connect the MODE0 and MODE1 pins directly to the VDD or VSS pin.
14
mPD78P368A
4. PROM PROGRAMMING
The m PD78P368A is provided with an electrically writable PROM of 48K ¥ 8 bits. When programming this PROM,
use the MODE0/VPP and MODE1 pins to set the mPD78P368A to the PROM programming mode.
The mPD78P368A provides programming characteristics compatibility with the mPD27C1001A.
Table 4-1 Pin Functions in Programming Mode
Normal operation mode
Programming mode
P00-P07, P21, P20, P80-P85, P30
A0-A16
P40-P47
D0-D7
ASTB
PGM
Chip enable
P91
CE
Output enable
P90
Function
Address input
Data input
Program pulse
OE
MODE0/VPP
Program voltage
MODE1
Mode control
4.1 OPERATION MODE
To enter the program write/verify mode, set each pin as follows: MODE0/VPP = H, MODE1 = L. In addition, any
of the operation modes listed in Table 4-2 can be selected by setting the CE, OE, and PGM pins in this mode.
Set the mPD78P368A to the read mode in order to read the contents of PROM.
Handle unused pins as described in PIN CONFIGURATION (2).
Table 4-2 Operation Modes for PROM Programming
MODE1
CE
OE
PGM
MODE0/VPP
VDD
L
H
L
H
+12.5 V
+6.5 V
Page program
H
H
L
High impedance
Byte program
L
H
L
Data input
Program verify
L
L
H
Data output
Program inhibit
¥
¥
L
H
L
H
High impedance
Read
L
L
H
Output disable
L
H
¥
High impedance
Standby
H
¥
¥
High impedance
Mode
Page data latch
+5 V
+5 V
D0-D7
Data input
Data output
Remark ¥: L or H
15
mPD78P368A
4.2
PROCEDURE FOR WRITING ON PROM (PAGE PROGRAM MODE)
The following is a procedure for writing on PROM. (See Fig. 4-1.)
In the page program mode, data is written in units of pages (four bytes). When write data completes midway of
a page, latch FFH after the data so that the data fits into pages.
Always set each pin as follows: MODE0/VPP = H and MODE1 = L. Connect unused pins according to PIN
(1)
CONFIGURATION (2).
(2)
Apply +6.5 V to the VDD pin and +12.5 V to the VPP pin.
(3)
Input an initial address to the A0 to A16 pins.
(4)
Clear the page counter.
(5)
Data latch mode. Input write data to the D0 to D7 pins and input an active-low pulse to the OE pin. Increment
(6)
Repeat step (5) for a page (four bytes).
(7)
Input a 0.1 ms program pulse (active low) to the PGM pin.
(8)
Verify mode. Checks if data has been written in PROM.
the address and the page counter.
Apply a low level to the CE pin, input an active-low pulse to the OE pin, and then read the write data from the
D0 to D7 pins. Repeat this for a page (four bytes). When verification completes, apply a high level to the CE
pin.
• If data has been written, go to step (10).
• If not, repeat steps (7) and (8). If no data is written yet after the steps have been repeated 10 times, go to
step (9).
(9)
Assume the device to be defective and stop write operation.
(10) Increment the address.
(11) Repeat steps (4) to (10) until the address exceeds the last address.
Fig. 4-2 is a timing chart of these steps (2) to (9).
16
mPD78P368A
Fig. 4-1 Flowchart of Procedure for Writing (Page Program Mode)
(1)
Start writing
(2)
Apply power supply voltage
(3)
Set an initial address
(4)
Clear the counter to 0
(5)
Latch write dataNote
Increment the address and counter
(6)
< 4 bytes
Counter
= 4 bytes
(7)
Write failure
(up to 9th)
Input a program pulse
(8)
Write failure (10th)
Verify mode
Write succeeded
(10)
Increment the address
(11)
≤ Last address
Last address
> Last address
Write is completed
(9)
Defective device
Note If write data does not fill a page, latch FFH for the rest of the page.
17
mPD78P368A
Fig. 4-2 PROM Write/Verify Timing Chart (Page Program Mode)
Page data latch
Page program
Address input
A2 - A16
Address input
A0, A1
Data input
D0 - D7
Program verify
Hi-Z
Data output
Hi-Z
Hi-Z
+12.5 V
MODE0/VPP
VDD
+6.5 V
VDD
VDD
CE (input)
PGM (input)
OE (input)
4.3
PROCEDURE FOR WRITING ON PROM (BYTE PROGRAM MODE)
The following is a procedure for writing on PROM. (See Fig. 4-3.)
(1)
Always set each pin as follows: MODE0/VPP = H and MODE1 = L. Connect unused pins according to PIN
CONFIGURATION (2).
(2)
Apply +6.5 V to the VDD pin and +12.5 V to the MODE0/VPP pin, and input a low-level signal to the CE pin.
(3)
Input an initial address to the A0 to A16 pins.
(4)
Input write data to the D0 to D7 pins.
(5)
Input a 0.1 ms program pulse (active low) to the PGM pin.
(6)
Verify mode. Checks if data has been written in PROM.
Input an active-low pulse to the OE pin and read the write data from the D0 to D7 pins.
• If data has been written, go to step (8).
• If not, repeat steps (4) to (6). If no data is written yet after the steps have been repeated 10 times, go to
step (7).
(7)
Assume the device to be defective and stop write operation.
(8)
Increment the address.
(9)
Repeat steps (4) to (8) until the address exceeds the last address.
Fig. 4-4 is a timing chart of these steps (2) to (7).
18
mPD78P368A
Fig. 4-3 Flowchart of Procedure for Writing (Byte Program Mode)
(1)
Start writing
(2)
Apply power supply voltage
(3)
Set an initial address
(4)
Input write data
(5)
Input a program pulse
(6)
Write failure (up to 9th)
Write failure (10th)
Verify mode
Write succeeded
(8)
Increment the address
(9)
≤ Last address
Last address
> Last address
Write is completed
(7)
Defective device
19
mPD78P368A
Fig. 4-4 PROM Write/Verify Timing Chart (Byte Program Mode)
Byte program
A0 - A16
D0 - D7
+12.5 V
MODE0/ VPP
VDD
+6.5 V
VDD
VDD
CE (input)
PGM (input)
OE (input)
20
Program verify
Address input
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
mPD78P368A
4.4
PROCEDURE FOR READING FROM PROM
The following is a procedure for reading out the contents of PROM to the external data bus (D0 to D7).
(1)
Always set each pin as follows: MODE0/V PP = H and MODE1 = L. Connect unused pins according to PIN
CONFIGURATION (2).
(2)
Apply +5 V to the VDD and MODE0/VPP pins.
(3)
Input the address of data to be read into the A0 to A16 pins.
(4)
Read mode (CE = L, OE = L)
(5)
Output the data on the D0 to D7 pins.
Fig. 4-5 is a timing chart of these steps (2) to (5).
Fig. 4-5 PROM Read Timing Chart
A0 - A16
Address input
CE (input)
OE (input)
D0 - D7
Hi-Z
Data output
Hi-Z
21
mPD78P368A
5. ERASURE CHARACTERISTICS (mPD78P368AKL-S ONLY)
Data written in the mPD78P368AKL-S program memory can be erased (FFH); therefore users can write other data
in the memory.
To erase the written data, expose the erasure window to light with a wavelength shorter than approx. 400 nm. Normally,
ultraviolet light with a wavelength of 254 nm is employed. The amount of light required to completely erase the data
is as follows:
• Intensity of ultraviolet light ¥ erasing time: 15 W•s/cm2 min.
• Erasing time: 15 to 20 minutes (When using a 12,000 mW/cm2 ultraviolet lamp. It may, however, take more time
due to lamp deterioration, dirt on the erasure window, or the like.)
The ultraviolet lamp should be placed within 2.5 cm from the erasure window during erasure. In addition, if a filter
is attached to the ultraviolet lamp, remove the filter before erasure.
6. PROTECTIVE FILM COVERING THE ERASURE WINDOW (mPD78P368AKL-S ONLY)
After the erasure window of the mPD78P368AKL-S has been exposed to sunlight or a fluorescent lamp for a long
time, data in EPROM may be erased and the internal circuits may malfunction. To prevent these failures, the erasure
window should be covered with a protective film when it is not used for erasure.
EPROM package products with a window are supplied with a NEC-guaranteed protective film when they are
delivered.
7.
SCREENING ONE-TIME PROM PRODUCTS
NEC cannot execute a complete test of one-time PROM products (mPD78P368AGF-3B9) due to their structure
before shipment. It is recommended that you screen (verify) PROM products after writing necessary data into them
and storing them at 125 °C for 24 hours.
NEC offers a charged service called QTOP microcomputer service. This service includes writing to one-time
PROM, marking, screening, and verification.
22
Ask your sales representative for details.
mPD78P368A
H
8. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T A = 25 °C)
Parameter
Symbol
Power supply voltage
Rating
Unit
V DD
–0.5 to +7.0
V
AV DD
–0.5 to V DD + 0.5
V
VPP
–0.5 to +13.5
V
AVSS
–0.5 to +0.5
V
–0.5 to VDD + 0.5
V
Input voltage
VI
Output voltage
VO
Conditions
Pins other than
P70/ANI0-P77/ANI7
–0.5 to V DD + 0.5
V
Note
20
mA
Output pins other than
those in the note
4.0
mA
Total of all output pins
200
mA
All output pins
–3.0
mA
Total of all output pins
–25
mA
AV SS – 0.5 to AV DD + 0.5
V
AVREF
AVSS – 0.5 to AV DD + 0.5
V
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–60 to +150
°C
Low-level output current
I OL
High-level output current
IOH
Analog input voltage
V IAN
A/D converter reference input voltage
P70/ANI0-P77/ANI7 pins
Note P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40, P07/TCLRUD, P10-P17, and
P80/TO00-P85/TO05 pins.
Caution
Absolute maximum ratings are rated values beyond which some physical damages may be
caused to the product; if any of the parameters in the table above exceeds its rated value even
for a moment, the quality of the product may deteriorate. Be sure to use the product within the
rated values.
RECOMMENDED OPERATING CONDITIONS
Oscillation frequency
TA
3 MHz - f XX - 8 MHz
–40 to +85 °C
VDD
+5.0 V ±10 %
CAPACITANCE (TA = 25 °C, V SS = VDD = 0 V)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input capacitance
CI
f = 1 MHz
20
pF
Output capacitance
CO
0 V except measured pins
20
pF
I/O capacitance
CIO
20
pF
23
mPD78P368A
OSCILLATOR CHARACTERISTICS (T A = –40 to +85 °C, VDD = +5 V ±10 %, V SS = 0 V)
Resonator
Ceramic resonator or
crystal
Recommended circuit
VSS
X1
C1
Parameter
Min.
Max.
Unit
Oscillation frequency (f XX )
3
8
MHz
X1 input frequency (fX )
3
8
MHz
X1 rise/fall time (tXR , t XF )
0
30
ns
X1 input high-/low-level
width (t WXH , t WXL)
40
170
ns
X2
C2
External clock
X1
X2
Open
HCMOS
inverter
Caution When using system clock oscillation circuits, to reduce the effect of the wiring capacitance,
etc, wire the area indicated by dotted-line as follows:
• Make the wiring as short as possible.
• Do not allow the wiring to intersect other signal lines. Keep it away from other lines in which
varying high currents flow.
• Make sure that the ground point of the oscillation circuit capacitor is always at the same electric
potential as VSS. Do not allow the wiring to be grounded to a ground pattern in which very high
currents are flowing.
• Do not extract signals from the oscillation circuit.
24
mPD78P368A
DC CHARACTERISTICS (T A = –40 to +85 °C, VDD = +5 V ±10 %, V SS = 0 V)
Parameter
Low-level input voltage
High-level input voltage
Low-level output voltage
High-level output voltage
Symbol
Conditions
Min.
Typ.
Max.
Unit
VIL1
Note 1
0
0.8
V
VIL2
Note 2
0
0.2V DD
V
V IH1
Note 1
2.2
V
V IH2
Note 2
0.8V DD
V
V OL1
Note 3
I OL = 2.0 mA
0.45
V
V OL2
Note 4
I OL = 15 mA
1.5
V
V OL3
Note 5
I OL = 10 mA
1.5
V
V OH
I OH = –400 mA
V DD – 1.0
V
Input leakage current
ILI
0 V - V I - V DD , AVDD = V DD
±10
mA
Output leakage current
I LO
0 V - V O - VDD, AVDD = V DD
±10
mA
V DD supply current
IDD1
Operating mode
70
120
mA
IDD2
HALT mode
45
70
mA
Data retention voltage
V DDDR
STOP mode
Data retention current
I DDDR
STOP mode
2.5
V DDDR = 2.5 V
V DDDR = 5.0 V ±10 %
Pull-up resistance
RL
VI = 0 V
15
V
2
10
mA
10
50
mA
60
150
Ký
Notes 1. Pins other than those specified in Note 2.
2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3/TI, P25/INTP4, P32/SO/
SB0, P33/SI/SB1 and P34/SCK pins.
3. Pins other than those specified in Notes 4 and 5.
4. P80/TO00-P85/TO05 pins (When IOL = 15 mA is in operation, up to three pins can be ON simultaneously.)
5. P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40 and P07/TCLRUD pins (When
IOL = 10 mA is in operation, up to four pins can be ON simultaneously.) as well as P10-P17 pins (When
IOL = 10 mA is in operation, up to four pins can be ON simultaneously.).
Caution When the P80-P85, P00-P07, and P10-P17 pins are not used under the conditions specified in
Notes 4 and 5, they have the same characteristics as in Note 3.
25
mPD78P368A
AC CHARACTERISTICS (T A = –40 to +85 °C, V DD = +5 V ±10 %, V SS = 0 V, C L = 100 pF, f XX = 8 MHz)
Read/Write Operation (when general-purpose memory is connected)
Parameter
Symbol
Conditions
Min.
Max.
Unit
166.7
ns
System clock cycle time
t CYK
62.5
Address setup time (vs. ASTB Ø)
tSAST
7
ns
Address hold time (vs. ASTB Ø)
t HSTA
11
ns
RD Ø Æ address float time
tFRA
24
ns
Address Æ data input time
t DAID
100
ns
RD Ø Æ data input time
tDRID
49
ns
ASTB Ø Æ RD Ø delay time
tDSTR
15
ns
Data hold time (vs. RD •)
tHRID
0
ns
RD • Æ address active time
tDRA
17
ns
RD low-level width
t WRL
63
ns
ASTB high-level width
tWSTH
14
ns
WR Ø Æ data output time
t DWOD
ASTB Ø Æ WR Ø delay time
tDSTW
15
ns
WR • Æ ASTB • delay time
tDWST
78
ns
Data setup time (vs. WR •)
tSODW
57
ns
Data hold time (vs. WR •)
t HWOD
8
ns
WR low-level width
t WWL
63
ns
21
tCYK-dependent Bus Timing Definition
Parameter
Arithmetic expression
Min./Max.
Unit
tSAST
(0.5 + a) T – 24
Min.
ns
t HSTA
0.5T – 20
Min.
ns
t WSTH
(0.5 + a) T – 17
Min.
ns
tDSTR
0.5T – 16
Min.
ns
t WRL
(1.5 + n) T – 30
Min.
ns
tDAID
(2.5 + a + n) T – 56
Max.
ns
t DRID
(1.5 + n) T – 44
Max.
ns
t DRA
0.5T – 14
Min.
ns
t DSTW
0.5T – 16
Min.
ns
t DWST
1.5T – 15
Min.
ns
tWWL
(1.5 + n) T – 30
Min.
ns
tDWOD
0.5T – 10
Max.
ns
t SODW
(1 + n) T – 5
Min.
ns
Remarks 1. T = tCYK = 1/fCLK (f CLK refers to the internal system clock frequency.)
2. a becomes 1 when the address wait is inserted. Otherwise, it becomes 0.
3. n refers to the number of wait cycles that is inserted by specifying the PWC register.
4. Only the bus timings indicated in this table depend on tCYK.
26
ns
mPD78P368A
SERIAL OPERATION (T A = –40 to +85 °C, V DD = +5 V ±10 %, VSS = 0 V)
Parameter
Serial clock cycle time
Serial clock low-level width
Serial clock high-level width
Symbol
tCYSK
tWSKL
tWSKH
Conditions
Min.
Max.
Unit
SCK output
Internal 8 dividing
500
ns
SCK input
External clock
500
ns
SCK output
Internal 8 dividing
210
ns
SCK input
External clock
210
ns
SCK output
Internal 8 dividing
210
ns
SCK input
External clock
210
ns
SI setup time (vs. SCK •)
t SRXSK
80
ns
SI hold time (vs. SCK •)
tHSKRX
80
ns
SCK Ø Æ SO delay time
tDSKTX
R = 1 ký, C = 100 pF
210
ns
Max.
Unit
UP/DOWN COUNTER OPERATION (TA = –40 to +85 °C, V DD = +5 V ±10 %, V SS = 0 V)
Parameter
TIUD high-/low-level width
TCUD high-/low-level width
Symbol
t WTIUH, t WTIUL
Conditions
Min.
Other than mode 4
2T
ns
Mode 4
4T
ns
t WTCUH, t WTCUL Other than mode 4
2T
ns
Mode 4
4T
ns
2T
ns
TCLRUD high-/low-level width
tWCLUH, t WCLUL
TCUD setup time (vs. TIUD •)
tSTCU
Mode 3
T
ns
TCUD hold time (vs. TIUD •)
tHTCU
Mode 3
T
ns
TIUD setup time (vs. TCUD)
tS4TIU
Mode 4
2T
ns
TIUD hold time (vs. TCUD)
t H4TIU
Mode 4
2T
ns
TIUD & TCUD cycle time
tCYC
Other than mode 4
4
MHz
t CYC4
Mode 4
2
MHz
Remark T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.)
27
mPD78P368A
OTHER OPERATIONS (TA = –40 to +85 °C, VDD = +5 V ±10 %, V SS = 0 V)
Parameter
Symbol
Conditions
Min.
Max.
Unit
NMI high-/low-level width
t WNIH, t WNIL
2
ms
RESET high-/low-level width
t WRSH , t WRSL
1.5
ms
INTP0 high-/low-level width
t WI0H, t WI0L
Ts = T
250
ns
Ts = 4T
1.0
ms
Ts = 8T
2.0
ms
Ts = 16T
4.0
ms
Ts = T
250
ns
Ts = 4T
1.0
ms
Ts = 8T
2.0
ms
Ts = 16T
4.0
ms
Ts = T
250
ns
Ts = 4T
1.0
ms
Ts = T
250
ns
Ts = 4T
1.0
ms
Ts = 8T
2.0
ms
Ts = 16T
4.0
ms
Ts = 64T
16.0
ms
Ts = 128T
32.0
ms
Ts = 256T
64.0
ms
Ts = T
250
ns
Ts = 4T
1.0
ms
Ts = 8T
2.0
ms
Ts = 16T
4.0
ms
INTP1 high-/low-level width
INTP2 high-/low-level width
INTP3(TI) high-/low-level width
INTP4 high-/low-level width
t WI1H, t WI1L
t WI2H, t WI2L
t WI3H, t WI3L
t WI4H, t WI4L
Remarks 1. T = tCYK = 1/fCLK (f CLK refers to the internal system clock frequency.)
2. Ts refers to the input sampling frequency. INTP0-INTP4 can be selected to programmable.
28
mPD78P368A
A/D CONVERTER CHARACTERISTICS (T A = –40 to +85 °C, VDD = +5 V ±10 %, V SS = AVSS = 0 V,
V DD – 0.5 V - AVDD - V DD)
Parameter
Symbol
Conditions
Min.
Resolution
Total
Typ.
10
error Note 1
Conversion time
Sampling time
t CONV
tSAMP
Zero-scale error Note 1
Full-scale error Note 1
Nonlinearity error Note 1
voltage Note 2
Analog input impedance
4.5 V - AV REF - A V DD
±0.4
%FSR
3.4 V - AV REF - A V DD
±0.7
%FSR
±1/2
LSB
62.5 ns - t CYK < 80 ns
208
tCYK
80 ns - t CYK - 166.6 ns
169
tCYK
62.5 ns - t CYK < 80 ns
8
tCYK
80 ns - t CYK - 166.6 ns
6
tCYK
4.5 V - AV REF - A V DD
±1.5
±2.5
LSB
3.4 V - AV REF - A V DD
±1.5
±4.5
LSB
4.5 V - AV REF - A V DD
±1.5
±2.5
LSB
3.4 V - AV REF - A V DD
±1.5
±4.5
LSB
4.5 V - AV REF - A V DD
±1.5
±2.5
LSB
3.4 V - AV REF - A V DD
±1.5
±4.5
LSB
AV REF + 0.3
V
VIAN
R AN
–0.3
When not sampling
10
AV REF
AV REF1 current
AIREF
AV DD supply current
AIDD
A/D converter data
retention current
AI DDDR
3.4
AVDD
V
1.0
3.0
mA
2.0
6.0
mA
AVDDDR = 2.5 V
2
10
mA
AV DDDR = 5 V ±10 %
10
50
mA
Operating mode
STOP mode
MW
Note 3
When sampling
Reference voltage
Unit
bit
Quantization error
Analog input
Max.
Notes 1. The quantization error is excluded.
2. When –0.3 V - VIAN - 0 V, the conversion result becomes 000H.
When 0 V < VIAN < AV REF, the conversion is performed with the 10-bit resolution.
When AVREF - VIAN - AV REF + 0.3 V, the conversion result becomes 3FFH.
3. The analog input impedance at the time of sampling is the same as the equivalent circuit shown below.
(The values in the diagram are TYP. values; they are not guaranteed values.)
1 kΩ
Analog input pin
25 pF
(Input
capacitance
included)
1.4 pF
29
mPD78P368A
Cautions 1. When using the P70/ANI0-P77/ANI7 pins for both digital and analog inputs, the previously
described characteristics are not guaranteed. Therefore, ensure that all of the eight P70/
ANI0-P77/ANI7 pins are used either for analog input or digital input.
2. When using the P70/ANI0-P77/ANI7 pins as digital input, make sure to set that AVDD = V DD,
and AVSS = VSS .
AC Timing Test Point
VDD
0.8VDD or 2.2 V
0.8VDD or 2.2 V
Test point
0.2VDD or 0.8 V
0V
30
0.2VDD or 0.8 V
mPD78P368A
Read Operation
tCYK
(CLK)
A8 - A15
(output)
High-order address
tDAID
tSAST
AD0 - AD7
(input/output)
Hi-Z
High-order address
Hi-Z
Low-order address (output)
Hi-Z
Data (input)
tWSTH
Low-order address (output)
Hi-Z
tHRID
ASTB
(output)
tHSTA
tFRA
RD
(output)
tDSTR
tDRID
tDRA
tWRL
Write Operation
(CLK)
A8 - A15
(output)
High-order address
High-order address
tSAST
AD0 - AD7
(output)
Low-order address (output)
Undefined
Data (output)
tWSTH
Low-order address (output)
tHWOD
ASTB
(output)
tHSTA
tDWST
WR
(output)
tDSTW
tDWOD
tSODW
tWWL
31
mPD78P368A
Serial Operation
tCYSK
tWSKH
tWSKL
SCK
tDSKTX
SO
SI
tSRXSK
tHSKRX
Up/Down Counter (Timer 4) Input Timing
tWTIUH
TIUD
tWTIUL
tSTCU
tHTCU
tWTCUL
TCUD
tWTCUH
tWCLUH
TCLRUD
tWCLUL
TIUD
tS4TIU
TCUD
32
tH4TIU
tS4TIU
tH4TIU
mPD78P368A
Interrupt Input Timing
tWNIH
tWNIL
0.8VDD
NMI
0.2VDD
tWInH
tWInL
0.8VDD
INTPn
0.2VDD
Remark n = 0 – 4
Reset Input Timing
tWRSH
tWRSL
0.8VDD
RESET
0.2VDD
33
mPD78P368A
DC PROGRAMMING CHARACTERISTICS (TA = 25 ±5 °C, VSS = 0 V)
Symbol
SymbolNote 1
High-level input
voltage
VIH
VIH
Low-level input
voltage
VIL
VIL
Input leakage current
ILIP
ILI
High-level output
voltage
VOH
VOH
IOH = –400 mA
Low-level output
voltage
VOL
VOL
IOL = 2.1 mA
0.45
V
Output leakage
current
ILO
–
0 - VO - V DDP, OE = V IH
±10
mA
VDDP supply voltage
VDDP
VCC
Parameter
VPP supply voltage
VDDP supply current
VPP supply current
VPP
IDD
IPP
VPP
IDD
IPP
Conditions
Min.
Max.
Unit
2.4
VDDP + 0.3
V
–0.3
0.8
V
±10
mA
0 - VI - VDDPNote 2
2.4
V
Program memory write mode
6.25
6.5
6.75
V
Program memory read mode
4.5
5.0
5.5
V
Program memory write mode
12.2
12.5
12.8
V
Program memory read mode
VDD – 0.6
VDD
VDD + 0.6
V
Program memory write mode
50
mA
Program memory read mode
50
mA
Program memory write mode
50
mA
Program memory read mode
100
mA
Notes 1. Symbols for the corresponding mPD27C1001A
2. The VDDP represents the VDD pin as viewed in the programming mode.
34
Typ.
mPD78P368A
AC PROGRAMMING CHARACTERISTICS (TA = 25 ±5 °C, VSS = 0 V)
PROM Write Mode (Page Program Mode)
Parameter
SymbolNote 1
Conditions
Min.
Typ.
Max.
Unit
Address set up time
tAS
2
ms
CE set time
tCES
2
ms
Input data setup time
tDS
2
ms
Address hold time
tAH
2
ms
tAHL
2
ms
tAHV
0
ms
Input data hold time
tDH
2
ms
Output data hold time
tDF
0
VPP setup time
tVPS
1
ms
VDDP setup time
tVDSNote 2
1
ms
Initial program pulse width
tPW
0.095
OE set time
tOES
2
Valid data delay time from OE
tOE
OE pulse width in the data latch
tLW
1
ms
PGM setup time
tPGMS
2
ms
CE hold time
tCEH
2
ms
OE hold time
tOEH
2
ms
250
0.105
ns
ms
ms
1.0
ms
Notes 1. These symbols (except t VDS) correspond to those of the mPD27C1001A.
2. For mPD27C1001A, read tVDS as tVCS.
35
mPD78P368A
PROM Write Mode (Byte Program Mode)
Parameter
SymbolNote 1
Conditions
Min.
Typ.
Max.
Unit
Address set up time
tAS
2
ms
CE set time
tCES
2
ms
Input data setup time
tDS
2
ms
Address hold time
tAH
2
ms
Input data hold time
tDH
2
ms
Output data hold time
tDF
0
VPP setup time
tVPS
1
ms
VDDP setup time
tVDSNote 2
1
ms
Initial program pulse width
tPW
0.095
OE set time
tOES
2
Valid data delay time from OE
tOE
250
0.105
ns
ms
ms
1.0
ms
Max.
Unit
Notes 1. These symbols (except t VDS) correspond to those of the mPD27C1001A.
2. For mPD27C1001A, read tVDS as tVCS.
PROM Read Mode
Symbol Note
Conditions
Data output time from address
tACC
CE = OE = VIL
1.0
ms
CE Ø Æ data output time
tCE
OE = VIL
1.0
ms
OE Ø Æ data output time
tOE
CE = V IL
1.0
ms
Data hold time to OE •
tDF
CE = V IL
0
250
ns
Data hold time to address
tOH
CE = OE = VIL
0
Parameter
Note These symbols correspond to those of the mPD27C1001A.
36
Min.
Typ.
ns
mPD78P368A
PROM Write Mode Timing (Page Program Mode)
Page data latch
Page program
Program verify
A2 - A16
tAS
tAHL
tAHV
tDS
tDH
tDF
A0, A1
D0 - D7
Hi-Z
Hi-Z
tVPS
Data input
Hi-Z
tPGMS
tOE
Data
output
tAH
VPP
VPP
VDDP
tVDS
VDDP + 1.5
VDDP
VDDP
tCES
tOEH
VIH
CE
VIL
tCEH
tPW
VIH
PGM
VIL
VIH
tLW
tOES
OE
VIL
37
mPD78P368A
PROM Write Mode Timing (Byte Program Mode)
Program
Program verify
A0 - A16
tAS
D0 - D7
Hi-Z
tDF
Hi-Z
Data input
tDS
Hi-Z
Data output
tDH
tAH
VPP
VPP
VDDP
tVPS
VDDP + 1.5
VDDP
VDDP
tVDS
VIH
CE
VIL
tCES
tPW
VIH
PGM
VIL
tOES
tOE
VIH
OE
VIL
Cautions 1. VDDP must be applied before V PP, and must be cut after V PP.
2. VPP including overshoot must not exceed +13.5 V.
3. Plugging in or out the board with the VPP pin supplied with +12.5 V may adversely affect its
reliability.
PROM Read Mode Timing
Valid address
A0 - A16
CE
tCE
OE
tDFNote 2
tACCNote 1
D0 - D7
Hi-Z
tOE
Note 1
tOH
Data output
Hi-Z
Notes 1. For reading within t ACC, the delay of the OE input from falling edge of CE must be within tACC – tOE.
2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster.
38
mPD78P368A
9. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14 20)
A
B
41
40
64
65
detail of lead end
S
C D
Q
R
25
24
80
1
F
G
J
H
I
M
K
P
M
N
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
L
ITEM
MILLIMETERS
INCHES
A
23.6±0.4
0.929±0.016
B
20.0±0.2
0.795 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.6±0.4
0.693±0.016
F
1.0
0.039
G
0.8
0.031
H
0.35±0.10
0.014 +0.004
–0.005
0.006
I
0.15
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8±0.2
0.071 +0.008
–0.009
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1±0.1
0.004±0.004
R
S
5°±5°
5°±5°
3.0 MAX.
0.119 MAX.
P80GF-80-3B9-3
39
mPD78P368A
80 PIN CERAMIC WQFN
A
B
Q
C
D
U1
T
S
80
W
K
1
H
I
M
F
G
J
Z
X80KW-80A1
NOTE
Each lead centerline is located within 0.08
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
20.0 ± 0.25
0.787+0.011
–0.010
B
19.0
0.748
C
13.4
0.528
D
14.2 ± 0.2
0.559 ± 0.008
F
1.84
0.072
G
3.56MAX.
0.141MAX.
H
0.51 ± 0.1
0.02 ± 0.004
I
0.08
0.003
J
0.8 (T.P.)
K
1.0±0.15
Q
C0.3
0.031 (T.P.)
+ 0.007
0.039 – 0.006
C0.012
R
0.8
0.031
S
1.1
0.043
T
φ 7.62
φ 0.3
2.6
0.102
0.03+0.006
– 0.007
0.004
U1
40
W
0.75±0.15
Z
0.10
R
mPD78P368A
H
10. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the conditions recommended below.
For details of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535J).
For soldering methods and conditions other than those recommended, please contact your NEC sales
representative.
Table 10-1. Surface Mount Type Soldering Conditions
m PD78P368AGF-3B9: 80-Pin Plastic QFP (14 ¥ 20 mm)
Soldering method
Infrared reflow
Soldering conditions
Package peak temperature: 235 °C, Duration: 30 sec. max. (210 °C or above)
Number of times: 2 max.
Exposure limit: 7 days Note (20 hours of pre-baking is required at 125 °C
Recommended
condition symbol
IR35-207-2
afterward)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be baked
before unpacking.
VPS
Package peak temperature: 215 °C, Duration: 40 sec. max. (200 °C or above)
Number of times: 2 max.
Exposure limit: 7 days Note (20 hours of pre-baking is required at 125 °C
afterward)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be baked
before unpacking.
VP15-207-2
Wave soldering
Solder bath temperature: 260 °C or less, Time: 10 sec. max.,
Number of times: 1, Pre-heating temperature: 120 °C max. (Package surface
temperature)
Exposure limit: 7 days Note (20 hours of pre-baking is required at 125 °C
WS60-207-1
afterward)
Partial heating
Pin temperature: 300 °C or less
–
Duration: 3 sec. max. (per side of device)
Note Maximum number of days during which the product can be stored at a temperature of 25 °C and a relative
humidity of 65 % or less after dry-pack package is opened.
Caution Use of more than one soldering method should be avoided (except in the case of partial heating).
41
mPD78P368A
APPENDIX A TOOLS
A.1 DEVELOPMENT TOOLS
The following tools are provided for developing a system that uses the mPD78P368A:
Language processor
78K/III series relocatable assembler
(RA78K3)
This relocatable program can be used for all 78K/III series emulators. With its
macro functions, it allows the user to improve program development efficiency.
A structured-programming assembler is also provided, which enables explicit
description of program control structures. This assembler could improve productivity in program production and maintenance.
Host machine
Part number
OS
PC-9800 series
MS-DOSTM
IBM PC/ATTM or
compatibles
PC DOSTM
HP9000 series
700 TM
HP-UXTM
SPARCstationTM SunOSTM
NEWS TM
78K/III series C compiler
(CC78K3)
NEWS-OSTM
Distribution media
3.5-inch 2HD
mS5A13RA78K3
5.25-inch 2HD
mS5A10RA78K3
3.5-inch 2HC
mS7B13RA78K3
5.25-inch 2HC
mS7B10RA78K3
DAT
mS3P16RA78K3
Cartridge tape
(QIC-24)
mS3K15RA78K3
mS3R15RA78K3
This C compiler can be used for all 78K/III series emulators. The compiler
converts programs written in C language into object codes executable on the
microcomputer. When the compiler is used, the 78K/III series relocatable
assembler package (RA78K3) is needed.
Host machine
Part number
OS
PC-9800 series MS-DOS
Distribution media
3.5-inch 2HD
mS5A13CC78K3
5.25-inch 2HD
mS5A10CC78K3
3.5-inch 2HC
mS7B13CC78K3
5.25-inch 2HC
mS7B10CC78K3
IBM PC/AT or
compatibles
PC DOS
HP9000 series
700
HP-UX
DAT
mS3P16CC78K3
SPARCstation
SunOS
mS3K15CC78K3
NEWS
NEWS-OS
Cartridge tape
(QIC-24)
mS3R15CC78K3
Remark It is guaranteed that the relocatable assembler and C compiler run only under the OSs on the
corresponding host machines described above.
42
mPD78P368A
PROM programming tools
Hardware
Software
PG-1500
The PG-1500 PROM programmer is used together with an accessory board and
optional program adapter. It allows the user to program a single chip microcomputer containing PROM independently or from a host machine. The PG-1500 can
be used to program typical 256K-bit to 4M-bit PROMs.
PA-78P368GF
PA-78P368KL
Programmer adapter for writing programs to the mPD78P368A. Used with a
PROM programmer such as the PG-1500.
PA-78P368GF : For mPD78P368AGF
PA-78P368KL : For mPD78P368AKL
PG-1500 controller
This program enables the host machine to control the PG-1500 through the serial
and parallel interfaces.
Host machine
Part number
OS
PC-9800 series
IBM PC/AT or
compatibles
MS-DOS
PC DOS
Distribution media
3.5-inch 2HD
mS5A13PG1500
5.25-inch 2HD
mS5A10PG1500
3.5-inch 2HC
mS7B13PG1500
5.25-inch 2HC
mS7B10PG1500
Remark It is guaranteed that the PG-1500 controller runs only under the OSs on the corresponding host machines
described above.
Debugging tools (when the IE controller is used)
Hardware
IE-78350-R
In-circuit emulator for developing and debugging an application system. For
debugging, connect the emulator to the host machine.
IE-78365-R-EM1
I/O emulation board for emulating peripheral hardware such as the I/O ports
of the target device.
EP-78365GF-R
Emulation probe for connecting the IE-78350-R to the target system.
One EV-9200G-80 conversion socket is provided for connection to the target
system.
EV-9200G-80
Software
IE-78350-R control program
(IE controller)
This control program allows the user to control the IE-78350-R from the host
machine. Its automatic command execution function ensures more efficient
debugging.
Part number
Host machine
OS
PC-9800 series
IBM PC/AT or
compatibles
MS-DOS
PC DOS
Distribution media
3.5-inch 2HD
mS5A13IE78365A
H
5.25-inch 2HD
mS5A10IE78365A
H
3.5-inch 2HC
mS7B13IE78365A
H
5.25-inch 2HC
mS7B10IE78365A
H
Remark It is guaranteed that the IE controller runs only under the OSs on the corresponding host machines
described above.
43
mPD78P368A
Configuration of development tools (when the IE controller is used)
Host machine:
PC-9800 series
IBM PC/AT
EWS
RS-232-C
IE-78350-R
in-circuit emulator
+
IE-78365-R-EM1
I/O emulation board
(option)
Emulation probe
Software
RS-232-C
PROM programmer
Relocatable
assembler
C compiler
PG-1500
controller
EP-78365GF-R
+
PG-1500
Socket for connecting the
emulation probe and target
systemNote
IE controller
Device containing PROM
µPD78P368AGF
EV-9200G-80
µPD78P368AKL
+
Programmer adapter
+
Target system
PA-78P368GF
PA-78P368KL
Note The socket is supplied with the emulation probe.
Remarks 1. The PG-1500 can be directly connected to the host machine via the RS-232-C interface.
2. In this figure, the distribution media of software is represented by the 3.5-inch floppy disk.
44
mPD78P368A
Debugging tools (when the integrated debugger is used)
Hardware
Software
IE-784000-R
In-circuit emulator for developing and debugging an application system. For
debugging, connect the emulator to the host machine.
IE-78350-R-EM-A Note
Emulation board for emulating peripheral hardware such as the I/O ports of the
target device.
IE-78365-R-EM1
I/O emulation board for emulating peripheral hardware such as the I/O ports of
the target device.
EP-78365GF-R
EV-9200G-80
Emulation probe for connecting the IE-784000-R to the target system. One EV9200G-80 conversion socket is provided for connection to the target system.
IE-70000-98-IF-B
Interface adapter when the PC-9800 series computer (other than a notebook) is
used as the host machine.
IE-70000-98N-IF
Interface adapter and cable when a PC-9800 series notebook is used as the host
machine.
IE-70000-PC-IF-B
Interface adapter when the IBM PC/AT is used as the host machine.
IE-78000-R-SV3
Interface adapter and cable when the EWS is used as the host machine.
Integrated debugger
(ID78K3)
Program for controlling the in-circuit emulator for the 78K/III series. The integrated debugger (ID78K3) is used together with the device file (DF78365).
Debugging can be performed for the source program written in C, structured
assembly language, or assembly language. The ID78K3 can display various
information simultaneously on the host machine screen divided into multiple
areas. This ensures efficient debugging.
Host machine
Part number
OS
PC-9800 series
MS-DOS
+
WindowsTM
3.5-inch 2HD
mSAA13ID78K3
5.25-inch 2HD
mSAA10ID78K3
IBM PC/AT or
compatibles
(Japanese Windows)
PC DOS
+
Windows
3.5-inch 2HC
mSAB13ID78K3
5.25-inch 2HC
mSAB10ID78K3
3.5-inch 2HC
mSBB13ID78K3
5.25-inch 2HC
mSBB10ID78K3
IBM PC/AT or
compatibles
(Windows)
Device file (DF78365)
Distribution media
File which contains the device-specific information. The device file (DF78365) is
used together with the assembler (RA78K3), C compiler (CC78K3), or integrated
debugger (ID78K3).
Host machine
OS
PC-9800 series
MS-DOS
IBM PC/AT or
compatibles
PC DOS
Distribution media
Part number
3.5-inch 2HD
mS5A13DF78365
5.25-inch 2HD
mS5A10DF78365
3.5-inch 2HC
mS7B13DF78365
5.25-inch 2HC
mS7B10DF78365
Note Under development
Remark It is guaranteed that the integrated debugger and device file run only under the OSs on the corresponding
host machines described above.
45
mPD78P368A
Configuration of development tools (when the integrated debugger is used)
Host machine:
PC-9800 series
IBM PC/AT
EWS
IE-70000-98-IF-B
IE-70000-98N-IF
IE-70000-PC-IF-B
Software
RS-232-C
IE-784000-R
in-circuit emulator
+
IE-78350-R-EM-A
emulation board
(option)
+
IE-78365-R-EM1
I/O emulation board
(option)
Emulation probe
EP-78365GF-R
Relocatable
assembler
C compiler
PG-1500
controller
+
PROM programmer
PG-1500
Integrated
debugger
Socket for connecting the
emulation probe and target
systemNote
Device file
EV-9200G-80
Device containing PROM
µPD78P368AGF
µPD78P368AKL
+
Programmer adapter
PA-78P368GF
+
Target system
PA-78P368KL
Note The socket is supplied with the emulation probe.
Remarks 1. In this figure, the host machine is represented by the desktop personal computer.
2. In this figure, the distribution media of software is represented by the 3.5-inch floppy disk.
46
mPD78P368A
A.2 EMBEDDED SOFTWARE
To improve the efficiency of program development and simplify the maintenance of systems incorporating this
microcontroller, the following embedded software is provided.
Real-time OS
Real-time OS
(RX78K/III) Note
This operating system was designed to provide a multitasking environment for control
applications that require real-time processing. System performance is improved by using
the idling CPU for other processing.
RX78K/III provides system calls that conform to mITRON specifications.
The RX78K/III package provides the RX78K/III nucleus and a tool (Configurator) that is used
for creating multiple information tables.
Part number
Host machine
OS
PC-9800 series
IBM PC/AT or
compatibles
MS-DOS
PC DOS
Distribution media
3.5-inch 2HD
Undecided
5.25-inch 2HD
Undecided
3.5-inch 2HC
Undecided
5.25-inch 2HC
Undecided
Note Under development
Caution Before purchasing this software, complete the purchase application sheet and sign the software
license agreement.
Remark To use the RX78K/III real-time operating system, the optional RA78K3 assembler package is required.
47
mPD78P368A
Fuzzy inference development support system
Tool for creating fuzzy
knowledge data
(FE9000, FE9200)
This program supports the input/editing and simulation of fuzzy knowledge data (fuzzy rules
and membership functions).
Part number
Host machine
OS
PC-9800 series
IBM PC/AT or
compatibles
Translator
(FT78K3) Note
Distribution media
3.5-inch 2HD
mS5A13FE9000
5.25-inch 2HD
mS5A10FE9000
PC DOS
3.5-inch 2HC
mS7B13FE9200
Windows
5.25-inch 2HC
mS7B10FE9200
MS-DOS
+
This program converts fuzzy knowledge data, obtained using the tool for creating fuzzy
knowledge data, into an assembler source program for RA78K3.
Part number
Host machine
OS
PC-9800 series
IBM PC/AT or
compatibles
Fuzzy inference module
(FI78K/III)Note
MS-DOS
PC DOS
mS5A13FT78K3
5.25-inch 2HD
mS5A10FT78K3
3.5-inch 2HC
mS7B13FT78K3
5.25-inch 2HC
mS7B10FT78K3
Part number
OS
PC-9800 series
IBM PC/AT or
compatibles
(FD78K/III)
3.5-inch 2HD
This program performs fuzzy inference by linking the fuzzy knowledge data converted by
Translator.
Host machine
Fuzzy inference debugger
Distribution media
MS-DOS
PC DOS
Distribution media
3.5-inch 2HD
mS5A13FI78K3
5.25-inch 2HD
mS5A10FI78K3
3.5-inch 2HC
mS7B13FI78K3
5.25-inch 2HC
mS7B10FI78K3
This software supports the evaluation and adjustment of fuzzy knowledge data at the
hardware level, by using an in-circuit emulator.
Part number
Host machine
OS
PC-9800 series
IBM PC/AT or
compatibles
Note Under development
48
MS-DOS
PC DOS
Distribution media
3.5-inch 2HD
mS5A13FD78K3
5.25-inch 2HD
mS5A10FD78K3
3.5-inch 2HC
mS7B13FD78K3
5.25-inch 2HC
mS7B10FD78K3
mPD78P368A
APPENDIX B DIMENSIONS OF THE CONVERSION SOCKET AND RECOMMENDED PATTERN
ON BOARDS
Fig. B-1 Dimensions of the Conversion Socket (EV-9200G-80)(Reference)
Based on EV-9200G-80
(1) Package drawing (in mm)
A
N
O
G
P
R
B
L
M
U
K
E
D
C
T
S
F
EV-9200G-80
1
Q
No.1 pin index
H
I
J
EV-9200G-80-G0
ITEM
MILLIMETERS
INCHES
A
25.0
0.984
B
20.30
0.799
C
4.0
0.157
D
14.45
0.569
E
19.0
0.748
F
4-C 2.8
4-C 0.11
G
0.8
0.031
H
11.0
0.433
I
22.0
0.866
J
24.7
0.972
K
5.0
0.197
L
16.2
0.638
M
18.9
0.744
O
8.0
0.315
N
7.8
0.307
P
2.5
0.098
Q
2.0
0.079
R
1.35
0.053
S
0.35 ± 0.1
0.014+0.004
–0.005
T
φ 2.3
φ 0.091
U
φ 1.5
φ 0.059
49
mPD78P368A
Fig. B-2 Recommended Pattern on Boards for the Conversion Socket (EV-9200G-80)(Reference)
Based on EV-9200G-80
(2) Pad drawing (in mm)
G
J
H
I
D
E
F
L
K
M
C
B
A
EV-9200G-80-P0
ITEM
MILLIMETERS
A
25.7
B
21.0
1.012
0.827
C
0.8±0.02 × 23=18.4±0.05
D
+0.003
0.8±0.02 × 15=12.0±0.05 0.031+0.002
–0.001 × 0.591=0.472 –0.002
0.031+0.002
–0.001
× 0.906=0.724 +0.003
–0.002
E
15.2
0.598
F
19.9
0.783
G
11.00 ± 0.08
0.433+0.004
–0.003
H
5.50 ± 0.03
0.217+0.001
–0.002
I
5.00 ± 0.08
0.197+0.003
–0.004
J
2.50 ± 0.03
0.098+0.002
–0.001
K
0.5 ± 0.02
0.02+0.001
–0.002
L
φ 2.36 ± 0.03
φ 0.093+0.001
–0.002
M
φ 1.57 ± 0.03
φ 0.062+0.001
–0.002
Caution
50
INCHES
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (IEI-1207).
mPD78P368A
Cautions on CMOS Devices
Countermeasures against static electricity for all MOSs
Caution When handling MOS devices, take care so that they are not electrostatically charged.
Strong static electricity may cause dielectric breakdown in gates. When transporting or storing
MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC
uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not
allow MOS devices to stand on plastic plates or do not touch pins.
Also handle boards on which MOS devices are mounted in the same way.
CMOS-specific handling of unused input pins
Caution Hold CMOS devices at a fixed input level.
Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting
in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused
pins may function as output pins at unexpected times, each unused pin should be separately
connected to the VDD or GND pin through a resistor.
If handling of unused pins is documented, follow the instructions in the document.
Statuses of all MOS devices at initialization
Caution The initial status of a MOS device is unpredictable when power is turned on.
Since characteristics of a MOS device are determined by the amount of ions implanted in
molecules, the initial status cannot be determined in the manufacture process. NEC has no
responsibility for the output statuses of pins, input and output settings, and the contents of
registers at power on. However, NEC assures operation after reset and items for mode setting
if they are defined.
When you turn on a device having a reset function, be sure to reset the device first.
QTOP is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
TRON stands for The Realtime Operating system Nucleus.
ITRON stands for Industrial TRON.
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mPD78P368A
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed
The customer must judge the need for license
: mPD78P368AKL-S
: mPD78P368AGF-3B9
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94. 11
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