DATA SHEET MOS INTEGRATED CIRCUIT µ PD8862 (2700 + 2700) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The µ PD8862 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µ PD8862 has 3 rows of (2700 + 2700) staggered pixels, and each row has a dual-sided readout-type charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on. FEATURES • Valid photocell : (2700 + 2700) staggered pixels × 3 • Photocell pitch : 5.25 µ m • Line spacing : 63 µ m (12 lines) Red line - Green line, Green line - Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) • Resolution : 24 dot/mm A4 (210 × 297 mm) size (shorter side) 10.5 µ m (2 lines) Odd line - Even line (for each color) 7 600 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate : 6 MHz Max. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number µ PD8862CY Package CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16033EJ3V0DS00 (3rd edition) Date Published July 2003 NS CP (K) Printed in Japan The mark shows major revised points. 2002 µ PD8862 BLOCK DIAGRAM VOD GND φ 2L φ2 φ1 19 11 17 15 14 φTG1 (Blue) 12 φ TG2 (Green) 10 φ TG3 (Red) D70 D68 S5399 D67 Photocell (Blue) S5400 S2 ······ D66 D14 S1 VOUT1 20 (Blue) 13 D69 CCD analog shift register Transfer gate Transfer gate CCD analog shift register D69 D68 D70 S5399 Photocell (Green) S5400 S2 ······ D66 D14 S1 VOUT2 21 (Green) D67 CCD analog shift register Transfer gate Transfer gate CCD analog shift register D69 D70 D68 S5399 Photocell (Red) S5400 S2 ······ D66 D14 S1 VOUT3 22 (Red) D67 CCD analog shift register Transfer gate Transfer gate CCD analog shift register 3 2 φ CLB φ RB 2 4 8 9 φ 1L φ2 φ1 Data Sheet S16033EJ3V0DS µ PD8862 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) • µ PD8862CY 22 VOUT3 Output signal 3 (Red) Reset gate clock φ RB 2 21 VOUT2 Output signal 2 (Green) Reset feed-through level clamp clock φ CLB 3 20 VOUT1 Output signal 1 (Blue) Last stage shift register clock 1 φ1L 4 19 VOD Output drain voltage No connection NC 5 18 NC No connection No connection NC 6 17 φ 2L Last stage shift register clock 2 No connection NC 7 16 NC No connection Shift register clock 2 φ2 8 15 φ2 Shift register clock 2 Shift register clock 1 φ1 9 14 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φ TG3 10 13 φ TG1 Transfer gate clock 1 (for Blue) Ground GND 11 12 φ TG2 Transfer gate clock 2 (for Green) Blue 5400 Green 5400 Red 5400 1 1 1 NC 1 No connection Caution Connect the No connection pins (NC) to GND. Data Sheet S16033EJ3V0DS 3 µ PD8862 PHOTOCELL STRUCTURE DIAGRAM 2.5 µ m 5.25 µ m 2.75 µ m Channel stopper Aluminum shield PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 5.25 µ m 5.25 µ m 5.25 µ m Blue photocell array Blue photocell array 2 lines (10.5 µ m) 10 lines (52.5 µ m) 5.25 µ m 5.25 µ m 5.25 µ m Green photocell array Green photocell array 2 lines (10.5 µ m) 10 lines (52.5 µ m) 5.25 µ m 5.25 µ m 5.25 µ m 4 Red photocell array Red photocell array Data Sheet S16033EJ3V0DS 12 lines (63 µ m) 2 lines (10.5 µ m) 12 lines (63 µ m) µ PD8862 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +15 V Shift register clock voltage Vφ 1, Vφ 2, Vφ 1L, Vφ 2L −0.3 to +8 V Reset gate clock voltage Vφ RB −0.3 to +8 V Reset feed-through level clamp clock Vφ CLB −0.3 to +8 V Vφ TG1 to Vφ TG3 −0.3 to +8 V TA 0 to +60 °C Tstg −40 to +70 °C voltage Transfer gate clock voltage Operating ambient temperature Note Storage temperature Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Symbol Min. Typ. Max. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level Vφ 1_H, Vφ 2_H, Vφ 1LH, Vφ 2LH 4.75 5.0 5.5 V Shift register clock low level Vφ 1_L, Vφ 2_L, Vφ 1LL, Vφ 2LL −0.3 0 +0.25 V Reset gate clock high level Vφ RBH 4.5 5.0 5.5 V Reset gate clock low level Vφ RBL −0.3 0 +0.5 V Reset feed-through level clamp clock Vφ CLBH 4.5 5.0 5.5 V Vφ CLBL −0.3 0 +0.5 V Transfer gate clock high level Vφ TG1H to Vφ TG3H 4.75 Vφ 1_H Transfer gate clock low level Vφ TG1L to Vφ TG3L −0.3 0 +0.15 V Data rate fφ RB − 2.0 6.0 MHz high level Reset feed-through level clamp clock low level Note Vφ 1_H Note V Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1_H), Image lag can increase. Data Sheet S16033EJ3V0DS 5 µ PD8862 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Min. Typ. Max. Unit Vsat 2.0 2.5 − V Red SER − 0.421 − lx•s Green SEG − 0.477 − lx•s Blue SEB − 0.740 − lx•s Saturation voltage Saturation exposure Test Conditions PRNU VOUT = 1.0 V − 6 20 % Average dark signal ADS Light shielding − 0.2 2.0 mV Dark signal non-uniformity DSNU Light shielding − 1.5 5.0 mV Power consumption PW − 360 540 mW Output impedance ZO − 0.35 1 kΩ Red RR 4.15 5.94 7.73 V/lx•s Green RG 3.66 5.24 6.82 V/lx•s Blue RB 2.36 3.38 4.39 V/lx•s − 3.0 7.0 % Photo response non-uniformity Response Image lag Offset level IL Note 1 VOUT = 1.0 V 4.5 6.0 7.5 V td VOUT = 1.0 V, t1’, t2’ = 5 ns − 25 − ns Total transfer efficiency TTE VOUT = 1.0 V, data rate = 6 MHz 92 98 − % Register imbalance RI VOUT = 1.0 V − 1.0 4.0 % Red − 630 − nm Green − 540 − nm Blue − 460 − nm − 1666 − times Output fall delay time VOS Note 2 Response peak Dynamic range Reset feed-through noise Random noise (CDS) Note 1 DR1 Vsat/DSNU DR2 Vsat/σ CDS − 2500 − times RFTN Light shielding −2000 +300 +1000 mV σ CDS Light shielding − 1.0 − mV Notes 1. Refer to TIMING CHART 2, 3. 2. When each fall time of φ 1L and φ 2L (t1’, t2’) is the Typ. value (refer to TIMING CHART 2, 3). 6 Data Sheet S16033EJ3V0DS µ PD8862 INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Symbol Shift register clock pin capacitance 1 Cφ 1 Pin name φ1 Pin No. Min. Typ. Max. Unit 9 − 250 − pF 14 − 250 − pF − 500 − pF 8 − 250 − pF 15 − 250 − pF − 500 − pF φ 1 total capacitance Shift register clock pin capacitance 2 Cφ 2 φ2 φ 2 total capacitance Last stage shift register clock pin capacitance Cφ L φ 1L 4 − 10 − pF φ 2L 17 − 10 − pF Reset gate clock pin capacitance Cφ RB φ RB 2 − 10 − pF Reset feed-through level clamp clock pin capacitance Cφ CLB φ CLB 3 − 10 − pF Transfer gate clock pin capacitance Cφ TG φ TG1 13 − 100 − pF φ TG2 12 − 100 − pF φ TG3 10 − 100 − pF Remarks 1. 2. Pins 9 and 14 (φ 1), 8 and 15 (φ 2) are each connected inside of the device. Cφ 1 and Cφ 2 show the equivalent capacity of the real drive including the capacity of between φ 1 and φ 2. Data Sheet S16033EJ3V0DS 7 8 TIMING CHART 1-1 (Bit clamp mode, for each color) φ TG1 to φ TG3 φ 1, φ 1L φ 2, φ 2L φ RB Note Note 5466 5467 5468 5469 5470 5471 61 62 63 64 65 66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data Sheet S16033EJ3V0DS φ CLB VOUT1 to VOUT3 Optical black (49 pixels) Valid photocell (5400 pixels) Invalid photocell (4 pixels) Invalid photocell (4 pixels) Note Set the φ RB and φ CLB to high level during this period. µ PD8862 TIMING CHART 1-2 (Line clamp mode, for each color) φ TG1 to φ TG3 φ 1, φ 1L φ 2, φ 2L φ RB Note Note 5466 5467 5468 5469 5470 5471 61 62 63 64 65 66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data Sheet S16033EJ3V0DS φ CLB (φ TG1 to φ TG3) VOUT1 to VOUT3 Optical black (49 pixels) Valid photocell (5400 pixels) Invalid photocell (4 pixels) Invalid photocell (4 pixels) Note Set the φ RB to high level during this period. 9 µ PD8862 Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. µ PD8862 TIMING CHART 2 (Bit clamp mode, for each color) t1 t2 90% φ1 10% 90% φ2 10% t1' 90% φ 1L 10% 90% φ 2L 10% t5 φ RB t2' t6 t3 t5 t4 t3 t6 t4 90% 10% t7 t9 t8 t10 t11 t7 t9 t8 t10 t11 90% φ CLB 10% td td RFTN RFTN VOUT VOS 10% 10% Symbol Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3 20 100 − ns t4 30 150 − ns t5, t6 0 25 − ns 25 − ns −5 t7 Note t8 20 100 − ns t9, t10 0 25 − ns t11 5 25 − ns Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 10 90% Data Sheet S16033EJ3V0DS µ PD8862 TIMING CHART 3 (Line clamp mode, for each color) t1 t2 90% φ1 10% 90% φ2 10% t1' 90% φ 1L 10% 90% φ 2L 10% t5 t6 t3 t5 t4 t3 t6 t4 90% φ RB φ CLB t2' 10% "H" td td RFTN RFTN VOUT VOS 10% 10% Symbol Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3 20 100 − ns t4 30 150 − ns t5, t6 0 25 − ns Data Sheet S16033EJ3V0DS 11 µ PD8862 φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART t13 t14 t12 90% 10% t15 φ TG1 to φ TG3 t16 90% φ1 φ2 t17 Note 1 t18 90% φ RB t7 φ CLB (Bit clamp mode) t20 t22 Note 2 t21 t23 φ CLB (Line clamp mode) t9 Symbol Min. −5 t7 t9, t10 t12 Note 3 t19 t10 Typ. Max. Unit 25 − ns 0 25 − ns 5000 10000 50000 ns t13, t14 0 50 − ns t15, t16 900 1000 − ns t17, t18 200 400 − ns t19 t12 t12 50000 ns t20, t21 0 50 − ns t22, t23 0 350 − ns Notes 1. Set the φ RB and φ CLB to high level during this period. 2. Set the φ RB to high level during this period. 3. Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. 12 Data Sheet S16033EJ3V0DS µ PD8862 φ 1, φ 2 cross points φ1 φ2 1.0 V to 4.0 V 1.0 V to 4.0 V φ 1, φ 2L cross points φ1 2.0 V or more 0.5 V or more 2.0 V or more 0.5 V or more φ 2L φ 2, φ 1L cross points φ2 φ 1L Remark Adjust cross points (φ 1, φ 2), (φ 1, φ 2L) and (φ 2, φ 1L) with input resistance of each pin. Data Sheet S16033EJ3V0DS 13 µ PD8862 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆ x : maximum of xj − x 5400 Σx j x= j=1 5400 xj : Output voltage of valid pixel number j VOUT Register Dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 5400 Σd j ADS (mV) = j=1 5400 dj : Dark signal of valid pixel number j 14 Data Sheet S16033EJ3V0DS µ PD8862 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 5400 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT Data Sheet S16033EJ3V0DS 15 µ PD8862 9. Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n ∑ (V2j –1 – V2j) j=1 RI (%) = × 100 n 1 n ∑ Vj j=1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise (CDS) : σ CDS Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the video output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by VCDSi = VDi – VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σ CDS using the following equation. 100 σ CDS (mV) = Σ (VCDS – V) i 2 i=1 100 , V= 1 100 Σ VCDS 100 i = 1 Reset feed-through Video output 16 Data Sheet S16033EJ3V0DS i µ PD8862 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 8 2 1 Relative Output Voltage 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA (°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 R B G 80 Response Ratio (%) Relative Output Voltage 4 60 40 G 20 B 0 400 500 600 700 800 Wavelength (nm) Data Sheet S16033EJ3V0DS 17 µ PD8862 APPLICATION CIRCUIT EXAMPLE +12 V +5 V 10 µ F/16 V + 1 0.1 µ F φ RB φ CLB φ 1L 47 Ω 47 Ω 150 Ω 2 3 4 5 6 7 φ2 + µ PD8862 4.7 Ω 8 4.7 Ω 9 10 Ω 10 11 NC VOUT3 φ RB VOUT2 φ CLB VOUT1 φ 1L VOD NC NC NC φ 2L NC NC φ2 φ2 φ1 φ1 φ TG3 φ TG1 GND φ TG2 22 21 20 B3 0.1 µ F 47 µ F/25 V B2 +5 V B1 19 18 17 + 150 Ω 0.1 µ F 10 µ F/16 V 16 φ 2L 15 4.7 Ω 14 4.7 Ω 13 10 Ω 12 10 Ω φ1 φ TG Caution Connect the No connection pins (NC) to GND. Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (2 ≤ data rate < 6 MHz). 2. Inverters B1 to B3 in the above application circuit example are shown in the figure below. B1 to B3 EQUIVALENT CIRCUIT +12 V + 100 Ω CCD VOUT 100 Ω 2SC945 2 kΩ 18 Data Sheet S16033EJ3V0DS 47 µ F/25 V µ PD8862 PACKAGE DRAWING µ PD8862CY CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400) ) (Unit : mm) 44.0±0.3 1st valid pixel 6.36±0.3 1 9.25±0.3 22 12 1 11 2.0 37.5 1.02±0.15 0.46±0.1 4.39±0.4 2.54±0.25 (5.42) (1.72) 2 2.62±0.2 3 10.16±0.2 0.25±0.05 10.16 +0.7 −0.2 4.21±0.5 Name Dimensions Refractive index Plastic cap 42.9×8.35×0.7 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 22C-1CCD-PKG12-2 Data Sheet S16033EJ3V0DS 19 µ PD8862 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device µ PD8862CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) Process Partial heating method Cautions 1. Conditions Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin) During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. 20 Data Sheet S16033EJ3V0DS µ PD8862 NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. Ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. Either handle bare handed or use non-chargeable gloves, clothes or material. 4. Ionized air is recommended for discharge when handling CCD image sensor. 5. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S16033EJ3V0DS 21 µ PD8862 [MEMO] 22 Data Sheet S16033EJ3V0DS µ PD8862 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S16033EJ3V0DS 23 µ PD8862 • The information in this document is current as of July, 2003. The information is subject to change without notice. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1