DATA SHEET MOS INTEGRATED CIRCUIT μ PD8884A (10680 PIXELS × 4 LINES) × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The μ PD8884A is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The μ PD8884A has 3 rows of (10680 × 4) staggered pixels, and each row has a dual-sided readout-type charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 4800 dpi/A4 color image scanners. FEATURES • Valid photocell : (10680 pixels × 4) × 3 • Photocell’s size : 4 μm • Line spacing : Quad staggered pixels • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) • Resolution : 192 dot/mm A4 (210 × 297 mm) size (shorter side) 96 μ m (24 lines) Red line - Green line, Green line - Blue line 7 4800 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate : 5.0 MHz Max. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number μ PD8884ACY-A Remark Package CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) The μ PD8884ACY-A is a lead-free product. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S17546EJ1V0DS00 (1st edition) Date Published May 2005 NS CP (K) Printed in Japan 2005 μ PD8884A BLOCK DIAGRAM VOD GND GND 29 φ SEL2 φ 2-2 φ 1-2 30 11 22 14 4 Drain gate Transfer gate CCD analog shift register Transfer gate Photocell (Blue) Transfer gate CCD analog shift register Transfer gate VOUT1 31 (Blue) 18 φTG1 (Blue) 17 φ TG2 (Green) 16 φ TG3 (Red) Drain gate Drain gate Transfer gate CCD analog shift register Transfer gate Photocell (Green) Transfer gate CCD analog shift register Transfer gate VOUT2 32 (Green) Drain gate Drain gate Transfer gate CCD analog shift register Transfer gate Photocell (Red) Transfer gate CCD analog shift register Transfer gate VOUT3 1 (Red) Drain gate 2 3 5 28 φ CLB φ RB φ 2-1 φ 1-1 2 Data Sheet S17546EJ1V0DS 19 15 φ SEL1 φ SEL3 μ PD8884A PIN CONFIGURATION (Top View) CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) • μ PD8884ACY-A 32 VOUT2 Output signal 2 (Green) Reset feed-through level clamp clock φ CLB 2 31 VOUT1 Output signal 1 (Blue) Reset gate clock φ RB 3 30 φ SEL2 Dpi selector 2 Ground GND 4 29 VOD Output drain voltage Shift register clock 2-1 φ 2-1 5 28 φ 1-1 Shift register clock 1-1 Internal connection IC 6 27 IC Internal connection Internal connection IC 7 26 IC Internal connection No connection NC 8 25 NC No connection No connection NC 9 24 NC No connection No connection NC 10 23 NC No connection Shift register clock 2-2 φ 2-2 11 22 φ 1-2 Shift register clock 1-2 Internal connection IC 12 21 IC Internal connection Internal connection IC 13 20 IC Internal connection Ground GND 14 19 φ SEL1 Dpi selector 1 Dpi selector 3 φ SEL3 15 18 φ TG1 Transfer gate clock 1 (for Blue) 17 φ TG2 Transfer gate clock 2 (for Green) φ TG3 16 Blue 21360 × 2 Green 21360 × 2 21360 × 2 Red Transfer gate clock 3 (for Red) 1 1 1 VOUT3 1 Output signal 3 (Red) Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Data Sheet S17546EJ1V0DS 3 μ PD8884A PHOTOCELL STRUCTURE DIAGRAM (4800 dpi, for each color) 2 4 μm 6 10 14 5 22 1.0 μ m 3.0 μ m 1 18 9 13 CCD 17 33.5 μ m 21 8 μm 3 7 11 15 19 23 CCD 4 4 8 12 16 Data Sheet S17546EJ1V0DS 20 24 33.5 μ m μ PD8884A PHOTOCELL ARRAY STRUCTURE DIAGRAM-1 (Line spacing) Drain gate Blue photocell array 4 μm CCD analog shift register 4 μm 4 μm 4 μm Blue photocell array Blue photocell array CCD analog shift register Resolution Select 4 μm Blue photocell array Drain gate Drain gate Blue photocell array 4 μm CCD analog shift register 4 μm 4 μm 4 μm Blue photocell array Blue photocell array CCD analog shift register Resolution Select 4 μm Blue photocell array Drain gate Drain gate Blue photocell array 4 μm CCD analog shift register 4 μm 4 μm 4 μm Blue photocell array Blue photocell array CCD analog shift register Resolution Select 4 μm (33.5 μ m) 2 lines (8 μ m) (33.5 μ m) 24 lines (96 μ m) (21 μ m) (33.5 μ m) 2 lines (8 μ m) (33.5 μ m) 271 μ m 24 lines (96 μ m) (21 μ m) (33.5 μ m) 2 lines (8 μ m) (33.5 μ m) Blue photocell array Drain gate PHOTOCELL ARRAY STRUCTURE DIAGRAM-2 (Dummy, OB, for each color) Dummy (160 pixels) 4800 dpi 2 Optical black (192 pixels) 158 162 1 157 161 Invalid photocell (16 pixels) 350 354 358 362 366 370 374 349 353 357 361 365 369 373 Valid photocell (42720 pixels) Invalid photocell (8 pixels) 43082 43086 43081 43085 2400 dpi 3 4800 dpi 4 159 163 160 164 351 355 359 363 367 371 375 352 356 360 364 368 372 376 Data Sheet S17546EJ1V0DS 43083 43087 43084 43088 5 μ PD8884A ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +15 V Shift register clock voltage Vφ 1, Vφ 2 −0.3 to +8 V Reset gate clock voltage Vφ RB −0.3 to +8 V Reset feed-through level clamp clock voltage Vφ CLB −0.3 to +8 V Dpi select signal voltage Vφ SEL1 to Vφ SEL3 −0.3 to +8 V Vφ TG1 to Vφ TG3 Transfer gate clock voltage Operating ambient temperature Note Storage temperature −0.3 to +8 V TA 0 to +60 °C Tstg −40 to +70 °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Symbol Min. Typ. Max. Unit 12.5 V Output drain voltage VOD 11.5 12.0 Shift register clock high level Vφ 1H, Vφ 2H 4.75 5.0 5.5 V Shift register clock low level Vφ 1L, Vφ 2L −0.3 0 +0.3 V Reset gate clock high level Vφ RBH 4.5 5.0 5.5 V Reset gate clock low level Vφ RBL −0.3 0 +0.3 V Reset feed-through level clamp clock high level Vφ CLBH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level Vφ CLBL −0.3 0 +0.3 V Dpi select signal high level Vφ SEL1H to Vφ SEL3H 4.5 5.0 5.5 V Dpi select signal low level Vφ SEL1L to Vφ SEL3L −0.3 0 +0.3 V Transfer gate clock high level Vφ TG1H to Vφ TG3H 4.5 5.0 5.5 V Transfer gate clock low level Vφ TG1L to Vφ TG3L −0.3 0 +0.3 V Data rate fφ RB − 2.0 5.0 MHz Clock pulse frequency fφ 1, fφ 2 − 1.0 10.0 MHz 6 Data Sheet S17546EJ1V0DS μ PD8884A ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Min. Typ. Max. Unit Vsat 2.3 2.7 − V Red SER − 0.79 − lx•s Green SEG − 0.87 − lx•s Saturation voltage Saturation exposure Test Conditions − 1.35 − lx•s Photo response non-uniformity PRNU VOUT = 1.0 V − 6 20 % Average dark signal ADS Light shielding − 0.1 4.0 mV Dark signal non-uniformity DSNU Light shielding − 2.0 8.0 mV Power consumption PW − 380 540 mW Output impedance ZO − 0.4 1.0 kΩ RR 2.38 3.40 4.42 V/lx•s Blue Response Offset level Red SEB Green RG 2.17 3.10 4.03 V/lx•s Blue RB 1.40 2.00 2.60 V/lx•s VOS 4.5 6.0 7.5 V 92 98 − % Red − 630 − nm Green − 540 − nm Note Total transfer efficiency TTE VOUT = 1.0 V Clock pulse frequency = 10 MHz Response peak − 460 − nm Image lag IL VOUT = 1.0 V − 0.05 3.0 % Response difference between RDIO VOUT = 1.0 V − 1.0 6.0 % Blue inside and outside Potocell array imbalance Reset feed-through noise Random noise (CDS) Note PAIIN VOUT = 1.0 V − 1.0 6.0 % PAIOUT VOUT = 1.0 V − 1.0 6.0 % RFTN Light shielding − −500 +1000 mV σ CDS Light shielding − 1.2 − mV Note Refer to TIMING CHART 2-1 to 2-3. Data Sheet S17546EJ1V0DS 7 μ PD8884A INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Symbol Pin name Pin No. Min. Typ. Max. Unit Shift register clock pin capacitance 1 Cφ 1-1 φ 1-1 28 − 750 − pF Shift register clock pin capacitance 2 Cφ 1-2 φ 1-2 22 − 750 − pF Shift register clock pin capacitance 3 Cφ 2-1 φ 2-1 5 − 750 − pF Shift register clock pin capacitance 4 Cφ 2-2 φ 2-2 11 − 750 − pF Reset gate clock pin capacitance Cφ RB φ RB 3 − 20 − pF Reset feed-through level clamp clock pin capacitance Cφ CLB φ CLB 2 − 20 − pF Select signal and gain pin capacitance Cφ SEL1 φ SEL1 19 − 20 − pF Cφ SEL2 φ SEL2 30 − 20 − pF Cφ SEL3 φ SEL3 15 − 20 − pF Cφ TG φ TG1 18 − 20 − pF φ TG2 17 − 20 − pF φ TG3 16 − 20 − pF Transfer gate clock pin capacitance Remark Cφ 1-1 to Cφ 2-2 show the equivalent capacity of the real drive including the capacity of between each clock pin (φ 1-1, φ 1-2, φ 2-1 and φ 2-2). INPUT SIGNAL TABLE Mode φ SEL1 φ SEL2 φ SEL3 (Even-line enable (CCD-drain switch) (TG-select switch) High level High level High level Even-line electron read photodiode to CCD High level High level Low level Odd-line electron read photodiode to CCD Low level High level Low level Odd-line electron read photodiode to CCD Note switch) 4800 dpi 2400 dpi Even-line electron sink to drain 1200 dpi Low level Low level Low level 2 to 4, 6 to 8, 10 to 12, … : Sink to drain 600 dpi 8 1, 5, 9, 13, … : Line photodiode use Data Sheet S17546EJ1V0DS TIMING CHART 1-1 (4800 dpi, for each color) Storage time (l2, l4) Storage time (l1, l3) φ TG1 to φ TG3 2400 dpi cycle Odd line read 2400 dpi cycle Even line read φ SEL3 Data Sheet S17546EJ1V0DS φ SEL1, φ SEL2 “H” φ 1-2400 φ 2-2400 21360 pixels Odd 2400 dpi Data read 21360 pixels Even 2400 dpi Data read 21360 pixels Odd 2400 dpi Data read 21360 pixels Even 2400 dpi Data read Remark Above means, storage time of each photocell array is “TG period × 2”. And storage time of (l1, l3) and (l2, l4) is a half overlap each other. μ PD8884A 9 10 TIMING CHART 1-2 (2400 dpi, for each color) Storage time φ TG1 to φ TG3 φ1 φ2 φ RB Note Note 43083 43085 43087 43089 43091 43093 43095 “L” 365 367 369 371 φ SEL3 “H” 347 349 351 353 φ SEL2 “L” 157 159 161 163 φ SEL1 1 3 5 7 9 11 Data Sheet S17546EJ1V0DS φ CLB VOUT1 to VOUT3 Valid photocell (21360 pixels) Optical black (96 pixels) Note Set the φ RB and the φ CLB to high level during this period. Invalid photocell (4 pixels) μ PD8884A Invalid photocell (8 pixels) TIMING CHART 1-3 (1200 dpi, for each color) Storage time φ TG1 to φ TG3 φ1 φ2 φ RB Note Note “L” φ SEL3 “L” 43081 43085 43089 43093 43097 φ SEL2 345 349 353 357 361 365 369 373 “L” 153 157 161 165 φ SEL1 1 5 9 13 17 21 Data Sheet S17546EJ1V0DS φ CLB VOUT1 to VOUT3 Valid photocell (10680 pixels) Optical black (48 pixels) Note Set the φ RB and the φ CLB to high level during this period. Invalid photocell (2 pixels) 11 μ PD8884A Invalid photocell (4 pixels) 12 TIMING CHART 1-4 (600 dpi, for each color) Storage time φ TG1 to φ TG3 φ1 φ2 φ RB Note Note 42989+ 42993 42981+ 42985 42973+ 42977 369+373 361+365 “L” 353+357 φ SEL3 345+349 “L” 161+165 φ SEL2 153+157 “L” 9+13 φ SEL1 1+5 Data Sheet S17546EJ1V0DS φ CLB VOUT1 to VOUT3 Optical black (24 pixels) Valid photocell (5340 pixels) N Note Set the φ RB and the φ CLB to high level during this period. Remark 2 pixels data merge at the charge detected capacitance. Invalid photocell (1 pixels) μ PD8884A Invalid photocell (2 pixels) μ PD8884A TIMING CHART 2-1 (4800 dpi / 2400 dpi, for each color) t1 φ1 90% 10% φ2 90% 10% t5 t3 t6 φ RB t5 t3 t6 t4 t4 90% 10% t9 t7 φ CLB t2 t8 t10 t11 t7 t9 t8 t10 t11 90% 10% td td RFTN VOS VOUT 10% Symbol 10% Min. Typ. Max. Unit t1, t2 0 30 − ns t3 20 100 − ns t4 40 150 − ns 0 10 − ns t7 −10 +25 − ns t8 20 100 − ns t9, t10 0 10 − ns t11 10 25 − ns td − 15 − ns t5, t6 Data Sheet S17546EJ1V0DS 13 μ PD8884A TIMING CHART 2-2 (1200 dpi, for each color) t1 φ1 90% 10% φ2 90% 10% t5 t3 t6 φ RB t4 90% 10% t9 t7 φ CLB t2 t8 t10 t11 90% 10% td RFTN VOS VOUT 10% Min. Typ. Max. Unit t1, t2 Symbol 0 30 − ns t3 20 100 − ns t4 40 150 − ns 0 10 − ns t7 −10 +25 − ns t8 20 100 − ns t9, t10 0 10 − ns t11 10 25 − ns td − 15 − ns t5, t6 14 Data Sheet S17546EJ1V0DS μ PD8884A TIMING CHART 2-3 (600 dpi, for each color) t1 φ1 90% 10% φ2 90% 10% t5 t3 t6 φ RB t4 90% 10% t9 t7 φ CLB t2 t8 t10 t11 90% 10% td RFTN 10% VOUT VOS Min. Typ. Max. Unit t1, t2 Symbol 0 30 − ns t3 20 100 − ns t4 40 150 − ns 0 10 − ns t7 −10 +25 − ns t8 20 100 − ns t9, t10 0 10 − ns t11 10 25 − ns td − 15 − ns t5, t6 Data Sheet S17546EJ1V0DS 15 μ PD8884A TIMING CHART 3 (readout) t13 t14 t12 90% 10% t15 φ TG1 to φ TG3 t16 90% 10% φ SEL3 t18 t17 90% φ1 φ2 t20 t19 φ RB, φ CLB 90% Symbol Min. Typ. Max. Unit 8000 15000 (50000) ns t13, t14 0 50 − ns t15, t16 1000 2000 − ns t17 1000 2000 − ns t18 7000 10000 − ns t19, t20 500 1000 − ns t12 φ 1, φ 2 CROSS POINTS φ2 φ1 2.0 V or more 2.0 V or more Remark Adjust cross points of φ 1 and φ 2 with input resistance of each pin. 16 Data Sheet S17546EJ1V0DS μ PD8884A DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. Photo pixel and CCD register electron saturate level. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. PRNU of 4800 dpi is calculated by the following formula. Δx × 100 x PRNUIN (%) = Δ x : maximum of ⎪xj − x ⎪ Δ x : maximum of ⎪yj − y ⎪ IV x= Σx j=1 Δy × 100 y PRNUOUT (%) = IO j y= IV Σy j=1 j IO xj : Output voltage of valid pixel number j yj : Output voltage of valid pixel number j IV : Number of inside valid pixels (21360 bits) IO : Number of outside valid pixels (21360 bits) The following figure shows output waveform of 4800 dpi mode. VOUT x Register Dark DC level y Δx Δy Inside 2400 dpi data set Outnside 2400 dpi data set 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. Vaild pixels Σd ADS (mV) = j j=1 Valid pixels dj : Dark signal of valid pixel number j Data Sheet S17546EJ1V0DS 17 μ PD8884A 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of ⎪dj − ADS ⎪j = 1 to Valid pixels dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). R of 4800 dpi is defined as following (refer to 3. Photo response non-uniformity). x divided by exposure (lx•s) RIN : ¯¯ y divided by exposure (lx•s) ROUT : ¯¯ 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG ON Light OFF VOUT V1 VOUT IL (%) = 18 V1 × 100 VOUT Data Sheet S17546EJ1V0DS μ PD8884A 9. Response difference between inside and outside : RDIO Difference of average output voltage between inside 2400 dpi and outside 2400 dpi (refer to 3. Photo response non-uniformity). RDIO (%) = 2⎪x−y⎪ × 100 x+y 10. Photocell array imbalance : PAI PAI is calculated by following formula (refer to 3. Photo response non-uniformity). n m 2 2 n 2 ∑ (x2j –1 – x2j) j=1 PAIIN (%) = n 1 n 2 m × 100 ∑ (y2j –1 – y2j) j=1 PAIOUT (%) = ∑ xj m 1 n j=1 xj : Output voltage of each pixel n : Number of valid pixels (21360 bits) × 100 ∑ yj j=1 yj : Output voltage of each pixel m : Number of valid pixels (21360 bits) 11. Offset level : VOS DC level of output signal is defined as follows. 12. Reset feed-through noise : RFTN Reset feed-through noise (RFTN) are defined as follows. RFTN VOS VOUT Data Sheet S17546EJ1V0DS 19 μ PD8884A 13. Random noise (CDS) : σ CDS Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the video output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by the following formula. VCDSi = VDi – VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σ CDS using the following formula equation. 100 σ CDS (mV) = Σ (VCDS – V) i=1 i 2 100 , V= 1 100 Σ VCDS i 100 i = 1 The following figure shows output waveform (valid photocell under dark condition). Reset feed-through Video output 20 Data Sheet S17546EJ1V0DS μ PD8884A STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 8 2 Relative Output Voltage 2 1 0.5 1 0.2 0.25 0.1 0 10 20 30 40 0.1 1 50 Operating Ambient Temperature TA (°C) 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 R B G 80 Response Ratio (%) Relative Output Voltage 4 60 40 G 20 B 0 400 500 600 700 800 Wavelength (nm) Data Sheet S17546EJ1V0DS 21 μ PD8884A APPLICATION CIRCUIT EXAMPLE +12 V μ PD8884A B3 1 47 Ω 32 2 φ CLB 47 Ω 3 φ RB VOUT3 VOUT2 φ CLB VOUT1 φ RB 31 φ SEL2 4 5.1 Ω GND VOD φ 2-1 φ 1-1 6 IC IC IC NC NC NC NC 28 5.1 Ω φ 1-1 NC NC 23 11 φ 2-2 φ 1-2 12 22 5.1 Ω φ 1-2 21 IC IC IC IC 13 20 14 GND 15 47 Ω φ SEL2 24 10 φ SEL3 47 μ F/25 V 25 9 47 Ω 0.1 μ F 26 8 5.1 Ω 47 Ω 27 IC 7 φ 2-2 B1 30 29 5 φ 2-1 + B2 16 φ SEL1 φ SEL3 φ TG1 φ TG3 φ TG2 19 47 Ω 18 47 Ω 17 47 Ω φ SEL1 φ TG Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Remarks 1. φ RB, φ CLB, φ TG1 to φ TG3 and φ SEL1 to φ SEL3 driving inverters shown in the above application circuit example are the 74HC04. φ 1-1 to φ 2-2 driving inverters shown in the above application circuit example are the 74HC04 (≤ 2.0 MHz) or the 74AC04 (> 2.0 MHz). 2. Inverters B1 to B3 in the above application circuit example are shown in the figure below. B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 100 Ω 47 μ F/25 V 2SC1842 2 kΩ 22 Data Sheet S17546EJ1V0DS μ PD8884A PACKAGE DRAWING μ PD8884ACY CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400)) (Unit : mm) 55.2±0.5 54.8±0.5 1st valid pixel 5.85±0.3 1 9.05±0.3 9.25±0.3 17 32 16 1 46.7 4 2.0 12.6±0.5 4 4.1±0.5 4.55±0.5 1.02±0.15 10.16±0.20 (1.775) 2 3 2.725±0.3 0.46±0.1 (5.42) 2.54±0.25 4.21±0.5 10.16 +0.70 −0.20 0.25±0.05 Name Dimensions Refractive index Plastic cap 52.2×6.4×0.8 (0.7 5) 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 4 Mirror finishied surface 5 Thickness of mirror finished surface Data Sheet S17546EJ1V0DS 23 μ PD8884A RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Type of Through-hole Device μ PD8884ACY-A : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) Process Partial heating method Cautions 1. Conditions Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin) During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. 24 Data Sheet S17546EJ1V0DS μ PD8884A NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. 6. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S17546EJ1V0DS 25 μ PD8884A [MEMO] 26 Data Sheet S17546EJ1V0DS μ PD8884A NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S17546EJ1V0DS 27 μ PD8884A • The information in this document is current as of May, 2005. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1