DATA SHEET MOS INTEGRATED CIRCUIT µPD98409 ATM LIGHT SAR CONTROLLER DESCRIPTION The µPD98409 (NEASCOT-S40CTM) is a high-performance SAR chip for segmentation and reassembly of ATM cells. Provided with a PCI (Peripheral Component Interconnect) bus interface control memory and supporting a MPEG packet transfer engine function to mitigate the workload of the CPU in transferring compressed image data, this chip has ideal specifications for use in a set top box (STB) to interface with an ATM network. The µPD98409 conforms to ATM Forum recommendations and has AAL5-SAR sublayer and ATM layer functions. FEATURES • Conforms to ATM Forum • PCI bus interface (5/3.3 V, 32/64 bits, 33 MHz) Conforms to PCI Local Bus Specification Revision 2.1 • AAL-5 SAR sublayer and ATM layer functions • Hardware support of AAL-5 processing (non-AAL-5 processing can be supported in software) • Supports up to 64 virtual channels (VC) (64-VC control memory) • Two traffic shapers for transmission scheduling • MPEG packet transfer engine mitigating the workload of compressed image data transfer by CPU • Receive FIFO of 12 cells • PHY device I/F: UTOPIA Level-1 interface (octet/cell level handshake) • JTAG boundary scan test functions • 0.35-µm CMOS process, +5/+3.3-V power supply - Bus interface +5 V : +5/+3.3-V power supply - Bus interface +3.3 V : +3.3-V single power supply ORDERING INFORMATION Part Number µPD98409GN-LMU Package 240-pin plastic QFP (0.5-mm fine pitch) (32 × 32 mm) The information in this document is subject to change without notice. Document No. S12775EJ2V0DS00 (2nd edition) Date Published May 1998 N CP(K) Printed in Japan The mark shows major revised points. © 1997, 1998 µPD98409 EXAMPLE OF SYSTEM CONFIGURATION ATM STB PCI bus MPEG decoder block µ PD98409 Line interface Memory CPU BLOCK DIAGRAM Receive data FIFO (12 cells) MPEG packet transfer engine PCI interface PCI interface block DMA controller Receive PHY interface Rx UTOPIA interface Receive controller Sequencer Control memory interface Control memory (64 VCs) PHY control interface Transmit controller Transmit PHY interface Transmit data FIFO (2 cells) 2 Tx UTOPIA interface µPD98409 PIN CONFIGURATION (Top View) 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 GND GND CA8 CA7 CA6 CA5 GND CA4 CA3 CA2 CA1 VDD3 GND CA0 PHCE_B PHOE_B CD0 CD1 CD2 GND VDD3 CD3 CD4 CD5 GND CD6 CD7 PHRW_B PHINT_B VDD3 GND TX0 TX1 TX2 TX3 GND TX4 TX5 TX6 TX7 VDD3 GND TCLK GND TENBL_B TSOC FULL_B/TXCLAV RSOC RENBL_B EMPTY_B/RXCLAV VDD3 GND RCLK GND RX0 RX1 RX2 RX3 GND GND VDD3 AD4 AD3 AD2 AD1 GND VDD5 AD0 REQ_B GND GNT_B GND BUSCLK GND INTR_B VDD5 GND GND E2PCLK GND VDD3 E2PDO E2PDI E2PCS GND IC IC IC IC GND VDD3 IC IC IC IC GND IC GND IC VDD3 GND IC IC IC IC IC IC IC IC GND IC GND IC IC IC RX7 RX6 RX5 RX4 VDD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 µ PD98409GN-LMU GND GND AD29 AD28 AD27 AD26 GND VDD5 AD25 AD24 PCBE3_B GND IDSEL VDD5 GND AD23 AD22 AD21 AD20 GND VDD3 AD19 AD18 AD17 AD16 GND PCBE2_B FRAME_B IRDY_B TRDY_B GND VDD5 DEVSEL_B STOP_B PERR_B GND SERR_B PAR PCBE1_B VDD3 GND AD15 AD14 AD13 AD12 GND VDD5 AD11 AD10 AD9 AD8 VDD5 GND PCBE0_B AD7 AD6 AD5 VDD5 GND GND 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 VDD3 AD30 AD31 VDD5 GND RST_B VDD5 GND RSTOUT_B IC IC IC GND IC IC PHYSEL1 IC GND NC GND VDD3 JRST_B JMS JDO JDI GND JCK GND IC IC IC IC IC GND VDD3 IC IC IC IC VDD3 GND IC L L GND PO0 PO1 PO2 PO3 GND VDD3 LASTB LA0 LA1 GND LA2 LA3 LA4 LA5 VDD3 • 240-pin plastic QFP (0.5-mm fine pitch) (32 × 32 mm) NC : No connection. Leave this pin open. IC : Input pin with pull-down resistor for internal test. It is recommended to fix this pin to the low level. L : Fix this pin to the low level. 3 µPD98409 PIN NAMES AD31_AD0 : Address/Data PHINT_B : PHY Interrupt BUSCLK : Bus Clock PHOE_B : PHY Output Enable CA8-CA0 : PHY Device Address PHRW_B : PHY Read/Write CD7-CD0 : PHY Device Data PHYSEL1 : PHY Select PO3-PO0 : Generic Output Port RCLK : Receive Clock DEVSEL_B : Device Select E2PCLK : Clock for EEPROM TM E2PCS : EEPROM Chip Select RENBL_B : Receive Enable E2PDI : Serial Data Input from EEPROM REQ_B : Request E2PDO : Serial Data Output to EEPROM RSOC : Receive Start of Cell EMPTY_B/RxCLAV: PHY Empty / Rx Cell Available RST_B : Reset FRAME_B : Cycle Frame RSTOUT_B : Reset Output FULL_B/TxCLAV : PHY Buffer Full / Tx Cell Available Rx7-Rx0 : Receive Data Bus GND : Ground SERR_B : System Error GNT_B : Grant STOP_B : Stop IDSEL : ID Select TCLK : Transmit Clock INTR_B : Interrupt TENBL_B : Transmit Enable IRDY_B : Initiator Ready TRDY_B : Target Ready JCK : JTAG Test Pin TSOC : Transmit Start of Cell JDI : JTAG Test Pin Tx7-Tx0 : Transmit Data Bus JDO : JTAG Test Pin VDD3 : +3.3 V Power Supply JMS : JTAG Test Pin VDD5 : +5 V Power Supply JRST_B : JTAG Test Pin LA5-LA0 : Internal Test Pin LASTB : Internal Test Pin PAR : Parity PCBE_B3-PCBE_B0: Bus Command and Byte Enables PERR_B : Parity Error PHCE_B : PHY Chip Enable 4 µPD98409 CONTENTS 1. PIN FUNCTION ...................................................................................................................................... 6 1.1 PHY Device Interface Pin............................................................................................................................... 6 1.1.1 UTOPIA interface................................................................................................................................. 6 1.1.2 PHY device control interface ............................................................................................................. 7 1.2 Bus Interface Pins.......................................................................................................................................... 8 1.3 Serial EEPROM Interface Pins .................................................................................................................... 10 1.4 JTAG Boundary Scan Pins.......................................................................................................................... 10 1.5 Other Pins..................................................................................................................................................... 11 1.6 Power and Ground Pins .............................................................................................................................. 11 2. ELECTRICAL SPECIFICATIONS ........................................................................................................ 12 3. PACKAGE DRAWING ......................................................................................................................... 33 4. SOLDERING CONDITIONS ................................................................................................................. 34 5 µPD98409 1. PIN FUNCTION The pin function of the µPD98409 is descibed below. A detailed explanation of how to use each pin, and the points to be noted in using the pins are given in µPD98409 User’s Manual (Document Number: S12776E). Be sure to refer to this user’s manual. The following describes the I/O levels in the tables. LV-TTL input : Can be connected to 5 V CMOS output TTL output : Can be connected to 5 V TTL input, VOH = 3.3 V, IOL = 6 mA CMOS output : 3.3 V CMOS output, VOH = 3.3 V, IOL = 12 mA PCI input : 5/3.3 V PCI input PCI output : 5/3.3 V PCI output 1.1 PHY Device Interface Pin PHY device interfaces include a UTOPIA interface through which the µPD98409 transfers ATM cells with a PHY device, and a PHY control interface by which the µPD98409 controls the PHY device. 1.1.1 UTOPIA interface (1/2) Pin Name Pin No. I/O I/O Level 116 - 119, 123 - 126 I LV-TTL Receive Data Bus. Rx7 through Rx0 constitute an 8-bit input bus which inputs data received from a network in byte format from a PHY device. The µPD98409 loads data in at the rising edge of RCLK. RSOC 133 I LV-TTL Receive Start Cell. The RSOC signal is input in synchronization with the first byte of the cell data from a PHY device. This signal remains high while the first byte of the header is input to Rx7 through Rx0. RENBL_B 132 O TTL Receive Enable. The RENBL_B signal indicates to a PHY device that the µPD98409 is ready to receive data in the next clock cycle. EMPTY_B/ RxCLAV 131 I LV-TTL PHY Output Buffer Empty/Rx Cell Available. This signal notifies the µPD98409 that there is no cell data to be transferred in the receive FIFO and that no receive data can be supplied to the PHY device. When the UTOPIA interface is in the octet-level handshake mode, this signal serves as EMPTY_B, indicating that the data on Rx7 through Rx0 are invalid in the current clock cycle. In the cell-level handshake mode, it serves as RxCLAV, indicating that there is no cell to be supplied next after the transfer of the current cell is completed. RCLK 128 O TTL Receive Clock. This is a synchronization clock used to transfer cell data with the PHY device at the receive side. The system clock input to the BUSCLK pin is output from this pin as is. 141 - 144, 146 - 149 O TTL Transmit Data Bus. Tx7 through Tx0 constitute an 8-bit output bus which outputs transmit data in byte format to a PHY device. The µPD98409 outputs data at the rising edge of TCLK. 135 O TTL Transmit Start of Cell. The TSOC signal is output in synchronization with the first byte of transmit cell data. Rx7-Rx0 Tx7-Tx0 TSOC 6 Function µPD98409 (2/2) Pin Name TENBL_B Pin No. I/O I/O Level 136 O TTL Function Transmit Enable. The TENBL_B signal indicates to a PHY device that data has been output to Tx7 through Tx0 in the current clock cycle. FULL_B/ TxCLAV 134 I LV-TTL PHY Buffer Full/Tx Cell Available. This signal notifies the µPD98409 that the input buffer of the PHY device is full and that the device can receive no more data. When the UTOPIA interface is in the octet-level handshake mode, the PHY device inputs an inactive level to receive cell data. In the celllevel handshake mode, the PHY device inputs a signal that indicates that the PHY device can receive all the next one cell of data after the current cell has been completely transferred. TCLK 138 O TTL Transmit Clock. This is a synchronization clock used to transfer cell data with the PHY device at the transmission side. The system clock input to the BUSCLK pin is output from this pin as is. 1.1.2 PHY device control interface Pin Name PHRW_B Pin No. I/O I/O Level 153 O TTL Function PHY Read/Write. The µPD98409 indicates the direction in which the PHY device is controlled, by using PHRW_B. 1: Read 0: Write PHOE_B 165 O TTL PHY Output Enable. The µPD98409 enables output from the PHY device by making PHOE_B low PHCE_B 166 O TTL PHY Chip Enable. The µPD98409 makes PHCE_B low to access a PHY device. PHINT_B 152 I LV-TTL PHY Interrupt. This is an interrupt input signal from a PHY device. The PHY device indicates to the µPD98409 that it has an interrupt source, by inputting a low level to PHINT_B. RSTOUT_B 232 O TTL Reset Output. This is a signal to reset a PHY device. The µPD98409 makes this pin low for the duration of 11 to 22 clock cycles when a low level is input to the RST_B pin or a software reset is executed. 154, 155, 157 - 159, 162 - 164 I/O 3-state LV-TTL in TTL out PHY device data. CD7 through CD0 constitute an 8-bit data bus. These pins are threestate I/O pins. They are used to transfer data with a PHY device. O TTL CD7-CD0 CA8-CA0 178 - 175, 173 - 170, 167 PHY device address. CA8 through CA0 constitute a 9-bit address bus that outputs an address to a PHY device during read/write operation. 7 µPD98409 1.2 Bus Interface Pins The µPD98409 employs a 32-bit PCI bus interface as a bus interface with the host. This interface conforms to “PCI Local Bus Specification Revision 2.1”. (1/2) Pin Name 8 Pin No. I/O I/O Level Function AD31-AD0 238, 239, 3 - 6, 9, 10, 16 - 19, 22 - 25, 42 - 45, 48 - 51, 55 - 57, 62 - 65, 68 I/O 3-state PCI Address/data. AD31 through AD0 are 32 bits of multiplexed address and data bus signals. When the µPD98409 operates as the bus master, it drives an address at the first one clock, and transfers data at the second clock and onward. PCBE3_B PCBE2_B PCBE1_B PCBE0_B 11, 27, 39, 54 I/O 3-state PCI Bus command and byte enable. These signals define “bus commands” (generated bus transaction) in an address phase. In a data phase, they indicate which byte lane holds valid data. The PCBE3_B pin corresponds to byte 3 (bits 31 through 24), and PCBE0_B pin corresponds to byte 0 (bits 7 through 0). PAR 38 I/O 3-state PCI Parity. This signal inputs/outputs an even parity on the AD31 through AD0 and PCBE3_B through PCBE0_B pins including the PAR signal. When the µPD98409 operates as the master, the PAR signal is output in the address and write data phases. When the µPD98409 operates as a target, the PAR signal is output in the read data phase. FRAME_B 28 I/O Sustained 3-state PCI Frame. This signal indicates the start and period of bus transaction. When this signal becomes active, it indicates the start of bus transaction. While it is active, data is transferred. When the next data transfer phase is for the last data of the transaction, this signal becomes inactive. TRDY_B 30 I/O Sustained 3-state PCI Target ready. This signal goes low when the target device is ready to complete the transaction of the current data phase. This signal is used in pairs with IRDY_B. When both IRDY_B and TRDY_B are low, read/write data transfer is executed. IRDY_B 29 I/O Sustained 3-state PCI Initiator ready. This signal goes low when the initiator is ready to complete the transaction of the current data phase. This signal is used in pairs with TRDY_B. When both IRDY_B and TRDY_B are low, read/write data transfer is executed. If both FRAME_B and IRDY_B are inactive, the bus cycle is not executed, and wait cycles are inserted until both IRDY_B and TRDY_B become active. µPD98409 (2/2) Pin Name Pin No. I/O I/O Level STOP_B 34 I/O Sustained 3-state PCI Stop. This signal goes low when the target device requests the master device to stop the current transaction. DEVSEL_B 33 I/O Sustained 3-state PCI Device select. This signal goes low when the µPD98409 operates as a target and recognizes an address after the FRAME_B signal has become active. When the µPD98409 operates as the master, it samples this signal to check to see whether a target device has been selected. IDSEL 13 I PCI Initialization device select. This signal inputs a high level when the configuration register of the µPD98409 is read/written. REQ_B 69 ONote PCI Request. The µPD98409 requests the arbiter for the bus mastership by making this signal low. GNT_B 71 I PCI Grant. This signal goes low when the arbiter grants the µPD98409 the bus mastership. PERR_B 35 I/O Sustained 3-state PCI Parity error. This signal indicates that the µPD98409 has detected a parity error. It is enabled when the “Parity Error Response” bit of the configuration register is set to 1. SERR_B 37 O N-ch System error. This signal indicates that the µPD98409 has detected an address parity error. It is enabled when both the “Parity Error Response” and “System Error Enable” bits of the configuration register are set to 1. open-drain INTR_B 75 O N-ch open-drain Function Interrupt output. Pull up this pin because it outputs an open-drain signal. INTR_B informs the CPU that the interrupt bit (not masked) of the GSR register is set. BUSCLK 73 I PCI PCI bus clock. Bus clock input pin. It inputs a clock of up to 33 MHz. RST_B 235 I PCI Reset. The RST_B signal initializes the µPD98409 (on starting). When a low level is input to RST_B, the internal state machine and registers of the µPD98409 are reset, and all the 3-state signals go into a highimpedance state. When this signal is input while the µPD98409 is operating, the operating status at that time is lost. Keep the input to RST_B low at least for the duration of 1 clock cycle. Do not access the µPD98409 at least for 20 clocks after it has been reset. Note Although the “PCI Local Bus Specification Revision 2.1” specifies that the REQ_B pin go into a highimpedance state while a low level is input to the RST_B pin, the REQ_B pin of the µPD98409 outputs a high level. 9 µPD98409 1.3 Serial EEPROM Interface Pins The µPD98409 has an interface for serial EEPROM supporting the MICROWIRETM interface. Some of the contents of the PCI configuration register can be loaded from the EEPROM connected. As the EEPROM, “NM93C46L” of National Semiconductor Corp. is recommended. Pin Name Pin No. I/O I/O Level Function E2PCS 84 O TTL E2PDI 83 I TTL Internally pulled up E2PDO 82 O TTL EEPROM data output. This pin is connected to the data input pin of the EEPROM. Pull up or open this pin when it is not used. E2PCLK 79 O TTL EEPROM clock. This pin supplies a clock necessary for data transfer with the EEPROM. It outputs the clock input to the BUSCLK pin divided by 36. Leave this pin open when it is not used. EEPROM chip select. A chip select signal for EEPROM. Leave this pin open when it is not used. EEPROM data input. This pin is connected to the data output pin of the EEPROM. Pull up or open this pin when it is not used. 1.4 JTAG Boundary Scan Pins (These functions can be supported by request.) Pin Name JDI Pin No. I/O I/O Level 216 I LV-TTL Function JTAG Test Data Input. The JDI pin is used to input data to the JTAG boundary scan circuit register. Normally, fix this pin to high or low level. JDO 217 O 3-state TTL JTAG Test Data Output. The JDO pin is used to output data from the JTAG boundary scan circuit register. It changes output at the falling edge of the clock input to the JCK pin. Normally, leave this pin open. JCK 214 I LV-TTL JTAG Test Clock. This pin is used to supply a clock to the JTAG boundary scan circuit register. Normally, fix this pin to a high or low level. JMS 218 I LV-TTL JTAG Test Mode Select. Normally, fix this pin to a high or low level. JRST_B 219 I LV-TTL JTAG Test Reset. This pin initializes the JTAG boundary scan circuit register. Normally, fix this pin to a low level. 10 µPD98409 1.5 Other Pins Pin Name PHYSEL1 Pin No. I/O I/O Level 225 I LV-TTL Function Internal test pin. Input a low level to this pin. PO3-PO0 192 - 195 O CMOS LA5-LA0 182 - 185, 187, 188 O TTL Internal test pins. Leave these pins open during normal operation. 189 O TTL Internal test pin. Leave this pin open during normal operation. LASTB General-purpose output port. General-purpose output port pins. These pins output the value written to the GPOR register. 1.6 Power and Ground Pins Pin Name Pin No. I/O Function VDD3 21, 40, 61, 81, 91, 100, 120, 130, 140, 151, 160, 169, 181, 190, 201, 206, 220, 240 +3.3-V power supply. These pins supply +3.3 V to the chip. VDD5 8, 14, 32, 47, 52, 58, 67, 76, 234, 237 +5 V power supply. These pins supply +5 V to the chip when a +5-V bus interface is used. Supply +3.3 V to these pins when a +3.3-V bus interface is used. GND 1, 2, 7, 12, 15, 20, 26, 31, 36, 41, 46, 53, 59, 60, 66, 70, 72, 74, 77, 78, 80, 85, 90, 96, 98, 101, 110, 112, 121, 122, 127, 129, 137, 139, 145, 150, 156, 161, 168, 174, 179, 180, 186, 191, 196, 200, 207, 213, 215, 221, 223, 228, 233, 236 Ground. Connect to ground. 11 µPD98409 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Supply voltage Symbol Output voltage Output current Ratings Unit −0.5 to +4.6 V VDD3 ≤ VDD5 −0.5 to +6.6 V Except pin PCI, VI < VDD3 + 3.0 V −0.5 to +6.6 V PCI pin –5.5 to +11.0 V Except PCI pin and PO0-PO3, VO < VDD3 + 3.0 V −0.5 to +6.6 V PO3-PO0, VO < VDD3 + 0.5 V −0.5 to +4.6 V PCI pin –0.5 to +6.6 V Except PCI pin and PO0-PO3 20 mA PO3-PO0 40 mA PCI pin 20 mA VDD3 Note VDD5 Input voltage Conditions VI VO IO Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg −65 to +150 °C Note VDD5: Dedicated power supply for clamping diode Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit 3.0 3.3 3.6 V +3.3 V PCI 3.0 3.3 3.6 V +5 V PCI 4.75 5.00 5.25 V 0 +70 °C VDD3 VDD5 Note Note VDD5 Operating ambient temperature TA High-level input voltage VIH1 Input pins except PCI 2.0 5.5 V VIH2 RST_B pin 2.2 VDD5 + 0.5 V VIH3 PCI pins except RST_B 2.0 VDD5 + 0.5 V VIL1 Input pins except PCI 0 +0.8 V VIL2 PCI pin −0.5 +0.8 V Low-level input voltage Note VDD5: Dedicated power supply for clamping diode 12 µPD98409 DC Charateristics (TA = 0 to +70°°C, VDD3 = +3.3 V ±0.3 V) Parameter High-level output voltage Low-level output voltage Symbol Conditions VOH1 IOH = −2.0 mA VOH2 IOH = −12.0 mA Note 1 Note 2 TYP. MAX. Unit 2.4 V 2.4 V VOL1 IOL = 3.0 mA Note 3 0.55 V VOL2 IOL = 6.0 mANote 4 0.55 V VOL3 Note 5 0.40 V 0.40 V 400 mA ±10− ±10 µA 80 200 µA VOL4 IOL = 6.0 mA Note 6 IOL = 12.0 mA Supply current IDD fCLK = 33 MHz, normal transmission/ reception Input leakage current (normal input) II1 VI = VDD3 Input leakage current (E2PDI pin with pull-up resistor) II2 VI = GND Notes 1. MIN. 250 4 10 VOH1 applies to all output pins except pins PO3-PO0. 2. VOH2 applies to pins PO3-PO0. 3. VOL1 applies to PCI output pins AD31-AD0, PCBE3_B-PCBE0_B, PAR, REQ_B and INTR_B. 4. VOL2 applies to PCI output pins FRAME_B, TRDY_B, IRDY_B, DEVSEL_B, STOP_B, SERR_B, and PERR_B. 5. VOL3 applies to pins other than PCI output pins and pins other than pins PO3-PO0. 6. VOL4 applies to pins PO3-PO0. Capacitance (TA = +25°°C, VDD3 = 0 V) Parameter Input capacitance Symbol Conditions MIN. TYP. MAX. Unit CIN f = 1 MHz 10 20 pF Output capacitance COUT f = 1 MHz 10 20 pF I/O capacitance CI/O f = 1 MHz 10 20 pF 13 µPD98409 AC Characteristics (TA = 0 to +70°°C, VDD3 = +3.3 V ± 0.3 V) BUSCLK input Parameter Symbol Conditions MIN. TYP. MAX. Unit 125 ns CLK cycle time tCYCLK 30 CLK high-level width tCLKH 11 ns CLK low-level width tCLKL 11 ns VPPCLK 2 V CLK amplitude CLK through rate , @ À @ À , @ À , @ À , @ À , @ À , @ À , ÀÀ @@ ,, ÀÀ @@ ,, @ À , @ À , @ À , @ À , @ À , ÀÀ @@ ,, @ À , ,,,,,, ÀÀÀ @@@ ,,, ÀÀÀÀÀÀÀ @@@@@@@ ,,,,,,, @ À , ,À@,À@@@@ ,,, ÀÀÀ ,À@,À@ @ À , ,À@ slewCLK 1 4 V/ns MAX. Unit 2.4 V (MIN.) 2.0 V CLK VPPCLK 1.5 V 0.8 V 0.4 V (MAX.) tCLKL tCLKH tCYCLK RST input Parameter RST low-level width RST through rate 14 Symbol Conditions MIN. TYP. tRSTL tCYCLK ns slewRST 50 mV/ns µPD98409 PCI Bus Interface Bus master read Parameter Symbol Conditions MIN. TYP. MAX. Unit CLK↑→FRAME_B valid time tDFRAME 2 11 ns CLK↑→AD (Address) valid time tDADDR 2 11 ns CLK↑→AD (Address) float time tDADDRF 28 ns AD (Data) setup time tSDATA 7 ns Note 1 2 AD (Data) hold time tHDATA CLK↑→PCBE_B valid time tDPCBE CLK↑→PCBE_B float time tDPCBEF CLK↑→IRDY_B valid time tDIRDY CLK↑→IRDY_B float time tDIRDYF TRDY_B setup time tSTRDY 9Note 2 ns tHTRDY Note 1 ns TRDY_B hold time DEVSEL_B setup time 2 2 tHDEVSEL CLK↑→PAR valid time tDPAR CLK↑→PAR float time tDPARF PAR setup time tSPAR PAR hold time tHPAR CLK↑→PERR_B valid time tDPERR CLK↑→PERR_B float time tDPERRF 11 ns 28 ns 11 ns 28 ns 2 tSDEVSEL DEVSEL_B hold time ns 7 ns Note 1 2 2 ns 11 ns 28 ns 7 ns Note 1 2 2 Notes 1. Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns → 2 ns 2. Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns → 9 ns ns 11 ns 28 ns 15 µPD98409 Bus master read CLK ÀÀ,À@ ,À@,À@,, @@ ÀÀ,À@ ,, @@ ÀÀ,À@ @@ À@,,, ÀÀ,À@,À@ ,À@,À@ ,À@ ,À@ @@ ,À@,, ÀÀ @@ ,, ,À@,À@,À@,, ÀÀ @@ ÀÀ @@ @ À , @ À , ,À@,À@,À@,À@,, @ À , @ À , ,À@,À@,À@,À@,À@ ,À@ @ À , ÀÀ,À@ ,À@ @@ ,, ,À@,, @ À , @ À , @ À , @ À , ,À@,À@,À@ ,À@,À@ ,À@ ,À@ ÀÀ @@ @ À , ,À@@@ @ À , @ À , @ À , ,@À,,À@,À@ ,, ,, ÀÀ ÀÀ @@ ,@À ,À@ @ À , ,À@,À@ ,À@,À@,À@,À@,@À,@À,À@,À@ ,À@ @ À , ,@À ,, ÀÀ @@ ,À@,À@,@À,À@ ,À@ @ À , ,À@ ,À@,À@ ,À@,À@ ,À@,À@ ,À@,@À ,, ÀÀ @@ ,, ,À@,À@ ÀÀ @@ tDFRAME FRAME_B tDADDR AD31-AD0 tSDATA tHDATA tDADDRF (Address) (Data) tDPCBE PCBE3_BPCBE0_B tDPCBEF tDIRDYF tDIRDY IRDY_B tSTRDY TRDY_B tSDEVSEL DEVSEL_B tDPAR PAR tDPARF (output) tHTRDY tHDEVSEL tSPAR tHPAR (input) tDPERR PERR_B 16 tDPERRF µPD98409 Bus master write Parameter Symbol Conditions MIN. TYP. MAX. Unit CLK↑ → FRAME_B valid time tDFRAME 2 11 ns CLK↑ → AD (Address) valid time tDADDR 2 11 ns CLK↑ → data valid time tDDATA 2 11 ns CLK↑ → data float time tDDATAF 28 ns CLK↑ → PCBE_B valid time tDPCBE 11 ns CLK↑ → PCBE_B float time tDPCBEF 28 ns CLK↑ → IRDY_B valid time tDIRDY 11 ns CLK↑ → IRDY_B float time tDIRDYF 28 ns 2 2 Note 2 TRDY_B setup time tSTRDY 9 ns TRDY_B hold time tHTRDY 2Note 1 ns 7 ns DEVSEL_B setup time DEVSEL_B hold time tSDEVSEL tHDEVSEL Note 1 2 ns CLK↑ → PAR valid time tDPAR CLK↑ → PAR float time tDPARF PERR_B setup time tSPERR 7 ns PERR_B hold time tHPERR 2Note 1 ns 2 Notes 1. Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns → 2 ns 2. Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns → 9 ns 11 ns 28 ns 17 µPD98409 Bus master write CLK À@,,À@@@ ,,, ,À@,À@ ,, ÀÀ @@ ,, ÀÀ ÀÀ @@ ,, ÀÀ,À@,À@,, @@ ,, ,À@,À@,À@,@À ÀÀ @@ ,À@,À@,À@ ÀÀ,À@,À@ @@ ,, ,À@,À@,À@ ÀÀ @@ ,, @ À , ,À@ ,À@,À@,, ÀÀ,@À @@ tDFRAME FRAME_B tDADDR AD31-AD0 tDDATAF tDDATA (Address) (Data) tDPCBEF tDPCBE PCBE3_BPCBE0_B tDIRDYF tDIRDY IRDY_B TRDY_B DEVSEL_B tSTRDY PERR_B 18 tHTRDY tHDEVSEL tSDEVSEL tDPAR PAR À@,,À@,, ÀÀ,À@,À@,À@,À@ @@ ,À@,À@,À@,À@,À@,À@,À@,À@ ÀÀ @@ ,, ,À@ ,À@,À@,À@,À@ ,À@,, ÀÀ @@ À @ , ,À@,À@ ,À@,À@,À@ ÀÀ @@ ,, À @ , ,À@ ,À@,À@,À@,À@ ,À@,À@,, @ À , ÀÀ @@ @ À , ,@À,À@ ,À@,, ÀÀ @@ ,, ,À@,@À,À@@@ ÀÀ @@ ,@À,@À,À@ ,, ÀÀ (output) tDPARF (output) tSPERR tHPERR µPD98409 Target read Parameter Symbol FRAME_B setup time tSFRAME Conditions MIN. TYP. MAX. 7 Unit ns Note 1 2 FRAME_B hold time tHFRAME AD (Address) setup time tSADDR 7 ns AD (Address) hold time tHADDR 2Note 1 ns CLK↑ → AD (Data) valid time tDDATA 2 CLK↑ → AD (Data) float time tDDATAF PCBE_B setup time tSPCBE PCBE_B hold time tHPCBE ns 11 ns 28 ns 7 ns Note 1 ns Note 2 2 IRDY_B setup time tSIRDY 9 ns IRDY_B hold time tHIRDY 2Note 1 ns CLK↑ → TRDY_B valid time tDTRDY 2 CLK↑ → TRDY_B float time tDTRDYF CLK↑ → DEVSEL_B valid time tDDEVSEL CLK↑ → DEVSEL_B float time tDDEVSELF 2 11 ns 28 ns 11 ns 28 ns PAR setup time tSPAR 7 ns PAR hold time tHPAR 2Note 1 ns CLK↑ → PAR valid time tDPAR 2 CLK↑ → PAR float time tDPARF PERR_B setup time tSPERR PERR_B hold time tHPERR 7 11 ns 28 ns ns Note 1 2 Notes 1. Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns → 2 ns 2. Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns → 9 ns 19 µPD98409 Target read CLK FRAME_B AD31-AD0 ÀÀ,À@,À@ ,À@ @@ ,À@,, , @ À ÀÀ,À@ ,À@,À@ ,À@ @@ ,À@,À@,, ,À@ ,À@ ,, ,À@,À@ ,À@,À@ ÀÀ @@ ,À@,, ÀÀ @@ ,À@,À@ ,À@,À@,À@,À@ ,À@ ,À@,À@,À@,, ,À@,, ÀÀ @@ ,@À,À@ ,À@,À@,À@ ,À@ ÀÀ @@ ,@À ,À@,, ÀÀ @@ À @ , ,À@ ,À@ ÀÀ @@ ,, @ À , @ À , ,À@,À@,À@,À@ ,@À,À@,,, ,À@,À@ ,À@,À@ ÀÀ @@ ,, ÀÀÀ @@@ ,@À,, ÀÀ @@ ,, ,@À ÀÀ @@ tSFRAME tHFRAME tSADDR tHADDR (Data) tHPCBE tSIRDY IRDY_B tDDATAF (Address) tSPCBE PCBE3_BPCBE0_B tDDATA tHIRDY tDTRDYF tDTRDY TRDY_B tDDEVSELF DEVSEL_B tDDEVSEL tSPAR PAR tHPAR (input) tDPAR tDPARF (output) tHPERR PERR_B 20 tSPERR µPD98409 Target write Parameter Symbol FRAME_B setup time tSFRAME Conditions MIN. TYP. MAX. 7 Unit ns Note 1 2 FRAME_B hold time tHFRAME AD (Address) setup time tSADDR 7 ns AD (Address) hold time tHADDR 2Note 1 ns AD (Data) setup time tSDATA 7 ns AD (Data) hold time tHDATA PCBE_B setup time tSPCBE PCBE_B hold time tHPCBE ns Note 1 2 ns 7 ns Note 1 ns Note 2 2 IRDY_B setup time tSIRDY 9 ns IRDY_B hold time tHIRDY 2Note 1 ns CLK↑ → TRDY_B valid time tDTRDY 2 CLK↑ → TRDY_B float time tDTRDYF CLK↑ → DEVSEL_B valid time tDDEVSEL CLK↑ → DEVSEL_B float time tDDEVSELF 2 11 ns 28 ns 11 ns 28 ns PAR setup time tSPAR 7 ns PAR hold time tHPAR 2Note 1 ns CLK↑ → PERR_B valid time tDPERR 2 CLK↑ → PERR_B float time tDPERRF Notes 1. Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns → 2 ns 2. Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns → 9 ns 11 ns 28 ns 21 µPD98409 Target write CLK FRAME_B AD31-AD0 ÀÀ,À@,À@ ,À@ @@ ,, À@,,, @ À , ÀÀ,À@ ,À@,À@ ,À@ ,À@,À@@@ ÀÀ,À@ ,À@,À@ ,À@ @@ ,À@,À@,À@,, ÀÀ @@ ,, ,À@,À@,À@,À@ ,À@,À@ ,À@ ,À@,, ,À@,À@,À@ ,À@,À@ ,À@ ÀÀ @@ ,À@,À@ ,À@,À@ ,À@ ÀÀ @@ ,, ,@À ,À@,, ÀÀ @@ ,@À ,À@,, ,À@ ,@À ÀÀ @@ @ À , @ À , ÀÀ @@ ,, ,À@,À@,À@,À@ ,À@ ,À@ ,À@,À@,@À ,À@,, @ À , ,À@,À@ ÀÀ @@ tSFRAME tHFRAME tSADDR tHADDR tSDATA tSPCBE PCBE3_BPCBE0_B tHDATA (Data) (Address) tHPCBE tSIRDY IRDY_B tHIRDY tDTRDYF tDTRDY TRDY_B tDDEVSELF DEVSEL_B tDDEVSEL tSPAR PAR tHPAR (input) (input) tDPERR PERR_B 22 tDPERRF µPD98409 Bus arbitration Parameter Symbol Conditions MIN. CLK↑ → REQ_B valid time tDREQ 2 GNT_B setup time tSGNT 10 GNT_B hold time Note 2 tHGNT TYP. MAX. Unit 12 ns ns ns Note Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns → 2 ns Bus arbitration CLK ,,,À@,@À ÀÀ @@ tDREQ REQ_B GNT_B À@,,À@ ,À@,À@,À@,, ,, ÀÀ @@ ÀÀ @@ ,À@ tSGNT tHGNT 23 µPD98409 Configuration read Parameter Symbol FRAME_B setup time tSFRAME Conditions MIN. TYP. MAX. 7 Unit ns Note 1 2 FRAME_B hold time tHFRAME ns AD (Address) setup time tSADDR 7 ns AD (Address) hold time tHADDR 2Note 1 ns CLK↑ → AD (Data) valid time tDDATA 2 CLK↑ → AD (Data) float time tDDATAF PCBE_B setup time tSPCBE 11 ns 28 ns 7 ns Note 1 2 PCBE_B hold time tHPCBE IDSEL setup time tSIDSEL 7 ns IDSEL hold time tHIDSEL 2Note 1 ns Note 2 ns Note 1 ns IRDY_B setup time tSIRDY IRDY_B hold time tHIRDY CLK↑ → TRDY_B valid time tDTRDY CLK↑ → TRDY_B float time tDTRDYF CLK↑ → DEVSEL_B valid time tDDEVSEL CLK↑ → DEVSEL_B float time tDDEVSELF CLK↑ → PAR valid time tDPAR CLK↑ → PAR float time tDPARF PAR setup time tSPAR ns 9 2 2 2 2 7 Note 1 2 11 ns 28 ns 11 ns 28 ns 11 ns 28 ns ns PAR hold time tHPAR PERR_B setup time tSPERR 7 ns PERR_B hold time tHPERR 2Note 1 ns 24 Notes 1. Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns → 2 ns 2. Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns → 9 ns ns µPD98409 Configuration read CLK ,À@,À@,, À@, ,@À,À@,, ,À@,, ÀÀ @@ ÀÀ @@ ÀÀ @@ @@ ÀÀ ,À@,À@,À@ ,À@,À@,À@,, ÀÀ @@ ,, @@ ÀÀ ,, ÀÀ @@ ,, @ À , À @ , @ À , ÀÀ @@ ,, @@ ÀÀ ,À@ ,À@,À@ ,À@,À@,À@,À@,À@,, ,À@,@À,, @@ ÀÀ ,, ÀÀ @@ À @ , @@ ÀÀ ,À@,À@ ,À@ ,À@,À@,, ,À@,, @ À , ÀÀ @@ @@ ÀÀ ,, @ À , ,À@,À@,À@,, ÀÀ @@ ,, @@ ÀÀ ,À@,À@ ,À@,À@ ,À@,À@,À@,, ,À@,, ÀÀ @@ @@ ÀÀ ,, ÀÀ @@ ÀÀ @@ ,, @ À , @@ ÀÀ ,, @ À , @ À , @ À , @ À , ÀÀ @@ ,, ÀÀ @@ ,, @@ ÀÀ ,À@,À@,À@,À@ @À,,À@ ,, ,À@,À@,À@,, ,,,, ÀÀÀ @@@ ,,, ÀÀ @@ @@ ÀÀ ,À@,, @@,@À,À@ ÀÀ ,@À,, tHFRAME tSFRAME FRAME_B tSADDR AD31-AD0 PCBE3_BPCBE0_B IDSEL tDDATA tHADDR (Data) (Address) tSPCBE tHPCBE tSIDSEL tHIDSEL tSIRDY IRDY_B tDDATAF tHIRDY tDTRDYF tDTRDY TRDY_B tDDEVSELF DEVSEL_B tDDEVSEL tSPAR PAR tHPAR (input) tDPAR tDPARF (output) tHPERR tSPERR PERR_B 25 µPD98409 EEPROM Interface Parameter Symbol Conditions MIN. TYP. MAX. Unit E2PCLK high-level width tWE2PCLKH tCYCLK × 18 tCYCLK × 18 tCYCLK × 18 + 50 − 50 ns E2PCLK low-level width tWE2PCLKL tCYCLK × 18 tCYCLK × 18 tCYCLK × 18 + 50 − 50 ns E2PCLK↓ → E2PCS valid time tDE2PCS 50 ns E2PCS↑ → E2PCLK tSE2PCS 50 ns P2PCLK↓ → E2PDO valid time tDE2PDO E2PDI → E2PCLK setup time tSE2PDI 500 ns E2PCLK → E2PDI hold time tHE2PDI 70 ns E2PCS↑ → E2PDI (Status) valid delay time tDE2PSTV E2PCS↓ → E2PDI (Status) invalid delay time tDE2PSTI 300 0 À@, ,,,, @ À , ÀÀÀÀ @@@@ @ À , @ À , ,À@,À@,, ÀÀ @@ ,, @ À , @ À , @ À , ÀÀ @@ ,, @ À , ÀÀ @@ @ À , @ À , @ À , ÀÀ,À@ ,À@ @@ ,À@,, ÀÀÀÀ @@@@ ,,,, ,À@,À@ @ À , ,À@,À@,, ÀÀ @@ @ À , @ À , ,À@,À@ EEPROM interface tWE2PCLKH E2PCLK tDE2PCS E2PCS tWE2PCLKL tDE2PDO E2PDO tSE2PDI E2PDI (READ) E2PDI (Status) 26 500 ns 100 ns À@,,, ,À@,À@,À@ ÀÀ @@ ,À@,À@ ,À@,À@ ,À@ tDE2PCS tSE2PCS tHE2PDI tDE2PSTV tDE2PSTI (Status) ns µPD98409 UTOPIA Interface Transmission operation Parameter TCLK↑ → Tx delay time Symbol Conditions MIN. TYP. MAX. Unit tDTX 3 18 ns TCLK↑ → TSOC delay time tDTSOC 3 18 ns TCLK↑ → TENBL_B delay time tDTEN 3 18 ns FULL_B setup time tSFULL 8 ns FULL_B hold time tHFULL 1 ns Reception operation Parameter Symbol Conditions MIN. TYP. MAX. Unit Rx setup time tSRX 8 ns Rx hold time tHRX 1 ns RSOC setup time tSRSOC 8 ns RSOC hold time tHRSOC 1 ns RCLK↑ → RENBL_B delay time tDREN 3 EMPTY_B setup time tSEMPT 8 ns EMPTY_B hold time tHEMPT 1 ns 18 ns 27 28 UTOPIA interface (1) Transmission operation TCLK P9 P8 P7 P6 P5 P4 tDTEN TENBL_B tHFULL FULL_B H1-H4: ATM header P1-P9: Payload data ÀÀÀ @@@ ,,, ,@À ÀÀÀÀÀÀ @@@@@@ ,,,,,, ,À@,À@ ÀÀÀÀÀÀ @@@@@@ ,,,,,, ÀÀÀ @@@ ,,, ,@À ,À@,À@ ,,, ÀÀÀ @@@ ,À@,À@ ÀÀÀÀÀÀÀÀ @@@@@@@@ ,,,,,,,, ,,, ÀÀÀ @@@ ,@À,À@ P3 tSFULL tDTEN P2 INVALID P1 ‘00H’ H1 Tx7-Tx0 tDTSOC tDTSOC H2 TSOC H3 H4 ,À@ ,,,,, ÀÀÀÀÀ @@@@@ ÀÀ @@ ,À@,, ,À@,,,, ,À@,À@ ÀÀÀ @@@ ,,, ÀÀÀÀÀ @@@@@ ,,,,, À @ , ÀÀ @@ ,, À @ , À@,,À@ ,À@,À@ tDTX µPD98409 UTOPIA interface (2) Reception operation RCLK P7 P6 P5 P4 ,@À,@À ÀÀ @@ ,, ÀÀÀÀÀÀ @@@@@@ ,,,,,, ,,,,,, ÀÀÀÀÀÀ @@@@@@ ,À@,À@,À@,À@ ÀÀ @@ ,, P3 P2 INVALID tDREN tDREN P1 RSOC RENBL_B tHEMPT EMPTY_B ÀÀÀ @@@ ,,, ÀÀÀÀÀÀÀÀ @@@@@@@@ ,,,,,,,, ,À@,À@,À@,À@ ÀÀÀÀÀÀÀÀ @@@@@@@@ ,,,,,,,, ,À@ ÀÀ @@ ,À@,, À @ , ,À@,À@ ,À@,À@,À@ ÀÀÀ @@@ ,,, ÀÀÀÀÀ @@@@@ ,,,,, @ À , ÀÀ @@ ,, @ À , ,,À@,@À ,@À,, ÀÀÀ @@@ À@,,, ÀÀ,À@,À@ @@ H5 tHRSOC tSRSOC tSEMPT H2 29 µPD98409 H1-H4: ATM header P1-P7: Payload data H4 INVALID H1 H3 tHRX Rx7-Rx0 tSRX µPD98409 PHY Status Access Write Parameter Symbol MAX. Unit tDPCA 20 ns CLK↑ → PHRW_B delay time tDPHRW 20 ns CLK↑ → PHCE_B delay time tDPHCE 20 ns CLK↑ → CD delay time tDPCD 20 ns PHCE_B↑ → CD float time tFPCD 1tCYCLK + 10 ns MAX. Unit CLK↑ → CA delay time Write timing 4 clocks 1 clock tDPHRW PHRW_B PHOE_B tDPHCE “H” tFPCD tDPCD CD7-CD0 Read Parameter tDPCA tDPHRW tDPHCE PHCE_B TYP. 1tCYCLK − 10 tDPCA CA8-CA0 MIN. @ À , ÀÀÀÀÀÀÀ @@@@@@@ @À,,,,,,,, À @ , À @ , ,À@,, @ À , ,À@,, @ À , ÀÀ @@ ,, ÀÀ @@ @ À , ,À@,@À,À@,À@ ,À@,, ÀÀ @@ ÀÀ @@ @ À , @ À , ,À@,À@,, ,À@ ,,, ÀÀ @@ ÀÀÀ @@@ ,À@,À@,À@ ,À@,À@ ÀÀ @@ ,, ,À@,À@,@À ÀÀ @@ ,, 1 clock CLK Conditions (output) Symbol Conditions MIN. TYP. CD setup time tSPCD 0 ns CD hold time tHPOECD 0 ns CLK↑ → CA delay time tDPCA 20 ns CLK↑ → PHRW_B delay time tDPHRW 20 ns CLK↑ → PHCE_B delay time tDPHCE 20 ns CLK↑ → PHOE_B delay time tDPHOE 20 ns 30 Read timing CA8-CA0 PHRW_B PHCE_B PHOE_B tDPCA tDPCA (input) CD7-CD0 ÀÀ @@ ,, ,,, ÀÀÀ @@@ ,, ÀÀ @@ ,@À,, ÀÀÀÀÀÀÀÀ @@@@@@@@ ,,,,,,,, ,À@,À@,À@,À@,À@,À@,À@ @ À , @ À , @ À , @ À , @ À , ÀÀÀÀÀÀ @@@@@@ ,,,,,, ÀÀ @@ ,, À @ , À @ , ÀÀ @@ ,, @ À , @ À , @ À , @ À , @ À , @ À , @ À , @ À , ÀÀ @@ ,, À @ , @ À , @ À , @ À , @ À , ÀÀ @@ ,, @ À , @ À , @ À , À @ , ÀÀÀÀ @@@@ ,,,, ÀÀ @@ ,, ,, ÀÀ @@ @ À , @ À , , @ À @ À , ,,,, À @ ,À@,À@,À@,,, ÀÀÀ @@@ @ À , CLK 4 clocks 5 clocks 6 clocks 1 clock tDPHRW tDPHCE tDPHCE tDPHOE tDPHOE tHPOECD tSPCD µPD98409 31 µPD98409 Others Parameter Symbol Conditions MIN. TYP. MAX. Unit PHINT_B setup time tSPHI 8 ns PHINT_B hold time tHPHI 1 ns CLK↑ → PO delay time tDPO 2 25 ns CLK↑ → RSTOUT_B delay time tDRSTO 2 25 ns RSTOUT_B output pulse width tWRSTO 11 22 tCYCLK Other timing CLK À@,,À@ ,À@, À @ , ÀÀ @@ ,, À @ ,À@ ÀÀ @@ ,, @ À , @ À , À @ , ,À@,@À ,À@,@À ÀÀÀÀÀÀÀÀÀÀÀ @@@@@@@@@@@ ,,,,,,,,,,, tSPHI PHINT_B tDPO PO3-PO0 tDRSTO RSTOUT_B 32 tWRSTO tHPHI µPD98409 3. PACKAGE DRAWING 240 PIN PLASTIC QFP (FINE PITCH) (32x32) A B 180 181 121 120 detail of lead end S C D R Q 240 1 F G 61 60 H I J M P K M N S L NOTE 1. Controlling dimention S ITEM millimeter. 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 34.6±0.2 1.362±0.008 B 32.0±0.2 1.260±0.008 C 32.0±0.2 1.260±0.008 D 34.6±0.2 1.362±0.008 F 1.25 G 1.25 0.049 0.049 H 0.22 +0.05 –0.04 0.009±0.002 0.004 I 0.10 J 0.5 (T.P.) 0.020 (T.P.) K 1.3±0.2 0.051+0.009 –0.008 L 0.5±0.2 0.020 +0.009 –0.008 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N P 0.10 0.004 3.2±0.1 0.126±0.004 Q 0.4±0.1 0.016 +0.004 –0.005 R 3° +7° –3° 3° +7° –3° S 3.8 MAX. 0.150 MAX. P240GN-50-LMU, MMU-2 33 µPD98409 4. SOLDERING CONDITIONS Solder the product under the following recommended conditions. For details of the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and soldering conditions other than those recommended, consult NEC. Surface Mount Type µPD98409GN-LMU: 240-pin plastic QFP (0.5-mm fine pitch) (32 × 32 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (210°C min.), Number of Note times: once, Number of days: 3 (Afterwards, prebaking is necessary at 125°C for Symbol of Recommended Condition IR35-203-1 20 hours.) <Precaution> Products other than in heat-resistant trays (such as those packaged in a magazine, taping, or non-thermal-resistant tray) cannot be baked in their package. Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per side of device) — Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25°C, 65%RH max. 34 µPD98409 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 35 µPD98409 NEASCOT-S40C and EEPROM are trademarks of NEC Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5