NJU3553 PRELIMINARY 4-BIT SINGLE CHIP OTP MICRO CONTROLLER ■ PACKAGE OUTLINE ■ GENERAL DESCRIPTION The NJU3553 is the C-MOS 4-bit Single Chip OTP type Micro Controller with programmable Flash Memory. It is completely compatible with the NJU3503 in function and the pin configuration. Therefore, the NJU3553 is suitable for the final evaluation before NJU3503 mask generation, the small quantity production and short leadtime. * NJU3553L NJU3553M In this data sheet, only OTP programming and the difference between NJU3553 and NJU3503 are mentioned mainly. Therefore the detail function and specification should be referred on the NJU3503 data sheet. ■ FEATURES ● ● ● ● ● Internal One Time Programmable ROM 2,048 X 8bits Internal Data RAM 128 X 4bits Wide operating voltage range 2.7V ~ 5.5V Package outline SDIP28 / SDMP30 (Compatible with NJU3503) ROM programmer “SUPERPRO/L” by XELTEK co,. ■ PIN CONFIGURATION IN OTP PROGRAMMING MODE [ SDIP28 ] 1 2 28 27 D5 3 4 26 D6 D7 VDD 5 6 7 8 CNT1 CNT2 Open 9 10 11 12 13 VSS 14 NJU3553L D3 D4 25 24 VDD RESET D2 D1 D0 20 19 18 Open D6 D7 23 22 21 D3 D4 D5 VDD Open CNT1 CNT2 Open 17 PROM 16 15 REQ CLK VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NJU3553M [ SDMP30 ] 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD RESET D2 D1 D0 Open PROM Open REQ CLK Note) The pin configuration in Normal operating mode is the same as NJU3503. -1- -2- AVDD ADCK/PC0 VREF/PC1 PE2 AIN5/PE1 AIN4/PE0 AIN3/PD3 AIN2/PD2 AIN1/PD1 AIN0/PD0 SCK/CKOUT SDI(O)/PG1 SDO/PG0 A/D SIO TIMER2 TIMER1 PC ID IR 2048 x 8 bits OTP ROM MUX TLU addr STACK Logic ALU STANDBY CONTROLLER CPU TIMING GENERATOR OSC PRESCALER PORT_B AC PB2 PORT_A Y’ Reg Y Reg CPU CORE 128 x 4 bits RAM X’ Reg X Reg * Refer [INPUT OUTPUT TERMINAL TYPE] INT4 INT3 INT2 Interrupt OSC2 OSC1 RESET TEST VSS VDD ■ BLOCK DIAGRAM CNTI/PF1 EXTI/PF0 INT1 NJU3553 NJU3553 PA3 PB1 PB0 PA2 PA1 PA0 NJU3553 ■ TERMINAL DESCRIPTION IN OTP PROGRAMMING MODE No. NJU NJU 3553L 3553M 27 SYMBOL INPUT / OUTPUT FUNCTION RESET INPUT RESET terminal. When the low-level input-signal, the system is initialized. 29 26-28, 1-3, 5, 6 8, 9 17 16 19 7, 30 15 24-26, 1-5 7, 8 16 15 17 6, 28 14 Note 1) 2) D0 - D7 INPUT/OUTPUT Data bus CNT1 CNT2 REQ CLK PROM VDD VSS INPUT INPUT OUTPUT INPUT INPUT - OTP control input terminal Request output terminal Clock input terminal OTP programming enable terminal Power Source (5V) Power Source (0V) Use at VDD=5V in OTP programming mode. Non connect anything to the other terminals. ■ Difference between NJU3553 (OTP version) and NJU3503 (MASK version) ● Operating mode NJU3553 has two operating modes. One is ”Normal operating mode” and the other is “OTP programming mode”. ● • Normal operating mode The ”TEST” terminal is set to low level. (The terminal is recommended to connect to GND.) Operating voltage range; 2.7V ~ 5.5V. • OTP Programming mode User program is read out from or written into the OTP by the universal programmer “SUPERPRO/L” and converting adapter made by XELTEK co,.(USA). Reset Terminal Type NJU3553 With Pull-up Internal Pull-up Resistance ● NJU3503 Without Pull-up Option information set in the initialization When the initialization is performed(RESET terminal is “L”), the operation information stored in option area is set as shown in the following timing chart . The option information is set in the term of 1 / fOSC x 512clock after RESET releasing and oscillation stability time. After information set, the program counter is set to 0000H and the NJU3553 operates in normal. [ TIMING CHART ] Oscillation Stability Time Option information setting 1/fOSCx512clock Normal Operation Oscillator Clock Oscillation Start RESET PC=0000H fOSC=4MHz about 128µsec -3- NJU3553 ■ ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATINGS UNIT Supply Voltage VDD -0.3 ~ +7.0 V Input Voltage VIN -0.3 ~ VDD + 0.3 V Output Voltage VOUT -0.3 ~ VDD + 0.3 V Analog Supply Voltage AVDD -0.3 ~ VDD + 0.3 V Analog Reference Voltage VREF -0.3 ~ AVDD + 0.3 V AIN0 ~ AIN5 -0.3 ~ AVDD + 0.3 V Analog Input Voltage Operating Temperature Topr -20 ~ +75 °C Storage Temperature Tstg -55 ~ +125 °C Note) The difference of electrical characteristics between NJU3553 (OTP version) and NJU3503 (MASK version) NJU3503 NJU3553 Supply Voltage (VDD) MIN. 2.4V → 2.7V Supply Current 5V (IDD1) Max. (IDD2) Max. (IDD3) Max. (IDD4) Max. (IDD5) Max. 1.2mA 1.2mA 1.6mA 3.6mA 4.0µA → → → 30mA 30mA 30mA 30mA 20µA 0.5mA 0.5mA 0.6mA 1.0mA 2.0µA → → • • 3V -4- (IDD1) Max. (IDD2) Max. (IDD3) Max. (IDD4) Max. (IDD5) Max. → → → 20mA 20mA 20mA 20mA 20µA NJU3553 ■ ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS 1-1 (VDD=3.6~5.5V, VSS=0V, Ta=-20~75°C) PARAMETER Supply Voltage SYM BOL VDD CONDITIONS VDD VDD IDD1 VDD=5V, fOSC=2MHz X’tal Oscillation in Reset VDD IDD2 VDD=5V, fOSC=2MHz Ceramic Oscillation in Reset VDD IDD3 VDD=5V, fOSC=2MHz Supply Current CR Oscillation in Reset VDD IDD4 VDD=5V, fOSC=4MHz Operating (Except ADC) VDD IDD5 VDD=5V, STANDBY Mode AVDD IADD AVDD=VDD=5V, ADCK=225kHz PA0~PA3, AIN0/PD0~ AIN3/PD3, VIH1 AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1, SCK/CKOUT High-Level Input Voltage PB0~PB2, ADCK/PC0, VREF/PC1, VIH2 EXTI/PF0, CNTI/PF1, RESET OSC1 VIH3 PA0~PA3, AIN0/PD0~ AIN3/PD3, VIL1 AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1, SCK/CKOUT Low-level Input Voltage PB0~PB2, ADCK/PC0, VREF/PC1, VIL2 EXTI/PF0, CNTI/PF1, RESET OSC1 VIL3 *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister. MIN TYP 3.6 MAX UNIT NOTE 5.5 V 30 mA *3 30 mA *3 30 mA *3 30 mA *3 20 µA *3 5.0 mA *3 0.7VDD VDD V *1 0.8VDD VDD V *1 VDD-1.0 VDD V 0 0.3VDD V *1 0 0.2VDD V *1 0 1.0 V 3.0 -5- NJU3553 ■ ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS 1-2 (VDD=3.6~5.5V, VSS=0V, Ta=-20~75°C) PARAMETER SYM BOL CONDITIONS VDD=5.5V, VIN=5.5V PA0~PA3, PB0~PB2, ADCK/PC0, High-Level VREF/PC1, AIN0/PD0~AIN3/PD3, IIH Input Current AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, SCK/CKOUT, RESET VDD=5.5V, VIN=0V Without pull-up resistance PA0~PA3, PB0~PB2, ADCK/PC0, IIL1 VREF/PC1, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, Low-Level SCK/CKOUT Input Current VDD=5.5V, VIN=0V With pull-up resistance PA0~PA3, PB0~PB2, ADCK/PC0, IIL2 VREF/PC1, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, SCK/CKOUT, RESET IOH=-100µA High-Level VOH PB0~PB2, SDO/PG0, SDI(O)/PG1, Output Voltage SCK/CKOUT IOL1=400µA VOL1 PB0~PB2, SDO/PG0, SDI(O)/PG1, Low-Level SCK/CKOUT Output Voltage IOL2=15mA VOL2 PA0~PA3, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2 VDD=5.5V, VOH=5.5V Output Leakage IOD PA0~PA3, AIN0/PD0~AIN3/PD3, Current AIN4/PE0, AIN5/PE1, PE2 Except VDD, VSS terminals Input Capacitance CIN fOSC=1MHz Other terminals : 0V *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister. -6- MIN TYP MAX 10 µA *1 -10 µA *1 -100 µA *1 V *2 0.5 V *2 2.0 V *2 10 µA *2 20 pF VDD-0.5 10 UNIT NOTE NJU3553 ■ ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS 2-1 (VDD=2.7~3.6V, VSS=0V, Ta=-20~75°C) PARAMETER Supply Voltage SYM BOL VDD CONDITIONS VDD VDD IDD1 VDD=3V, fOSC=1MHz X’tal Oscillation in Reset VDD IDD2 VDD=3V, fOSC=1MHz Ceramic Oscillation in Reset VDD IDD3 VDD=3V, fOSC=1MHz Supply Current CR Oscillation in Reset VDD IDD4 VDD=3V, fOSC=2MHz Operating (Except ADC) VDD IDD5 VDD=3V, STANDBY Mode AVDD IADD AVDD=VDD=3V, ADCK=225kHz PA0~PA3, AIN0/PD0~AIN3/PD3, VIH1 AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1, SCK/CKOUT High-Level Input Current PB0~PB2, ADCK/PC0, VREF/PC1, VIH2 EXTI/PF0, CNTI/PF1, RESET OSC1 VIH3 PA0~PA3, AIN0/PD0~AIN3/PD3, VIL1 AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1, SCK/CKOUT Low-Level Input Voltage PB0~PB2, ADCK/PC0, VREF/PC1, VIL2 EXTI/PF0, CNTI/PF1, RESET OSC1 VIL3 *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister. MIN TYP 2.7 MAX UNIT NOTE 3.6 V 20 mA *3 20 mA *3 20 mA *3 20 mA *3 20 µA *3 3.5 mA *3 0.8VDD VDD V *1 0.85VDD VDD V *1 VDD-0.3 VDD V 0 0.2VDD V *1 0 0.15VDD V *1 0 0.3 V 2.5 -7- NJU3553 ■ ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS 2-2 (VDD=2.7~3.6V, VSS=0V, Ta=-20~75°C) PARAMETER SYM BOL CONDITIONS VDD=3.6V, VIN=3.6V PA0~PA3, PB0~PB2, ADCK/PC0, High-Level VREF/PC1, AIN0/PD0~AIN3/PD3, IIH Input Current AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, SCK/CKOUT, RESET VDD=3.6V, VIN=0V Without pull-up resistance PA0~PA3, PB0~PB2, ADCK/PC0, IIL1 VREF/PC1, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, Low-Level SCK/CKOUT Input Current VDD=3.6V, VIN=0V With pull-up resistance PA0~PA3, PB0~PB2, ADCK/PC0, IIL2 VREF/PC1, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, EXTI/PF0, CNTI/PF1, SDI(O)/PG1, SCK/CKOUT, RESET IOH=-80µA High-Level VOH PB0~PB2, SDO/PG0, SDI(O)/PG1, Output Voltage SCK/CKOUT IOL1=350µA VOL1 PB0~PB2, SDO/PG0, SDI(O)/PG1, Low-Level SCK/CKOUT Output Voltage IOL2=5mA VOL2 PA0~PA3, AIN0/PD0~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2 VDD=3.6V, VOH=3.6V Output Leakage IOD PA0~PA3, AIN0/PD0~AIN3/PD3, Current AIN4/PE0, AIN5/PE1, PE2 Except VDD, VSS terminals fOSC=1MHz Input Capacitance CIN Other terminals : 0Ｖ *1 Input/output port is set as an Input terminal. *2 Input/output port is set as an Output terminal. *3 Except the current through Pull-up resister. -8- MIN TYP MAX 10 µA *1 -10 µA *1 -100 µA *1 V *2 0.5 V *2 1.0 V *2 10 µA *2 20 pF VDD-0.5 10 UNIT NOTE NJU3553 ■ ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS 1 (VSS=0V, Ta= -20~75°C) PARAMETER SYM BOL CONDITIONS VDD=2.7~3.6V Operating Frequency fOSC VDD=3.6~5.5V Instruction Cycle Time External Clock Pulse Width External Clock Rise Time Fall Time RESET Low-Level Width RESET Rise Time Port Input Level Width Edge Detection (PB1) Rise Time Fall Time Restart Signal (PB0) Rise Time External interrupt input (EXTI) Rise Time Fall Time CNTI Clock Frequency CNTI High-Level Width CNTI Rise Time Fall Time X’tal Resonator Ceramic Resonator External Resistor Oscillation External Clock X’tal Resonator Ceramic Resonator External Resistor Oscillation External Clock MIN TYP MAX 0.03 0.03 2.0 2.0 0.03 1.0 0.03 0.03 0.03 2.0 4.0 4.0 0.03 2.0 0.03 4.0 6/fOSC tC MHz s tCPH tCPL VDD=2.7~3.6V VDD=3.6~5.5V tCPR tCPF VDD=2.7~5.5V tRST VDD=2.7~5.5V tRSR VDD=2.7~5.5V tPIN VDD=2.7~5.5V tEDR tEDF VDD=2.7~5.5V 200 ns tSTR VDD=2.7~5.5V 200 ns VDD=2.7~5.5V 200 ns fCT VDD=2.7~5.5V fOSC/64 Hz tCT VDD=2.7~5.5V tCTR tCTF VDD=2.7~5.5V tEXR tEXF 250 125 UNIT 16600 16600 ns 20 ns 4/fOSC s 20 6/fOSC ms s 6/fOSC s 200 ns -9- NJU3553 ■ AC CHARACTERISTICS 1 TIMING CHART EXTERNAL CLOCK 1/fOSC VIH3 OSC1 VIL3 tCPH tCPF RESET INPUT tRST tCPR tCPL tRSR VIH2 RESET VIL2 PORT INPUT tPIN VIH1, VIH2 PORT VIL1, VIL2 EDGE DETECTOR INPUT tEDF tEDR VIH2 PB1 VIL2 RESTART SIGNAL INPUT tSTR VIH2 PB0 VIL2 EXTERNAL INTERRUPT tEXR tEXF VIH2 EXTI VIL2 TIMER2 EXTERNAL CLOCK TIMING CHART 1/fCT VIH2 CNTI VIL2 tCTR - 10 - tCT tCTF NJU3553 ■ ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS 2 SERIAL INTERFACE (VSS=0V, VDD=2.7~5.5V, Ta= -20~75°C) PARAMETER SYM BOL Serial Operating Frequency fSC Clock Pulse Width Low-Level tSCL CONDITIONS MIN Internal Clock External Clock Internal Clock tSCH Internal Clock VDD=2.7~3.6V fOSC=2MHz VDD=3.6~5.5V fOSC=4MHz UNIT 3.0 µs 1.5 1.0 VDD=2.7~3.6V fOSC=2MHz VDD=3.6~5.5V fOSC=4MHz 3.0 µs 1.5 External Clock SDI setup Time tDS To SCK SDI Hold time tDH To SCK SDO Data t Fix Time To SCK DCD * The dividing ratio of the internal clock is 1/2. ■ AC CHARACTERISTICS 2 MAX (1/12)×fOSC* Hz 500k External Clock Clock Pulse Width High-Level TYP 1.0 0.5 µs 0.5 µs 0.5 µs SERIAL INTERFACE TIMING CHART 1/fSC tSCL tSCH VIH1 SCK VIL1 tDS tDH VIH1 SDI(O) INPUT DATA VIL1 tDCD VOH OUTPUT DATA SDO/SDI(O) VOL1 - 11 - NJU3553 ■ ELECTRICAL CHARACTERISTICS A/D CONVERTER CHARACTERISTICS (VDD=AVDD=2.7~5.5V, VSS=0V, Ta=25°C, fOSC=4MHz) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT - 8 - bits ±2 LSB Resolution - Absolute Accuracy - VDD=5V, AVDD=5V, VREF=5V Conversion Time tCONV VDD=5V, AVDD=5V, VREF=5V Reference Voltage VREF 2.7 AVDD V VIA VSS VREF V 225 kHz Analog Input Voltage ADCK Frequency - 12 - fADCK µs 40 NJU3553 ■ OPTION as same as mask version (NJU3503) PA0 PA2 PA3 PB1 EXTRA FUNCTION REMARKS IOP IO IOP IO IOP IO IOP IO PA1 PB0 Programmable Input / Output Port of Output SYMBOL Port of Input 1) INPUT OUTPUT Terminal Selection All of input-output terminals select a terminal type for each port from the following table1 and table2 by the mask option. [ CIRCUIT TYPE TABLE 1 ] TERMINAL TYPES Input / Output Terminal*1 ISP IS ISP IS OC Restart signal input OC Edge detection E D R F D With restart input Without restart input Rise edge detection Fall edge detection Without edge detection PB2 ISP OC IS ACP External clock input ADCK / PC0 ISP AC (ADCK) *2 IS AD Reference input VREF / PC1 ISP (VREF) *2 IS AD Analog input to ADC AIN0 / PD0 ICP ONP (AIN0) *2 IC ON AD Analog input to ADC AIN1 / PD1 ICP ONP (AIN1) *2 IC ON AD Analog input to ADC AIN2/ PD2 ICP ONP (AIN2) *2 IC ON AD Analog input to ADC AIN3 / PD3 ICP ONP (AIN3) *2 IC ON AD Analog input to ADC AIN4 / PE0 ICP ONP (AIN4) *2 IC ON AD Analog input to ADC AIN5 / PE1 ICP ONP (AIN5) *2 IC ON PE2 ICP ONP IC ON Note) The symbol in the above table is the same as in mask option generator software. *1) The symbol and the detail circuits of INPUT OUTPUT TERMINAL are written in INPUT OUTPUT TERMINAL TYPE. *2) The pull-up resistance is added to the terminal selected as the extra function. - 13 - NJU3553 [ CIRCUIT TYPE TABLE 2 ] TERMINAL TYPES ISP IS ISP IS CNTI /PF1 SDO / PG0 SDI(O) / PG1 *2 SCK / CKOUT *2 *3 ICP IC OC OC Programmable Input / Output EXTI / PF0 Port of Output SYMBOL Port of Input Input / Output Terminal*1 EXTRA FUNCTION IIP II IIP II SO SDP SD SCP SC REMARKS External interrupt input R Rise interrupt input (EXTI) F Fall interrupt input External clock of Timer 2 input (CNTI) Serial data output MSB MSB first Serial data input/output LSB LSB first Serial clock input/output Output clock divide by pre-scaler Note) The symbol in the above table is the same as in mask option generator software. *1) The symbol and the detail circuits of INPUT OUTPUT TERMINAL are written in INPUT OUTPUT TERMINAL TYPE. *2) The pull-up resistance is added to the terminal selected as the extra function. *3) When Serial INPUT-OUTPUT is selected, “SCK” is selected automatically. When it is not selected, “CKOUT” is selected automatically. - - 14 - NJU3553 [MASK OPTION LIST] SYM BOL SYM BOL FUNCTION FUNCTION ICP C-MOS input with pull-up resistance R Rise edge detection ISP C-MOS Schmitt trigger input with pull-up resistance F Fall edge detection IC C-MOS input D Prohibition of edge detection IS C-MOS Schmitt trigger input MSB Serial data order MSB first Nch-FET Open-Drain output with pull-up resistance LSB Serial data order LSB first ONP OC C-MOS output 1 1/2 ON Nch-FET Open-Drain output 2 1/4 IIP External interrupt resistance 3 1/8 4 1/16 5 1/32 II SDP input with pull-up External interrupt input Serial data resistance input/output with pull-up SD Serial data input/output 6 1/64 SO Serial data output 7 1/128 Serial clock input/output with pull-up resistance 8 1/256 SC Serial clock input/output 9 1/512 AD A/D converter a 1/1024 External clock input with pull-up resistance for ADC b 1/2048 AC External clock input for ADC c 1/4096 IOP Programmable input/output with pull-up resistance E permission Programmable input/output D prohibit SCP ACP IO - 15 - NJU3553 [ INPUT OUTPUT TERMINAL TYPE ] Types With Pull-up Without Pull-up Type ICP Type IC AIN0/PD0 ~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2, SDI(O)/PG1 Type ISP Type IS PB0~PB2, ADCK/PC0, VREF/PC1, EXTI/PF0, CNTI/PF1 Type ON PB0~PB2, SDO/PG0, SDI(O)/PG1 Type ONP Type ON AIN0/PD0 ~AIN3/PD3, AIN4/PE0, AIN5/PE1, PE2 Type IOP Type IO PA0~PA3 C-MOS INPUT TERMINAL Terminals SCHMITT TRIGGER PROGRAMMABLE INPUT OUTPUT TERMINAL OUTPUT TERMINAL C-MOS - 16 - N-channel(Nch) OPEN DRAIN C-MOS INPUT / Nch OPEN DRAIN OUTPUT NJU3553 2) Re-start signal Input Selection PB0 terminal performs as the re-start terminal to return from “STANDBY” mode. It is selected by mask option. The STANDBY mode is released by the rising edge of the input signal to PB0 terminal, and the CPU restarts the execution from the last address before the STANDBY mode in. 3) Edge Detector Selection PB1 terminal is added the “Edge detect function” by the mask option. Rising edge Falling edge 4) External Interrupt of the edge Selection When the interrupt function is set by mask option. PF0 terminal performs as the interrupt input terminal. The polarity of the edge, rising as “low to high” or falling as “high to low”, is selected by the mask option. Rising edge Falling edge 5) The data order (MSB, LSB) of the Serial Interface The data order of the Serial Interface is selected select either MSB or LSB first by the mask option. 6) A/D Control Clock A/D Control Clock is selected either the external clock from ADCK terminal or the internal clock from the prescaler by the mask option. 7) Dividing ration of the internal clock Each dividing ration of the count clocks of Timer1 and Timer2, the Internal shift clock of the Serial Interface, the clock of the A/D control clock and the output clock through the SCK/CKOUT terminal is selected among the following by the mask option. The frequency of each clock is determined by the dividing ration and the 1-instruction term (1/fOSCx6). 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024, 1/2048, 1/4096 Note) As Timer2 clock, the external clock or the internal is selected by the program. As the shift clock of the serial interface, the external clock or the internal is selected by the program. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 17 -