NJU6533 PRELIMINARY 1/3, 1/4 Duty LCD Driver ! GENERAL DESCRIPTION ! PACKAGE OUTLINE NJU6533 is a 1/3 or 1/4 duty segment type LCD driver. It incorporates 4 common driver circuits and 32 segment driver circuits. NJU6533 can drive maximum 96 segments in 1/3 duty ratio and maximum 128 segments in 1/4 duty ratio. Controlled by MPU, NJU6533 can be used in many LCD applications NJU6533KQ1 ! FEATURES # LCD driving circuit # Programmable Duty Ratio 1/3 duty ratio 1/4 duty ratio # Programmable Bias Ratio # Serial Data Transfer # Built-in Oscillator # Display OFF # Operating Voltage # C-MOS Technology # Package Outline :Max. 32outputs (4 outputs as for general purpose ports) :Driving max. 96 segments :Driving max. 128 segments :1/2, 1/3 bias ratio :Shift clock max. 2MHz :CR oscillation with external resistor, or external oscillation signal input. :INHb pin :3V / 5.0V :P-Sub :QFN48 ! BLOCK DIAGRAM COM1 COM4 SEG1 SEG8 SEG9 SEG16 SEG17 SEG24 SEG25 SEG32/P4 VDD VLCD COM Drivers Segment Drivers /General Purpose Output Ports V1 V2 VSS Data Latch Circuit INHb OSC1 Oscillator Display Data Register OSC2 CSb SCK Decoder Command Register SI RSTb Ver.2004-03-05 Power ON Reset Circuit -1- SEG23 SEG22 SEG21 26 25 SEG26 SEG25 30 27 SEG28 SEG27 SEG24 SEG29/P1 32 31 29 28 SEG31/P3 SEG30/P2 SEG32/P4 35 34 33 ! PIN CONFIGURATION 36 NJU6533 37 38 24 23 39 22 SEG19 SEG18 VSS 40 21 SEG17 INHb 41 42 20 19 SEG16 VLCD V1 V2 RSTb CSb NJU6533 SEG20 SEG15 SEG14 SEG5 SEG3 SEG1 SEG2 COM3 COM4 COM1 COM2 11 12 SEG10 SEG9 10 14 13 SEG7 SEG8 47 48 SEG6 OSC1 OSC2 8 9 SEG12 SEG11 SEG4 16 15 6 7 45 46 3 4 5 SCK VDD 2 18 17 1 SI 43 44 SEG13 ! TERMINAL DISCRIPTION No. 46 Pad Name VDD 37 VLCD 38, 39 V1, V2 40 VSS 41 INHb 42 RSTb 43 CSb 44 45 47, 48 1~4 5~32 SI SCK OSC1, OSC2 COM1 ~ COM4 SEG1 ~ SEG28 33~36 SEG29/P1 ~ SEG32 /P4 -2- Function Power supply: 3V /5V LCD driving voltage VLCD ≥ V1 ≥ V2 ≥ VSS, VLCD ≥VDD Bias At 1/3 bias ratio, keep V1- V2 open At 1/2 bias ratio, short V1- V2 GND VSS =0V Display OFF When INHb is "H", display is ON, and when INHb is "L", display is off. When INHb is “L", all segment and common drivers output VSS, and the oscillator stop operation. But, if at the same time RSTb="L", the oscillator functions and all segment and common drivers output VSS Reset When RSTb is “L", command register and latch circuit is reset Chip select When CSb is "L", data can be read in. Serial data input (8 bit=1word) Serial clock External resistor connection pin for CR oscillation, or external clock input pin. When external clock is used, input the signal to OSC1 and keep OSC2 open. Common driver outputs Segment driver outputs Segment driver outputs/general purpose output ports These 4 pins can be used as segment driver outputs or general purpose output ports by setting Command Register. When selected as general purpose ports, data can be outputted via these ports during COM1 timing. According to transferred data, "H"=VDD or "L"=VSS will be outputted. Ver.2004-03-05 NJU6533 ! FUNCTION DESCRIPTION (1) Block Function • Oscillator The oscillator includes a built-in capacitor and an external resistor. It generates clock signal for LCD driving. use external clock, input the clock signal to OSC1 and keep OSC2 open. • Decoder Input serial data is decoded and sent to the appropriate block. • Command Register Command data is written to this 8 bits command register to control NJU6533 operation. • Display Data Register Data is written to this 8 bits register as display data. • Latch Circuit Data stored in display data register is assigned to the corresponding SEG/port. • Segment Driver/General Purpose Ports Basing on display data, segment drivers output LCD SEG driving signal. And, SEG29/P1 ~ SEG32/P4 pins can be selected as segment driver output or general-purpose ports by instruction. • Common Driver Common drivers output LCD COM driving signal. • Power On Reset When power is on, NJU6533 is automatically initialized. And if RSTb=”L”, NJU6533 is reset too. Ver.2004-03-05 When -3- NJU6533 ! APPLICATION CIRCUIT • 1/4 duty, 1/3 bias VLCD VDD VLCD + + SEG1 VDD VSS SEG34/P4 V1 NJU6533 V2 RSTb INHb CSb SCK SI OSC1 From MPU • COM1 COM2 COM3 COM4 LCD Panel OSC2 1/4 duty, 1/2 bias VLCD VDD VLCD + + SEG1 VDD VSS SEG34/P4 V1 NJU6533 V2 From MPU Note) RSTb INHb CSb SCK SI OSC1 COM1 COM2 COM3 COM4 LCD Panel OSC2 Because display data is not yet stable just after VDD on, if LCD panel is turned on, unexpected pattern will be displayed, therefore, keep INHb terminal to “L” level until data transfer from MPU is over. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -4- Ver.2004-03-05