NJU8714 NJU3555 STEREO BTL OUTPUTS SWITCHING DRIVER FOR Class D AMPLIFIER GENERAL DESCRIPTION PACKAGE OUTLINE The NJU8714 is a stereo BTL outputs switching driver for class D amplifier. It receives PWM/PDM signals from DSP outputs, and drives headphones or speakers by BTL outputs. Output drivers are composed of Series-Connected N-channel FETs, and output voltage levels can be controlled by variable power supply with keeping all of input signal information. The NJU8714 incorporates BTL outputs amplifiers, which eliminate AC coupling capacitors. Also, it provides “SEL” terminal which selects “Synchronous” or “Asynchronous”. “Asynchronous” can be reduced the operating current. Therefore, it is suitable for portable audio set and others. NJU8714VB2 PIN CONFIGURATION FEATURES 2-channel 1bit Audio Signal Input Stereo BTL Outputs Output Power : Typ.150mW@8Ω BEEP Function Standby Function Output Driver Control Function Operating Voltage VDD: 1.7V to 2.7V VDDO: 0V to 2.0V VG: 4.5V to 5.25V CMOS Technology Package Outline :SSOP20-B2 MCK VSS HALTB DIN1 BEEPIN OBEEP1 OUT1 VSSO OUT1X VDDO1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD SEL STBYB DIN2 VG OBEEP2 OUT2 VSSO OUT2X VDDO2 BLOCK DIAGRAM VDD VSS VG VDDO1 DIN1 Level Shifter OUT1 Control Logic Pre Driver OUT1X VSSO VDDO2 DIN2 Level Shifter MCK Level Shifter STBYB Level Shifter HALTB Level Shifter SEL Level Shifter OUT2 Control Logic Pre Driver OUT2X VSSO OBEEP1 BEEPIN OBEEP2 Ver.2004-05-21 -1- NJU8714 TERMINAL DESCRIPTION No. 1 2 3 4 5 6 7 8,13 9 10 11 12 14 15 16 17 18 SYMBOL MCK VSS HALTB DIN1 BEEPIN OBEEP1 OUT1 VSSO OUT1X VDDO1 VDDO2 OUT2X OUT2 OBEEP2 VG DIN2 STBYB I/O I I I I O O O O O O I I FUNCTION Master Clock Input Terminal Power GND: VSS=0V (Note.1) Output Driver Control Terminal 1bit Data Input Terminal 1 BEEP Signal Input Terminal BEEP Output terminal 1 Positive Output Terminal 1 Output GND terminal: VSS=0V (Note. 1) Negative Output 1 Output Power supply 1(Note. 2) Output Power supply 2(Note. 2) Negative Output 2 Positive Output Terminal 2 BEEP Output terminal 2 Pre-driver Power supply 1bit Data Input Terminal 2 Standby control terminal (L:Standby) Input Signal Synchronization With “MCK” 19 SEL I (H: Synchronous., L: Asynchronous.) 20 VDD Power Supply: VDD=2.5V (Note. 1) Pin No.2(VSS), 8(VSSO) and 13(VSSO) should be connected at the nearest point to the IC. (Note. 2) Pin No.10(VDDO1) and 11(VDDO2) should be connected at the nearest point to the IC. INPUT TERMINAL STRUCTURE VDD Input Terminal VSS MCK, HALTB, DIN1, DIN2, BEEPIN, STBYB, SEL -2- Ver.2004-05-21 NJU8714 NJU3555 FUNCTIONAL DESCRIPTION (1) Signal Output The OUT1/1X and OUT2/2X generate respectively L-channel and R-channel output signals, which will be converted to analog signals via external 2nd-order or higher LC filter. A switching regulator with a high response against a voltage fluctuation is the best selection for the VDDO1 and VDDO2, which are the power supply for output drivers. To obtain better T.H.D. performance, the stabilization of the power is required. (2) Master Clock (MCK) Input 1-bit audio signals such as PWM or PDM to the DIN1 and DIN2 pins. By setting the SEL pin to ”H”, master clock (MCK) synchronizes the audio signal inputs (DIN1 and DIN2). In case of “SEL” = “L”, input signals go into the amplifier circuits by own timing. Therefore, it requires careful design of PCB patterns from DSP to NJU8714. The setup time and the hold time should be kept in the AC characteristics because DIN1 and DIN2 are fetched with the rising edge of MCK. MCK requires jitter-free or jitter as small as possible because the jitter downs S/N ratio. (3) Power Supply VDD : Power supply for input part. VG : Power supply for control logic and pre-driver which drives the transistor gates of output drivers. It requires much higher power supply voltage than VDDO1 and VDDO2 for better T.H.D.. VDDO1, VDDO2 : Power supply for output drivers. (4) Output Control Output circuit is selected by the conditions of STBYB, HALTB, SEL, DIN1, DIN2 and MCK. STBYB L H L HALTB H H L H SEL * * * L H DIN1, DIN2 * * * L H L H MCK * * * * OUT1 OUT2 OUT1X OUT2X VSSO VSSO VSSO VSSO Hi-z VSSO VDDO1 VSSO VDDO1 Hi-z VSSO VDDO2 VSSO VDDO2 Hi-z VDDO1 VSSO VDDO1 VSSO Hi-z VDDO2 VSSO VDDO2 VSSO *Don’t care BEEP circuit is operated regardless of STBYB and HALTB. (5) Input Signal Synchronization Function DIN1 and DIN2 are synchronized with master clock by setting SEL pin to ”H”. By setting SEL pin to ”L”, DIN1 and DIN2 are asynchronous with master clock. (6) Output Driver Control Function By setting HALTB pin to ”L”, high side output drivers become OFF and Low side output drivers become ON, then both of OUT1/1X and OUT2/2X output VSSO level signals. This function works regardless of STBYB pin setting. (7) Standby Control Function By setting STBYB pin to ”L”, the NJU8714 becomes standby condition. During standby condition, by setting HALTB to ”L”, OUT1/1X and OUT2/2X become VSSO, and by setting HALTB pin to ”H”, OUT1/1X and OUT2/2X become Hi-z. To save the power supply current at standby, MCK requires ”L” level. Ver.2004-05-21 -3- NJU8714 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL VDD VG VDDO RATING -0.3 to +2.75 VDD to +5.5 -0.3 to +5.5 UNIT Input Voltage Vin -0.3 to VDD+0.3 V Operating Temperature Topr -40 to +85 °C Storage Temperature Tstg -40 to +125 °C PD 450* mW Supply Voltage Power Dissipation V * : Mounted on two-layer board of based on the JEDEC. Note.1) All voltage values are specified as VSS=0V. Note.2) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electrical characteristics conditions will cause malfunction and poor reliability. Note.3) The relations of VDDO < VG must be maintained during operations. ELECTRICAL CHARACTERISTICS (Ta=25°C, VDD=2.5V, VG=5.0V, VDDO1= VDDO2=1.7V, VSS=VSSO=0V, STBYB=HALTB=SEL=2.5V, Load Impedance=32Ω, fS=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT VDD Supply Voltage VDD - 1.7 2.5 2.7 VDDO1,2 Input Voltage VG Supply Voltage VDDO VG 0 4.5 5.0 2.0 5.25 V Output Driver High side Resistance RHPH - 1.2 2 Ω Output Driver Low side Resistance RHPL OUT1, OUT1X, OUT2, OUT2X = VDDO1,2 – 0.1V VG=5.0V OUT1, OUT1X, OUT2, OUT2X = 0.1V VG= 5.0V - 1.2 2 Ω Beep High side Resistance RBEEPH OBEEP1, OBEEP2= VDD– 0.1V - 9.0 15 Ω Power Supply Current At Standby IST - - 1.0 uA - 0.05 0.1 - 0.25 0.5 1.0 2.0 0.7VDD - VDD V 0 - 0.3VDD V - - ±1.0 uA Power Supply Current At Operating (Mute signal input) Input Voltage Input Leakage Current IDD IDDO IG VIH VIL ILK Stopping MCK, DIN1, DIN2, BEEPIN STBYB= 0V No-load operating, MCK= 256fS, DIN1, DIN2= 32fS, VDDO1= VDDO2= 0.18V MCK, DIN1, DIN2, BEEPIN, HALTB, STBYB, SEL mA Note 1) High side resistance and low side resistance depend on VG and VDDO. Therefore, VG and VDDO should be adjusted on the application system. Note 2) Output power using 8Ω speaker is 150mW(TYP:THD+N=10%) at the following condition. →VDD=2.5V, VG=5.0V, VDDO1= VDDO2=3.0V -4- Ver.2004-05-21 NJU8714 NJU3555 TIMING CHARACTERISTICS • Audio Signal Input tMCKL tMCKH 0.7VDD 0.3VDD MCK 0.7VDD DIN1,DIN2 0.3VDD tDS tDH (Ta=25°C, VDD=2.5V, VDDO1=VDDO2=1.7V, VSS=VSSO=0V, STBYB=HALTB=SEL=2.5V, fs=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT • MCK Frequency fMCKI 8 - 35 MHz MCK Pulse Width (H) tMCKH 9 - - ns MCK Pulse Width (L) tMCKL 9 - - ns DIN1,DIN2 Setup Time tDS 5 - - ns DIN1,DIN2 Hold Time tDH 5 - - ns BEEP Frequency fb 0.1 20 kHz Output Control Signal Input 0.9VDD BEEPIN, HALTB STBYB, SEL 0.1VDD tUP tDN (Ta=25°C, VDD=2.5V, VDDO1=VDDO2=1.7V, VSS=VSSO=0V, STBYB=HALTB=SEL=2.5V, fs=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Rise Time tUP - - 50 ns Fall Time tDN - - 50 ns Ver.2004-05-21 -5- NJU8714 APPLICATION CIRCUIT -Load Impedance: 32Ω 100uH OUT1(7) MCK(1) 0.22uF HALTB(3) 100uH STBYB(18) OUT1X(9) DIN1(4) DIN2(17) VDD 10uF 2.2u NJU8714 SEL(19) 32Ω Speaker 100uH OUT2(14) 0.22uF 100uH 0.22uF OUT2X(12) VG(16) VDDO1(10) VDD(20) 0.22uF 32Ω Speaker VG 2.2uF 100uF VDDO VSSO(8) VSS(2) VDDO2(11) 2.2uF 100uF 2.2uF 10uF VSSO(13) -Load Impedance: 8Ω 22uH OUT1(7) MCK(1) 1.0uF HALTB(3) 22uH STBYB(18) OUT1X(9) DIN1(4) DIN2(17) VDD 10uF 2.2u VDD(20) NJU8714 SEL(19) 1.0uF 8Ω Speaker 22uH OUT2(14) 1.0uF 22uH 1.0uF OUT2X(12) VG(16) VDDO1(10) 2.2uF 100uF 8Ω Speaker VG VDDO VSSO(8) VSS(2) VDDO2(11) 2.2uF 100uF 2.2uF 10uF VSSO(13) Note 3) De-coupling capacitors must be connected between each power supply pin and GND pin. Note 4) The power supply for VDDO requires fast driving response performance such as a switching regulator for T.H.D.. Note 5) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please consider and check the circuit carefully to fit your application. -6- Ver.2004-05-21 NJU8714 NJU3555 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2004-05-21 -7-