SM5165AV PLL Synthesizer IC NIPPON PRECISION CIRCUITS INC. OVERVIEW PINOUT(TOP VIEW) ■ ■ ■ ■ ■ ■ ■ 16 FIN VSS TEST Up to 90 MHz operating frequency (VDD1 = VDD2 = 0.95 V) Up to 100 MHz operating frequency (VDD1 = VDD2 = 1.00 V) Supply voltages • VDD1 = VDD2 = 0.95 to 1.5 V (prescaler, counters) • VDD3 = 2.0 to 3.3 V (charge pump) 40 to 16376 reference frequency divider ratio range (with 1/8 prescaler built-in) 1056 to 262143 operating frequency divider ratio range Power-save function for reduced power dissipation −10 to 60 °C operating temperature range 16-pin VSOP Molybdenum-gate CMOS process APPLICATIONS ■ 1 DO DB NC 8 XIN XOUT LE CLK DATA OPR VDD2 9 VDD3 PACKAGE DIMENSIONS Unit: mm 16-pin VSOP 4.4 0.2 6.4 0.2 ■ VDD1 RO FEATURES ■ 16pin VSOP 5165AV The SM5165AV is a PLL synthesizer IC developed for application in pagers and fabricated using NPC’s Molybdenum-gate CMOS process. It incorporates independently-controlled reference frequency and operating frequency dividers, and operates from a low-voltage supply to realize low power dissipation. 0 + 0.1 0.05 0.15 - 5.1 0.2 Pagers ORDERING INFOMATION Device Package SM5165AV 16pin VSOP 0.65 0.10 0.05 1.15 0.1 0 10 + 0.10 0.22 - 0.05 0.5 0.2 NIPPON PRECISION CIRCUITS—1 SM5165AV BLOCK DIAGRAM 1/8 PRESCALER XIN VDD1 AREA XOUT VDD2 AREA VDD2 OPR 22 BIT SHIFT REGISTER LATCH SELECTER CLK LEVEL SHIFTER ∗ PHASE DETECTOR LEVEL SHIFTER VDD1 AREA 18 BIT N COUNTER FIN RO VDD3 AREA 18 BIT LATCH VDD1 TEST VDD2 AREA 11 BIT LATCH DATA LE 11 BIT R COUNTER VDD3 BOOSTER S. G. DB CHARGE PUMP DO LEVEL SHIFTER VDD2 AREA VSS WINDOW GENERATOR ∗Protection diodes are connected to VDD3. Logic level : V DD2 to V DD3 PIN DESCRIPTION Number Name I/O Description 1 VDD1 – Reference frequency and comparator frequency prescaler and counter 1 V supply 2 FIN I Operating frequency divider input pin. Feedback resistor built-in for AC-coupled inputs. 3 VSS1 – Ground pin 4 RO O Test output. LOW-level output for (1, 0) test bit patter. Leave open for normal operation. 5 TEST I Test pin. Pull-down resistor built-in. Leave open or connect to ground for normal operation. 6 DO O Phase detector output pin. Built-in charge pump and tristate output means that this output can be connected to a low-pass filter. The output polarity is preset for connection to a passive filter. 7 DB O Booster signal output for faster locking 8 NC – No connection 9 VDD3 – Phase comparator, charge pump and booster signal 3 V supply 10 VDD2 – Shift register and latch 1 V supply. Should be kept at the same potential as VDD1. 11 OPR I Power-save control pin. Operation when HIGH, standby mode when LOW. 12 DATA I Control data input pin 13 CLK I Control data clock input pin 14 LE I Control data latch enable signal input pin 15 XOUT O 16 XIN I Reference frequency divider crystal oscillator connection pins. Alternatively, an external clock input can be connected to XIN. The clock is also output on XOUT. Feedback resistor built-in for AC-coupled inputs. NIPPON PRECISION CIRCUITS—2 SM5165AV SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage Input voltage range Symbol Condition Rating Unit V DD1,2 −0.3 to 2.0 V V DD3 −0.3 to 7.0 V V IN1 FIN, XIN, TEST V SS − 0.3 to V DD1,2 + 0.3 V V IN2 OPR, CLK, DATA, LE V SS − 0.3 to V DD3 + 0.3 V Storage temperature range Tstg −40 to 125 °C Power dissipation PD 150 mW Soldering temperature Tsld 255 °C Soldering time tsld 10 s Rating Unit V DD1,2 0.95 to 1.5 V V DD3 2.0 to 3.3 V Tstg −10 to 60 °C Recommended Operating Conditions VSS = 0 V Parameter Supply voltage Storage temperature range Symbol Condition Electrical Characteristics VSS = 0 V, VDD1 = VDD2 = 0.95 to 1.5 V, VDD3 = 2.0 to 3.3 V, Ta = −10 to 60 °C Rating Parameter Symbol VDD1, VDD2 operating current consumption IDD1 VDD3 operating current consumption IDD2 VDD2 standby current IDD3 VDD3 standby current FIN maximum operating input frequency Condition typ max Note 1. – 0.70 1.10 Note 2. – 0.75 1.20 – 10 – µA – 0.1 – µA – 0.01 10.0 µA V DD1,2 = 0.95 to 1.50 V 90 – – V DD1,2 = 1.00 to 1.50 V 100 – – mA Note 3. IDD4 fmax1 Unit min 300 mVp-p sine wave MHz XIN maximum operating input frequency fmax2 300 mVp-p sine wave. Note 4. 16 – – MHz FIN minimum operating input frequency fmin1 300 mVp-p sine wave – – 40 MHz XIN minimum operating input frequency fmin2 300 mVp-p sine wave. Note 4. – – 9 MHz V DD1,2 = 0.95 to 1.50 V, fFIN = 90 MHz, AC coupling 0.3 – – V DD1,2 = 1.00 to 1.50 V, fFIN = 100 MHz, AC coupling 0.3 – – fXIN = 16 MHz, AC coupling 0.3 – – Vp-p – – 0.2VDD2 V FIN input amplitude XIN input amplitude OPR, CLK, DATA, LE LOW-level input voltage V FIN V XIN V IL Vp-p NIPPON PRECISION CIRCUITS—3 SM5165AV Rating Parameter Symbol OPR, CLK, DATA, LE HIGH-level input voltage V IH FIN LOW-level input current IIL1 XIN LOW-level input current IIL2 FIN HIGH-level input current IIH1 Condition Unit min typ max 0.8VDD2 – V DD3 V – – 60 µA – – 10 µA – – 60 µA – – 10 µA V IL = 0 V V IH = V DD1 XIN HIGH-level input current IIH2 DO, DB LOW-level output current IOL Note 5. 1.0 – – mA DO, DB HIGH-level output current IOH Note 6. 1.0 – – mA Tristate output high-impedance leakage current IOZL VOL = 0 V – – 100 nA IOZH VOH = V DD3 – – 100 nA 2 – – µs 2 – – µs 2 – – µs DATA → CLK setup time tSU1 CLK → LE setup time tSU2 Hold time Note 7. tH 1. V DD1 = V DD2 = 0.95 to 1.05 V, V DD3 = 2.7 to 3.3 V, fFIN = 90 MHz (300 mVp-p sine wave), fXIN = 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no output load 2. V DD1 = V DD2 = 1.00 to 1.05 V, V DD3 = 2.7 to 3.3 V, fFIN = 100 MHz (300 mVp-p sine wave), fXIN = 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no output load 3. V DD1 = 0 V, V DD2 = 0.95 to 1.05 V, V DD3 = 2.7 to 3.3 V, OPR = LOW, no input/output load (i.e. CLK = DATA = LE = 0 V) 4. Externally-input sine wave 5. DO and DB outputs are derived from the VDD3 supply. V DD3 = 2.7 to 3.3 V, VOL = 0.4 V 6. DO and DB outputs are derived from the VDD3 supply. V DD3 = 2.7 to 3.3 V, VOH = V DD3 − 0.4 V 7. Setup and hold times. DATA CLK LE VIH VIH tSU1 VIH tH tSU2 VIH NIPPON PRECISION CIRCUITS—4 SM5165AV FUNCTIONAL DESCRIPTION Operating Frequency Divider (N-counter) Structure The operating frequency divider generates a comparator frequency signal (FV), which is input to the phase comparator, by dividing the VCO signal input on pin FIN. The operating frequency divider is comprised by dual modulus prescalers, a 5-bit swallow counter and a 13-bit main counter. The settings for the dual modulus prescaler (P and P + 1), swallow counter (S) and main counter (M) are related to the comparator frequency divider ratio by: N = (P + 1) × S + P(M – S) = PM + S The counter value ranges are P = 32, P + 1 = 33, S = 0 to 31, and M = 32 to 8191. Therefore, the comparator frequency divider ratio range N is 1056 to 262143. Reference Frequency Divider (R-counter) Structure The reference frequency divider generates a comparator frequency signal (FR), which is input to the phase comparator, by dividing the reference oscillator frequency input either from an external signal on XIN or from a crystal oscillator connected between XIN and XOUT. The settings for the prescaler (A = 8) and reference counter (R) are related to the reference frequency divider ratio by: R = AB = 8B The counter value ranges are A = 8 and B = 5 to 2047. Therefore, the reference frequency divider ratio range is R = 40 to 16376. Input Data The input data should be specified keeping in mind both the VDD2 and VDD3 supplies. The data is input using CLK, DATA and LE pins into the shift register and latch which operate from the VDD2 supply. However, the input voltages can be specified using either the VDD2 or VDD3 supply levels. The control data input uses a 3-line 23-bit serial interface comprising the clock (CLK), data input (DATA) and latch enable (LE). The data is input with the MSB first. The last (23rd) bit is used as the latch select control bit. Data is written to the shift register on the rising edge of the clock signal. Accordingly, the data should change state on the falling edge of the clock signal. Data is transferred from the shift register to the latch when the latch enable (LE) signal goes HIGH. Accordingly, the latch enable signal should be held LOW while data is being written to the shift register. The clock and data input signals are both ignored when the latch enable signal goes HIGH. The reference frequency divider is comprised by a fixed divide-by-8 prescaler and an 11-bit reference counter. Input data format CLK DATA LE 1 MSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 LSB CONTROL NIPPON PRECISION CIRCUITS—5 SM5165AV Latch select The last (23rd) data bit determines the shift register data latch. Bit 23 Latch 0 Reference frequency counter divider ratio data latch select 1 Swallow counter and main counter frequency divider ratio and DO output latch select Swallow counter, main counter frequency divider data and DO output DATA MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2 12 2 11 2 10 29 28 27 26 25 24 23 22 21 20 24 23 22 21 20 19 20 21 22 LSB 23 No Swallow counter meaning (5-bit : 0 to 31) DO output select bits Main counter (13-bit : 32 to 8191) Latch select bit. Setting "1" Bits 19 and 20 have no meaning. These bits should be set to 0. Bits 20 and 21 control the state of the DO output pin. Bit 21 Bit 22 0 0 1 0 0 1 1 1 DO output High impedance Normal operation The DO output polarity can be set by master-slice for either a passive or active filter. Input data example If the VCO output is (fVCO) trebled, the output frequency (fLO) is 251.3 MHz, and the channel bandwidth (fCH: comparator frequency (fR) × 3) is 25 kHz, then the comparator frequency divider ratio N is given by: f LO f VCO × 3 251.3 ⁄ 3 N = ---------- = ----------------------- = -------------------- = 10052 = 32 × 314 + 4 f CH fR × 3 0.025 ⁄ 3 Therefore, the swallow counter count is 4 (00100)2 and the main counter count is 314 (0000100111010)2. Input Data MSB 1 2 12 0 2 2 11 0 3 2 10 0 4 29 0 5 28 1 6 27 0 7 26 0 8 25 1 9 24 1 10 23 1 11 22 0 12 21 1 Main counter (13-bit : 32 to 8191) Latch select bit. Setting "1" 13 20 0 14 24 0 15 23 0 16 22 1 17 21 0 18 20 0 19 20 21 22 LSB 23 0 0 1 1 1 No meaning Swallow counter (5-bit : 0 to 31) DO output select bits NIPPON PRECISION CIRCUITS—6 SM5165AV Reference counter frequency divider setting DATA MSB 1 2 3 4 5 6 7 8 9 No meaning 10 2 10 11 29 12 28 13 27 14 26 15 25 16 24 17 23 18 22 19 21 20 20 Reference counter (11-bit : 5 to 8191) Latch select bit. Set "0" Test bits 21 LSB 23 22 No meaning Bits 1 to 7 and bits 21 and 22 have no meaning. These bits should be set to 0. Bits 8 and 9 are used for testing at the manufacturers and should be set to 1 and 0, respectively, for normal operation. Input data example If the VCO output is (fVCO) trebled, the crystal oscillator frequency is 12.8 MHz and the channel bandwidth (fCH: comparator frequency (fR) × 3) is 25 kHz, then the reference frequency divider ratio R is given by: Xtal Xtal 12.8 NR = ----------- = --------------- = -------------------- = 1536 = 8 × 192 f CH fR × 3 0.025 ⁄ 3 Therefore, the reference counter count is 192 (00011000000)2. Input Data MSB 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 1 0 10 2 10 0 11 29 0 No meaning Test bits 12 28 0 13 27 1 14 26 1 15 25 0 16 24 0 17 23 0 18 22 0 19 21 0 Reference counter (11-bit : 5 to 8191) Latch select bit. Set "0" 20 20 0 21 22 LSB 23 0 0 0 No meaning Boost-up Signal When the PLL starts up with some phase tolerance, a level signal is output on pin DB. When the PLL phase error comes within the tolerance before in lock, output DB goes high impedance. When the PLL starts up, the signal on DB charges the low-pass filter capacitor in anticipation of high- speed locking. After the boost-up signal is output and the PLL phase error comes within tolerance, the boost-up circuit stops and operation continues when the 3 supplies (VDD1, VDD2) are applied and OPR goes HIGH once only. After the boost-up circuit stops, new data is written and the boost-up signal is not output even if the VCO is not in lock. FR FV Phase detector error correction signal ∗ ∗ WINDOWN DB (High impedance) (∗ : 32fFIN ) (HIGH level output) ∗ ∗ (High impedance) NIPPON PRECISION CIRCUITS—7 SM5165AV Operating principles Standby Mode When the PLL is operating with a phase error within fixed tolerance, an internal WINDOWN signal is generated. This signal is in sync with the N counter output signal (FV) and is 62 cycles of the FIN input period in length centered about the falling edge of FV. The SM5165AV enters standby mode when OPR goes LOW. In this mode, the following pin states and functions occur. If the phase detector error correction signal occurs before the WINDOWN LOW-level pulse, the HIGHlevel output from DB continues. However, if the error correction signal occurs wholly within the WINDOWN LOW-level pulsewidth, DB goes high impedance and the boost-up circuit operation stops. The above description applies when the error correction signal is revising up. When the error correction signal is revising down, DB goes LOW. Function State Outputs DO and DB Floating (high impedance) Phase detector Reset Input FIN Feedback resistor is cutoff (internal HIGH level) Input XIN Feedback resistor is cutoff (internal HIGH level) N counter Reset R counter Reset Latch data Stored Note that even in standby mode, some current flows into VDD1 (FIN and XIN prescaler current). It is recommended that VDD1 be grounded in standby mode to reduce current consumption if necessary. Note also that the above pin states and functions are only valid if VDD2 and VDD3 are maintained within normal operating conditions. If VDD2 and/or VDD3 are not within normal operating conditions, the latch data is not retained. Phase Comparator Timing Diagram FR FV DO LD FV and FR are the internal comparator frequency divider output signal and reference frequency divider output signal, respectively. Passive Low-pass Filter R1 DO VCO R2 C NIPPON PRECISION CIRCUITS—8 SM5165AV Input/Output Equivalent Circuits XIN, XOUT DO (for passive filter) VDD2 XOUT Lagging Phase Correction Signal VDD1 VDD1 From Internal Circuit DO Leading Phase Correction Signal To Internal Counter XIN DB Intenal Circuit VDD1 VDD2 From Internal Circuit From Internal Circui Transistor Resistor DB From Internal Circui RO FIN VDD1 VDD2 From Internal Circuit VDD1 From Internal Circuit To Internal Counter FIN1 RO (FV, FR) (for TEST mode) Diffused Resistor OPR, CLK, DATA, LE TEST VDD1 VDD2 OPR CLK DATA LE To Intenal Circuit VDD1 To Intenal Circuit TEST Transistor Resistor NIPPON PRECISION CIRCUITS—9 SM5165AV NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9609BE 1997.08 NIPPON PRECISION CIRCUITS—10