SM5302A 3-channel Video Buffer with Built-in wideband LPF OVERVIEW The SM5302A is a 3-channel video buffer with built-in 5th-order lowpass filters. The lowpass filter cutoff frequency range can be linearly controlled from 4.8MHz to 43MHz*1. The lowpass filter supports 480i to 1080i format, video signal equipment analog input/outputs. For video input systems, the device functions as a nextstage ADC system anti-aliasing filter. For video output systems, the filter removes video DAC aliasing and external noise and can drive a maximum of two 75Ω terminated loads. The cutoff frequency, signal input type, and output gain switching can be controlled using an I2C*2 control bus, and the I2C slave address can be set by ADS (3-state input) to allow a maximum of three devices to be used simultaneously. *1. When the resistor connected to ISET (RISET) is 1.8kΩ. *2. I2C BUS is a registered trademark of Philips Electronics N.V. PINOUT ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ (Top view) REF1 1 28 REF2 VDD 2 27 REF3 SDA 3 26 VCC1 SCL 4 25 OUT1A VSS 5 24 OUT1B MUXSEL 6 23 GND1 ADS 7 22 VCC2 IN1A 8 21 OUT2A IN1B 9 20 OUT2B ISET 10 19 GND2 IN2A 11 18 VCC3 IN2B 12 17 OUT3A IN3A 13 16 OUT3B IN3B 14 15 GND3 PACKAGE DIMENSIONS (Unit: mm) + 0.1 0.15 − 0. 05 ■ ■ HDTVs LCD TVs PDPs Projectors 2.2 ± 0.1 ■ ■ 7.5 ± 0.2 APPLICATIONS 0.5 ± 0.2 ■ Supply voltages • Analog: 4.75 to 5.25V • Digital: 3.0 to 5.5V Lowpass filter with linearly adjustable cutoff frequency (256 values) • Cutoff frequency range: 4.8MHz to 43MHz (RISET = 1.8kΩ) Filter bypass mode function for display specifications up to SXGA resolution • Passband: 80MHz (typ) Half fc mode switch function (CH-2, CH-3) suitable for digital component signals 2-system input multiplexer function (switchable using I2C or MUXSEL input) Video input pins can be independently set to synctip clamp/bias/direct inputs Maximum two 75Ω terminated load drive capability Output gain switching: 0dB/6dB Disable function • ≤ 300µA current consumption when disabled Output sag compensation circuit built-in I2C interface control • Slave address: 90h, 92h, or 94h (up to three devices can be used simultaneously, selected by ADS input) • Data transfer rate: Fast mode (up to 400kbit/s) Operating ambient temperature range: 0 to 70°C Package: 28-pin HSOP 1.3TYP 18.6 ± 0.3 ORDERING INFORMATION Device Package SM5302AS 28-pin HSOP 0.8 5.15 0.10 0.35 ± 0.05 0.12 M 0 to 10 ° 0.1 ± 0.05 ■ 9.9 ± 0.3 FEATURES NIPPON PRECISION CIRCUITS INC.—1 SM5302A BLOCK DIAGRAM VDD VSS ISET ADS MUXSEL REF1 SDA Vref Current Source I 2C Control SCL REF3 Bypass 0dB/6dB IN1A Clamp/Bias/Direct MUX IN1B Clamp/Bias/Direct 5th Order LPF (Standard fc) OUT1A OUT1B GND1 Bypass 0dB/6dB Clamp/Bias/Direct MUX IN2B Clamp/Bias/Direct 5th Order LPF (Standard /Half fc) OUT2A OUT2B GND2 Bypass 0dB/6dB Clamp/Bias/Direct IN3B Clamp/Bias/Direct VCC2 Filter CH-2 IN3A VCC1 Filter CH-1 IN2A REF2 MUX 5th Order LPF (Standard /Half fc) VCC3 OUT3A Filter OUT3B CH-3 GND3 Note. The recommended value of the external resistor connected to ISET is 1.8kΩ. NIPPON PRECISION CIRCUITS INC.—2 SM5302A PIN DESCRIPTION Number Name I/O*1 A/D*2 1 REF1 O A Internal reference voltage 1 2 VDD − D Digital supply (3.0 to 5.5V) 3 SDA I/O D I2C data signal input/output 4 SCL I D I2C clock signal input 5 VSS − D Digital ground 6 MUXSEL I D Input multiplexer switch control 7 ADS I D I2C slave address select (3-state input) 8 IN1A I A Video signal input (CH-1, input A) 9 IN1B I A Video signal input (CH-1, input B) 10 ISET − A Internal current-setting resistor (RISET) connection (standard 1.8kΩ) 11 IN2A I A Video signal input (CH-2, input A) 12 IN2B I A Video signal input (CH-2, input B) 13 IN3A I A Video signal input (CH-3, input A) 14 IN3B I A Video signal input (CH-3, input B) 15 GND3 − A Analog ground (CH-3) 16 OUT3B O A Video signal output (CH-3, for sag compensation) 17 OUT3A O A Video signal output (CH-3) 18 VCC3 − A Analog supply (CH-3) (4.75 to 5.25V) 19 GND2 − A Analog ground (CH-2) 20 OUT2B O A Video signal output (CH-2, for sag compensation) 21 OUT2A O A Video signal output (CH-2) 22 VCC2 − A Analog supply (CH-2) (4.75 to 5.25V) 23 GND1 − A Analog ground (CH-1, Vref) 24 OUT1B O A Video signal output (CH-1, for sag compensation) 25 OUT1A O A Video signal output (CH-1) 26 VCC1 − A Analog supply (CH-1, Vref) (4.75 to 5.25V) 27 REF3 O A Internal reference voltage 3 28 REF2 O A Internal reference voltage 2 Description *1. I: input, O: output *2. A: analog, D: digital NIPPON PRECISION CIRCUITS INC.—3 SM5302A PIN EQUIVALENT CIRCUITS Number Name I/O Equivalent circuit VCCn 8 9 11 12 13 14 IN1A IN1B IN2A IN2B IN3A IN3B I INnA INnB GNDn VCCn OUTnA 25 26 21 20 17 16 OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B O GNDn 750Ω VCCn OUTnB GNDn VCC1 1 REF1 O REF1 GND1 NIPPON PRECISION CIRCUITS INC.—4 SM5302A Number Name I/O Equivalent circuit VCC1 REF2 28 27 REF2 REF3 O GND1 VCC1 REF3 GND1 VDD 3 SDA 250Ω I/O SDA VSS VDD 4 6 SCL MUXSEL I 180Ω SCL MUXSEL VSS VDD 7 ADS I 250Ω ADS VSS Note. Resistance values indicate design values. NIPPON PRECISION CIRCUITS INC.—5 SM5302A SPECIFICATIONS Absolute Maximum Ratings VSS = GND1 = GND2 = GND3 = 0V, VCC1 = VCC2 = VCC3 = VDD = VCC Parameter Symbol Condition Rating Unit Supply voltage VCC VCC1, VCC2, VCC3, VDD − 0.3 to 7.0 V Input voltage VIN MUXSEL, ADS, SDA, SCL, INnA, INnB (n = 1, 2, 3) GND – 0.3 to VCC + 0.3 V − 55 to + 125 °C 1.0 W 125 °C Rating Unit 4.75 to 5.25 V ± 0.1 V 3.0 to 5.5 V 0 to 70 °C Storage temperature range TSTG Power dissipation PD Junction temperature TJ θja = 60°C/W Note. θja is the measured quantity under the mounted condition which NPC specified. Recommended Operating Conditions Parameter Supply voltage 1 Symbol Condition VCC VCC1, VCC2, VCC3 Supply voltage difference ∆VCC VCC1 − VCC2, VCC1 − VCC3, VCC2 − VCC3 Supply voltage 2 VDD VDD Operating ambient temperature Ta Note. VCC1 to VCC3 should be applied simultaneously. Electrical Characteristics DC Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75Ω, CH-1 set to clamp input, CH-2 and CH-3 set to bias input, FCDATA = 227, unless otherwise noted. Rating Parameter Symbol Condition min typ max Unit Test level Current consumption 1*1 ICC1 Filter mode, FCDATA = 255 − 130 155 mA I Current consumption 2*1 ICC2 Filter bypass mode − 85 110 mA I Current consumption 3*1 ICC3 Power-down mode, 3-address mode − − 300 µA I Current consumption 4*1 ICC4 Power-down mode , 2-address mode − − 250 µA I HIGH-level input voltage VIH1 SDA, SCL, MUXSEL, Ta = 0 to 70°C 0.7 VDD − − V I LOW-level Input voltage VIL1 SDA, SCL, MUXSEL, Ta = 0 to 70°C − − 0.3 VDD V I ADS HIGH-level input voltage VIH2 ADS, Ta = 0 to 70°C 0.8 VDD − − V I ADS LOW-level input voltage VIL2 ADS, Ta = 0 to 70°C − − 0.2 VDD V I ADS open-circuit input voltage VOPEN ADS, Ta = 0 to 70°C VDD/2 − 0.2 − VDD/2 + 0.2 V I LOW-level input leakage current ILL SDA, SCL, MUXSEL, VIN = 0V − − 1.0 µA I HIGH-level input leakage current ILH SDA, SCL, MUXSEL, VIN = VDD − − 1.0 µA I SDA output voltage VOL Sink current = 3mA SDA = LOW output 0 − 0.4 V I *1. Sum of VCC1 + VCC2 + VCC3 + VDD. No input signals. NIPPON PRECISION CIRCUITS INC.—6 SM5302A AC Characteristics (I2C) VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, unless otherwise noted. Rating Unit Test level 400 kHz II − − µs II 1.3 − − µs II tHIGH 0.6 − − µs II tSU;STA 0.6 − − µs II SDA data hold time tHD;DAT 0.15*1 − 0.9 µs II SDA data setup time tSU;DAT 100 − − ns II SDA, SCL rise time tr − − 300 ns II SDA, SCL fall time tf − − 300 ns II tSU;STO 0.6 − − µs II Ci − − 10 pF II Parameter Symbol Condition min typ max fSCL 0 − tHD;STA 0.6 SCL clock LOW-level pulsewidth tLOW SCL clock HIGH-level pulsewidth SCL setup time (start condition) SCL clock frequency SCL hold time (start condition) SCL setup time (stop condition) SDA, SCL input capacitance *1. This value is not conforming to the I2C BUS specification established by Philips Corporation. SDA tf tLOW tr tr tSU;DAT tf tBUF tHD;STA SCL tHD;DAT tHD;STA S tHIGH tSU;STA Sr tSU;STO P NIPPON PRECISION CIRCUITS INC.—7 SM5302A Analog Characteristics Analog input characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75Ω, CH-1 set to clamp input, CH-2 and CH-3 set to bias input, FCDATA = 227, unless otherwise noted. Internal mode settings are shown in table 1 in "Mode Condition Settings". Rating Parameter Symbol Condition min typ max Unit Test level Clamp voltage VCLMP Clamp input 1.8 2.0 2.2 V I Bias voltage VBIAS Bias input 2.2 2.4 2.6 V I Input resistance RBIAS Bias input − 20 − kΩ II VAI1 Mode: b0 (bias, 0dB), THD < 1.0% 1.4 − − Vp-p I VAI2 Mode: b6 (bias, 6dB), THD < 1.0% 1.4 − − Vp-p I VAI3 Mode: c0 (clamp, 0dB), THD < 1.0% 1.4 − − Vp-p I VAI4 Mode: c6 (clamp, 6dB), THD < 1.5% 1.0 − − Vp-p I VAI5 Mode: f0 (bias, 0dB), THD < 1.0% 1.4 − − Vp-p I VAI6 Mode: f6 (bias, 6dB), THD < 1.5% 1.2 − − Vp-p I VAI7 Mode: g0 (clamp, 0dB), THD < 1.0% 1.4 − − Vp-p I VAI8 Mode: g6 (clamp, 6dB), THD < 1.5% 1.0 − − Vp-p I VIDC1 Mode: h0 , THD < 1.5%, VIN < 1.4Vp-p 1.5 − 3.5 V I VIDC2 Mode: h6, THD < 1.5%, VIN < 1.2Vp-p 1.7 − 3.0 V I VIDC3 Mode: j0 , THD < 1.5%, VIN < 1.4Vp-p 1.1 − 3.3 V I VIDC4 Mode: j6, THD < 1.5%, VIN < 1.2Vp-p 1.4 − 2.9 V I Filter mode maximum input voltage Bias mode maximum input voltage Direct mode input DC voltage range NIPPON PRECISION CIRCUITS INC.—8 SM5302A Filter mode and bypass mode frequency characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75Ω, CH-1 set to clamp input, CH-2 and CH-3 set to bias input, FCDATA = 227, unless otherwise noted. Rating Parameter Cutoff frequency Symbol Condition min typ max Unit Test level FC1 FCDATA = 0 − 4.74 − MHz II FC2 FCDATA = 10 5.98 6.79 7.60 MHz I FC3 FCDATA = 227 32.5 36.89 41.3 MHz I FC4 FCDATA = 255 − 43.73 − MHz II Half fc mode cutoff frequency ratio Rhalf1 Half fc mode, FCDATA = 10 44 49 54 % I Rhalf2 Half fc mode, FCDATA = 227 49 54 59 % I 4fc attenuation GSB fin ≥ 4fc, attenuation from fin = 100kHz − 50 − dB II Filter bypass mode passband FBP VIN = 0.7Vp-p, Gain = − 1dB 68 80 − MHz I Analog output characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75Ω, CH-1 set to clamp input, CH-2 and CH-3 set to bias input, FCDATA = 227, unless otherwise noted. Internal mode settings are shown in table 1 in "Mode Condition Settings". Rating Parameter Symbol Condition min typ max Unit Test level AVF1 Gain = 0dB − 0.5 0 0.5 dB I AVF2 Gain = 6dB 5.5 6.0 6.5 dB I AVB1 Gain = 0dB − 0.5 0 0.5 dB I AVB2 Gain = 6dB 5.5 6.0 6.5 dB I Filter bypass mode gain error dAVBP Gain error between filter mode and bypass mode − ± 0.2 − dB I Channel to channel gain error dAVCH − − ± 0.2 dB I Filter mode output gain Filter bypass mode output gain Vout1 Mode: b0, c0 (0dB), THD < 1.0% 1.4 − − Vp-p I Vout2 Mode: b6, c6 (6dB), THD < 1.5% 2.4 − − Vp-p I THDB1 Mode: b0, fin = 1kHz, VIN = 1.4Vp-p − 0.2 1.0 % I THDB2 Mode: b6, fin = 1kHz, VIN = 1.2Vp-p − 0.2 1.0 % I THDC1 Mode: c0, fin = 1kHz, VIN = 1.4Vp-p − 0.2 1.0 % I THDC2 Mode: c6, fin = 1kHz, VIN = 1.0Vp-p − 0.5 1.5 % I Channel to channel crosstalk XTLK1 0.5Vp-p input, fin = 1MHz, between 2 channels − − 71 − dB II MUX input to input crosstalk XTLK2 0.5Vp-p input, fin = 1MHz, between INnA-INnB, 6dB − − 50 − dB II Maximum output voltage Output distortion Drive load resistance RL 1 load = 150Ω − − 2 load I I2C response time TIC Response time from ACK bit output when changing I2C settings − − 1 µs II MUXSEL switch response time TMS Response time at L → H, H → L − − 1 µs II NIPPON PRECISION CIRCUITS INC.—9 SM5302A Reference Voltage Characteristics (REF) VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, unless otherwise noted. Rating Parameter Symbol REF output voltage Condition min typ max Unit Test level VR1 REF1 − 2.45 − V II VR2 REF2 − 2.65 − V II VR3 REF3 − 1.90 − V II Test level I : 100% of products tested at Ta = + 25°C. II : Guaranteed as result of design and characteristics evaluation. Mode Condition Settings Table 1. Mode settings Input type Mode setting Output gain CH-1 CH-2 CH-3 Clamp Bias Bias a0 fc mode Filter/Bypass mode 0dB a6 6dB b0 0dB Bias b6 Standard 6dB c0 0dB Clamp c6 Filter 6dB d0 0dB Bias d6 6dB e0 0dB Half Clamp e6 6dB f0 0dB Bias f6 6dB g0 0dB − Bypass Clamp g6 6dB h0 0dB h6 6dB i0 0dB Standard Filter Direct Half i6 6dB j0 0dB j6 6dB − Bypass NIPPON PRECISION CIRCUITS INC.—10 SM5302A Evaluation Circuit Diagram I 2C Controller REF1 REF2 VDD REF3 SDA VCC1 SCL OUT1A VSS OUT1B MUXSEL GND1 ADS VCC2 + 10µ + 10µ + + + 10µ 100µ 0.1µ 100µ 75Ω + 75Ω 4.7µ + 4.7µ 100µ + 4.7µ + Input 4.7µ + 4.7µ + 75Ω + IN1A OUT2A IN1B OUT2B ISET GND2 IN2A VCC3 IN2B OUT3A IN3A OUT3B IN3B GND3 4.7µ Output 75Ω 100µ 75Ω + 75Ω + RISET = 1.8kΩ Note. This is the electrical characteristics evaluation circuit only, then it is not a recommended application circuit. NIPPON PRECISION CIRCUITS INC.—11 SM5302A FUNCTIONAL DESCRIPTION I2C BUS Control The SM5302A uses an I2C BUS interface to set the following functions. 1) 2) 3) 4) 5) 6) 7) 8) Cutoff frequency Output gain fc mode switching (1/2 cutoff frequency switching) Filter mode/filter bypass mode switching Input multiplexer selection Input type switching (sync-tip clamp, bias, direct) Disable function Maximum number of slave addresses It supports fast-mode data transfer rate (up to 400kbit/s). Note that the SM5302A does not have a read function (IC is write only). Basic cycle SDA SCL Start condition Stop condition I2C start/stop condition The basic access cycle comprises the following elements. 1) 2) 3) 4) 5) Start condition 1st byte: Slave address 2nd byte: Subaddress 3rd byte: Control data Stop condition If the input data does not match the slave address or the subaddress is incorrect, the corresponding ACK (acknowledge) bit is not output LOW. However, the ACK bit is output after 3rd byte irrespective of the byte data. Also note that the IC does not have a subaddress auto-increment function, hence each subaddress access requires all the basic cycle steps 1 to 5. Start SDA 1st byte:Slave address D7 D6 D1 2nd byte:Subaddress D0 3rd byte:Control data Stop ACK D7 D6 D1 D0 ACK D7 D6 D1 D0 ACK 9 1 2 7 8 9 1 2 7 8 9 Low SCL 1 2 7 8 NIPPON PRECISION CIRCUITS INC.—12 SM5302A 1st byte: slave address The ADS pin can set one of three slave addresses. Note that D0 must be “0 (Write)”. 1st byte: slave address ADS *1. HEX D7 D6 D5 D4 D3 D2 D1 D0 L 90h 1 0 0 1 0 0 0 0 (W) H 92h 1 0 0 1 0 0 1 0 (W) Open*1 94h 1 0 0 1 0 1 0 0 (W) When ADS is open (94h), I2C control may not be able to set the address. See “P16. (8) Maximum number of slave addresses.” 2nd byte: subaddress The 2nd byte sets the subaddress, selecting one of three registers. 2nd byte: subaddress Register name HEX D7 D6 D5 D4 D3 D2 D1 D0 FCSET 01h 0 0 0 0 0 0 0 1 CONDITION1 02h 0 0 0 0 0 0 1 0 CONDITION2 03h 0 0 0 0 0 0 1 1 3rd byte: control data The 3rd byte control data sets the register flags corresponding to the subaddress selected by 2nd byte. The flags assigned are shown in the following table. 3rd byte: control data Register name D7 D6 D5 D4 D3 D2 D1 D0 FCSET FCM FC6 FC5 FC4 FC3 FC2 FC1 FC0 CONDITION1 CB5 CB4 CB3 CB2 CB1 CB0 − GS CONDITION2 PD MUX HALF BYPASS − NCA − − NIPPON PRECISION CIRCUITS INC.—13 SM5302A Flag settings (1) Cutoff frequency Register name: FCSET Flag names: FCM, FC [6:0] The FCSET register setting sets the cutoff frequency using one of two tuning adjustment functions, thus a total of 256 values are possible. The cutoff frequency is determined by the following equations. The values are shown in “Lowpass Filter”. • FCDATA = 0 to 127 : fc = k11 × FCDATA2 + k12 × FCDATA + k13 [MHz] • FCDATA = 128 to 255: fc = k21 × FCDATA2 + k22 × FCDATA + k23 [MHz] The coefficients when RISET = 1.8kΩ are: • k11 = − 1.95e − 4, k12 = 2.07e − 1, k13 = 4.74 • k21 = − 3.92e − 4, k22 = 4.33e − 1, k23 = − 41.2 Flag name FCDATA FCM FC6 FC5 FC4 FC3 FC2 FC1 FC0 Cutoff frequency [MHz] FCSET 0 00h 0 0 0 0 0 0 0 0 4.74 1 01h 0 0 0 0 0 0 0 1 4.95 2 02h 0 0 0 0 0 0 1 0 5.15 Default : 125 7Dh 0 1 1 1 1 1 0 1 27.57 126 7Eh 0 1 1 1 1 1 1 0 27.73 127 7Fh 0 1 1 1 1 1 1 1 27.88 128 80h 1 0 0 0 0 0 0 0 7.80 129 81h 1 0 0 0 0 0 0 1 8.13 130 82h 1 0 0 0 0 0 1 0 8.47 : 253 FDh 1 1 1 1 1 1 0 1 43.26 254 FEh 1 1 1 1 1 1 1 0 43.49 255 FFh 1 1 1 1 1 1 1 1 43.73 (2) Input type switching (sync-tip clamp, bias, direct) Register name: CONDITION1 Flag names: CB [5:4], CB [3:2], CB [1:0] These flags set the input type of CH-1, CH-2, and CH-3 to one of three types: sync-tip clamp input, bias input, or direct input. Channel CH-1 CH-2 CH-3 Flag name CB5 CB3 CB1 CB4 CB2 CB0 Input type L L Sync-tip clamp input L H Bias input H Don't care Direct input*1 Default *1. An input coupling capacitor should not be connected when direct input is selected. NIPPON PRECISION CIRCUITS INC.—14 SM5302A (3) Output gain Register name: CONDITION1 Flag name: GS Flag name Output gain Default GS L 0dB H 6dB (4) Disable mode select Register name: CONDITION2 Flag name: PD This flag enables/disables the analog block. When the analog block is disabled, the output pins are high impedance. Flag name Mode Default PD L Enable (normal operation) H Disable (no operation) (5) Input multiplexer selection Register name: CONDITION2 Flag name: MUX This flag selects the A or B input for all three channels (IN1×, IN2×, IN3×). Note that this flag is significant only when the MUXSEL input is LOW. See “Input Multiplexer Switching (MUXSEL)”. Flag name Input selection*1 Default MUX L INnA H INnB *1. n = 1, 2, 3 (6) fc mode switching (1/2 cutoff frequency switching) Register name: CONDITION2 Flag name: HALF This flag switches the cutoff frequency of CH-2 and CH-3 to divide the value set by the FCSET register into halves. Note that the CH-1 cutoff frequency cannot be switched. This mode is suitable for systems where the sampling frequency varies due to Y, Cr, and Cb requirements, such as digital component signals or digital HDTV signals. Flag name fc mode Default HALF L Standard fc mode (CH-1, CH-2, CH-3 cutoff frequency is identical) H Half fc mode (CH-2, CH-3 cutoff frequency is 1/2 that of CH-1) NIPPON PRECISION CIRCUITS INC.—15 SM5302A (7) Filter bypass mode Register name: CONDITION2 Flag name: BYPASS This flag allows the lowpass filter to be bypassed. The output gain can be switched, even in filter bypass mode. The input type, multiplexer function, and output gain can all be set just as in filter mode. However, the cutoff frequency and fc mode settings have no effect on the outputs. Flag name Filter BYPASS Default L Filter mode (signals pass through lowpass filter) H Filter bypass mode (signals bypass lowpass filter) (8) Maximum number of slave addresses Register name: CONDITION2 Flag name: NCA The NCA flag sets the maximum number of slave addresses to either 2 or 3. The NCA setting modifies the ADS input pin equivalent circuit as shown below. When NCA = LOW (max = 2), switches SW31 to SW33 are OFF, reducing the current consumed in comparison to when NCA = HIGH (max = 3). Note that only 2 ADS input levels (LOW or HIGH) are valid. When NCA = HIGH (max = 3), switches SW31 to SW33 are ON and hence current is consumed regardless of whether the ADS input is LOW, HIGH, or Open. However, note that 3 ADS input levels are valid. Note. The default value for NCA is HIGH (max = 3). If NCA is once set to LOW (max = 2) for a device addressed by the setting when ADS is Open, that device is subsequently no longer accessible. Flag name NCA Maximum number of slave address Default ADS level Slave address ADS pin current flow L 2 (2-address mode) LOW HIGH Open 1001000 1001001 Invalid No H 3 (3-address mode) LOW HIGH Open 1001000 1001001 1001010 Yes NCA=2 SW21 I 2C Control NCA=L(2) Address decoder NCA=3 ADS NCA=H(3) SW31 SW32 SW33 NIPPON PRECISION CIRCUITS INC.—16 SM5302A Lowpass Filter The IC has built-in 5th-order lowpass filters with variable cutoff frequency. The frequency range is determined by the resistor (RISET) connected between ISET and GND, and the cutoff frequency is set by register FCDATA data. The cutoff frequency vs. FCDATA values are listed in table 2, and shown graphically in figure 1. Table 2. Cutoff frequency vs. FCDATA (RISET = 1.8kΩ) FCDATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 FCSET (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Cutoff freq. [MHz] 4.74 4.95 5.15 5.36 5.56 5.77 5.97 6.18 6.38 6.59 6.79 6.99 7.20 7.40 7.60 7.80 8.00 8.20 8.40 8.60 8.80 9.00 9.20 9.40 9.60 9.79 9.99 10.19 10.38 10.58 10.77 10.97 11.16 11.36 11.55 11.75 11.94 12.13 12.32 12.52 12.71 12.90 13.09 13.28 13.47 13.66 13.85 14.04 14.23 14.41 14.60 14.79 14.98 15.16 15.35 15.54 15.72 15.91 16.09 16.27 16.46 16.64 16.82 17.01 FCDATA 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 FCSET (hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Cutoff freq. [MHz] 17.19 17.37 17.55 17.73 17.91 18.09 18.27 18.45 18.63 18.81 18.99 19.17 19.35 19.52 19.70 19.88 20.05 20.23 20.40 20.58 20.75 20.93 21.10 21.27 21.45 21.62 21.79 21.96 22.13 22.30 22.47 22.65 22.81 22.98 23.15 23.32 23.49 23.66 23.83 23.99 24.16 24.33 24.49 24.66 24.82 24.99 25.15 25.31 25.48 25.64 25.80 25.97 26.13 26.29 26.45 26.61 26.77 26.93 27.09 27.25 27.41 27.57 27.73 27.88 FCDATA 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 FCSET (hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Cutoff freq. [MHz] 7.80 8.13 8.47 8.80 9.13 9.45 9.78 10.11 10.44 10.76 11.09 11.41 11.74 12.06 12.38 12.70 13.02 13.34 13.66 13.98 14.30 14.61 14.93 15.25 15.56 15.87 16.19 16.50 16.81 17.12 17.43 17.74 18.04 18.35 18.66 18.96 19.27 19.57 19.88 20.18 20.48 20.78 21.08 21.38 21.68 21.98 22.27 22.57 22.87 23.16 23.45 23.75 24.04 24.33 24.62 24.91 25.20 25.49 25.78 26.06 26.35 26.63 26.92 27.20 FCDATA 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 FCSET (hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Cutoff freq. [MHz] 27.49 27.77 28.05 28.33 28.61 28.89 29.17 29.44 29.72 30.00 30.27 30.55 30.82 31.09 31.36 31.63 31.90 32.17 32.44 32.71 32.98 33.24 33.51 33.77 34.04 34.30 34.56 34.83 35.09 35.35 35.61 35.87 36.12 36.38 36.64 36.89 37.15 37.40 37.65 37.91 38.16 38.41 38.66 38.91 39.16 39.40 39.65 39.90 40.14 40.39 40.63 40.87 41.11 41.36 41.60 41.84 42.07 42.31 42.55 42.79 43.02 43.26 43.49 43.73 NIPPON PRECISION CIRCUITS INC.—17 fc [MHz] SM5302A 50 45 40 35 30 25 20 15 10 5 0 0 32 64 96 128 160 192 224 256 FCDATA Figure 1. Cutoff frequency vs. FCDATA (RISET = 1.8kΩ) RISET RISET controls the internal current source, and its connection is essential. The recommended value is 1.8kΩ. In disable mode and filter bypass mode, the ISET pin is high impedance, and no current flows into RISET. Note. A value other than 1.8kΩ will change the current consumption, so caution should be taken to ensure the power dissipation does not exceed the absolute maximum rating for the package. Half fc Mode In half fc mode, the CH-2 and CH-3 cutoff frequency is 1/2 that of the CH-1 cutoff frequency setting. Half fc mode is useful for systems where the sampling frequency varies due to luminance (Y) and color difference signal (Cr, Cb) requirements as in digital component signals. Note in figure 2 that the cutoff frequency ratio for a given cutoff frequency setting (FCDATA) is not constant. Group Delay Characteristics 60% 58% HALF = High RISET = 1.8kΩ 56% 54% 52% 50% 48% 46% 44% 42% 40% 0 32 64 100 90 80 70 60 50 40 30 20 10 0 FCDATA = 10 Group delay [ns] Ratio * The group delay varies with the cutoff frequency setting, as shown in figure 3. Note also that in half fc mode, the group delay between CH-1 and CH-2/CH-3 varies. 96 128 160 192 224 256 FCDATA Figure 2. Cutoff frequency ratio (half fc mode) FCDATA = 227 0 10 20 30 40 50 Frequency [MHz] 60 Figure 3. Group delay characteristics * Ratio of CH-2 and CH-3 cutoff frequency at half fc mode based on CH-1 cutoff frequency. NIPPON PRECISION CIRCUITS INC.—18 SM5302A Filter Bypass Mode In filter bypass mode, the lowpass filter is bypassed and the signal is input to the output buffer stage. The input type, multiplexer function, and output gain are set just as for filter mode. The cutoff frequency setting and fc mode setting have no effect on the outputs. In this mode, the passband frequency is 80MHz (typ), which can support SXGA-class signals. Input Multiplexer Switching (MUXSEL) The input multiplexer setting can also be set using the MUXSEL input. When set using the I2C BUS, a certain amount of communication time is required, but the setting can be made using the MUXSEL input with arbitrary timing for high-speed switching. MUXSEL pin MUX flag Multiplexer selection*1 L L INnA L H INnB H L INnB H H INnB *1. n = 1, 2, 3 Power-ON Reset When power is applied, an internal power-ON reset circuit operates initializing the internal register flags to their default settings. At power-ON, all supplies should be applied simultaneously. Sag Compensation Circuit A sag compensation circuit is built-in between the OUTnA and OUTnB pins. In circuits where the load resistance is small and the capacitance required is large, using the sag compensation circuit allows the total capacitance and mounting area to be reduced. If the sag compensation circuit is not used, output OUTnA should be connected to OUTnB. The electrical characteristics are not guaranteed if OUTnB is left open circuit. OUTnA OUTnA OUTnB OUTnB Figure 4. Connection without sag compensation circuit Figure 5. Connection with sag compensation circuit Reference Voltage (REF) The REFn pins (n = 1, 2, 3) are internal reference voltage outputs. A 10 µF capacitor connected to ground is recommended for stability. REF1, REF2, and REF3 are independent reference voltage outputs, and have no correspondence with channels CH-1, CH-2, and CH-3. In disable mode, they are high impedance outputs. NIPPON PRECISION CIRCUITS INC.—19 SM5302A USAGE PRECAUTIONS Slave Address (94h) Setting When slave address 94h is used, the ADS input must be left open circuit. In this case, an external resistor should be connected as shown in figure 6 to reduce the risk of malfunction due to large external spikes or other noise. The recommended value is 10kΩ. Oscillation Prevention Capacitor Connection If the sag compensation circuit is used with 2 output capacitors connected, the capacitors should be mounted within approximately 8cm of the IC pins. If the distance exceeds 8cm, they may cause an oscillation. A 15pF oscillation prevention capacitor should be connected between OUTnA and OUTnB. If the sag compensation circuit is not used, OUTnA is connected to OUTnB. As there is only 1 output capacitor, an oscillation prevention capacitor is not required. Unused Analog Inputs It is recommended that unused analog inputs should be connected to ground through a capacitor as shown in figure 8. Direct Input Mode In direct input mode, the signal is connected to the input without an input capacitor. However, the input DC voltage range varies with the mode setting, hence the signal must be appropriately biased for the corresponding mode. The recommended LOW-level voltage (VL) and HIGH-level voltage (VH) for each mode is shown in table 3 (see figure 9, VCC = 5V). If the input voltage exceeds these limits, harmonic distortion may occur in the output signal. Note that even if these limits are exceeded, device breakdown will not occur if still within the absolute maximum ratings. > 8cm VDD OUTnA 10k ADS 15p 10k OUTnB VSS Slave address = 94h Figure 6. Slave address 94h setting Figure 7. Oscillation prevention capacitor connection VCC INnA (Used input) Video Signal In VH Video Signal In INnB (Unused input) INnA INnB VL GND Figure 8. Unused analog inputs Figure 9. Direct input mode NIPPON PRECISION CIRCUITS INC.—20 SM5302A Table 3. Direct mode recommended input DC voltage range (VCC = 5V) Mode setting Gain fc mode Filter/Bypass mode Sag compensation circuit*1 Channel VL [V] VH [V] 1.5 3.5 1.3 3.7 CH-1 1.5 3.5 CH-2, CH-3 1.6 3.6 CH-1 1.3 3.7 CH-2, CH-3 1.5 3.7 1.0 3.3 1.1 3.6 1.7 3.0 1.6 3.1 CH-1 1.7 3.0 CH-2, CH-3 1.8 2.95 CH-1 1.6 3.1 CH-2, CH-3 1.7 3.0 1.4 2.9 1.4 2.9 CH-1 Used CH-2, CH-3 h0 Standard CH-1 Not used CH-2, CH-3 Filter Used i0 0dB Half Not used CH-1 Used − j0 CH-2, CH-3 Bypass CH-1 Not used CH-2, CH-3 CH-1 Used CH-2, CH-3 h6 Standard CH-1 Not used CH-2, CH-3 Filter Used i6 6dB Half Not used CH-1 Used j6 − CH-2, CH-3 Bypass CH-1 Not used CH-2, CH-3 *1. Refer to figure 4 or 5 in “Sag Compensation Circuit”. NIPPON PRECISION CIRCUITS INC.—21 SM5302A TYPICAL CHARACTERISTICS Phase [deg] Gain [dB] 270 180 90 0 -90 -180 -270 -360 -450 -540 -630 100 Group delay Figure 14. Gain and Phase Characteristics (6dB, half fc mode, FCDATA = 10) 20 40 60 80 Frequency [MHz] Group delay [ns] Gain [dB] 200 180 160 140 120 100 80 60 40 20 0 100 12 6 0 -6 -12 -18 -24 -30 -36 -42 -48 200 180 160 140 120 100 80 60 40 20 0 Gain Group delay 10 20 30 Frequency [MHz] Group delay [ns] Figure 11. Gain and Group delay characteristics (6dB, filter bypass mode) 0 Figure 12. Gain and Phase characteristics (6dB, standard fc mode, FCDATA = 10) 12 Gain 6 0 Phase -6 -12 -18 -24 -30 -36 -42 -48 0.1 1 10 Frequency [MHz] Gain 40 Figure 13. Gain and Group delay characteristics (6dB, standard fc mode, FCDATA = 10) 12 6 0 -6 -12 -18 -24 -30 -36 -42 -48 200 180 160 140 120 100 80 60 40 20 0 Gain Group delay 0 10 20 30 Frequency [MHz] Group delay [ns] 270 180 90 0 -90 -180 -270 -360 -450 -540 -630 100 Phase [deg] Gain [dB] Figure 10. Gain and Phase characteristics (6dB, filter bypass mode) 12 Gain 6 0 Phase -6 -12 -18 -24 -30 -36 -42 -48 0.1 1 10 Frequency [MHz] 12 6 0 -6 -12 -18 -24 -30 -36 -42 -48 0 Gain [dB] 270 180 90 0 -90 -180 -270 -360 -450 -540 -630 100 Gain [dB] 12 Gain 6 0 Phase -6 -12 -18 -24 -30 -36 -42 -48 0.1 1 10 Frequency [MHz] Phase [deg] Gain [dB] VCC = 5.0V, VDD = 5.0V, Ta = 25°C, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75Ω, unless otherwise noted. 40 Figure 15. Gain and Group delay characteristics (6dB, half fc mode, FCDATA = 10) NIPPON PRECISION CIRCUITS INC.—22 270 180 90 0 -90 -180 -270 -360 -450 -540 -630 100 Figure 18. Gain and Phase characteristics (6dB, half fc mode, FCDATA = 227) 200 180 160 140 120 100 80 60 40 20 0 100 Group delay [ns] 12 Gain 6 0 -6 -12 -18 -24 -30 -36 Group delay -42 -48 0 20 40 60 80 Frequency [MHz] Figure 17. Gain and Group delay characteristics (6dB, standard fc mode, FCDATA = 227) 12 Gain 6 0 -6 -12 -18 -24 -30 Group delay -36 -42 -48 0 20 40 60 80 Frequency [MHz] 200 180 160 140 120 100 80 60 40 20 0 100 Group delay [ns] 12 Gain 6 0 Phase -6 -12 -18 -24 -30 -36 -42 -48 0.1 1 10 Frequency [MHz] Phase [deg] Gain [dB] Figure 16. Gain and Phase characteristics (6dB, standard fc mode, FCDATA = 227) Gain [dB] 270 180 90 0 -90 -180 -270 -360 -450 -540 -630 100 Gain [dB] 12 Gain 6 0 Phase -6 -12 -18 -24 -30 -36 -42 -48 0.1 1 10 Frequency [MHz] Phase [deg] Gain [dB] SM5302A Figure 19. Gain and Group delay characteristics (6dB, half fc mode, FCDATA = 227) NIPPON PRECISION CIRCUITS INC.—23 SM5302A (Bypass mode) 0 -90 Phase [deg] Gain [dB] (Bypass mode) 12 6 0 -6 -12 -18 -24 -30 -36 -42 -48 0.1 (1) (2) (3) (4) -180 (4) -270 (3) -360 (2) -450 (1) -540 -630 1 10 Frequency [MHz] 100 0.1 1 10 Frequency [MHz] 100 Figure 20. Gain vs. FCDATA, fc mode (6dB) Figure 21. Phase vs. FCDATA, fc mode (6dB) FCDATA fc mode FCDATA fc mode (1) 227 standard (1) 227 standard (2) 227 half (2) 227 half (3) 10 standard (3) 10 standard (4) 10 half (4) 10 half 180 Group delay [ns] 160 140 (4) 120 (3) 100 80 (2) 60 (1) (Bypass mode) 40 20 0 0 10 20 30 40 50 Frequency [MHz] 60 Figure 22. Group delay vs. FCDATA, fc mode (6dB) FCDATA fc mode (1) 227 standard (2) 227 half (3) 10 standard (4) 10 half NIPPON PRECISION CIRCUITS INC.—24 160 150 140 ICC1*1 130 120 110 100 ICC2*2 90 80 70 60 4.25 4.5 4.75 5 5.25 5.5 5.75 VCC [V] Figure 23. ICC1 vs. VCC (6dB, FCDATA = 255) *1. filter mode, FCDATA = 255 *2. filter bypass mode ICC [mA] ICC [mA] SM5302A 160 150 140 130 ICC1*1 120 110 100 ICC2*2 90 80 70 60 -50 -25 0 25 50 Ta [°C] 75 100 Figure 24. ICC1 vs. Ta (6dB, FCDATA = 255) *1. filter mode, FCDATA = 255 *2. filter bypass mode 7 160 150 Gain [dB] ICC1 [mA] 6.5 140 130 6 120 5.5 110 5 4.25 4.5 4.75 5 5.25 5.5 5.75 VCC [V] 100 0 64 128 192 256 FCDATA Figure 25. ICC1 vs. FCDATA (6dB) Figure 26. Gain vs. VCC (6dB) 6.5 0.5 Gain [dB] 1 Gain [dB] 7 6 -0.5 5.5 5 -50 -25 0 0 25 50 75 100 Ta [°C] Figure 27. Gain vs. Ta (6dB) -1 4.25 4.5 4.75 5 5.25 5.5 5.75 VCC [V] Figure 28. Gain vs. VCC (0dB) 1 Gain [dB] 0.5 0 -0.5 -1 -50 -25 0 25 50 Ta [°C] 75 100 Figure 29. Gain vs. Ta (0dB) NIPPON PRECISION CIRCUITS INC.—25 SM5302A Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from NIPPON PRECISION CIRCUITS INC. (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: [email protected] NC0301AE 2004.04 NIPPON PRECISION CIRCUITS INC.—26