SM5838AS 5120 × 8-bit Synchronous FIFO NIPPON PRECISION CIRCUITS INC. OVERVIEW PINOUT The SM5838AS is a 5120 × 8-bit synchronous FIFO (first in, first out) high-speed line buffer. Internally, it employs static CMOS circuits which mean that it effectively has limitless data hold times. It can operate at speeds up to 33.3 MHz (normal-voltage specification). (TOP VIEW) 24 DIN0 23 DIN1 DOUT2 3 22 DIN2 DOUT3 4 21 DIN3 OE 5 RR 6 VSS 7 FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ RE 8 DOUT4 9 5120 × 8-bit structure Variable-length delay (21 to 5120 bits) 33.3 MHz high-speed operation (normal-voltage specification) All input/outputs TTL compatible Independent read enable and output enable pins, allowing read address pointer increment in output data hold and output high-impedance states Supply voltage • 4.5 to 5.5 V (normal-voltage specification) • 3.0 to 4.5 V (low-voltage specification) 24-pin SOP package Molybdenum-gate CMOS process A3-paper 1-line (16 dots/mm) compatible S M5 8 3 8 AS The SM5838AS can be used to easily realize a 1-line delay in high-speed facsimile machines and digital copiers. DOUT0 1 DOUT1 2 20 WE 19 RW 18 VDD 17 CLK 16 DIN4 DOUT5 10 15 DIN5 DOUT6 11 14 DIN6 DOUT7 12 13 DIN7 PACKAGE DIMENSIONS 8.4TYP 15.8TYP 11.8 0.3 0.6MAX 24-pin SOP (Unit: mm) 0 10 1.0 0.2 + 0.10 + 0.08 0.4 - 0.05 0.17 - 0.07 2.5MAX 1.27 0.1 0.10MIN 0.915 NIPPON PRECISION CIRCUITS—1 SM5838AS WE Write address pointer RW 32 SRAM 8 Output buffer 32 P/S converter 8 Cache 8 S/P converter DIN Input buffer BLOCK DIAGRAM 8 DOUT OE Decoder Read address pointer RE RR CLK PIN DESCRIPTION Number Name I/O Function 1 DOUT0 O Read data output bit 0 2 DOUT1 O Read data output bit 1 3 DOUT2 O Read data output bit 2 4 DOUT3 O Read data output bit 3 5 OE I Output enable input 6 RR I Reset read input 7 VSS – Ground (0 V) pin 8 RE I Read enable input (read address pointer) 9 DOUT4 O Read data output bit 4 10 DOUT5 O Read data output bit 5 11 DOUT6 O Read data output bit 6 12 DOUT7 O Read data output bit 7 13 DIN7 I Write data input bit 7 14 DIN6 I Write data input bit 6 15 DIN5 I Write data input bit 5 16 DIN4 I Write data input bit 4 17 CLK I Clock input 18 VDD – Supply pin 19 RW I Reset write input 20 WE I Write enable input (write address pointer) 21 DIN3 I Write data input bit 3 22 DIN2 I Write data input bit 2 23 DIN1 I Write data input bit 1 24 DIN0 I Write data input bit 0 NIPPON PRECISION CIRCUITS—2 SM5838AS SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Symbol Condition Rating Unit Supply voltage range V DD −0.3 to 7.0 V Input voltage range VIN V SS − 0.3 to VDD + 0.3 V Storage temperature range T stg −40 to 125 °C Power dissipation PD 500 mW Soldering temperature T sld 255 °C Soldering time tsld 10 s Recommended Operating Conditions VSS = 0 V Rating Parameter Supply voltage range Operating temperature Symbol V DD Condition Unit min typ max Normal-voltage specification 4.5 5.0 5.5 V Low-voltage specification 3.0 3.3 4.5 V −20 – 70 °C Topr DC Characteristics 5 V supply Parameter Symbol 3 V supply Condition Unit min typ max min typ max – 75 90 – 22 30 mA – – 50 – – 50 µA Operating current consumption IDD Standby current consumption IST Input leakage current2 ILH V IN = VDD – – 1 – – 1 µA Input leakage current3 ILL V IN = 0 V – – 1 – – 1 µA Input voltage2 V IH 2.4 – – 2.0 – – V Input voltage3 V IL – – 0.5 – – 0.5 V Output high-impedance leakage current4 IZH OE = HIGH, VOUT = VDD – – 5 – – 5 IZL OE = HIGH, VOUT = 0 V – – 5 – – 5 Output voltage4 No output load1 VOH IOH = −1 mA 2.5 – – 2.0 – – VOL IOH = 2 mA – – 0.4 – – 0.8 µA V 1. Normal-voltage specification (CLK = 33.3 MHz); Low-voltage specification (CLK = 20 MHz, V DD = 3.3 ± 0.3 V) 2. Pins CLK, RR and RE. 3. Pins DIN0 to DIN7, RW, WE and OE. 4. Pins DOUT0 to DOUT7. Input/Outputs Ta = 25°C, f = 1 MHz Rating Parameter Symbol Condition Unit min typ max Input capacitance CI – – 10 pF Output capacitance CO – – 10 pF NIPPON PRECISION CIRCUITS—3 SM5838AS AC Characteristics Input timing 5 V supply Parameter Symbol 3 V supply Condition Unit min typ max min typ max Clock cycle time tCK 30 – – 50 – – ns Clock pulsewidth tCKW 13 – – 23 – – ns Input data setup time tDS 7 – – 10 – – ns Input data hold time tDH 3 – – 4 – – ns RW and RR setup time tRS 10 – – 17 – – ns RW and RR hold time tRH 0 – – 0 – – ns WE setup time tWES 13 – – 23 – – ns WE hold time tWEH 0 – – 0 – – ns RE setup time tRES 13 – – 23 – – ns RE hold time tREH 0 – – 0 – – ns OE setup time tOES 10 – – 17 – – ns OE hold time tOEH 0 – – 0 – – ns Tt – – 30 – – 30 ns Rise and fall transition times 1. All voltages measured with relative to VSS . 2. Input timing input voltage levels are VIL = 0 V and VIH = 3.0/2.5 V (5/3 V supply). Transition time is measured between VIH and VIL. 3. Input signal reference level is VTH = 1.5 V. 4. Input timing ratings measured with tT = 5 ns. Normal-voltage (5 V) specification Low-voltage (3 V) specification 3.0V 2.5V 0V 0V 5ns 5ns 5ns 5ns t CK t CKW CLK RW RR t CKW t RS t RW t RH t RS t RR t RH t RH t RS t RS t RH t WEH t WES t WEH t WES t REH t RES t REH t RES t OEH t OES WE RE t OEH t OES OE DIN ,,,,,, ,,,,,, ,,,,,, ,,,,,, t DS t DH ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, t DS t DH ,,,,,, ,,,,,, ,,,,,, ,,,,,, NIPPON PRECISION CIRCUITS—4 SM5838AS Output timing 5 V supply Parameter Symbol Access time tA Output hold time tOH Output enable delay time1 tZO Output disable delay time1 3 V supply Condition Unit min typ max min typ max – – 20 – – 40 ns 5 – – 5 – – ns 5 – 27 5 – 40 ns 5 – 27 5 – 40 ns “Load circuit 1” “Load circuit 2” tOZ 1. tZO and tOZ are measured with ±200 mV tolerance. Normal-voltage (5 V) specification Low-voltage (3 V) specification 2.0V 1.8V 0.8V 1.0V t CK t CKW CLK t CKW t OEH t OES t OEH t OES OE tA tA DOUT ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t OH Hi-Z t OZ ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t ZO RR="H" ,RE="L" Load circuit 1 Load circuit 2 VDD VDD 1.8k Ω DOUT 1.1kΩ 1.8kΩ DOUT 30pF 1.1kΩ 5pF NIPPON PRECISION CIRCUITS—5 SM5838AS FUNCTIONAL DESCRIPTION At power-ON reset, device operation can become irregular during the interval when the control circuits are being reset. After power-ON reset is released, this can take up to several 10s of ms in some cases. Write Reset Cycle, Read Reset Cycle After power-ON, the write address pointer and read address pointer positions are undefined. Accordingly, it is necessary to initialize the pointers using a write reset cycle and read reset cycle, respectively. both the CLK rising edge setup time (tRS) and hold time (tRH). Note that a write reset cycle (read reset cycle) can occur simultaneously with a write cycle (read cycle). If the cycles are not simultaneous, then the write reset cycle (read reset cycle) is completed at the start of the next write cycle (read cycle). A write reset cycle (read reset cycle) is valid when RW (RR) goes LOW for an interval that satisfies Write reset cycle n cycle CLK reset cycle t CKW 0 cycle 1 cycle t CKW t RW t RS t RH RW t RH DIN (n-1) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t DS t DH (n) ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, t RS t DS t DH (0) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, (1) WE="L" Read reset cycle n cycle CLK reset cycle t CKW 1 cycle t CKW t RS RR DOUT 0 cycle t RH tA (n-1) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t RR t RH t RS tA (n) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t OH tA (0) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t OH tA (0) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, (1) t OH RE="L" , OE="L" Note the even if a reset period (tRW, tRR) is zero length in the write reset and read reset cycles, the reset operation does take place. NIPPON PRECISION CIRCUITS—6 SM5838AS Write Cycle The input data address is determined by the write address pointer position. The write address pointer is reset by RW (write reset cycle), and is incremented on the rising edge of CLK whenever WE is LOW. n cycle CLK n+1 cycle t CKW Data input occurs on the rising edge of CLK at the end of the write cycle. When WE goes HIGH, write operation is disabled and the write address pointer stops. disable cycle n+2 cycle t CKW t WEH t WES t WEH t WES WE DIN (n-1) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t DS (n) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, t DS (n+1) t DH ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, (n+2) t DH RW="H" Read Cycle The output data address is determined by the read address pointer position. The read address pointer is reset by RR (read reset cycle), and is incremented on the rising edge of CLK whenever RE is LOW. Data output starts tA (max) after the rising edge of CLK at the start of the read cycle and continues until tOH (min) after the next rising edge of CLK. n cycle CLK n+1 cycle t CKW When RE goes HIGH, read operation is disabled and the read address pointer stops. Note that data being read was written at least 20 write cycles previously (FIFO minimum delay). Therefore, if (write address pointer) − (read address pointer) = 1 to 19, then a possibility exists that data from the preceding line is output instead. disable cycle n+2 cycle t CKW t REH t RES t REH t RES RE tA DOUT (n-1) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, tA tA (n) ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, t OH (n+1) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, (n+2) t OH RR="H" , OE="L" NIPPON PRECISION CIRCUITS—7 SM5838AS Output Enable When OE is HIGH, DOUT0 to DOUT7 become high impedance. Note that because RE operation is independent of OE operation, the read address pointer can be incremented even when the outputs are high impedance. n cycle n+1 cycle t CKW n+2 cycle n+3 cycle CLK t CKW t OEH t OES t OES t OEH OE tA tA ,,,,,,, DOUT (n-1) ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, Hi-Z (n) t OZ (n+3) t ZO RR="H" ,RE="L" TYPICAL APPLICATIONS Note that at power-ON, the write address pointer and read address pointer positions are undefined. Accordingly, RW and RR reset cycles are required. 1H Delay Line A 5120-word delay line can be realized by performing simultaneous write reset and read reset at powerON. An n-word delay line (21 to 5210-word) can be realized using any of the following methods. 1. Perform reset in sync with desired delay length. 2. Stagger RW and RR timing to desired delay length. 3. Manipulate the write or read address pointer using WE or RE to disable incrementing to maintain sync with desired delay length. 1H (5120-word) delay line timing 1H 0 cycle 1 cycle 2H 5119 cycle 2 cycle 5120+0 cycle 5120+1 cycle 5120+2 cycle 5120+3 cycle CLK t RS t RH RW RR DIN DOUT ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, t DS t DH ,,, ,,, ,,, ,,, ,,, 0 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 0 0 ,,, ,,, ,,, ,,, ,,, 1 ,,, ,,, ,,, ,,, ,,, 5120 cycle 2 ,,, ,,, 5118 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 5119 ,,, ,,, ,,, ,,, ,,, 1 ,,, ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, ,,, 3 ,, ,, ,, ,, ,, ,,, ,,, ,,, ,,, ,,, 1 ,,, ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, ,,, 3 ,, ,, ,, ,, ,, t OH tA WE="L" , RE="L" , OE="L" NIPPON PRECISION CIRCUITS—8 SM5838AS n-word delay line timing 1 1H 0 cycle 1 cycle 2H n-1 cycle 2 cycle n+0 cycle n+1 cycle n+2 cycle n+3 cycle CLK t RS t RH RW RR t DS t DH ,,,,,,,,,, ,,, ,,, ,,, ,,,,,,,,,, ,,, ,,, ,,, n-2 ,,, ,,, n-1 ,, ,, DIN ,,,,,,,,,, 0 ,,, 1 ,,, 2 ,,, ,,, ,, ,,,,,,,,,, ,,, ,,, ,,, ,,, ,, ,,,,,,,,,, ,,, ,,, ,,, ,,, ,, t n cycle ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, DOUT ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 0 t OH A 0 ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, 1 1 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 2 2 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, 3 3 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, WE="L" , RE="L" , OE="L" n-word delay line timing 2 1H 0 cycle 1 cycle 2H n-1 cycle 2 cycle n+0 cycle n+1 cycle n+2 cycle n+3 cycle CLK t RS t RH RW t RS t RH RR DIN ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, t DS t DH 0 ,,, ,,, ,,, ,,, 1 ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, n-2 ,,, ,,, ,,, ,,, n-1 ,, ,, ,, ,, 0 t OH tA n cycle ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, DOUT ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 0 ,, ,, ,, ,, 1 ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, 3 ,,, ,,, ,,, ,,, ,, ,, ,, ,, 1 ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, 3 ,,, ,,, ,,, ,,, WE="L" , RE="L" , OE="L" n-word delay line timing 3 1H 0 cycle 1 cycle 2H n-1 cycle 2 cycle n+0 cycle n+1 cycle n+2 cycle n+3 cycle CLK t RS t RH RW RR t RES RE DIN ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, t DS t DH 0 ,,, ,,, ,,, ,,, 1 ,,, ,,, ,,, ,,, n cycle 2 ,,, ,,, ,,, ,,, n-2 ,,, ,,, ,,, ,,, n-1 ,, ,, ,, ,, 0 t OH tA ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, DOUT ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 0 ,, ,, ,, ,, 1 ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, 3 ,,, ,,, ,,, ,,, ,, ,, ,, ,, 1 ,,, ,,, ,,, ,,, 2 ,,, ,,, ,,, ,,, 3 ,,, ,,, ,,, ,,, WE="L" , RE="L" , OE="L" NIPPON PRECISION CIRCUITS—9 SM5838AS High-speed Conversion For example, an NTSC signal interlace-to-noninterlace conversion. If interpolated line data can be assumed to be similar to the preceding line data and the write data rate is 14.3 MHz (4fSC), then conversion can be realized by reading twice at 28.6 MHz (8fSC). line by alternating between 2 SM5838AS devices (1 line/device). In reality, however, double the number of devices are required for luminance signal (Y) and color difference signal (C) systems. And triple the number of devices are required for RGB signal systems. Furthermore, interpolated line data, with appropriate signal processing separation, can be read out line-byPreceding line data used as interpolated line 1819 0 1 2 3 4 5 0 1 2 CLK WE RW nH DIN 0 1 nH+1H 2 909 0 1 2 909 RE OE RR nH-1H DOUT 0 1 2 3 4 5 nH nH 0 1 2 3 4 5 0 1 2 3 4 5 909 909 * 909 nH+1H 0 1 2 3 4 5 909 * *Output data 867 to 909 forms the preceding 1H data. Interpolated data used as interpolated line 1819 0 1 2 3 4 5 0 1 2 CLK WE RW nH (A)DIN 0 1 2 (B)DIN 0 1 2 nH+1H 909 0 1 2 909 0 1 2 nH' 909 nH'+1H 909 (A)RE (A)OE (A)RR nH (A)DOUT nH+1H 0 1 2 3 4 5 0 1 2 3 4 5 909 * 909 * (B)RE (B)OE (B)RR nH'-1H (B)DOUT nH' 0 1 2 3 4 5 0 1 2 3 4 5 909 909 *Output data 867 to 909 forms the preceding 1H data. NIPPON PRECISION CIRCUITS—10 SM5838AS 1/2 Data Reduction Input data rate reduction by half can be realized by taking WE and RE simultaneously HIGH only once every two clock cycles. Noninterlace-to-interlace conversions line extraction can be realized by switching WE LOW/HIGH in line units and RE LOW/HIGH in word units. 1/2 data reduction 5119 0 1 2 3 4 5 0 1 2 CLK WE RW nH DIN nH+1H 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 5119 5119 RE OE RR nH-1H DOUT 0 2 4 6 8 10 nH 12 14 5118 0 2 4 6 8 10 12 14 5118 1/2 line extraction (noninterlace-to-interlace conversion) 1819 0 1 2 3 4 5 0 1 2 CLK WE RW nH-1H DIN nH 0 1 2 3 4 5 nH+1H 0 1 2 3 4 5 909 nH+2H 0 1 2 3 4 5 909 0 1 2 3 4 5 909 909 RE OE RR nH-2H DOUT 0 1 2 nH 909 0 1 2 909 NIPPON PRECISION CIRCUITS—11 SM5838AS 1/2n data reduction (n × n pixel reduction) Screen resolution reduction, or 2 × 2 pixel reduction, can be realized by combining both 1/2 data reduction and 1/2 line extraction schemes. Furthermore, n × n pixel reduction (for integer n) can be realized by changing the WE and RE disable intervals and the RW and RR reset timing. Also, if the same data is repeatedly read out in place of other data that has been discarded, the screen resolution can be reduced without changing the data rate to realize a mosaic filter function. 2 × 2 pixel reduction (1/4 reduction) 2 pixels Valid 2 pixels Invalid Invalid Invalid 909 0 1 2 3 4 5 CLK WE RW nH-1H DIN nH 0 1 2 3 4 5 nH+1H 0 1 2 3 4 5 nH+2H 0 1 2 3 4 5 0 1 2 3 4 5 909 909 909 909 RE OE RR nH-2H DOUT 0 nH 2 908 0 2 908 2 × 2 pixel reduction (mosaic) 2 pixels Valid 2 pixels 909 0 1 2 3 4 5 CLK WE RW nH-1H DIN nH 0 1 2 3 4 5 nH+1H 0 1 2 3 4 5 nH+2H 0 1 2 3 4 5 0 1 2 3 4 5 909 909 909 909 RE OE RR nH-2H DOUT 0 2 4 nH nH-2H 6 908* 0 2 4 908 0 2 4 nH 6 908* 0 2 4 908 *Output date 902 to 908 forms the preceding 1H data. NIPPON PRECISION CIRCUITS—12 SM5838AS Wipe Function (Screen Switching) Because RE and OE operate independently, a screen wipe function can be realized using 2 SM5838AS devices by switching OE LOW/HIGH in field units. Screen wipe (OE changes in field units) 909 0 1 2 3 4 5 CLK WE RW nH-1H (A)DIN nH 0 1 2 3 4 5 909 0 1 2 3 4 5 909 0 1 2 3 4 5 909 909 nH'+1H nH' 0 1 2 3 4 5 nH+2H 0 1 2 3 4 5 909 nH'-1H (B)DIN nH+1H 0 1 2 3 4 5 nH'+2H 0 1 2 3 4 5 909 0 1 2 3 4 5 909 909 (A)RE (A)OE (A)RR (A)DOUT nH-2H nH-1H nH 4 5 4 5 4 5 909 909 nH+1H 4 5 909 909 (B)RE (B)OE (B)RR nH'-2H (B)DOUT 0 1 2 3 nH'-1H 0 1 2 3 nH' 0 1 2 3 nH'+1H 0 1 2 3 Screen wipe image (left to right) (B) (A) NIPPON PRECISION CIRCUITS—13 SM5838AS NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, 2-chome Fukuzumi Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9411AE 1996.09 NIPPON PRECISION CIRCUITS—14